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authorDavid S. Miller <davem@davemloft.net>2009-11-09 14:17:24 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-09 14:17:24 -0500
commitf6d773cd4f3c18c40ab25a5cb92453756237840e (patch)
tree5631a6ea4495ae2eb5058fb63b25dea3b197d61b /drivers/net/wireless/rt2x00
parentd0e1e88d6e7dbd8e1661cb6a058ca30f54ee39e4 (diff)
parentbcb628d579a61d0ab0cac4c6cc8a403de5254920 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig18
-rw-r--r--drivers/net/wireless/rt2x00/Makefile1
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h1816
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c1817
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h134
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c1908
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.h1780
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c1828
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h1818
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h43
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00leds.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h24
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h17
14 files changed, 4049 insertions, 7161 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 390c0c7b3ac2..bf60689aaabb 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -1,6 +1,6 @@
1menuconfig RT2X00 1menuconfig RT2X00
2 tristate "Ralink driver support" 2 tristate "Ralink driver support"
3 depends on MAC80211 && WLAN_80211 3 depends on MAC80211
4 ---help--- 4 ---help---
5 This will enable the support for the Ralink drivers, 5 This will enable the support for the Ralink drivers,
6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>. 6 developed in the rt2x00 project <http://rt2x00.serialmonkey.com>.
@@ -64,8 +64,9 @@ config RT2800PCI_SOC
64 default y 64 default y
65 65
66config RT2800PCI 66config RT2800PCI
67 tristate "Ralink rt2800 (PCI/PCMCIA) support" 67 tristate "Ralink rt2800 (PCI/PCMCIA) support (VERY EXPERIMENTAL)"
68 depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL 68 depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL
69 select RT2800_LIB
69 select RT2X00_LIB_PCI if RT2800PCI_PCI 70 select RT2X00_LIB_PCI if RT2800PCI_PCI
70 select RT2X00_LIB_SOC if RT2800PCI_SOC 71 select RT2X00_LIB_SOC if RT2800PCI_SOC
71 select RT2X00_LIB_HT 72 select RT2X00_LIB_HT
@@ -77,6 +78,9 @@ config RT2800PCI
77 This adds support for rt2800 wireless chipset family. 78 This adds support for rt2800 wireless chipset family.
78 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052 79 Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052
79 80
81 This driver is non-functional at the moment and is intended for
82 developers.
83
80 When compiled as a module, this driver will be called "rt2800pci.ko". 84 When compiled as a module, this driver will be called "rt2800pci.ko".
81 85
82config RT2500USB 86config RT2500USB
@@ -104,8 +108,9 @@ config RT73USB
104 When compiled as a module, this driver will be called rt73usb. 108 When compiled as a module, this driver will be called rt73usb.
105 109
106config RT2800USB 110config RT2800USB
107 tristate "Ralink rt2800 (USB) support" 111 tristate "Ralink rt2800 (USB) support (EXPERIMENTAL)"
108 depends on USB && EXPERIMENTAL 112 depends on USB && EXPERIMENTAL
113 select RT2800_LIB
109 select RT2X00_LIB_USB 114 select RT2X00_LIB_USB
110 select RT2X00_LIB_HT 115 select RT2X00_LIB_HT
111 select RT2X00_LIB_FIRMWARE 116 select RT2X00_LIB_FIRMWARE
@@ -115,8 +120,15 @@ config RT2800USB
115 This adds experimental support for rt2800 wireless chipset family. 120 This adds experimental support for rt2800 wireless chipset family.
116 Supported chips: RT2770, RT2870 & RT3070. 121 Supported chips: RT2770, RT2870 & RT3070.
117 122
123 Known issues:
124 - support for RT2870 chips doesn't work with 802.11n APs yet
125 - support for RT3070 chips is non-functional at the moment
126
118 When compiled as a module, this driver will be called "rt2800usb.ko". 127 When compiled as a module, this driver will be called "rt2800usb.ko".
119 128
129config RT2800_LIB
130 tristate
131
120config RT2X00_LIB_PCI 132config RT2X00_LIB_PCI
121 tristate 133 tristate
122 select RT2X00_LIB 134 select RT2X00_LIB
diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
index 912f5f67e159..971339858297 100644
--- a/drivers/net/wireless/rt2x00/Makefile
+++ b/drivers/net/wireless/rt2x00/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o
13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o 13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o
14obj-$(CONFIG_RT2X00_LIB_SOC) += rt2x00soc.o 14obj-$(CONFIG_RT2X00_LIB_SOC) += rt2x00soc.o
15obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o 15obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00usb.o
16obj-$(CONFIG_RT2800_LIB) += rt2800lib.o
16obj-$(CONFIG_RT2400PCI) += rt2400pci.o 17obj-$(CONFIG_RT2400PCI) += rt2400pci.o
17obj-$(CONFIG_RT2500PCI) += rt2500pci.o 18obj-$(CONFIG_RT2500PCI) += rt2500pci.o
18obj-$(CONFIG_RT61PCI) += rt61pci.o 19obj-$(CONFIG_RT61PCI) += rt61pci.o
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
new file mode 100644
index 000000000000..d9b6a72e6d27
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -0,0 +1,1816 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800
23 Abstract: Data structures and registers for the rt2800 modules.
24 Supported chipsets: RT2800E, RT2800ED & RT2800U.
25 */
26
27#ifndef RT2800_H
28#define RT2800_H
29
30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * Chipset version.
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Default offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * USB registers.
87 */
88
89/*
90 * INT_SOURCE_CSR: Interrupt source register.
91 * Write one to clear corresponding bit.
92 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
93 */
94#define INT_SOURCE_CSR 0x0200
95#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
96#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
97#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
98#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
99#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
100#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
101#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
102#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
103#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
104#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
105#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
106#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
107#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
108#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
109#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
110#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
111#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
112#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
113
114/*
115 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
116 */
117#define INT_MASK_CSR 0x0204
118#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
119#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
120#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
121#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
122#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
123#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
124#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
125#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
126#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
127#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
128#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
129#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
130#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
131#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
132#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
133#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
134#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
135#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
136
137/*
138 * WPDMA_GLO_CFG
139 */
140#define WPDMA_GLO_CFG 0x0208
141#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
142#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
143#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
144#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
145#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
146#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
147#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
148#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
149#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
150
151/*
152 * WPDMA_RST_IDX
153 */
154#define WPDMA_RST_IDX 0x020c
155#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
156#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
157#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
158#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
159#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
160#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
161#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
162
163/*
164 * DELAY_INT_CFG
165 */
166#define DELAY_INT_CFG 0x0210
167#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
168#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
169#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
170#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
171#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
172#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
173
174/*
175 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
176 * AIFSN0: AC_BE
177 * AIFSN1: AC_BK
178 * AIFSN2: AC_VI
179 * AIFSN3: AC_VO
180 */
181#define WMM_AIFSN_CFG 0x0214
182#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
183#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
184#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
185#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
186
187/*
188 * WMM_CWMIN_CSR: CWmin for each EDCA AC
189 * CWMIN0: AC_BE
190 * CWMIN1: AC_BK
191 * CWMIN2: AC_VI
192 * CWMIN3: AC_VO
193 */
194#define WMM_CWMIN_CFG 0x0218
195#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
196#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
197#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
198#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
199
200/*
201 * WMM_CWMAX_CSR: CWmax for each EDCA AC
202 * CWMAX0: AC_BE
203 * CWMAX1: AC_BK
204 * CWMAX2: AC_VI
205 * CWMAX3: AC_VO
206 */
207#define WMM_CWMAX_CFG 0x021c
208#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
209#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
210#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
211#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
212
213/*
214 * AC_TXOP0: AC_BK/AC_BE TXOP register
215 * AC0TXOP: AC_BK in unit of 32us
216 * AC1TXOP: AC_BE in unit of 32us
217 */
218#define WMM_TXOP0_CFG 0x0220
219#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
220#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
221
222/*
223 * AC_TXOP1: AC_VO/AC_VI TXOP register
224 * AC2TXOP: AC_VI in unit of 32us
225 * AC3TXOP: AC_VO in unit of 32us
226 */
227#define WMM_TXOP1_CFG 0x0224
228#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
229#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
230
231/*
232 * GPIO_CTRL_CFG:
233 */
234#define GPIO_CTRL_CFG 0x0228
235#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
236#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
237#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
238#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
239#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
240#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
241#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
242#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
243#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
244
245/*
246 * MCU_CMD_CFG
247 */
248#define MCU_CMD_CFG 0x022c
249
250/*
251 * AC_BK register offsets
252 */
253#define TX_BASE_PTR0 0x0230
254#define TX_MAX_CNT0 0x0234
255#define TX_CTX_IDX0 0x0238
256#define TX_DTX_IDX0 0x023c
257
258/*
259 * AC_BE register offsets
260 */
261#define TX_BASE_PTR1 0x0240
262#define TX_MAX_CNT1 0x0244
263#define TX_CTX_IDX1 0x0248
264#define TX_DTX_IDX1 0x024c
265
266/*
267 * AC_VI register offsets
268 */
269#define TX_BASE_PTR2 0x0250
270#define TX_MAX_CNT2 0x0254
271#define TX_CTX_IDX2 0x0258
272#define TX_DTX_IDX2 0x025c
273
274/*
275 * AC_VO register offsets
276 */
277#define TX_BASE_PTR3 0x0260
278#define TX_MAX_CNT3 0x0264
279#define TX_CTX_IDX3 0x0268
280#define TX_DTX_IDX3 0x026c
281
282/*
283 * HCCA register offsets
284 */
285#define TX_BASE_PTR4 0x0270
286#define TX_MAX_CNT4 0x0274
287#define TX_CTX_IDX4 0x0278
288#define TX_DTX_IDX4 0x027c
289
290/*
291 * MGMT register offsets
292 */
293#define TX_BASE_PTR5 0x0280
294#define TX_MAX_CNT5 0x0284
295#define TX_CTX_IDX5 0x0288
296#define TX_DTX_IDX5 0x028c
297
298/*
299 * RX register offsets
300 */
301#define RX_BASE_PTR 0x0290
302#define RX_MAX_CNT 0x0294
303#define RX_CRX_IDX 0x0298
304#define RX_DRX_IDX 0x029c
305
306/*
307 * PBF_SYS_CTRL
308 * HOST_RAM_WRITE: enable Host program ram write selection
309 */
310#define PBF_SYS_CTRL 0x0400
311#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
312#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
313
314/*
315 * HOST-MCU shared memory
316 */
317#define HOST_CMD_CSR 0x0404
318#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
319
320/*
321 * PBF registers
322 * Most are for debug. Driver doesn't touch PBF register.
323 */
324#define PBF_CFG 0x0408
325#define PBF_MAX_PCNT 0x040c
326#define PBF_CTRL 0x0410
327#define PBF_INT_STA 0x0414
328#define PBF_INT_ENA 0x0418
329
330/*
331 * BCN_OFFSET0:
332 */
333#define BCN_OFFSET0 0x042c
334#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
335#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
336#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
337#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
338
339/*
340 * BCN_OFFSET1:
341 */
342#define BCN_OFFSET1 0x0430
343#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
344#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
345#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
346#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
347
348/*
349 * PBF registers
350 * Most are for debug. Driver doesn't touch PBF register.
351 */
352#define TXRXQ_PCNT 0x0438
353#define PBF_DBG 0x043c
354
355/*
356 * RF registers
357 */
358#define RF_CSR_CFG 0x0500
359#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
360#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
361#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
362#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
363
364/*
365 * MAC Control/Status Registers(CSR).
366 * Some values are set in TU, whereas 1 TU == 1024 us.
367 */
368
369/*
370 * MAC_CSR0: ASIC revision number.
371 * ASIC_REV: 0
372 * ASIC_VER: 2860 or 2870
373 */
374#define MAC_CSR0 0x1000
375#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
376#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
377
378/*
379 * MAC_SYS_CTRL:
380 */
381#define MAC_SYS_CTRL 0x1004
382#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
383#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
384#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
385#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
386#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
387#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
388#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
389#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
390
391/*
392 * MAC_ADDR_DW0: STA MAC register 0
393 */
394#define MAC_ADDR_DW0 0x1008
395#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
396#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
397#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
398#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
399
400/*
401 * MAC_ADDR_DW1: STA MAC register 1
402 * UNICAST_TO_ME_MASK:
403 * Used to mask off bits from byte 5 of the MAC address
404 * to determine the UNICAST_TO_ME bit for RX frames.
405 * The full mask is complemented by BSS_ID_MASK:
406 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
407 */
408#define MAC_ADDR_DW1 0x100c
409#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
410#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
411#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
412
413/*
414 * MAC_BSSID_DW0: BSSID register 0
415 */
416#define MAC_BSSID_DW0 0x1010
417#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
418#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
419#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
420#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
421
422/*
423 * MAC_BSSID_DW1: BSSID register 1
424 * BSS_ID_MASK:
425 * 0: 1-BSSID mode (BSS index = 0)
426 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
427 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
428 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
429 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
430 * BSSID. This will make sure that those bits will be ignored
431 * when determining the MY_BSS of RX frames.
432 */
433#define MAC_BSSID_DW1 0x1014
434#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
435#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
436#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
437#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
438
439/*
440 * MAX_LEN_CFG: Maximum frame length register.
441 * MAX_MPDU: rt2860b max 16k bytes
442 * MAX_PSDU: Maximum PSDU length
443 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
444 */
445#define MAX_LEN_CFG 0x1018
446#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
447#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
448#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
449#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
450
451/*
452 * BBP_CSR_CFG: BBP serial control register
453 * VALUE: Register value to program into BBP
454 * REG_NUM: Selected BBP register
455 * READ_CONTROL: 0 write BBP, 1 read BBP
456 * BUSY: ASIC is busy executing BBP commands
457 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
458 * BBP_RW_MODE: 0 serial, 1 paralell
459 */
460#define BBP_CSR_CFG 0x101c
461#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
462#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
463#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
464#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
465#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
466#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
467
468/*
469 * RF_CSR_CFG0: RF control register
470 * REGID_AND_VALUE: Register value to program into RF
471 * BITWIDTH: Selected RF register
472 * STANDBYMODE: 0 high when standby, 1 low when standby
473 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
474 * BUSY: ASIC is busy executing RF commands
475 */
476#define RF_CSR_CFG0 0x1020
477#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
478#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
479#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
480#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
481#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
482#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
483
484/*
485 * RF_CSR_CFG1: RF control register
486 * REGID_AND_VALUE: Register value to program into RF
487 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
488 * 0: 3 system clock cycle (37.5usec)
489 * 1: 5 system clock cycle (62.5usec)
490 */
491#define RF_CSR_CFG1 0x1024
492#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
493#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
494
495/*
496 * RF_CSR_CFG2: RF control register
497 * VALUE: Register value to program into RF
498 */
499#define RF_CSR_CFG2 0x1028
500#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
501
502/*
503 * LED_CFG: LED control
504 * color LED's:
505 * 0: off
506 * 1: blinking upon TX2
507 * 2: periodic slow blinking
508 * 3: always on
509 * LED polarity:
510 * 0: active low
511 * 1: active high
512 */
513#define LED_CFG 0x102c
514#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
515#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
516#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
517#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
518#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
519#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
520#define LED_CFG_LED_POLAR FIELD32(0x40000000)
521
522/*
523 * XIFS_TIME_CFG: MAC timing
524 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
525 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
526 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
527 * when MAC doesn't reference BBP signal BBRXEND
528 * EIFS: unit 1us
529 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
530 *
531 */
532#define XIFS_TIME_CFG 0x1100
533#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
534#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
535#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
536#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
537#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
538
539/*
540 * BKOFF_SLOT_CFG:
541 */
542#define BKOFF_SLOT_CFG 0x1104
543#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
544#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
545
546/*
547 * NAV_TIME_CFG:
548 */
549#define NAV_TIME_CFG 0x1108
550#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
551#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
552#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
553#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
554
555/*
556 * CH_TIME_CFG: count as channel busy
557 */
558#define CH_TIME_CFG 0x110c
559
560/*
561 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
562 */
563#define PBF_LIFE_TIMER 0x1110
564
565/*
566 * BCN_TIME_CFG:
567 * BEACON_INTERVAL: in unit of 1/16 TU
568 * TSF_TICKING: Enable TSF auto counting
569 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
570 * BEACON_GEN: Enable beacon generator
571 */
572#define BCN_TIME_CFG 0x1114
573#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
574#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
575#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
576#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
577#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
578#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
579
580/*
581 * TBTT_SYNC_CFG:
582 */
583#define TBTT_SYNC_CFG 0x1118
584
585/*
586 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
587 */
588#define TSF_TIMER_DW0 0x111c
589#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
590
591/*
592 * TSF_TIMER_DW1: Local msb TSF timer, read-only
593 */
594#define TSF_TIMER_DW1 0x1120
595#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
596
597/*
598 * TBTT_TIMER: TImer remains till next TBTT, read-only
599 */
600#define TBTT_TIMER 0x1124
601
602/*
603 * INT_TIMER_CFG:
604 */
605#define INT_TIMER_CFG 0x1128
606
607/*
608 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
609 */
610#define INT_TIMER_EN 0x112c
611
612/*
613 * CH_IDLE_STA: channel idle time
614 */
615#define CH_IDLE_STA 0x1130
616
617/*
618 * CH_BUSY_STA: channel busy time
619 */
620#define CH_BUSY_STA 0x1134
621
622/*
623 * MAC_STATUS_CFG:
624 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
625 * if 1 or higher one of the 2 registers is busy.
626 */
627#define MAC_STATUS_CFG 0x1200
628#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
629
630/*
631 * PWR_PIN_CFG:
632 */
633#define PWR_PIN_CFG 0x1204
634
635/*
636 * AUTOWAKEUP_CFG: Manual power control / status register
637 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
638 * AUTOWAKE: 0:sleep, 1:awake
639 */
640#define AUTOWAKEUP_CFG 0x1208
641#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
642#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
643#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
644
645/*
646 * EDCA_AC0_CFG:
647 */
648#define EDCA_AC0_CFG 0x1300
649#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
650#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
651#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
652#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
653
654/*
655 * EDCA_AC1_CFG:
656 */
657#define EDCA_AC1_CFG 0x1304
658#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
659#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
660#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
661#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
662
663/*
664 * EDCA_AC2_CFG:
665 */
666#define EDCA_AC2_CFG 0x1308
667#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
668#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
669#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
670#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
671
672/*
673 * EDCA_AC3_CFG:
674 */
675#define EDCA_AC3_CFG 0x130c
676#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
677#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
678#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
679#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
680
681/*
682 * EDCA_TID_AC_MAP:
683 */
684#define EDCA_TID_AC_MAP 0x1310
685
686/*
687 * TX_PWR_CFG_0:
688 */
689#define TX_PWR_CFG_0 0x1314
690#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
691#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
692#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
693#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
694#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
695#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
696#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
697#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
698
699/*
700 * TX_PWR_CFG_1:
701 */
702#define TX_PWR_CFG_1 0x1318
703#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
704#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
705#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
706#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
707#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
708#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
709#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
710#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
711
712/*
713 * TX_PWR_CFG_2:
714 */
715#define TX_PWR_CFG_2 0x131c
716#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
717#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
718#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
719#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
720#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
721#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
722#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
723#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
724
725/*
726 * TX_PWR_CFG_3:
727 */
728#define TX_PWR_CFG_3 0x1320
729#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
730#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
731#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
732#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
733#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
734#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
735#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
736#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
737
738/*
739 * TX_PWR_CFG_4:
740 */
741#define TX_PWR_CFG_4 0x1324
742#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
743#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
744#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
745#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
746
747/*
748 * TX_PIN_CFG:
749 */
750#define TX_PIN_CFG 0x1328
751#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
752#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
753#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
754#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
755#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
756#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
757#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
758#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
759#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
760#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
761#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
762#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
763#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
764#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
765#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
766#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
767#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
768#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
769#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
770#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
771
772/*
773 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
774 */
775#define TX_BAND_CFG 0x132c
776#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
777#define TX_BAND_CFG_A FIELD32(0x00000002)
778#define TX_BAND_CFG_BG FIELD32(0x00000004)
779
780/*
781 * TX_SW_CFG0:
782 */
783#define TX_SW_CFG0 0x1330
784
785/*
786 * TX_SW_CFG1:
787 */
788#define TX_SW_CFG1 0x1334
789
790/*
791 * TX_SW_CFG2:
792 */
793#define TX_SW_CFG2 0x1338
794
795/*
796 * TXOP_THRES_CFG:
797 */
798#define TXOP_THRES_CFG 0x133c
799
800/*
801 * TXOP_CTRL_CFG:
802 */
803#define TXOP_CTRL_CFG 0x1340
804
805/*
806 * TX_RTS_CFG:
807 * RTS_THRES: unit:byte
808 * RTS_FBK_EN: enable rts rate fallback
809 */
810#define TX_RTS_CFG 0x1344
811#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
812#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
813#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
814
815/*
816 * TX_TIMEOUT_CFG:
817 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
818 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
819 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
820 * it is recommended that:
821 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
822 */
823#define TX_TIMEOUT_CFG 0x1348
824#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
825#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
826#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
827
828/*
829 * TX_RTY_CFG:
830 * SHORT_RTY_LIMIT: short retry limit
831 * LONG_RTY_LIMIT: long retry limit
832 * LONG_RTY_THRE: Long retry threshoold
833 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
834 * 0:expired by retry limit, 1: expired by mpdu life timer
835 * AGG_RTY_MODE: Aggregate MPDU retry mode
836 * 0:expired by retry limit, 1: expired by mpdu life timer
837 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
838 */
839#define TX_RTY_CFG 0x134c
840#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
841#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
842#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
843#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
844#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
845#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
846
847/*
848 * TX_LINK_CFG:
849 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
850 * MFB_ENABLE: TX apply remote MFB 1:enable
851 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
852 * 0: not apply remote remote unsolicit (MFS=7)
853 * TX_MRQ_EN: MCS request TX enable
854 * TX_RDG_EN: RDG TX enable
855 * TX_CF_ACK_EN: Piggyback CF-ACK enable
856 * REMOTE_MFB: remote MCS feedback
857 * REMOTE_MFS: remote MCS feedback sequence number
858 */
859#define TX_LINK_CFG 0x1350
860#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
861#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
862#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
863#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
864#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
865#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
866#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
867#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
868
869/*
870 * HT_FBK_CFG0:
871 */
872#define HT_FBK_CFG0 0x1354
873#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
874#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
875#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
876#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
877#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
878#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
879#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
880#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
881
882/*
883 * HT_FBK_CFG1:
884 */
885#define HT_FBK_CFG1 0x1358
886#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
887#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
888#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
889#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
890#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
891#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
892#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
893#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
894
895/*
896 * LG_FBK_CFG0:
897 */
898#define LG_FBK_CFG0 0x135c
899#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
900#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
901#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
902#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
903#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
904#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
905#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
906#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
907
908/*
909 * LG_FBK_CFG1:
910 */
911#define LG_FBK_CFG1 0x1360
912#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
913#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
914#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
915#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
916
917/*
918 * CCK_PROT_CFG: CCK Protection
919 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
920 * PROTECT_CTRL: Protection control frame type for CCK TX
921 * 0:none, 1:RTS/CTS, 2:CTS-to-self
922 * PROTECT_NAV: TXOP protection type for CCK TX
923 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
924 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
925 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
926 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
927 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
928 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
929 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
930 * RTS_TH_EN: RTS threshold enable on CCK TX
931 */
932#define CCK_PROT_CFG 0x1364
933#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
934#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
935#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
936#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
937#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
938#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
939#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
940#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
941#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
942#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
943
944/*
945 * OFDM_PROT_CFG: OFDM Protection
946 */
947#define OFDM_PROT_CFG 0x1368
948#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
949#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
950#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
951#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
952#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
953#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
954#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
955#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
956#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
957#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
958
959/*
960 * MM20_PROT_CFG: MM20 Protection
961 */
962#define MM20_PROT_CFG 0x136c
963#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
964#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
965#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
966#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
967#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
968#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
969#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
970#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
971#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
972#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
973
974/*
975 * MM40_PROT_CFG: MM40 Protection
976 */
977#define MM40_PROT_CFG 0x1370
978#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
979#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
980#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
981#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
982#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
983#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
984#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
985#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
986#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
987#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
988
989/*
990 * GF20_PROT_CFG: GF20 Protection
991 */
992#define GF20_PROT_CFG 0x1374
993#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
994#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
995#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
996#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
997#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
998#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
999#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1000#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1001#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1002#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1003
1004/*
1005 * GF40_PROT_CFG: GF40 Protection
1006 */
1007#define GF40_PROT_CFG 0x1378
1008#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1009#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1010#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1011#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1012#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1013#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1014#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1015#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1016#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1017#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1018
1019/*
1020 * EXP_CTS_TIME:
1021 */
1022#define EXP_CTS_TIME 0x137c
1023
1024/*
1025 * EXP_ACK_TIME:
1026 */
1027#define EXP_ACK_TIME 0x1380
1028
1029/*
1030 * RX_FILTER_CFG: RX configuration register.
1031 */
1032#define RX_FILTER_CFG 0x1400
1033#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1034#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1035#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1036#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1037#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1038#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1039#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1040#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1041#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1042#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1043#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1044#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1045#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1046#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1047#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1048#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1049#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1050
1051/*
1052 * AUTO_RSP_CFG:
1053 * AUTORESPONDER: 0: disable, 1: enable
1054 * BAC_ACK_POLICY: 0:long, 1:short preamble
1055 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1056 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1057 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1058 * DUAL_CTS_EN: Power bit value in control frame
1059 * ACK_CTS_PSM_BIT:Power bit value in control frame
1060 */
1061#define AUTO_RSP_CFG 0x1404
1062#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1063#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1064#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1065#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1066#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1067#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1068#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1069
1070/*
1071 * LEGACY_BASIC_RATE:
1072 */
1073#define LEGACY_BASIC_RATE 0x1408
1074
1075/*
1076 * HT_BASIC_RATE:
1077 */
1078#define HT_BASIC_RATE 0x140c
1079
1080/*
1081 * HT_CTRL_CFG:
1082 */
1083#define HT_CTRL_CFG 0x1410
1084
1085/*
1086 * SIFS_COST_CFG:
1087 */
1088#define SIFS_COST_CFG 0x1414
1089
1090/*
1091 * RX_PARSER_CFG:
1092 * Set NAV for all received frames
1093 */
1094#define RX_PARSER_CFG 0x1418
1095
1096/*
1097 * TX_SEC_CNT0:
1098 */
1099#define TX_SEC_CNT0 0x1500
1100
1101/*
1102 * RX_SEC_CNT0:
1103 */
1104#define RX_SEC_CNT0 0x1504
1105
1106/*
1107 * CCMP_FC_MUTE:
1108 */
1109#define CCMP_FC_MUTE 0x1508
1110
1111/*
1112 * TXOP_HLDR_ADDR0:
1113 */
1114#define TXOP_HLDR_ADDR0 0x1600
1115
1116/*
1117 * TXOP_HLDR_ADDR1:
1118 */
1119#define TXOP_HLDR_ADDR1 0x1604
1120
1121/*
1122 * TXOP_HLDR_ET:
1123 */
1124#define TXOP_HLDR_ET 0x1608
1125
1126/*
1127 * QOS_CFPOLL_RA_DW0:
1128 */
1129#define QOS_CFPOLL_RA_DW0 0x160c
1130
1131/*
1132 * QOS_CFPOLL_RA_DW1:
1133 */
1134#define QOS_CFPOLL_RA_DW1 0x1610
1135
1136/*
1137 * QOS_CFPOLL_QC:
1138 */
1139#define QOS_CFPOLL_QC 0x1614
1140
1141/*
1142 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1143 */
1144#define RX_STA_CNT0 0x1700
1145#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1146#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1147
1148/*
1149 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1150 */
1151#define RX_STA_CNT1 0x1704
1152#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1153#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1154
1155/*
1156 * RX_STA_CNT2:
1157 */
1158#define RX_STA_CNT2 0x1708
1159#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1160#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1161
1162/*
1163 * TX_STA_CNT0: TX Beacon count
1164 */
1165#define TX_STA_CNT0 0x170c
1166#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1167#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1168
1169/*
1170 * TX_STA_CNT1: TX tx count
1171 */
1172#define TX_STA_CNT1 0x1710
1173#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1174#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1175
1176/*
1177 * TX_STA_CNT2: TX tx count
1178 */
1179#define TX_STA_CNT2 0x1714
1180#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1181#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1182
1183/*
1184 * TX_STA_FIFO: TX Result for specific PID status fifo register
1185 */
1186#define TX_STA_FIFO 0x1718
1187#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1188#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1189#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1190#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1191#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1192#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1193#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1194#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1195#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1196
1197/*
1198 * TX_AGG_CNT: Debug counter
1199 */
1200#define TX_AGG_CNT 0x171c
1201#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1202#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1203
1204/*
1205 * TX_AGG_CNT0:
1206 */
1207#define TX_AGG_CNT0 0x1720
1208#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1209#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1210
1211/*
1212 * TX_AGG_CNT1:
1213 */
1214#define TX_AGG_CNT1 0x1724
1215#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1216#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1217
1218/*
1219 * TX_AGG_CNT2:
1220 */
1221#define TX_AGG_CNT2 0x1728
1222#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1223#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1224
1225/*
1226 * TX_AGG_CNT3:
1227 */
1228#define TX_AGG_CNT3 0x172c
1229#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1230#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1231
1232/*
1233 * TX_AGG_CNT4:
1234 */
1235#define TX_AGG_CNT4 0x1730
1236#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1237#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1238
1239/*
1240 * TX_AGG_CNT5:
1241 */
1242#define TX_AGG_CNT5 0x1734
1243#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1244#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1245
1246/*
1247 * TX_AGG_CNT6:
1248 */
1249#define TX_AGG_CNT6 0x1738
1250#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1251#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1252
1253/*
1254 * TX_AGG_CNT7:
1255 */
1256#define TX_AGG_CNT7 0x173c
1257#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1258#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1259
1260/*
1261 * MPDU_DENSITY_CNT:
1262 * TX_ZERO_DEL: TX zero length delimiter count
1263 * RX_ZERO_DEL: RX zero length delimiter count
1264 */
1265#define MPDU_DENSITY_CNT 0x1740
1266#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1267#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1268
1269/*
1270 * Security key table memory.
1271 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1272 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1273 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1274 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1275 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1276 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1277 */
1278#define MAC_WCID_BASE 0x1800
1279#define PAIRWISE_KEY_TABLE_BASE 0x4000
1280#define MAC_IVEIV_TABLE_BASE 0x6000
1281#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1282#define SHARED_KEY_TABLE_BASE 0x6c00
1283#define SHARED_KEY_MODE_BASE 0x7000
1284
1285#define MAC_WCID_ENTRY(__idx) \
1286 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1287#define PAIRWISE_KEY_ENTRY(__idx) \
1288 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1289#define MAC_IVEIV_ENTRY(__idx) \
1290 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1291#define MAC_WCID_ATTR_ENTRY(__idx) \
1292 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1293#define SHARED_KEY_ENTRY(__idx) \
1294 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1295#define SHARED_KEY_MODE_ENTRY(__idx) \
1296 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1297
1298struct mac_wcid_entry {
1299 u8 mac[6];
1300 u8 reserved[2];
1301} __attribute__ ((packed));
1302
1303struct hw_key_entry {
1304 u8 key[16];
1305 u8 tx_mic[8];
1306 u8 rx_mic[8];
1307} __attribute__ ((packed));
1308
1309struct mac_iveiv_entry {
1310 u8 iv[8];
1311} __attribute__ ((packed));
1312
1313/*
1314 * MAC_WCID_ATTRIBUTE:
1315 */
1316#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1317#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1318#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1319#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1320
1321/*
1322 * SHARED_KEY_MODE:
1323 */
1324#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1325#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1326#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1327#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1328#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1329#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1330#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1331#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1332
1333/*
1334 * HOST-MCU communication
1335 */
1336
1337/*
1338 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1339 */
1340#define H2M_MAILBOX_CSR 0x7010
1341#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1342#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1343#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1344#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1345
1346/*
1347 * H2M_MAILBOX_CID:
1348 */
1349#define H2M_MAILBOX_CID 0x7014
1350#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1351#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1352#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1353#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1354
1355/*
1356 * H2M_MAILBOX_STATUS:
1357 */
1358#define H2M_MAILBOX_STATUS 0x701c
1359
1360/*
1361 * H2M_INT_SRC:
1362 */
1363#define H2M_INT_SRC 0x7024
1364
1365/*
1366 * H2M_BBP_AGENT:
1367 */
1368#define H2M_BBP_AGENT 0x7028
1369
1370/*
1371 * MCU_LEDCS: LED control for MCU Mailbox.
1372 */
1373#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1374#define MCU_LEDCS_POLARITY FIELD8(0x01)
1375
1376/*
1377 * HW_CS_CTS_BASE:
1378 * Carrier-sense CTS frame base address.
1379 * It's where mac stores carrier-sense frame for carrier-sense function.
1380 */
1381#define HW_CS_CTS_BASE 0x7700
1382
1383/*
1384 * HW_DFS_CTS_BASE:
1385 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1386 */
1387#define HW_DFS_CTS_BASE 0x7780
1388
1389/*
1390 * TXRX control registers - base address 0x3000
1391 */
1392
1393/*
1394 * TXRX_CSR1:
1395 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1396 */
1397#define TXRX_CSR1 0x77d0
1398
1399/*
1400 * HW_DEBUG_SETTING_BASE:
1401 * since NULL frame won't be that long (256 byte)
1402 * We steal 16 tail bytes to save debugging settings
1403 */
1404#define HW_DEBUG_SETTING_BASE 0x77f0
1405#define HW_DEBUG_SETTING_BASE2 0x7770
1406
1407/*
1408 * HW_BEACON_BASE
1409 * In order to support maximum 8 MBSS and its maximum length
1410 * is 512 bytes for each beacon
1411 * Three section discontinue memory segments will be used.
1412 * 1. The original region for BCN 0~3
1413 * 2. Extract memory from FCE table for BCN 4~5
1414 * 3. Extract memory from Pair-wise key table for BCN 6~7
1415 * It occupied those memory of wcid 238~253 for BCN 6
1416 * and wcid 222~237 for BCN 7
1417 *
1418 * IMPORTANT NOTE: Not sure why legacy driver does this,
1419 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1420 */
1421#define HW_BEACON_BASE0 0x7800
1422#define HW_BEACON_BASE1 0x7a00
1423#define HW_BEACON_BASE2 0x7c00
1424#define HW_BEACON_BASE3 0x7e00
1425#define HW_BEACON_BASE4 0x7200
1426#define HW_BEACON_BASE5 0x7400
1427#define HW_BEACON_BASE6 0x5dc0
1428#define HW_BEACON_BASE7 0x5bc0
1429
1430#define HW_BEACON_OFFSET(__index) \
1431 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1432 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1433 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1434
1435/*
1436 * BBP registers.
1437 * The wordsize of the BBP is 8 bits.
1438 */
1439
1440/*
1441 * BBP 1: TX Antenna
1442 */
1443#define BBP1_TX_POWER FIELD8(0x07)
1444#define BBP1_TX_ANTENNA FIELD8(0x18)
1445
1446/*
1447 * BBP 3: RX Antenna
1448 */
1449#define BBP3_RX_ANTENNA FIELD8(0x18)
1450#define BBP3_HT40_PLUS FIELD8(0x20)
1451
1452/*
1453 * BBP 4: Bandwidth
1454 */
1455#define BBP4_TX_BF FIELD8(0x01)
1456#define BBP4_BANDWIDTH FIELD8(0x18)
1457
1458/*
1459 * RFCSR registers
1460 * The wordsize of the RFCSR is 8 bits.
1461 */
1462
1463/*
1464 * RFCSR 6:
1465 */
1466#define RFCSR6_R FIELD8(0x03)
1467
1468/*
1469 * RFCSR 7:
1470 */
1471#define RFCSR7_RF_TUNING FIELD8(0x01)
1472
1473/*
1474 * RFCSR 12:
1475 */
1476#define RFCSR12_TX_POWER FIELD8(0x1f)
1477
1478/*
1479 * RFCSR 22:
1480 */
1481#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1482
1483/*
1484 * RFCSR 23:
1485 */
1486#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1487
1488/*
1489 * RFCSR 30:
1490 */
1491#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1492
1493/*
1494 * RF registers
1495 */
1496
1497/*
1498 * RF 2
1499 */
1500#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1501#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1502#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1503
1504/*
1505 * RF 3
1506 */
1507#define RF3_TXPOWER_G FIELD32(0x00003e00)
1508#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1509#define RF3_TXPOWER_A FIELD32(0x00003c00)
1510
1511/*
1512 * RF 4
1513 */
1514#define RF4_TXPOWER_G FIELD32(0x000007c0)
1515#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1516#define RF4_TXPOWER_A FIELD32(0x00000780)
1517#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1518#define RF4_HT40 FIELD32(0x00200000)
1519
1520/*
1521 * EEPROM content.
1522 * The wordsize of the EEPROM is 16 bits.
1523 */
1524
1525/*
1526 * EEPROM Version
1527 */
1528#define EEPROM_VERSION 0x0001
1529#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1530#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1531
1532/*
1533 * HW MAC address.
1534 */
1535#define EEPROM_MAC_ADDR_0 0x0002
1536#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1537#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1538#define EEPROM_MAC_ADDR_1 0x0003
1539#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1540#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1541#define EEPROM_MAC_ADDR_2 0x0004
1542#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1543#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1544
1545/*
1546 * EEPROM ANTENNA config
1547 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1548 * TXPATH: 1: 1T, 2: 2T
1549 */
1550#define EEPROM_ANTENNA 0x001a
1551#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1552#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1553#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1554
1555/*
1556 * EEPROM NIC config
1557 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1558 */
1559#define EEPROM_NIC 0x001b
1560#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1561#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1562#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1563#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1564#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1565#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1566#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1567#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1568#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1569#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1570
1571/*
1572 * EEPROM frequency
1573 */
1574#define EEPROM_FREQ 0x001d
1575#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1576#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1577#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1578
1579/*
1580 * EEPROM LED
1581 * POLARITY_RDY_G: Polarity RDY_G setting.
1582 * POLARITY_RDY_A: Polarity RDY_A setting.
1583 * POLARITY_ACT: Polarity ACT setting.
1584 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1585 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1586 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1587 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1588 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1589 * LED_MODE: Led mode.
1590 */
1591#define EEPROM_LED1 0x001e
1592#define EEPROM_LED2 0x001f
1593#define EEPROM_LED3 0x0020
1594#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1595#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1596#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1597#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1598#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1599#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1600#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1601#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1602#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1603
1604/*
1605 * EEPROM LNA
1606 */
1607#define EEPROM_LNA 0x0022
1608#define EEPROM_LNA_BG FIELD16(0x00ff)
1609#define EEPROM_LNA_A0 FIELD16(0xff00)
1610
1611/*
1612 * EEPROM RSSI BG offset
1613 */
1614#define EEPROM_RSSI_BG 0x0023
1615#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1616#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1617
1618/*
1619 * EEPROM RSSI BG2 offset
1620 */
1621#define EEPROM_RSSI_BG2 0x0024
1622#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1623#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1624
1625/*
1626 * EEPROM RSSI A offset
1627 */
1628#define EEPROM_RSSI_A 0x0025
1629#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1630#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1631
1632/*
1633 * EEPROM RSSI A2 offset
1634 */
1635#define EEPROM_RSSI_A2 0x0026
1636#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1637#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1638
1639/*
1640 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1641 * This is delta in 40MHZ.
1642 * VALUE: Tx Power dalta value (MAX=4)
1643 * TYPE: 1: Plus the delta value, 0: minus the delta value
1644 * TXPOWER: Enable:
1645 */
1646#define EEPROM_TXPOWER_DELTA 0x0028
1647#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1648#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1649#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1650
1651/*
1652 * EEPROM TXPOWER 802.11BG
1653 */
1654#define EEPROM_TXPOWER_BG1 0x0029
1655#define EEPROM_TXPOWER_BG2 0x0030
1656#define EEPROM_TXPOWER_BG_SIZE 7
1657#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1658#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1659
1660/*
1661 * EEPROM TXPOWER 802.11A
1662 */
1663#define EEPROM_TXPOWER_A1 0x003c
1664#define EEPROM_TXPOWER_A2 0x0053
1665#define EEPROM_TXPOWER_A_SIZE 6
1666#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1667#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1668
1669/*
1670 * EEPROM TXpower byrate: 20MHZ power
1671 */
1672#define EEPROM_TXPOWER_BYRATE 0x006f
1673
1674/*
1675 * EEPROM BBP.
1676 */
1677#define EEPROM_BBP_START 0x0078
1678#define EEPROM_BBP_SIZE 16
1679#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1680#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1681
1682/*
1683 * MCU mailbox commands.
1684 */
1685#define MCU_SLEEP 0x30
1686#define MCU_WAKEUP 0x31
1687#define MCU_RADIO_OFF 0x35
1688#define MCU_CURRENT 0x36
1689#define MCU_LED 0x50
1690#define MCU_LED_STRENGTH 0x51
1691#define MCU_LED_1 0x52
1692#define MCU_LED_2 0x53
1693#define MCU_LED_3 0x54
1694#define MCU_RADAR 0x60
1695#define MCU_BOOT_SIGNAL 0x72
1696#define MCU_BBP_SIGNAL 0x80
1697#define MCU_POWER_SAVE 0x83
1698
1699/*
1700 * MCU mailbox tokens
1701 */
1702#define TOKEN_WAKUP 3
1703
1704/*
1705 * DMA descriptor defines.
1706 */
1707#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1708#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1709
1710/*
1711 * TX WI structure
1712 */
1713
1714/*
1715 * Word0
1716 * FRAG: 1 To inform TKIP engine this is a fragment.
1717 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1718 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1719 * BW: Channel bandwidth 20MHz or 40 MHz
1720 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1721 */
1722#define TXWI_W0_FRAG FIELD32(0x00000001)
1723#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1724#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1725#define TXWI_W0_TS FIELD32(0x00000008)
1726#define TXWI_W0_AMPDU FIELD32(0x00000010)
1727#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1728#define TXWI_W0_TX_OP FIELD32(0x00000300)
1729#define TXWI_W0_MCS FIELD32(0x007f0000)
1730#define TXWI_W0_BW FIELD32(0x00800000)
1731#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1732#define TXWI_W0_STBC FIELD32(0x06000000)
1733#define TXWI_W0_IFS FIELD32(0x08000000)
1734#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1735
1736/*
1737 * Word1
1738 */
1739#define TXWI_W1_ACK FIELD32(0x00000001)
1740#define TXWI_W1_NSEQ FIELD32(0x00000002)
1741#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1742#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1743#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1744#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1745
1746/*
1747 * Word2
1748 */
1749#define TXWI_W2_IV FIELD32(0xffffffff)
1750
1751/*
1752 * Word3
1753 */
1754#define TXWI_W3_EIV FIELD32(0xffffffff)
1755
1756/*
1757 * RX WI structure
1758 */
1759
1760/*
1761 * Word0
1762 */
1763#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1764#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1765#define RXWI_W0_BSSID FIELD32(0x00001c00)
1766#define RXWI_W0_UDF FIELD32(0x0000e000)
1767#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1768#define RXWI_W0_TID FIELD32(0xf0000000)
1769
1770/*
1771 * Word1
1772 */
1773#define RXWI_W1_FRAG FIELD32(0x0000000f)
1774#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1775#define RXWI_W1_MCS FIELD32(0x007f0000)
1776#define RXWI_W1_BW FIELD32(0x00800000)
1777#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1778#define RXWI_W1_STBC FIELD32(0x06000000)
1779#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1780
1781/*
1782 * Word2
1783 */
1784#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1785#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1786#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1787
1788/*
1789 * Word3
1790 */
1791#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1792#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1793
1794/*
1795 * Macros for converting txpower from EEPROM to mac80211 value
1796 * and from mac80211 value to register value.
1797 */
1798#define MIN_G_TXPOWER 0
1799#define MIN_A_TXPOWER -7
1800#define MAX_G_TXPOWER 31
1801#define MAX_A_TXPOWER 15
1802#define DEFAULT_TXPOWER 5
1803
1804#define TXPOWER_G_FROM_DEV(__txpower) \
1805 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1806
1807#define TXPOWER_G_TO_DEV(__txpower) \
1808 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1809
1810#define TXPOWER_A_FROM_DEV(__txpower) \
1811 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1812
1813#define TXPOWER_A_TO_DEV(__txpower) \
1814 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1815
1816#endif /* RT2800_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
new file mode 100644
index 000000000000..5c7d74a6f16e
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -0,0 +1,1817 @@
1/*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3
4 Based on the original rt2800pci.c and rt2800usb.c:
5
6 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
7 <http://rt2x00.serialmonkey.com>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the
21 Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25/*
26 Module: rt2800lib
27 Abstract: rt2800 generic device routines.
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32
33#include "rt2x00.h"
34#ifdef CONFIG_RT2800USB
35#include "rt2x00usb.h"
36#endif
37#include "rt2800lib.h"
38#include "rt2800.h"
39#include "rt2800usb.h"
40
41MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
42MODULE_DESCRIPTION("rt2800 library");
43MODULE_LICENSE("GPL");
44
45/*
46 * Register access.
47 * All access to the CSR registers will go through the methods
48 * rt2800_register_read and rt2800_register_write.
49 * BBP and RF register require indirect register access,
50 * and use the CSR registers BBPCSR and RFCSR to achieve this.
51 * These indirect registers work with busy bits,
52 * and we will try maximal REGISTER_BUSY_COUNT times to access
53 * the register while taking a REGISTER_BUSY_DELAY us delay
54 * between each attampt. When the busy bit is still set at that time,
55 * the access attempt is considered to have failed,
56 * and we will print an error.
57 * The _lock versions must be used if you already hold the csr_mutex
58 */
59#define WAIT_FOR_BBP(__dev, __reg) \
60 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
61#define WAIT_FOR_RFCSR(__dev, __reg) \
62 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
63#define WAIT_FOR_RF(__dev, __reg) \
64 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
65#define WAIT_FOR_MCU(__dev, __reg) \
66 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
67 H2M_MAILBOX_CSR_OWNER, (__reg))
68
69static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
70 const unsigned int word, const u8 value)
71{
72 u32 reg;
73
74 mutex_lock(&rt2x00dev->csr_mutex);
75
76 /*
77 * Wait until the BBP becomes available, afterwards we
78 * can safely write the new data into the register.
79 */
80 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
81 reg = 0;
82 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
86 if (rt2x00_intf_is_pci(rt2x00dev))
87 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
88
89 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
90 }
91
92 mutex_unlock(&rt2x00dev->csr_mutex);
93}
94
95static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
96 const unsigned int word, u8 *value)
97{
98 u32 reg;
99
100 mutex_lock(&rt2x00dev->csr_mutex);
101
102 /*
103 * Wait until the BBP becomes available, afterwards we
104 * can safely write the read request into the register.
105 * After the data has been written, we wait until hardware
106 * returns the correct value, if at any time the register
107 * doesn't become available in time, reg will be 0xffffffff
108 * which means we return 0xff to the caller.
109 */
110 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
111 reg = 0;
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
114 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
115 if (rt2x00_intf_is_pci(rt2x00dev))
116 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
117
118 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
119
120 WAIT_FOR_BBP(rt2x00dev, &reg);
121 }
122
123 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
124
125 mutex_unlock(&rt2x00dev->csr_mutex);
126}
127
128static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
129 const unsigned int word, const u8 value)
130{
131 u32 reg;
132
133 mutex_lock(&rt2x00dev->csr_mutex);
134
135 /*
136 * Wait until the RFCSR becomes available, afterwards we
137 * can safely write the new data into the register.
138 */
139 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
140 reg = 0;
141 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
142 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
143 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
144 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
145
146 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
147 }
148
149 mutex_unlock(&rt2x00dev->csr_mutex);
150}
151
152static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
153 const unsigned int word, u8 *value)
154{
155 u32 reg;
156
157 mutex_lock(&rt2x00dev->csr_mutex);
158
159 /*
160 * Wait until the RFCSR becomes available, afterwards we
161 * can safely write the read request into the register.
162 * After the data has been written, we wait until hardware
163 * returns the correct value, if at any time the register
164 * doesn't become available in time, reg will be 0xffffffff
165 * which means we return 0xff to the caller.
166 */
167 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
168 reg = 0;
169 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
170 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
171 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
172
173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
174
175 WAIT_FOR_RFCSR(rt2x00dev, &reg);
176 }
177
178 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
179
180 mutex_unlock(&rt2x00dev->csr_mutex);
181}
182
183static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
184 const unsigned int word, const u32 value)
185{
186 u32 reg;
187
188 mutex_lock(&rt2x00dev->csr_mutex);
189
190 /*
191 * Wait until the RF becomes available, afterwards we
192 * can safely write the new data into the register.
193 */
194 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
195 reg = 0;
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
197 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
198 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
199 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
200
201 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
202 rt2x00_rf_write(rt2x00dev, word, value);
203 }
204
205 mutex_unlock(&rt2x00dev->csr_mutex);
206}
207
208void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
209 const u8 command, const u8 token,
210 const u8 arg0, const u8 arg1)
211{
212 u32 reg;
213
214 if (rt2x00_intf_is_pci(rt2x00dev)) {
215 /*
216 * RT2880 and RT3052 don't support MCU requests.
217 */
218 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
219 rt2x00_rt(&rt2x00dev->chip, RT3052))
220 return;
221 }
222
223 mutex_lock(&rt2x00dev->csr_mutex);
224
225 /*
226 * Wait until the MCU becomes available, afterwards we
227 * can safely write the new data into the register.
228 */
229 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
230 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
231 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
232 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
233 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
234 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
235
236 reg = 0;
237 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
238 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
239 }
240
241 mutex_unlock(&rt2x00dev->csr_mutex);
242}
243EXPORT_SYMBOL_GPL(rt2800_mcu_request);
244
245#ifdef CONFIG_RT2X00_LIB_DEBUGFS
246const struct rt2x00debug rt2800_rt2x00debug = {
247 .owner = THIS_MODULE,
248 .csr = {
249 .read = rt2800_register_read,
250 .write = rt2800_register_write,
251 .flags = RT2X00DEBUGFS_OFFSET,
252 .word_base = CSR_REG_BASE,
253 .word_size = sizeof(u32),
254 .word_count = CSR_REG_SIZE / sizeof(u32),
255 },
256 .eeprom = {
257 .read = rt2x00_eeprom_read,
258 .write = rt2x00_eeprom_write,
259 .word_base = EEPROM_BASE,
260 .word_size = sizeof(u16),
261 .word_count = EEPROM_SIZE / sizeof(u16),
262 },
263 .bbp = {
264 .read = rt2800_bbp_read,
265 .write = rt2800_bbp_write,
266 .word_base = BBP_BASE,
267 .word_size = sizeof(u8),
268 .word_count = BBP_SIZE / sizeof(u8),
269 },
270 .rf = {
271 .read = rt2x00_rf_read,
272 .write = rt2800_rf_write,
273 .word_base = RF_BASE,
274 .word_size = sizeof(u32),
275 .word_count = RF_SIZE / sizeof(u32),
276 },
277};
278EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
279#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
280
281int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
282{
283 u32 reg;
284
285 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
286 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
287}
288EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
289
290#ifdef CONFIG_RT2X00_LIB_LEDS
291static void rt2800_brightness_set(struct led_classdev *led_cdev,
292 enum led_brightness brightness)
293{
294 struct rt2x00_led *led =
295 container_of(led_cdev, struct rt2x00_led, led_dev);
296 unsigned int enabled = brightness != LED_OFF;
297 unsigned int bg_mode =
298 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299 unsigned int polarity =
300 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
301 EEPROM_FREQ_LED_POLARITY);
302 unsigned int ledmode =
303 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
304 EEPROM_FREQ_LED_MODE);
305
306 if (led->type == LED_TYPE_RADIO) {
307 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
308 enabled ? 0x20 : 0);
309 } else if (led->type == LED_TYPE_ASSOC) {
310 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
311 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
312 } else if (led->type == LED_TYPE_QUALITY) {
313 /*
314 * The brightness is divided into 6 levels (0 - 5),
315 * The specs tell us the following levels:
316 * 0, 1 ,3, 7, 15, 31
317 * to determine the level in a simple way we can simply
318 * work with bitshifting:
319 * (1 << level) - 1
320 */
321 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
322 (1 << brightness / (LED_FULL / 6)) - 1,
323 polarity);
324 }
325}
326
327static int rt2800_blink_set(struct led_classdev *led_cdev,
328 unsigned long *delay_on, unsigned long *delay_off)
329{
330 struct rt2x00_led *led =
331 container_of(led_cdev, struct rt2x00_led, led_dev);
332 u32 reg;
333
334 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
335 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
336 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
337 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
338 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
339 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
340 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
341 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
342 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
343
344 return 0;
345}
346
347void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
348 struct rt2x00_led *led, enum led_type type)
349{
350 led->rt2x00dev = rt2x00dev;
351 led->type = type;
352 led->led_dev.brightness_set = rt2800_brightness_set;
353 led->led_dev.blink_set = rt2800_blink_set;
354 led->flags = LED_INITIALIZED;
355}
356EXPORT_SYMBOL_GPL(rt2800_init_led);
357#endif /* CONFIG_RT2X00_LIB_LEDS */
358
359/*
360 * Configuration handlers.
361 */
362static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
363 struct rt2x00lib_crypto *crypto,
364 struct ieee80211_key_conf *key)
365{
366 struct mac_wcid_entry wcid_entry;
367 struct mac_iveiv_entry iveiv_entry;
368 u32 offset;
369 u32 reg;
370
371 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
372
373 rt2800_register_read(rt2x00dev, offset, &reg);
374 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
375 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
376 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
377 (crypto->cmd == SET_KEY) * crypto->cipher);
378 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
379 (crypto->cmd == SET_KEY) * crypto->bssidx);
380 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
381 rt2800_register_write(rt2x00dev, offset, reg);
382
383 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
384
385 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
386 if ((crypto->cipher == CIPHER_TKIP) ||
387 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
388 (crypto->cipher == CIPHER_AES))
389 iveiv_entry.iv[3] |= 0x20;
390 iveiv_entry.iv[3] |= key->keyidx << 6;
391 rt2800_register_multiwrite(rt2x00dev, offset,
392 &iveiv_entry, sizeof(iveiv_entry));
393
394 offset = MAC_WCID_ENTRY(key->hw_key_idx);
395
396 memset(&wcid_entry, 0, sizeof(wcid_entry));
397 if (crypto->cmd == SET_KEY)
398 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
399 rt2800_register_multiwrite(rt2x00dev, offset,
400 &wcid_entry, sizeof(wcid_entry));
401}
402
403int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
404 struct rt2x00lib_crypto *crypto,
405 struct ieee80211_key_conf *key)
406{
407 struct hw_key_entry key_entry;
408 struct rt2x00_field32 field;
409 u32 offset;
410 u32 reg;
411
412 if (crypto->cmd == SET_KEY) {
413 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
414
415 memcpy(key_entry.key, crypto->key,
416 sizeof(key_entry.key));
417 memcpy(key_entry.tx_mic, crypto->tx_mic,
418 sizeof(key_entry.tx_mic));
419 memcpy(key_entry.rx_mic, crypto->rx_mic,
420 sizeof(key_entry.rx_mic));
421
422 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
423 rt2800_register_multiwrite(rt2x00dev, offset,
424 &key_entry, sizeof(key_entry));
425 }
426
427 /*
428 * The cipher types are stored over multiple registers
429 * starting with SHARED_KEY_MODE_BASE each word will have
430 * 32 bits and contains the cipher types for 2 bssidx each.
431 * Using the correct defines correctly will cause overhead,
432 * so just calculate the correct offset.
433 */
434 field.bit_offset = 4 * (key->hw_key_idx % 8);
435 field.bit_mask = 0x7 << field.bit_offset;
436
437 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
438
439 rt2800_register_read(rt2x00dev, offset, &reg);
440 rt2x00_set_field32(&reg, field,
441 (crypto->cmd == SET_KEY) * crypto->cipher);
442 rt2800_register_write(rt2x00dev, offset, reg);
443
444 /*
445 * Update WCID information
446 */
447 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
448
449 return 0;
450}
451EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
452
453int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
454 struct rt2x00lib_crypto *crypto,
455 struct ieee80211_key_conf *key)
456{
457 struct hw_key_entry key_entry;
458 u32 offset;
459
460 if (crypto->cmd == SET_KEY) {
461 /*
462 * 1 pairwise key is possible per AID, this means that the AID
463 * equals our hw_key_idx. Make sure the WCID starts _after_ the
464 * last possible shared key entry.
465 */
466 if (crypto->aid > (256 - 32))
467 return -ENOSPC;
468
469 key->hw_key_idx = 32 + crypto->aid;
470
471 memcpy(key_entry.key, crypto->key,
472 sizeof(key_entry.key));
473 memcpy(key_entry.tx_mic, crypto->tx_mic,
474 sizeof(key_entry.tx_mic));
475 memcpy(key_entry.rx_mic, crypto->rx_mic,
476 sizeof(key_entry.rx_mic));
477
478 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
479 rt2800_register_multiwrite(rt2x00dev, offset,
480 &key_entry, sizeof(key_entry));
481 }
482
483 /*
484 * Update WCID information
485 */
486 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
487
488 return 0;
489}
490EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
491
492void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
493 const unsigned int filter_flags)
494{
495 u32 reg;
496
497 /*
498 * Start configuration steps.
499 * Note that the version error will always be dropped
500 * and broadcast frames will always be accepted since
501 * there is no filter for it at this time.
502 */
503 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
505 !(filter_flags & FIF_FCSFAIL));
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
507 !(filter_flags & FIF_PLCPFAIL));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
509 !(filter_flags & FIF_PROMISC_IN_BSS));
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
511 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
513 !(filter_flags & FIF_ALLMULTI));
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
515 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
521 !(filter_flags & FIF_CONTROL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
523 !(filter_flags & FIF_CONTROL));
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
527 !(filter_flags & FIF_PSPOLL));
528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
529 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
530 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
531 !(filter_flags & FIF_CONTROL));
532 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
533}
534EXPORT_SYMBOL_GPL(rt2800_config_filter);
535
536void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
537 struct rt2x00intf_conf *conf, const unsigned int flags)
538{
539 unsigned int beacon_base;
540 u32 reg;
541
542 if (flags & CONFIG_UPDATE_TYPE) {
543 /*
544 * Clear current synchronisation setup.
545 * For the Beacon base registers we only need to clear
546 * the first byte since that byte contains the VALID and OWNER
547 * bits which (when set to 0) will invalidate the entire beacon.
548 */
549 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
550 rt2800_register_write(rt2x00dev, beacon_base, 0);
551
552 /*
553 * Enable synchronisation.
554 */
555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
558 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
559 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
560 }
561
562 if (flags & CONFIG_UPDATE_MAC) {
563 reg = le32_to_cpu(conf->mac[1]);
564 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
565 conf->mac[1] = cpu_to_le32(reg);
566
567 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
568 conf->mac, sizeof(conf->mac));
569 }
570
571 if (flags & CONFIG_UPDATE_BSSID) {
572 reg = le32_to_cpu(conf->bssid[1]);
573 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
574 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
575 conf->bssid[1] = cpu_to_le32(reg);
576
577 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
578 conf->bssid, sizeof(conf->bssid));
579 }
580}
581EXPORT_SYMBOL_GPL(rt2800_config_intf);
582
583void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
584{
585 u32 reg;
586
587 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
588 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
589 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
590
591 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
592 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
593 !!erp->short_preamble);
594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
595 !!erp->short_preamble);
596 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
597
598 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
599 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
600 erp->cts_protection ? 2 : 0);
601 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
602
603 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
604 erp->basic_rates);
605 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
606
607 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
608 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
609 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
610 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
611
612 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
613 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
614 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
615 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
616 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
617 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
618 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
619
620 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
621 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
622 erp->beacon_int * 16);
623 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624}
625EXPORT_SYMBOL_GPL(rt2800_config_erp);
626
627void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
628{
629 u8 r1;
630 u8 r3;
631
632 rt2800_bbp_read(rt2x00dev, 1, &r1);
633 rt2800_bbp_read(rt2x00dev, 3, &r3);
634
635 /*
636 * Configure the TX antenna.
637 */
638 switch ((int)ant->tx) {
639 case 1:
640 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
641 if (rt2x00_intf_is_pci(rt2x00dev))
642 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
643 break;
644 case 2:
645 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
646 break;
647 case 3:
648 /* Do nothing */
649 break;
650 }
651
652 /*
653 * Configure the RX antenna.
654 */
655 switch ((int)ant->rx) {
656 case 1:
657 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
658 break;
659 case 2:
660 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
661 break;
662 case 3:
663 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
664 break;
665 }
666
667 rt2800_bbp_write(rt2x00dev, 3, r3);
668 rt2800_bbp_write(rt2x00dev, 1, r1);
669}
670EXPORT_SYMBOL_GPL(rt2800_config_ant);
671
672static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
673 struct rt2x00lib_conf *libconf)
674{
675 u16 eeprom;
676 short lna_gain;
677
678 if (libconf->rf.channel <= 14) {
679 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
680 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
681 } else if (libconf->rf.channel <= 64) {
682 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
683 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
684 } else if (libconf->rf.channel <= 128) {
685 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
686 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
687 } else {
688 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
689 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
690 }
691
692 rt2x00dev->lna_gain = lna_gain;
693}
694
695static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
696 struct ieee80211_conf *conf,
697 struct rf_channel *rf,
698 struct channel_info *info)
699{
700 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
701
702 if (rt2x00dev->default_ant.tx == 1)
703 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
704
705 if (rt2x00dev->default_ant.rx == 1) {
706 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
707 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
708 } else if (rt2x00dev->default_ant.rx == 2)
709 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
710
711 if (rf->channel > 14) {
712 /*
713 * When TX power is below 0, we should increase it by 7 to
714 * make it a positive value (Minumum value is -7).
715 * However this means that values between 0 and 7 have
716 * double meaning, and we should set a 7DBm boost flag.
717 */
718 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
719 (info->tx_power1 >= 0));
720
721 if (info->tx_power1 < 0)
722 info->tx_power1 += 7;
723
724 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
725 TXPOWER_A_TO_DEV(info->tx_power1));
726
727 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
728 (info->tx_power2 >= 0));
729
730 if (info->tx_power2 < 0)
731 info->tx_power2 += 7;
732
733 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
734 TXPOWER_A_TO_DEV(info->tx_power2));
735 } else {
736 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
737 TXPOWER_G_TO_DEV(info->tx_power1));
738 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
739 TXPOWER_G_TO_DEV(info->tx_power2));
740 }
741
742 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
743
744 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
745 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
746 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
747 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
748
749 udelay(200);
750
751 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
752 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
753 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
754 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
755
756 udelay(200);
757
758 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
759 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
760 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
761 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
762}
763
764static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
765 struct ieee80211_conf *conf,
766 struct rf_channel *rf,
767 struct channel_info *info)
768{
769 u8 rfcsr;
770
771 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
772 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
773
774 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
775 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
776 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
777
778 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
779 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
780 TXPOWER_G_TO_DEV(info->tx_power1));
781 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
782
783 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
784 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
785 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
786
787 rt2800_rfcsr_write(rt2x00dev, 24,
788 rt2x00dev->calibration[conf_is_ht40(conf)]);
789
790 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
791 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
792 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
793}
794
795static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
796 struct ieee80211_conf *conf,
797 struct rf_channel *rf,
798 struct channel_info *info)
799{
800 u32 reg;
801 unsigned int tx_pin;
802 u8 bbp;
803
804 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
805 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
806 else
807 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
808
809 /*
810 * Change BBP settings
811 */
812 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
813 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
814 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
815 rt2800_bbp_write(rt2x00dev, 86, 0);
816
817 if (rf->channel <= 14) {
818 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
819 rt2800_bbp_write(rt2x00dev, 82, 0x62);
820 rt2800_bbp_write(rt2x00dev, 75, 0x46);
821 } else {
822 rt2800_bbp_write(rt2x00dev, 82, 0x84);
823 rt2800_bbp_write(rt2x00dev, 75, 0x50);
824 }
825 } else {
826 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
827
828 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
829 rt2800_bbp_write(rt2x00dev, 75, 0x46);
830 else
831 rt2800_bbp_write(rt2x00dev, 75, 0x50);
832 }
833
834 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
835 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
836 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
837 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
838 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
839
840 tx_pin = 0;
841
842 /* Turn on unused PA or LNA when not using 1T or 1R */
843 if (rt2x00dev->default_ant.tx != 1) {
844 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
845 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
846 }
847
848 /* Turn on unused PA or LNA when not using 1T or 1R */
849 if (rt2x00dev->default_ant.rx != 1) {
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
852 }
853
854 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
855 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
856 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
857 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
858 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
859 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
860
861 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
862
863 rt2800_bbp_read(rt2x00dev, 4, &bbp);
864 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
865 rt2800_bbp_write(rt2x00dev, 4, bbp);
866
867 rt2800_bbp_read(rt2x00dev, 3, &bbp);
868 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
869 rt2800_bbp_write(rt2x00dev, 3, bbp);
870
871 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
872 if (conf_is_ht40(conf)) {
873 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
874 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
875 rt2800_bbp_write(rt2x00dev, 73, 0x16);
876 } else {
877 rt2800_bbp_write(rt2x00dev, 69, 0x16);
878 rt2800_bbp_write(rt2x00dev, 70, 0x08);
879 rt2800_bbp_write(rt2x00dev, 73, 0x11);
880 }
881 }
882
883 msleep(1);
884}
885
886static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
887 const int txpower)
888{
889 u32 reg;
890 u32 value = TXPOWER_G_TO_DEV(txpower);
891 u8 r1;
892
893 rt2800_bbp_read(rt2x00dev, 1, &r1);
894 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
895 rt2800_bbp_write(rt2x00dev, 1, r1);
896
897 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
898 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
899 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
900 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
906 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
907
908 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
909 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
910 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
911 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
917 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
918
919 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
920 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
921 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
922 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
928 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
929
930 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
938 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
939 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
940
941 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
943 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
944 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
945 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
946 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
947}
948
949static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
950 struct rt2x00lib_conf *libconf)
951{
952 u32 reg;
953
954 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
955 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
956 libconf->conf->short_frame_max_tx_count);
957 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
958 libconf->conf->long_frame_max_tx_count);
959 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
960 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
961 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
962 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
963 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
964}
965
966static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
967 struct rt2x00lib_conf *libconf)
968{
969 enum dev_state state =
970 (libconf->conf->flags & IEEE80211_CONF_PS) ?
971 STATE_SLEEP : STATE_AWAKE;
972 u32 reg;
973
974 if (state == STATE_SLEEP) {
975 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
976
977 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
978 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
979 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
980 libconf->conf->listen_interval - 1);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
982 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
983
984 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
985 } else {
986 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
987
988 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
989 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
990 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
991 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
992 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
993 }
994}
995
996void rt2800_config(struct rt2x00_dev *rt2x00dev,
997 struct rt2x00lib_conf *libconf,
998 const unsigned int flags)
999{
1000 /* Always recalculate LNA gain before changing configuration */
1001 rt2800_config_lna_gain(rt2x00dev, libconf);
1002
1003 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1004 rt2800_config_channel(rt2x00dev, libconf->conf,
1005 &libconf->rf, &libconf->channel);
1006 if (flags & IEEE80211_CONF_CHANGE_POWER)
1007 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1008 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1009 rt2800_config_retry_limit(rt2x00dev, libconf);
1010 if (flags & IEEE80211_CONF_CHANGE_PS)
1011 rt2800_config_ps(rt2x00dev, libconf);
1012}
1013EXPORT_SYMBOL_GPL(rt2800_config);
1014
1015/*
1016 * Link tuning
1017 */
1018void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1019{
1020 u32 reg;
1021
1022 /*
1023 * Update FCS error count from register.
1024 */
1025 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1026 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1027}
1028EXPORT_SYMBOL_GPL(rt2800_link_stats);
1029
1030static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1031{
1032 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1033 if (rt2x00_intf_is_usb(rt2x00dev) &&
1034 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1035 return 0x1c + (2 * rt2x00dev->lna_gain);
1036 else
1037 return 0x2e + rt2x00dev->lna_gain;
1038 }
1039
1040 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1041 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1042 else
1043 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1044}
1045
1046static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1047 struct link_qual *qual, u8 vgc_level)
1048{
1049 if (qual->vgc_level != vgc_level) {
1050 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1051 qual->vgc_level = vgc_level;
1052 qual->vgc_level_reg = vgc_level;
1053 }
1054}
1055
1056void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1057{
1058 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1059}
1060EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1061
1062void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1063 const u32 count)
1064{
1065 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1066 return;
1067
1068 /*
1069 * When RSSI is better then -80 increase VGC level with 0x10
1070 */
1071 rt2800_set_vgc(rt2x00dev, qual,
1072 rt2800_get_default_vgc(rt2x00dev) +
1073 ((qual->rssi > -80) * 0x10));
1074}
1075EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1076
1077/*
1078 * Initialization functions.
1079 */
1080int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1081{
1082 u32 reg;
1083 unsigned int i;
1084
1085 if (rt2x00_intf_is_usb(rt2x00dev)) {
1086 /*
1087 * Wait untill BBP and RF are ready.
1088 */
1089 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1090 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1091 if (reg && reg != ~0)
1092 break;
1093 msleep(1);
1094 }
1095
1096 if (i == REGISTER_BUSY_COUNT) {
1097 ERROR(rt2x00dev, "Unstable hardware.\n");
1098 return -EBUSY;
1099 }
1100
1101 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1102 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1103 reg & ~0x00002000);
1104 } else if (rt2x00_intf_is_pci(rt2x00dev))
1105 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1106
1107 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1108 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1109 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1110 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1111
1112 if (rt2x00_intf_is_usb(rt2x00dev)) {
1113 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1114#ifdef CONFIG_RT2800USB
1115 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1116 USB_MODE_RESET, REGISTER_TIMEOUT);
1117#endif
1118 }
1119
1120 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1121
1122 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1123 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1124 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1125 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1126 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1127 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1128
1129 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1130 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1131 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1132 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1133 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1134 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1135
1136 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1137 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1138
1139 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1140
1141 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1142 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1143 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1144 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1145 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1146 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1147 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1148 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1149
1150 if (rt2x00_intf_is_usb(rt2x00dev) &&
1151 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1152 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1153 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1154 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1155 } else {
1156 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1157 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1158 }
1159
1160 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1161 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1162 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1163 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1164 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1165 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1166 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1167 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1168 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1169 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1170
1171 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1172 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1173 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1174 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1175
1176 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1177 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1178 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1179 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1180 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1181 else
1182 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1183 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1184 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1185 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1186
1187 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1188
1189 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1190 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1191 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1192 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1193 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1194 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1195 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1196
1197 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1198 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1199 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1200 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1201 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1202 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1203 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1204 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1205 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1206 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1207 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1208
1209 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1210 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1211 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1212 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1213 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1214 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1215 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1216 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1217 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1218 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1219 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1220
1221 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1222 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1223 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1224 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1225 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1226 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1227 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1228 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1229 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1230 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1231 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1232
1233 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1234 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1235 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1236 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1237 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1238 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1239 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1240 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1241 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1242 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1243 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1244
1245 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1246 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1247 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1248 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1249 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1250 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1251 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1252 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1253 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1254 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1255 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1256
1257 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1258 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1259 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1260 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1261 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1262 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1263 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1264 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1265 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1266 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1267 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1268
1269 if (rt2x00_intf_is_usb(rt2x00dev)) {
1270 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1271
1272 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1273 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1274 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1275 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1276 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1277 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1278 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1282 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1283 }
1284
1285 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1286 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1287
1288 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1289 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1290 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1291 IEEE80211_MAX_RTS_THRESHOLD);
1292 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1293 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1294
1295 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1296 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1297
1298 /*
1299 * ASIC will keep garbage value after boot, clear encryption keys.
1300 */
1301 for (i = 0; i < 4; i++)
1302 rt2800_register_write(rt2x00dev,
1303 SHARED_KEY_MODE_ENTRY(i), 0);
1304
1305 for (i = 0; i < 256; i++) {
1306 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1307 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1308 wcid, sizeof(wcid));
1309
1310 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1311 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1312 }
1313
1314 /*
1315 * Clear all beacons
1316 * For the Beacon base registers we only need to clear
1317 * the first byte since that byte contains the VALID and OWNER
1318 * bits which (when set to 0) will invalidate the entire beacon.
1319 */
1320 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1321 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1322 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1323 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1324 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1325 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1326 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1327 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1328
1329 if (rt2x00_intf_is_usb(rt2x00dev)) {
1330 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1331 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1332 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1333 }
1334
1335 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1336 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1337 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1338 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1339 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1340 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1341 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1342 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1343 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1344 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1345
1346 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1347 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1348 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1349 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1350 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1351 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1352 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1353 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1354 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1355 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1356
1357 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1358 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1359 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1360 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1361 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1362 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1363 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1364 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1365 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1366 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1367
1368 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1369 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1370 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1371 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1372 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1373 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1374
1375 /*
1376 * We must clear the error counters.
1377 * These registers are cleared on read,
1378 * so we may pass a useless variable to store the value.
1379 */
1380 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1381 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1382 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1383 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1384 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1385 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1386
1387 return 0;
1388}
1389EXPORT_SYMBOL_GPL(rt2800_init_registers);
1390
1391static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1392{
1393 unsigned int i;
1394 u32 reg;
1395
1396 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1397 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1398 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1399 return 0;
1400
1401 udelay(REGISTER_BUSY_DELAY);
1402 }
1403
1404 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1405 return -EACCES;
1406}
1407
1408static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1409{
1410 unsigned int i;
1411 u8 value;
1412
1413 /*
1414 * BBP was enabled after firmware was loaded,
1415 * but we need to reactivate it now.
1416 */
1417 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1418 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1419 msleep(1);
1420
1421 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1422 rt2800_bbp_read(rt2x00dev, 0, &value);
1423 if ((value != 0xff) && (value != 0x00))
1424 return 0;
1425 udelay(REGISTER_BUSY_DELAY);
1426 }
1427
1428 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1429 return -EACCES;
1430}
1431
1432int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1433{
1434 unsigned int i;
1435 u16 eeprom;
1436 u8 reg_id;
1437 u8 value;
1438
1439 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1440 rt2800_wait_bbp_ready(rt2x00dev)))
1441 return -EACCES;
1442
1443 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1444 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1445 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1446 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1447 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1448 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1449 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1450 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1451 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1452 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1453 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1454 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1455 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1456 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1457
1458 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1459 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1460 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1461 }
1462
1463 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1464 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1465
1466 if (rt2x00_intf_is_usb(rt2x00dev) &&
1467 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1468 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1469 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1470 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1471 }
1472
1473 if (rt2x00_intf_is_pci(rt2x00dev) &&
1474 rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1475 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1476 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1477 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1478 }
1479
1480 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1481 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1482
1483 if (eeprom != 0xffff && eeprom != 0x0000) {
1484 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1485 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1486 rt2800_bbp_write(rt2x00dev, reg_id, value);
1487 }
1488 }
1489
1490 return 0;
1491}
1492EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1493
1494static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1495 bool bw40, u8 rfcsr24, u8 filter_target)
1496{
1497 unsigned int i;
1498 u8 bbp;
1499 u8 rfcsr;
1500 u8 passband;
1501 u8 stopband;
1502 u8 overtuned = 0;
1503
1504 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1505
1506 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1507 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1508 rt2800_bbp_write(rt2x00dev, 4, bbp);
1509
1510 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1511 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1512 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1513
1514 /*
1515 * Set power & frequency of passband test tone
1516 */
1517 rt2800_bbp_write(rt2x00dev, 24, 0);
1518
1519 for (i = 0; i < 100; i++) {
1520 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1521 msleep(1);
1522
1523 rt2800_bbp_read(rt2x00dev, 55, &passband);
1524 if (passband)
1525 break;
1526 }
1527
1528 /*
1529 * Set power & frequency of stopband test tone
1530 */
1531 rt2800_bbp_write(rt2x00dev, 24, 0x06);
1532
1533 for (i = 0; i < 100; i++) {
1534 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1535 msleep(1);
1536
1537 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1538
1539 if ((passband - stopband) <= filter_target) {
1540 rfcsr24++;
1541 overtuned += ((passband - stopband) == filter_target);
1542 } else
1543 break;
1544
1545 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1546 }
1547
1548 rfcsr24 -= !!overtuned;
1549
1550 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1551 return rfcsr24;
1552}
1553
1554int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1555{
1556 u8 rfcsr;
1557 u8 bbp;
1558
1559 if (rt2x00_intf_is_usb(rt2x00dev) &&
1560 rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1561 return 0;
1562
1563 if (rt2x00_intf_is_pci(rt2x00dev)) {
1564 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1565 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1566 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1567 return 0;
1568 }
1569
1570 /*
1571 * Init RF calibration.
1572 */
1573 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1574 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1575 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1576 msleep(1);
1577 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1578 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1579
1580 if (rt2x00_intf_is_usb(rt2x00dev)) {
1581 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1582 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1583 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1584 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1585 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1586 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1587 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1588 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1589 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1590 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1591 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1592 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1593 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1594 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1595 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1596 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1597 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1598 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1599 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1600 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1601 } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1602 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1603 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1604 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1605 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1606 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1607 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1608 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1609 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1610 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1611 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1612 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1613 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1614 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1615 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1616 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1617 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1618 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1619 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1620 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1621 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1622 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1623 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1624 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1625 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1626 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1627 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1628 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1629 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1630 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1631 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1632 }
1633
1634 /*
1635 * Set RX Filter calibration for 20MHz and 40MHz
1636 */
1637 rt2x00dev->calibration[0] =
1638 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1639 rt2x00dev->calibration[1] =
1640 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1641
1642 /*
1643 * Set back to initial state
1644 */
1645 rt2800_bbp_write(rt2x00dev, 24, 0);
1646
1647 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1648 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1649 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1650
1651 /*
1652 * set BBP back to BW20
1653 */
1654 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1655 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1656 rt2800_bbp_write(rt2x00dev, 4, bbp);
1657
1658 return 0;
1659}
1660EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1661
1662/*
1663 * IEEE80211 stack callback functions.
1664 */
1665static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
1666 u32 *iv32, u16 *iv16)
1667{
1668 struct rt2x00_dev *rt2x00dev = hw->priv;
1669 struct mac_iveiv_entry iveiv_entry;
1670 u32 offset;
1671
1672 offset = MAC_IVEIV_ENTRY(hw_key_idx);
1673 rt2800_register_multiread(rt2x00dev, offset,
1674 &iveiv_entry, sizeof(iveiv_entry));
1675
1676 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
1677 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
1678}
1679
1680static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
1681{
1682 struct rt2x00_dev *rt2x00dev = hw->priv;
1683 u32 reg;
1684 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
1685
1686 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1687 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
1688 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1689
1690 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1691 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
1692 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1693
1694 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1695 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
1696 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1697
1698 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1699 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
1700 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1701
1702 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1703 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
1704 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1705
1706 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1707 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
1708 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1709
1710 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1711 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
1712 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1713
1714 return 0;
1715}
1716
1717static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
1718 const struct ieee80211_tx_queue_params *params)
1719{
1720 struct rt2x00_dev *rt2x00dev = hw->priv;
1721 struct data_queue *queue;
1722 struct rt2x00_field32 field;
1723 int retval;
1724 u32 reg;
1725 u32 offset;
1726
1727 /*
1728 * First pass the configuration through rt2x00lib, that will
1729 * update the queue settings and validate the input. After that
1730 * we are free to update the registers based on the value
1731 * in the queue parameter.
1732 */
1733 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
1734 if (retval)
1735 return retval;
1736
1737 /*
1738 * We only need to perform additional register initialization
1739 * for WMM queues/
1740 */
1741 if (queue_idx >= 4)
1742 return 0;
1743
1744 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1745
1746 /* Update WMM TXOP register */
1747 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
1748 field.bit_offset = (queue_idx & 1) * 16;
1749 field.bit_mask = 0xffff << field.bit_offset;
1750
1751 rt2800_register_read(rt2x00dev, offset, &reg);
1752 rt2x00_set_field32(&reg, field, queue->txop);
1753 rt2800_register_write(rt2x00dev, offset, reg);
1754
1755 /* Update WMM registers */
1756 field.bit_offset = queue_idx * 4;
1757 field.bit_mask = 0xf << field.bit_offset;
1758
1759 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
1760 rt2x00_set_field32(&reg, field, queue->aifs);
1761 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
1762
1763 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
1764 rt2x00_set_field32(&reg, field, queue->cw_min);
1765 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
1766
1767 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
1768 rt2x00_set_field32(&reg, field, queue->cw_max);
1769 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
1770
1771 /* Update EDCA registers */
1772 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
1773
1774 rt2800_register_read(rt2x00dev, offset, &reg);
1775 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
1776 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
1777 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
1778 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
1779 rt2800_register_write(rt2x00dev, offset, reg);
1780
1781 return 0;
1782}
1783
1784static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
1785{
1786 struct rt2x00_dev *rt2x00dev = hw->priv;
1787 u64 tsf;
1788 u32 reg;
1789
1790 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
1791 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
1792 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
1793 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
1794
1795 return tsf;
1796}
1797
1798const struct ieee80211_ops rt2800_mac80211_ops = {
1799 .tx = rt2x00mac_tx,
1800 .start = rt2x00mac_start,
1801 .stop = rt2x00mac_stop,
1802 .add_interface = rt2x00mac_add_interface,
1803 .remove_interface = rt2x00mac_remove_interface,
1804 .config = rt2x00mac_config,
1805 .configure_filter = rt2x00mac_configure_filter,
1806 .set_tim = rt2x00mac_set_tim,
1807 .set_key = rt2x00mac_set_key,
1808 .get_stats = rt2x00mac_get_stats,
1809 .get_tkip_seq = rt2800_get_tkip_seq,
1810 .set_rts_threshold = rt2800_set_rts_threshold,
1811 .bss_info_changed = rt2x00mac_bss_info_changed,
1812 .conf_tx = rt2800_conf_tx,
1813 .get_tx_stats = rt2x00mac_get_tx_stats,
1814 .get_tsf = rt2800_get_tsf,
1815 .rfkill_poll = rt2x00mac_rfkill_poll,
1816};
1817EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
new file mode 100644
index 000000000000..5eea8fcba6cc
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -0,0 +1,134 @@
1/*
2 Copyright (C) 2009 Bartlomiej Zolnierkiewicz
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the
16 Free Software Foundation, Inc.,
17 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20#ifndef RT2800LIB_H
21#define RT2800LIB_H
22
23struct rt2800_ops {
24 void (*register_read)(struct rt2x00_dev *rt2x00dev,
25 const unsigned int offset, u32 *value);
26 void (*register_write)(struct rt2x00_dev *rt2x00dev,
27 const unsigned int offset, u32 value);
28 void (*register_write_lock)(struct rt2x00_dev *rt2x00dev,
29 const unsigned int offset, u32 value);
30
31 void (*register_multiread)(struct rt2x00_dev *rt2x00dev,
32 const unsigned int offset,
33 void *value, const u32 length);
34 void (*register_multiwrite)(struct rt2x00_dev *rt2x00dev,
35 const unsigned int offset,
36 const void *value, const u32 length);
37
38 int (*regbusy_read)(struct rt2x00_dev *rt2x00dev,
39 const unsigned int offset,
40 const struct rt2x00_field32 field, u32 *reg);
41};
42
43static inline void rt2800_register_read(struct rt2x00_dev *rt2x00dev,
44 const unsigned int offset,
45 u32 *value)
46{
47 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
48
49 rt2800ops->register_read(rt2x00dev, offset, value);
50}
51
52static inline void rt2800_register_write(struct rt2x00_dev *rt2x00dev,
53 const unsigned int offset,
54 u32 value)
55{
56 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
57
58 rt2800ops->register_write(rt2x00dev, offset, value);
59}
60
61static inline void rt2800_register_write_lock(struct rt2x00_dev *rt2x00dev,
62 const unsigned int offset,
63 u32 value)
64{
65 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
66
67 rt2800ops->register_write_lock(rt2x00dev, offset, value);
68}
69
70static inline void rt2800_register_multiread(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset,
72 void *value, const u32 length)
73{
74 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
75
76 rt2800ops->register_multiread(rt2x00dev, offset, value, length);
77}
78
79static inline void rt2800_register_multiwrite(struct rt2x00_dev *rt2x00dev,
80 const unsigned int offset,
81 const void *value,
82 const u32 length)
83{
84 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
85
86 rt2800ops->register_multiwrite(rt2x00dev, offset, value, length);
87}
88
89static inline int rt2800_regbusy_read(struct rt2x00_dev *rt2x00dev,
90 const unsigned int offset,
91 const struct rt2x00_field32 field,
92 u32 *reg)
93{
94 const struct rt2800_ops *rt2800ops = rt2x00dev->priv;
95
96 return rt2800ops->regbusy_read(rt2x00dev, offset, field, reg);
97}
98
99void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
100 const u8 command, const u8 token,
101 const u8 arg0, const u8 arg1);
102
103extern const struct rt2x00debug rt2800_rt2x00debug;
104
105int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev);
106void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
107 struct rt2x00_led *led, enum led_type type);
108int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
109 struct rt2x00lib_crypto *crypto,
110 struct ieee80211_key_conf *key);
111int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
112 struct rt2x00lib_crypto *crypto,
113 struct ieee80211_key_conf *key);
114void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
115 const unsigned int filter_flags);
116void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
117 struct rt2x00intf_conf *conf, const unsigned int flags);
118void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp);
119void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant);
120void rt2800_config(struct rt2x00_dev *rt2x00dev,
121 struct rt2x00lib_conf *libconf,
122 const unsigned int flags);
123void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
124void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual);
125void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
126 const u32 count);
127
128int rt2800_init_registers(struct rt2x00_dev *rt2x00dev);
129int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev);
130int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev);
131
132extern const struct ieee80211_ops rt2800_mac80211_ops;
133
134#endif /* RT2800LIB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index be81788b80c7..3c5b875cdee8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -37,6 +37,8 @@
37#include "rt2x00.h" 37#include "rt2x00.h"
38#include "rt2x00pci.h" 38#include "rt2x00pci.h"
39#include "rt2x00soc.h" 39#include "rt2x00soc.h"
40#include "rt2800lib.h"
41#include "rt2800.h"
40#include "rt2800pci.h" 42#include "rt2800pci.h"
41 43
42#ifdef CONFIG_RT2800PCI_PCI_MODULE 44#ifdef CONFIG_RT2800PCI_PCI_MODULE
@@ -54,205 +56,13 @@ static int modparam_nohwcrypt = 1;
54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56 58
57/*
58 * Register access.
59 * BBP and RF register require indirect register access,
60 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
61 * These indirect registers work with busy bits,
62 * and we will try maximal REGISTER_BUSY_COUNT times to access
63 * the register while taking a REGISTER_BUSY_DELAY us delay
64 * between each attampt. When the busy bit is still set at that time,
65 * the access attempt is considered to have failed,
66 * and we will print an error.
67 */
68#define WAIT_FOR_BBP(__dev, __reg) \
69 rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70#define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72#define WAIT_FOR_RF(__dev, __reg) \
73 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74#define WAIT_FOR_MCU(__dev, __reg) \
75 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
77
78static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
79 const unsigned int word, const u8 value)
80{
81 u32 reg;
82
83 mutex_lock(&rt2x00dev->csr_mutex);
84
85 /*
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
88 */
89 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
90 reg = 0;
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
92 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
94 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
95 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
96
97 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
98 }
99
100 mutex_unlock(&rt2x00dev->csr_mutex);
101}
102
103static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
104 const unsigned int word, u8 *value)
105{
106 u32 reg;
107
108 mutex_lock(&rt2x00dev->csr_mutex);
109
110 /*
111 * Wait until the BBP becomes available, afterwards we
112 * can safely write the read request into the register.
113 * After the data has been written, we wait until hardware
114 * returns the correct value, if at any time the register
115 * doesn't become available in time, reg will be 0xffffffff
116 * which means we return 0xff to the caller.
117 */
118 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
119 reg = 0;
120 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
121 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
123 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
124
125 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
126
127 WAIT_FOR_BBP(rt2x00dev, &reg);
128 }
129
130 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
131
132 mutex_unlock(&rt2x00dev->csr_mutex);
133}
134
135static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u8 value)
137{
138 u32 reg;
139
140 mutex_lock(&rt2x00dev->csr_mutex);
141
142 /*
143 * Wait until the RFCSR becomes available, afterwards we
144 * can safely write the new data into the register.
145 */
146 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
147 reg = 0;
148 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
149 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
150 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
151 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
152
153 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
154 }
155
156 mutex_unlock(&rt2x00dev->csr_mutex);
157}
158
159static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
160 const unsigned int word, u8 *value)
161{
162 u32 reg;
163
164 mutex_lock(&rt2x00dev->csr_mutex);
165
166 /*
167 * Wait until the RFCSR becomes available, afterwards we
168 * can safely write the read request into the register.
169 * After the data has been written, we wait until hardware
170 * returns the correct value, if at any time the register
171 * doesn't become available in time, reg will be 0xffffffff
172 * which means we return 0xff to the caller.
173 */
174 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
175 reg = 0;
176 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
178 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
179
180 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
181
182 WAIT_FOR_RFCSR(rt2x00dev, &reg);
183 }
184
185 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
186
187 mutex_unlock(&rt2x00dev->csr_mutex);
188}
189
190static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
191 const unsigned int word, const u32 value)
192{
193 u32 reg;
194
195 mutex_lock(&rt2x00dev->csr_mutex);
196
197 /*
198 * Wait until the RF becomes available, afterwards we
199 * can safely write the new data into the register.
200 */
201 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
202 reg = 0;
203 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
204 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
206 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
207
208 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
209 rt2x00_rf_write(rt2x00dev, word, value);
210 }
211
212 mutex_unlock(&rt2x00dev->csr_mutex);
213}
214
215static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
216 const u8 command, const u8 token,
217 const u8 arg0, const u8 arg1)
218{
219 u32 reg;
220
221 /*
222 * RT2880 and RT3052 don't support MCU requests.
223 */
224 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
225 rt2x00_rt(&rt2x00dev->chip, RT3052))
226 return;
227
228 mutex_lock(&rt2x00dev->csr_mutex);
229
230 /*
231 * Wait until the MCU becomes available, afterwards we
232 * can safely write the new data into the register.
233 */
234 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
235 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
237 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
239 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
240
241 reg = 0;
242 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
243 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
244 }
245
246 mutex_unlock(&rt2x00dev->csr_mutex);
247}
248
249static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) 59static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
250{ 60{
251 unsigned int i; 61 unsigned int i;
252 u32 reg; 62 u32 reg;
253 63
254 for (i = 0; i < 200; i++) { 64 for (i = 0; i < 200; i++) {
255 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
256 66
257 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
258 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -266,8 +76,8 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
266 if (i == 200) 76 if (i == 200)
267 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
268 78
269 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
270 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
271} 81}
272 82
273#ifdef CONFIG_RT2800PCI_WISOC 83#ifdef CONFIG_RT2800PCI_WISOC
@@ -289,7 +99,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
289 struct rt2x00_dev *rt2x00dev = eeprom->data; 99 struct rt2x00_dev *rt2x00dev = eeprom->data;
290 u32 reg; 100 u32 reg;
291 101
292 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 102 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
293 103
294 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
295 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -311,7 +121,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
311 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 121 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
312 !!eeprom->reg_chip_select); 122 !!eeprom->reg_chip_select);
313 123
314 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
315} 125}
316 126
317static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 127static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -319,7 +129,7 @@ static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
319 struct eeprom_93cx6 eeprom; 129 struct eeprom_93cx6 eeprom;
320 u32 reg; 130 u32 reg;
321 131
322 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 132 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
323 133
324 eeprom.data = rt2x00dev; 134 eeprom.data = rt2x00dev;
325 eeprom.register_read = rt2800pci_eepromregister_read; 135 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -340,23 +150,23 @@ static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
340{ 150{
341 u32 reg; 151 u32 reg;
342 152
343 rt2x00pci_register_read(rt2x00dev, EFUSE_CTRL, &reg); 153 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
344 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 154 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
345 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 155 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
346 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 156 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
347 rt2x00pci_register_write(rt2x00dev, EFUSE_CTRL, reg); 157 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
348 158
349 /* Wait until the EEPROM has been loaded */ 159 /* Wait until the EEPROM has been loaded */
350 rt2x00pci_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 160 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
351 161
352 /* Apparently the data is read from end to start */ 162 /* Apparently the data is read from end to start */
353 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA3, 163 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
354 (u32 *)&rt2x00dev->eeprom[i]); 164 (u32 *)&rt2x00dev->eeprom[i]);
355 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA2, 165 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
356 (u32 *)&rt2x00dev->eeprom[i + 2]); 166 (u32 *)&rt2x00dev->eeprom[i + 2]);
357 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA1, 167 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
358 (u32 *)&rt2x00dev->eeprom[i + 4]); 168 (u32 *)&rt2x00dev->eeprom[i + 4]);
359 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA0, 169 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
360 (u32 *)&rt2x00dev->eeprom[i + 6]); 170 (u32 *)&rt2x00dev->eeprom[i + 6]);
361} 171}
362 172
@@ -377,829 +187,6 @@ static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
377} 187}
378#endif /* CONFIG_RT2800PCI_PCI */ 188#endif /* CONFIG_RT2800PCI_PCI */
379 189
380#ifdef CONFIG_RT2X00_LIB_DEBUGFS
381static const struct rt2x00debug rt2800pci_rt2x00debug = {
382 .owner = THIS_MODULE,
383 .csr = {
384 .read = rt2x00pci_register_read,
385 .write = rt2x00pci_register_write,
386 .flags = RT2X00DEBUGFS_OFFSET,
387 .word_base = CSR_REG_BASE,
388 .word_size = sizeof(u32),
389 .word_count = CSR_REG_SIZE / sizeof(u32),
390 },
391 .eeprom = {
392 .read = rt2x00_eeprom_read,
393 .write = rt2x00_eeprom_write,
394 .word_base = EEPROM_BASE,
395 .word_size = sizeof(u16),
396 .word_count = EEPROM_SIZE / sizeof(u16),
397 },
398 .bbp = {
399 .read = rt2800pci_bbp_read,
400 .write = rt2800pci_bbp_write,
401 .word_base = BBP_BASE,
402 .word_size = sizeof(u8),
403 .word_count = BBP_SIZE / sizeof(u8),
404 },
405 .rf = {
406 .read = rt2x00_rf_read,
407 .write = rt2800pci_rf_write,
408 .word_base = RF_BASE,
409 .word_size = sizeof(u32),
410 .word_count = RF_SIZE / sizeof(u32),
411 },
412};
413#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
414
415static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
416{
417 u32 reg;
418
419 rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
420 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
421}
422
423#ifdef CONFIG_RT2X00_LIB_LEDS
424static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
425 enum led_brightness brightness)
426{
427 struct rt2x00_led *led =
428 container_of(led_cdev, struct rt2x00_led, led_dev);
429 unsigned int enabled = brightness != LED_OFF;
430 unsigned int bg_mode =
431 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
432 unsigned int polarity =
433 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
434 EEPROM_FREQ_LED_POLARITY);
435 unsigned int ledmode =
436 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
437 EEPROM_FREQ_LED_MODE);
438
439 if (led->type == LED_TYPE_RADIO) {
440 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
441 enabled ? 0x20 : 0);
442 } else if (led->type == LED_TYPE_ASSOC) {
443 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
444 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
445 } else if (led->type == LED_TYPE_QUALITY) {
446 /*
447 * The brightness is divided into 6 levels (0 - 5),
448 * The specs tell us the following levels:
449 * 0, 1 ,3, 7, 15, 31
450 * to determine the level in a simple way we can simply
451 * work with bitshifting:
452 * (1 << level) - 1
453 */
454 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
455 (1 << brightness / (LED_FULL / 6)) - 1,
456 polarity);
457 }
458}
459
460static int rt2800pci_blink_set(struct led_classdev *led_cdev,
461 unsigned long *delay_on,
462 unsigned long *delay_off)
463{
464 struct rt2x00_led *led =
465 container_of(led_cdev, struct rt2x00_led, led_dev);
466 u32 reg;
467
468 rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
469 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
470 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
471 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
472 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
473 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
474 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
475 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
476 rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
477
478 return 0;
479}
480
481static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
482 struct rt2x00_led *led,
483 enum led_type type)
484{
485 led->rt2x00dev = rt2x00dev;
486 led->type = type;
487 led->led_dev.brightness_set = rt2800pci_brightness_set;
488 led->led_dev.blink_set = rt2800pci_blink_set;
489 led->flags = LED_INITIALIZED;
490}
491#endif /* CONFIG_RT2X00_LIB_LEDS */
492
493/*
494 * Configuration handlers.
495 */
496static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
497 struct rt2x00lib_crypto *crypto,
498 struct ieee80211_key_conf *key)
499{
500 struct mac_wcid_entry wcid_entry;
501 struct mac_iveiv_entry iveiv_entry;
502 u32 offset;
503 u32 reg;
504
505 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
506
507 rt2x00pci_register_read(rt2x00dev, offset, &reg);
508 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
509 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
510 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
511 (crypto->cmd == SET_KEY) * crypto->cipher);
512 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
513 (crypto->cmd == SET_KEY) * crypto->bssidx);
514 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
515 rt2x00pci_register_write(rt2x00dev, offset, reg);
516
517 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
518
519 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
520 if ((crypto->cipher == CIPHER_TKIP) ||
521 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
522 (crypto->cipher == CIPHER_AES))
523 iveiv_entry.iv[3] |= 0x20;
524 iveiv_entry.iv[3] |= key->keyidx << 6;
525 rt2x00pci_register_multiwrite(rt2x00dev, offset,
526 &iveiv_entry, sizeof(iveiv_entry));
527
528 offset = MAC_WCID_ENTRY(key->hw_key_idx);
529
530 memset(&wcid_entry, 0, sizeof(wcid_entry));
531 if (crypto->cmd == SET_KEY)
532 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
533 rt2x00pci_register_multiwrite(rt2x00dev, offset,
534 &wcid_entry, sizeof(wcid_entry));
535}
536
537static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
538 struct rt2x00lib_crypto *crypto,
539 struct ieee80211_key_conf *key)
540{
541 struct hw_key_entry key_entry;
542 struct rt2x00_field32 field;
543 u32 offset;
544 u32 reg;
545
546 if (crypto->cmd == SET_KEY) {
547 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
548
549 memcpy(key_entry.key, crypto->key,
550 sizeof(key_entry.key));
551 memcpy(key_entry.tx_mic, crypto->tx_mic,
552 sizeof(key_entry.tx_mic));
553 memcpy(key_entry.rx_mic, crypto->rx_mic,
554 sizeof(key_entry.rx_mic));
555
556 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
557 rt2x00pci_register_multiwrite(rt2x00dev, offset,
558 &key_entry, sizeof(key_entry));
559 }
560
561 /*
562 * The cipher types are stored over multiple registers
563 * starting with SHARED_KEY_MODE_BASE each word will have
564 * 32 bits and contains the cipher types for 2 bssidx each.
565 * Using the correct defines correctly will cause overhead,
566 * so just calculate the correct offset.
567 */
568 field.bit_offset = 4 * (key->hw_key_idx % 8);
569 field.bit_mask = 0x7 << field.bit_offset;
570
571 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
572
573 rt2x00pci_register_read(rt2x00dev, offset, &reg);
574 rt2x00_set_field32(&reg, field,
575 (crypto->cmd == SET_KEY) * crypto->cipher);
576 rt2x00pci_register_write(rt2x00dev, offset, reg);
577
578 /*
579 * Update WCID information
580 */
581 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
582
583 return 0;
584}
585
586static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_crypto *crypto,
588 struct ieee80211_key_conf *key)
589{
590 struct hw_key_entry key_entry;
591 u32 offset;
592
593 if (crypto->cmd == SET_KEY) {
594 /*
595 * 1 pairwise key is possible per AID, this means that the AID
596 * equals our hw_key_idx. Make sure the WCID starts _after_ the
597 * last possible shared key entry.
598 */
599 if (crypto->aid > (256 - 32))
600 return -ENOSPC;
601
602 key->hw_key_idx = 32 + crypto->aid;
603
604
605 memcpy(key_entry.key, crypto->key,
606 sizeof(key_entry.key));
607 memcpy(key_entry.tx_mic, crypto->tx_mic,
608 sizeof(key_entry.tx_mic));
609 memcpy(key_entry.rx_mic, crypto->rx_mic,
610 sizeof(key_entry.rx_mic));
611
612 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
613 rt2x00pci_register_multiwrite(rt2x00dev, offset,
614 &key_entry, sizeof(key_entry));
615 }
616
617 /*
618 * Update WCID information
619 */
620 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
621
622 return 0;
623}
624
625static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
626 const unsigned int filter_flags)
627{
628 u32 reg;
629
630 /*
631 * Start configuration steps.
632 * Note that the version error will always be dropped
633 * and broadcast frames will always be accepted since
634 * there is no filter for it at this time.
635 */
636 rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
637 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
638 !(filter_flags & FIF_FCSFAIL));
639 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
640 !(filter_flags & FIF_PLCPFAIL));
641 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
642 !(filter_flags & FIF_PROMISC_IN_BSS));
643 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
644 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
645 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
646 !(filter_flags & FIF_ALLMULTI));
647 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
648 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
649 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
650 !(filter_flags & FIF_CONTROL));
651 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
652 !(filter_flags & FIF_CONTROL));
653 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
654 !(filter_flags & FIF_CONTROL));
655 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
656 !(filter_flags & FIF_CONTROL));
657 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
658 !(filter_flags & FIF_CONTROL));
659 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
660 !(filter_flags & FIF_PSPOLL));
661 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
663 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
664 !(filter_flags & FIF_CONTROL));
665 rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
666}
667
668static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
669 struct rt2x00_intf *intf,
670 struct rt2x00intf_conf *conf,
671 const unsigned int flags)
672{
673 unsigned int beacon_base;
674 u32 reg;
675
676 if (flags & CONFIG_UPDATE_TYPE) {
677 /*
678 * Clear current synchronisation setup.
679 * For the Beacon base registers we only need to clear
680 * the first byte since that byte contains the VALID and OWNER
681 * bits which (when set to 0) will invalidate the entire beacon.
682 */
683 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
684 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
685
686 /*
687 * Enable synchronisation.
688 */
689 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
690 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
691 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
692 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
693 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
694 }
695
696 if (flags & CONFIG_UPDATE_MAC) {
697 reg = le32_to_cpu(conf->mac[1]);
698 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
699 conf->mac[1] = cpu_to_le32(reg);
700
701 rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
702 conf->mac, sizeof(conf->mac));
703 }
704
705 if (flags & CONFIG_UPDATE_BSSID) {
706 reg = le32_to_cpu(conf->bssid[1]);
707 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
708 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
709 conf->bssid[1] = cpu_to_le32(reg);
710
711 rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
712 conf->bssid, sizeof(conf->bssid));
713 }
714}
715
716static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
717 struct rt2x00lib_erp *erp)
718{
719 u32 reg;
720
721 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
722 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
723 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
724
725 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
726 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
727 !!erp->short_preamble);
728 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
729 !!erp->short_preamble);
730 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
731
732 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
733 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
734 erp->cts_protection ? 2 : 0);
735 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
736
737 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
738 erp->basic_rates);
739 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
740
741 rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
742 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
743 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
744 rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
745
746 rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
747 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
748 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
749 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
750 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
751 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
752 rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
753
754 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
756 erp->beacon_int * 16);
757 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
758}
759
760static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
761 struct antenna_setup *ant)
762{
763 u8 r1;
764 u8 r3;
765
766 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
767 rt2800pci_bbp_read(rt2x00dev, 3, &r3);
768
769 /*
770 * Configure the TX antenna.
771 */
772 switch ((int)ant->tx) {
773 case 1:
774 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
775 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
776 break;
777 case 2:
778 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
779 break;
780 case 3:
781 /* Do nothing */
782 break;
783 }
784
785 /*
786 * Configure the RX antenna.
787 */
788 switch ((int)ant->rx) {
789 case 1:
790 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
791 break;
792 case 2:
793 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
794 break;
795 case 3:
796 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
797 break;
798 }
799
800 rt2800pci_bbp_write(rt2x00dev, 3, r3);
801 rt2800pci_bbp_write(rt2x00dev, 1, r1);
802}
803
804static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
805 struct rt2x00lib_conf *libconf)
806{
807 u16 eeprom;
808 short lna_gain;
809
810 if (libconf->rf.channel <= 14) {
811 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
812 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
813 } else if (libconf->rf.channel <= 64) {
814 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
815 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
816 } else if (libconf->rf.channel <= 128) {
817 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
818 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
819 } else {
820 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
821 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
822 }
823
824 rt2x00dev->lna_gain = lna_gain;
825}
826
827static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
828 struct ieee80211_conf *conf,
829 struct rf_channel *rf,
830 struct channel_info *info)
831{
832 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
833
834 if (rt2x00dev->default_ant.tx == 1)
835 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
836
837 if (rt2x00dev->default_ant.rx == 1) {
838 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
839 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
840 } else if (rt2x00dev->default_ant.rx == 2)
841 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
842
843 if (rf->channel > 14) {
844 /*
845 * When TX power is below 0, we should increase it by 7 to
846 * make it a positive value (Minumum value is -7).
847 * However this means that values between 0 and 7 have
848 * double meaning, and we should set a 7DBm boost flag.
849 */
850 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
851 (info->tx_power1 >= 0));
852
853 if (info->tx_power1 < 0)
854 info->tx_power1 += 7;
855
856 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
857 TXPOWER_A_TO_DEV(info->tx_power1));
858
859 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
860 (info->tx_power2 >= 0));
861
862 if (info->tx_power2 < 0)
863 info->tx_power2 += 7;
864
865 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
866 TXPOWER_A_TO_DEV(info->tx_power2));
867 } else {
868 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
869 TXPOWER_G_TO_DEV(info->tx_power1));
870 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
871 TXPOWER_G_TO_DEV(info->tx_power2));
872 }
873
874 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
875
876 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
877 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
878 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
879 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
880
881 udelay(200);
882
883 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
884 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
885 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
886 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
887
888 udelay(200);
889
890 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
891 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
892 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
893 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
894}
895
896static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
897 struct ieee80211_conf *conf,
898 struct rf_channel *rf,
899 struct channel_info *info)
900{
901 u8 rfcsr;
902
903 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
904 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
905
906 rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
907 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
908 rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
909
910 rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
911 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
912 TXPOWER_G_TO_DEV(info->tx_power1));
913 rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
914
915 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
916 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
917 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
918
919 rt2800pci_rfcsr_write(rt2x00dev, 24,
920 rt2x00dev->calibration[conf_is_ht40(conf)]);
921
922 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
923 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
924 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
925}
926
927static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
928 struct ieee80211_conf *conf,
929 struct rf_channel *rf,
930 struct channel_info *info)
931{
932 u32 reg;
933 unsigned int tx_pin;
934 u8 bbp;
935
936 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
937 rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
938 else
939 rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
940
941 /*
942 * Change BBP settings
943 */
944 rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
945 rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
946 rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
947 rt2800pci_bbp_write(rt2x00dev, 86, 0);
948
949 if (rf->channel <= 14) {
950 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
951 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
952 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
953 } else {
954 rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
955 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
956 }
957 } else {
958 rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
959
960 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
961 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
962 else
963 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
964 }
965
966 rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
967 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
968 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
969 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
970 rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
971
972 tx_pin = 0;
973
974 /* Turn on unused PA or LNA when not using 1T or 1R */
975 if (rt2x00dev->default_ant.tx != 1) {
976 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
977 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
978 }
979
980 /* Turn on unused PA or LNA when not using 1T or 1R */
981 if (rt2x00dev->default_ant.rx != 1) {
982 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
983 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
984 }
985
986 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
987 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
988 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
989 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
990 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
991 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
992
993 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
994
995 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
996 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
997 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
998
999 rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1000 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1001 rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1002
1003 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1004 if (conf_is_ht40(conf)) {
1005 rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1006 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1007 rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1008 } else {
1009 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1010 rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1011 rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1012 }
1013 }
1014
1015 msleep(1);
1016}
1017
1018static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1019 const int txpower)
1020{
1021 u32 reg;
1022 u32 value = TXPOWER_G_TO_DEV(txpower);
1023 u8 r1;
1024
1025 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1026 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1027 rt2800pci_bbp_write(rt2x00dev, 1, r1);
1028
1029 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1030 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1031 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1032 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1035 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1036 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1037 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1038 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1039
1040 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1041 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1042 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1043 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1046 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1047 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1048 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1049 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1050
1051 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1052 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1053 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1054 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1057 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1058 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1059 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1060 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1061
1062 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1063 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1064 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1065 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1068 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1069 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1070 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1071 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1072
1073 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1074 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1075 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1076 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1078 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1079}
1080
1081static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1082 struct rt2x00lib_conf *libconf)
1083{
1084 u32 reg;
1085
1086 rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1087 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1088 libconf->conf->short_frame_max_tx_count);
1089 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1090 libconf->conf->long_frame_max_tx_count);
1091 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1092 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1093 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1094 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1095 rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1096}
1097
1098static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1099 struct rt2x00lib_conf *libconf)
1100{
1101 enum dev_state state =
1102 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1103 STATE_SLEEP : STATE_AWAKE;
1104 u32 reg;
1105
1106 if (state == STATE_SLEEP) {
1107 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1108
1109 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1110 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1111 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1112 libconf->conf->listen_interval - 1);
1113 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1114 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1115
1116 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1117 } else {
1118 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1119
1120 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1121 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1122 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1123 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1124 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1125 }
1126}
1127
1128static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1129 struct rt2x00lib_conf *libconf,
1130 const unsigned int flags)
1131{
1132 /* Always recalculate LNA gain before changing configuration */
1133 rt2800pci_config_lna_gain(rt2x00dev, libconf);
1134
1135 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1136 rt2800pci_config_channel(rt2x00dev, libconf->conf,
1137 &libconf->rf, &libconf->channel);
1138 if (flags & IEEE80211_CONF_CHANGE_POWER)
1139 rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1140 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1141 rt2800pci_config_retry_limit(rt2x00dev, libconf);
1142 if (flags & IEEE80211_CONF_CHANGE_PS)
1143 rt2800pci_config_ps(rt2x00dev, libconf);
1144}
1145
1146/*
1147 * Link tuning
1148 */
1149static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1150 struct link_qual *qual)
1151{
1152 u32 reg;
1153
1154 /*
1155 * Update FCS error count from register.
1156 */
1157 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1158 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1159}
1160
1161static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1162{
1163 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1164 return 0x2e + rt2x00dev->lna_gain;
1165
1166 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1167 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1168 else
1169 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1170}
1171
1172static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1173 struct link_qual *qual, u8 vgc_level)
1174{
1175 if (qual->vgc_level != vgc_level) {
1176 rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1177 qual->vgc_level = vgc_level;
1178 qual->vgc_level_reg = vgc_level;
1179 }
1180}
1181
1182static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1183 struct link_qual *qual)
1184{
1185 rt2800pci_set_vgc(rt2x00dev, qual,
1186 rt2800pci_get_default_vgc(rt2x00dev));
1187}
1188
1189static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1190 struct link_qual *qual, const u32 count)
1191{
1192 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1193 return;
1194
1195 /*
1196 * When RSSI is better then -80 increase VGC level with 0x10
1197 */
1198 rt2800pci_set_vgc(rt2x00dev, qual,
1199 rt2800pci_get_default_vgc(rt2x00dev) +
1200 ((qual->rssi > -80) * 0x10));
1201}
1202
1203/* 190/*
1204 * Firmware functions 191 * Firmware functions
1205 */ 192 */
@@ -1257,7 +244,7 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1257 * Wait for stable hardware. 244 * Wait for stable hardware.
1258 */ 245 */
1259 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1260 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1261 if (reg && reg != ~0) 248 if (reg && reg != ~0)
1262 break; 249 break;
1263 msleep(1); 250 msleep(1);
@@ -1268,42 +255,42 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1268 return -EBUSY; 255 return -EBUSY;
1269 } 256 }
1270 257
1271 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 258 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1272 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 259 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1273 260
1274 /* 261 /*
1275 * Disable DMA, will be reenabled later when enabling 262 * Disable DMA, will be reenabled later when enabling
1276 * the radio. 263 * the radio.
1277 */ 264 */
1278 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 265 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 268 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 269 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 270 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1284 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 271 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1285 272
1286 /* 273 /*
1287 * enable Host program ram write selection 274 * enable Host program ram write selection
1288 */ 275 */
1289 reg = 0; 276 reg = 0;
1290 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 277 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1291 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 278 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1292 279
1293 /* 280 /*
1294 * Write firmware to device. 281 * Write firmware to device.
1295 */ 282 */
1296 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 283 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1297 data, len); 284 data, len);
1298 285
1299 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 286 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 287 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1301 288
1302 /* 289 /*
1303 * Wait for device to stabilize. 290 * Wait for device to stabilize.
1304 */ 291 */
1305 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 292 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1306 rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 293 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1307 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 294 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1308 break; 295 break;
1309 msleep(1); 296 msleep(1);
@@ -1322,8 +309,8 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1322 /* 309 /*
1323 * Initialize BBP R/W access agent 310 * Initialize BBP R/W access agent
1324 */ 311 */
1325 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 312 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1326 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 313 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1327 314
1328 return 0; 315 return 0;
1329} 316}
@@ -1373,7 +360,7 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1373 struct queue_entry_priv_pci *entry_priv; 360 struct queue_entry_priv_pci *entry_priv;
1374 u32 reg; 361 u32 reg;
1375 362
1376 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 363 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 364 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 365 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 366 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -1381,539 +368,54 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 368 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 369 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1383 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 370 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1384 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 371 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1385 372
1386 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 373 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1387 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 374 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1388 375
1389 /* 376 /*
1390 * Initialize registers. 377 * Initialize registers.
1391 */ 378 */
1392 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 379 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1393 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 380 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1394 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); 381 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1395 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0); 382 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1396 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0); 383 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1397 384
1398 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 385 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1399 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 386 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1400 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); 387 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1401 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0); 388 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1402 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0); 389 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1403 390
1404 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 391 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1405 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 392 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1406 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); 393 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1407 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0); 394 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1408 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0); 395 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1409 396
1410 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 397 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1411 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 398 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1412 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); 399 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0); 400 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0); 401 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1415 402
1416 entry_priv = rt2x00dev->rx->entries[0].priv_data; 403 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1417 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 404 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1418 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); 405 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1419 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); 406 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1420 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0); 407 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
1421 408
1422 /* 409 /*
1423 * Enable global DMA configuration 410 * Enable global DMA configuration
1424 */ 411 */
1425 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 412 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1426 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1429 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1430
1431 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1432
1433 return 0;
1434}
1435
1436static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1437{
1438 u32 reg;
1439 unsigned int i;
1440
1441 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1442
1443 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1444 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1445 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1446 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1447
1448 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1449
1450 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1451 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1452 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1453 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1454 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1455 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1456
1457 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1458 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1459 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1460 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1461 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1462 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1463
1464 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1465 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1466
1467 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1468
1469 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1470 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1471 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1472 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1473 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1474 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1475 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1476 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1477
1478 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1479 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1480
1481 rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1482 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1483 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1484 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1485 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1486 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1487 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1488 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1489 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1490 rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1491
1492 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1493 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1494 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1495 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1496
1497 rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1498 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1499 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1500 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1501 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1502 else
1503 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1504 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1505 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1506 rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1507
1508 rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1509
1510 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1511 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1512 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1513 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1514 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1516 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1517
1518 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1519 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1520 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1521 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1522 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1523 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1524 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1525 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1526 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1527 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1528 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1529
1530 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1531 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1532 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1533 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1534 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1535 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1536 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1537 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1538 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1539 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1540 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1541
1542 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1543 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1544 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1545 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1546 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1547 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1548 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1549 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1550 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1551 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1552 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1553
1554 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1555 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1556 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1557 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1558 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1559 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1560 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1561 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1562 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1563 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1564 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1565
1566 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1567 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1568 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1569 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1570 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1571 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1572 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1573 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1574 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1575 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1576 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1577
1578 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1579 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1580 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1581 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1584 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1585 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1586 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1587 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1588 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1589
1590 rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1591 rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1592
1593 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1594 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1595 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1596 IEEE80211_MAX_RTS_THRESHOLD);
1597 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1598 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1599
1600 rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1601 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1602
1603 /*
1604 * ASIC will keep garbage value after boot, clear encryption keys.
1605 */
1606 for (i = 0; i < 4; i++)
1607 rt2x00pci_register_write(rt2x00dev,
1608 SHARED_KEY_MODE_ENTRY(i), 0);
1609
1610 for (i = 0; i < 256; i++) {
1611 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1612 rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1613 wcid, sizeof(wcid));
1614
1615 rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1616 rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1617 }
1618
1619 /*
1620 * Clear all beacons
1621 * For the Beacon base registers we only need to clear
1622 * the first byte since that byte contains the VALID and OWNER
1623 * bits which (when set to 0) will invalidate the entire beacon.
1624 */
1625 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1626 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1627 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1628 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1629 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1630 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1631 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1632 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1633
1634 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1635 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1636 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1637 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1638 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1639 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1640 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1641 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1642 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1643 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1644
1645 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1646 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1647 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1648 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1649 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1650 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1651 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1652 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1653 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1654 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1655
1656 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1657 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1658 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1659 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1660 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1661 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1662 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1663 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1664 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1665 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1666
1667 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1668 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1669 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1670 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1671 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1672 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1673
1674 /*
1675 * We must clear the error counters.
1676 * These registers are cleared on read,
1677 * so we may pass a useless variable to store the value.
1678 */
1679 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1680 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1681 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1682 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1683 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1684 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1685
1686 return 0;
1687}
1688
1689static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1690{
1691 unsigned int i;
1692 u32 reg;
1693
1694 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1695 rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1696 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1697 return 0;
1698
1699 udelay(REGISTER_BUSY_DELAY);
1700 }
1701
1702 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1703 return -EACCES;
1704}
1705
1706static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1707{
1708 unsigned int i;
1709 u8 value;
1710
1711 /*
1712 * BBP was enabled after firmware was loaded,
1713 * but we need to reactivate it now.
1714 */
1715 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1716 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1717 msleep(1);
1718
1719 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1720 rt2800pci_bbp_read(rt2x00dev, 0, &value);
1721 if ((value != 0xff) && (value != 0x00))
1722 return 0;
1723 udelay(REGISTER_BUSY_DELAY);
1724 }
1725
1726 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1727 return -EACCES;
1728}
1729
1730static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1731{
1732 unsigned int i;
1733 u16 eeprom;
1734 u8 reg_id;
1735 u8 value;
1736
1737 if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1738 rt2800pci_wait_bbp_ready(rt2x00dev)))
1739 return -EACCES;
1740
1741 rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1742 rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1743 rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1744 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1745 rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1746 rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1747 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1748 rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1749 rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1750 rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1751 rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1752 rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1753 rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1754 rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1755
1756 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1757 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1758 rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1759 }
1760
1761 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1762 rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1763
1764 if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1765 rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1766 rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1767 rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1768 }
1769
1770 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1771 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1772
1773 if (eeprom != 0xffff && eeprom != 0x0000) {
1774 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1775 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1776 rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1777 }
1778 }
1779 417
1780 return 0; 418 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1781}
1782
1783static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1784 bool bw40, u8 rfcsr24, u8 filter_target)
1785{
1786 unsigned int i;
1787 u8 bbp;
1788 u8 rfcsr;
1789 u8 passband;
1790 u8 stopband;
1791 u8 overtuned = 0;
1792
1793 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1794
1795 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1796 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1797 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1798
1799 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1800 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1801 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1802
1803 /*
1804 * Set power & frequency of passband test tone
1805 */
1806 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1807
1808 for (i = 0; i < 100; i++) {
1809 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1810 msleep(1);
1811
1812 rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1813 if (passband)
1814 break;
1815 }
1816
1817 /*
1818 * Set power & frequency of stopband test tone
1819 */
1820 rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1821
1822 for (i = 0; i < 100; i++) {
1823 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1824 msleep(1);
1825
1826 rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1827
1828 if ((passband - stopband) <= filter_target) {
1829 rfcsr24++;
1830 overtuned += ((passband - stopband) == filter_target);
1831 } else
1832 break;
1833
1834 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1835 }
1836
1837 rfcsr24 -= !!overtuned;
1838
1839 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1840 return rfcsr24;
1841}
1842
1843static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1844{
1845 u8 rfcsr;
1846 u8 bbp;
1847
1848 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1849 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1850 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1851 return 0;
1852
1853 /*
1854 * Init RF calibration.
1855 */
1856 rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1857 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1858 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1859 msleep(1);
1860 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1861 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1862
1863 rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1864 rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1865 rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1866 rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1867 rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1868 rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1869 rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1870 rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1871 rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1872 rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1873 rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1874 rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1875 rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1876 rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1877 rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1878 rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1879 rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1880 rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1881 rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1882 rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1883 rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1884 rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1885 rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1886 rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1887 rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1888 rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1889 rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1890 rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1891 rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1892 rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1893
1894 /*
1895 * Set RX Filter calibration for 20MHz and 40MHz
1896 */
1897 rt2x00dev->calibration[0] =
1898 rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1899 rt2x00dev->calibration[1] =
1900 rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1901
1902 /*
1903 * Set back to initial state
1904 */
1905 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1906
1907 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1908 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1909 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1910
1911 /*
1912 * set BBP back to BW20
1913 */
1914 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1915 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1916 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1917 419
1918 return 0; 420 return 0;
1919} 421}
@@ -1926,11 +428,11 @@ static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1926{ 428{
1927 u32 reg; 429 u32 reg;
1928 430
1929 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 431 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1930 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 432 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1931 (state == STATE_RADIO_RX_ON) || 433 (state == STATE_RADIO_RX_ON) ||
1932 (state == STATE_RADIO_RX_ON_LINK)); 434 (state == STATE_RADIO_RX_ON_LINK));
1933 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 435 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1934} 436}
1935 437
1936static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 438static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
@@ -1944,11 +446,11 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1944 * should clear the register to assure a clean state. 446 * should clear the register to assure a clean state.
1945 */ 447 */
1946 if (state == STATE_RADIO_IRQ_ON) { 448 if (state == STATE_RADIO_IRQ_ON) {
1947 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 449 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1948 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 450 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1949 } 451 }
1950 452
1951 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 453 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1952 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask); 454 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1953 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask); 455 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1954 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask); 456 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
@@ -1967,7 +469,7 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1967 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask); 469 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1968 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask); 470 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1969 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask); 471 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1970 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 472 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
1971} 473}
1972 474
1973static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 475static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
@@ -1976,7 +478,7 @@ static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1976 u32 reg; 478 u32 reg;
1977 479
1978 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 480 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1979 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 481 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1980 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 482 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1981 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 483 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1982 return 0; 484 return 0;
@@ -1998,50 +500,50 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1998 */ 500 */
1999 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) || 501 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2000 rt2800pci_init_queues(rt2x00dev) || 502 rt2800pci_init_queues(rt2x00dev) ||
2001 rt2800pci_init_registers(rt2x00dev) || 503 rt2800_init_registers(rt2x00dev) ||
2002 rt2800pci_wait_wpdma_ready(rt2x00dev) || 504 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2003 rt2800pci_init_bbp(rt2x00dev) || 505 rt2800_init_bbp(rt2x00dev) ||
2004 rt2800pci_init_rfcsr(rt2x00dev))) 506 rt2800_init_rfcsr(rt2x00dev)))
2005 return -EIO; 507 return -EIO;
2006 508
2007 /* 509 /*
2008 * Send signal to firmware during boot time. 510 * Send signal to firmware during boot time.
2009 */ 511 */
2010 rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); 512 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2011 513
2012 /* 514 /*
2013 * Enable RX. 515 * Enable RX.
2014 */ 516 */
2015 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 517 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2016 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 518 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2017 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); 519 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2018 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 520 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2019 521
2020 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 522 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2021 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2022 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2023 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); 525 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2024 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 526 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2025 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 527 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2026 528
2027 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 529 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2028 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 530 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2029 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 531 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2030 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 532 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2031 533
2032 /* 534 /*
2033 * Initialize LED control 535 * Initialize LED control
2034 */ 536 */
2035 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); 537 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2036 rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff, 538 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2037 word & 0xff, (word >> 8) & 0xff); 539 word & 0xff, (word >> 8) & 0xff);
2038 540
2039 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 541 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2040 rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff, 542 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2041 word & 0xff, (word >> 8) & 0xff); 543 word & 0xff, (word >> 8) & 0xff);
2042 544
2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); 545 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2044 rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff, 546 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2045 word & 0xff, (word >> 8) & 0xff); 547 word & 0xff, (word >> 8) & 0xff);
2046 548
2047 return 0; 549 return 0;
@@ -2051,21 +553,21 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2051{ 553{
2052 u32 reg; 554 u32 reg;
2053 555
2054 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 556 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2055 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2056 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2057 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 559 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2058 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 560 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2059 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 561 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2060 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 562 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2061 563
2062 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 564 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2063 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0); 565 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2064 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0); 566 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2065 567
2066 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280); 568 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2067 569
2068 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 570 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2069 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 571 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
2070 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 572 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
2071 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 573 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -2073,10 +575,10 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2073 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 575 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
2074 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 576 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
2075 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 577 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
2076 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 578 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2077 579
2078 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 580 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
2079 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 581 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
2080 582
2081 /* Wait for DMA, ignore error */ 583 /* Wait for DMA, ignore error */
2082 rt2800pci_wait_wpdma_ready(rt2x00dev); 584 rt2800pci_wait_wpdma_ready(rt2x00dev);
@@ -2090,10 +592,10 @@ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2090 * if the device is booting and wasn't asleep it will return 592 * if the device is booting and wasn't asleep it will return
2091 * failure when attempting to wakeup. 593 * failure when attempting to wakeup.
2092 */ 594 */
2093 rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 595 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2094 596
2095 if (state == STATE_AWAKE) { 597 if (state == STATE_AWAKE) {
2096 rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); 598 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2097 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); 599 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2098 } 600 }
2099 601
@@ -2195,7 +697,7 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2195 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); 697 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2196 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 698 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2197 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 699 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2198 (skbdesc->entry->entry_idx + 1) : 0xff); 700 txdesc->key_idx : 0xff);
2199 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 701 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2200 skb->len - txdesc->l2pad); 702 skb->len - txdesc->l2pad);
2201 rt2x00_set_field32(&word, TXWI_W1_PACKETID, 703 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
@@ -2204,8 +706,8 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2204 706
2205 /* 707 /*
2206 * Always write 0 to IV/EIV fields, hardware will insert the IV 708 * Always write 0 to IV/EIV fields, hardware will insert the IV
2207 * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0. 709 * from the IVEIV register when TXD_W3_WIV is set to 0.
2208 * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data 710 * When TXD_W3_WIV is set to 1 it will use the IV data
2209 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 711 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2210 * crypto entry in the registers should be used to encrypt the frame. 712 * crypto entry in the registers should be used to encrypt the frame.
2211 */ 713 */
@@ -2265,18 +767,18 @@ static void rt2800pci_write_beacon(struct queue_entry *entry)
2265 * Disable beaconing while we are reloading the beacon data, 767 * Disable beaconing while we are reloading the beacon data,
2266 * otherwise we might be sending out invalid data. 768 * otherwise we might be sending out invalid data.
2267 */ 769 */
2268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 770 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2269 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 771 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2270 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 772 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2271 773
2272 /* 774 /*
2273 * Write entire beacon with descriptor to register. 775 * Write entire beacon with descriptor to register.
2274 */ 776 */
2275 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 777 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2276 rt2x00pci_register_multiwrite(rt2x00dev, 778 rt2800_register_multiwrite(rt2x00dev,
2277 beacon_base, 779 beacon_base,
2278 skbdesc->desc, skbdesc->desc_len); 780 skbdesc->desc, skbdesc->desc_len);
2279 rt2x00pci_register_multiwrite(rt2x00dev, 781 rt2800_register_multiwrite(rt2x00dev,
2280 beacon_base + skbdesc->desc_len, 782 beacon_base + skbdesc->desc_len,
2281 entry->skb->data, entry->skb->len); 783 entry->skb->data, entry->skb->len);
2282 784
@@ -2295,12 +797,12 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2295 u32 reg; 797 u32 reg;
2296 798
2297 if (queue_idx == QID_BEACON) { 799 if (queue_idx == QID_BEACON) {
2298 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 800 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2299 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 801 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 802 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2301 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 803 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2302 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 804 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2303 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 805 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2304 } 806 }
2305 return; 807 return;
2306 } 808 }
@@ -2316,7 +818,7 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2316 else 818 else
2317 qidx = queue_idx; 819 qidx = queue_idx;
2318 820
2319 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx); 821 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2320} 822}
2321 823
2322static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 824static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -2325,16 +827,16 @@ static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2325 u32 reg; 827 u32 reg;
2326 828
2327 if (qid == QID_BEACON) { 829 if (qid == QID_BEACON) {
2328 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0); 830 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2329 return; 831 return;
2330 } 832 }
2331 833
2332 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 834 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2333 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE)); 835 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2334 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK)); 836 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2335 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI)); 837 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2336 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO)); 838 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2337 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 839 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2338} 840}
2339 841
2340/* 842/*
@@ -2430,7 +932,7 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2430 * Set RX IDX in register to inform hardware that we have handled 932 * Set RX IDX in register to inform hardware that we have handled
2431 * this entry and it is available for reuse again. 933 * this entry and it is available for reuse again.
2432 */ 934 */
2433 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); 935 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2434 936
2435 /* 937 /*
2436 * Remove TXWI descriptor from start of buffer. 938 * Remove TXWI descriptor from start of buffer.
@@ -2467,7 +969,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2467 old_reg = 0; 969 old_reg = 0;
2468 970
2469 while (1) { 971 while (1) {
2470 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg); 972 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2471 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID)) 973 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2472 break; 974 break;
2473 975
@@ -2551,8 +1053,8 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2551 u32 reg; 1053 u32 reg;
2552 1054
2553 /* Read status and ACK all interrupts */ 1055 /* Read status and ACK all interrupts */
2554 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 1056 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2555 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1057 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2556 1058
2557 if (!reg) 1059 if (!reg)
2558 return IRQ_NONE; 1060 return IRQ_NONE;
@@ -2709,7 +1211,7 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2709 * Identify RF chipset. 1211 * Identify RF chipset.
2710 */ 1212 */
2711 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1213 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2712 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 1214 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2713 rt2x00_set_chip_rf(rt2x00dev, value, reg); 1215 rt2x00_set_chip_rf(rt2x00dev, value, reg);
2714 1216
2715 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) && 1217 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
@@ -2758,9 +1260,9 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2758 * Store led settings, for correct led behaviour. 1260 * Store led settings, for correct led behaviour.
2759 */ 1261 */
2760#ifdef CONFIG_RT2X00_LIB_LEDS 1262#ifdef CONFIG_RT2X00_LIB_LEDS
2761 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 1263 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2762 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 1264 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2763 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 1265 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2764 1266
2765 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); 1267 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2766#endif /* CONFIG_RT2X00_LIB_LEDS */ 1268#endif /* CONFIG_RT2X00_LIB_LEDS */
@@ -2948,10 +1450,25 @@ static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2948 return 0; 1450 return 0;
2949} 1451}
2950 1452
1453static const struct rt2800_ops rt2800pci_rt2800_ops = {
1454 .register_read = rt2x00pci_register_read,
1455 .register_write = rt2x00pci_register_write,
1456 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1457
1458 .register_multiread = rt2x00pci_register_multiread,
1459 .register_multiwrite = rt2x00pci_register_multiwrite,
1460
1461 .regbusy_read = rt2x00pci_regbusy_read,
1462};
1463
2951static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1464static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2952{ 1465{
2953 int retval; 1466 int retval;
2954 1467
1468 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
1469
1470 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1471
2955 /* 1472 /*
2956 * Allocate eeprom data. 1473 * Allocate eeprom data.
2957 */ 1474 */
@@ -2996,161 +1513,6 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2996 return 0; 1513 return 0;
2997} 1514}
2998 1515
2999/*
3000 * IEEE80211 stack callback functions.
3001 */
3002static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
3003 u32 *iv32, u16 *iv16)
3004{
3005 struct rt2x00_dev *rt2x00dev = hw->priv;
3006 struct mac_iveiv_entry iveiv_entry;
3007 u32 offset;
3008
3009 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3010 rt2x00pci_register_multiread(rt2x00dev, offset,
3011 &iveiv_entry, sizeof(iveiv_entry));
3012
3013 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
3014 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
3015}
3016
3017static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3018{
3019 struct rt2x00_dev *rt2x00dev = hw->priv;
3020 u32 reg;
3021 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3022
3023 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3024 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3025 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
3026
3027 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3028 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3029 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3030
3031 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3032 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3033 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3034
3035 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3036 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3037 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3038
3039 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3040 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3041 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3042
3043 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3044 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3045 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3046
3047 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3048 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3049 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3050
3051 return 0;
3052}
3053
3054static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3055 const struct ieee80211_tx_queue_params *params)
3056{
3057 struct rt2x00_dev *rt2x00dev = hw->priv;
3058 struct data_queue *queue;
3059 struct rt2x00_field32 field;
3060 int retval;
3061 u32 reg;
3062 u32 offset;
3063
3064 /*
3065 * First pass the configuration through rt2x00lib, that will
3066 * update the queue settings and validate the input. After that
3067 * we are free to update the registers based on the value
3068 * in the queue parameter.
3069 */
3070 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3071 if (retval)
3072 return retval;
3073
3074 /*
3075 * We only need to perform additional register initialization
3076 * for WMM queues/
3077 */
3078 if (queue_idx >= 4)
3079 return 0;
3080
3081 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3082
3083 /* Update WMM TXOP register */
3084 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3085 field.bit_offset = (queue_idx & 1) * 16;
3086 field.bit_mask = 0xffff << field.bit_offset;
3087
3088 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3089 rt2x00_set_field32(&reg, field, queue->txop);
3090 rt2x00pci_register_write(rt2x00dev, offset, reg);
3091
3092 /* Update WMM registers */
3093 field.bit_offset = queue_idx * 4;
3094 field.bit_mask = 0xf << field.bit_offset;
3095
3096 rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3097 rt2x00_set_field32(&reg, field, queue->aifs);
3098 rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3099
3100 rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3101 rt2x00_set_field32(&reg, field, queue->cw_min);
3102 rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3103
3104 rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3105 rt2x00_set_field32(&reg, field, queue->cw_max);
3106 rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3107
3108 /* Update EDCA registers */
3109 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3110
3111 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3112 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3113 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3114 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3115 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3116 rt2x00pci_register_write(rt2x00dev, offset, reg);
3117
3118 return 0;
3119}
3120
3121static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3122{
3123 struct rt2x00_dev *rt2x00dev = hw->priv;
3124 u64 tsf;
3125 u32 reg;
3126
3127 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3128 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3129 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3130 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3131
3132 return tsf;
3133}
3134
3135static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3136 .tx = rt2x00mac_tx,
3137 .start = rt2x00mac_start,
3138 .stop = rt2x00mac_stop,
3139 .add_interface = rt2x00mac_add_interface,
3140 .remove_interface = rt2x00mac_remove_interface,
3141 .config = rt2x00mac_config,
3142 .configure_filter = rt2x00mac_configure_filter,
3143 .set_key = rt2x00mac_set_key,
3144 .get_stats = rt2x00mac_get_stats,
3145 .get_tkip_seq = rt2800pci_get_tkip_seq,
3146 .set_rts_threshold = rt2800pci_set_rts_threshold,
3147 .bss_info_changed = rt2x00mac_bss_info_changed,
3148 .conf_tx = rt2800pci_conf_tx,
3149 .get_tx_stats = rt2x00mac_get_tx_stats,
3150 .get_tsf = rt2800pci_get_tsf,
3151 .rfkill_poll = rt2x00mac_rfkill_poll,
3152};
3153
3154static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 1516static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3155 .irq_handler = rt2800pci_interrupt, 1517 .irq_handler = rt2800pci_interrupt,
3156 .probe_hw = rt2800pci_probe_hw, 1518 .probe_hw = rt2800pci_probe_hw,
@@ -3162,23 +1524,23 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3162 .get_entry_state = rt2800pci_get_entry_state, 1524 .get_entry_state = rt2800pci_get_entry_state,
3163 .clear_entry = rt2800pci_clear_entry, 1525 .clear_entry = rt2800pci_clear_entry,
3164 .set_device_state = rt2800pci_set_device_state, 1526 .set_device_state = rt2800pci_set_device_state,
3165 .rfkill_poll = rt2800pci_rfkill_poll, 1527 .rfkill_poll = rt2800_rfkill_poll,
3166 .link_stats = rt2800pci_link_stats, 1528 .link_stats = rt2800_link_stats,
3167 .reset_tuner = rt2800pci_reset_tuner, 1529 .reset_tuner = rt2800_reset_tuner,
3168 .link_tuner = rt2800pci_link_tuner, 1530 .link_tuner = rt2800_link_tuner,
3169 .write_tx_desc = rt2800pci_write_tx_desc, 1531 .write_tx_desc = rt2800pci_write_tx_desc,
3170 .write_tx_data = rt2x00pci_write_tx_data, 1532 .write_tx_data = rt2x00pci_write_tx_data,
3171 .write_beacon = rt2800pci_write_beacon, 1533 .write_beacon = rt2800pci_write_beacon,
3172 .kick_tx_queue = rt2800pci_kick_tx_queue, 1534 .kick_tx_queue = rt2800pci_kick_tx_queue,
3173 .kill_tx_queue = rt2800pci_kill_tx_queue, 1535 .kill_tx_queue = rt2800pci_kill_tx_queue,
3174 .fill_rxdone = rt2800pci_fill_rxdone, 1536 .fill_rxdone = rt2800pci_fill_rxdone,
3175 .config_shared_key = rt2800pci_config_shared_key, 1537 .config_shared_key = rt2800_config_shared_key,
3176 .config_pairwise_key = rt2800pci_config_pairwise_key, 1538 .config_pairwise_key = rt2800_config_pairwise_key,
3177 .config_filter = rt2800pci_config_filter, 1539 .config_filter = rt2800_config_filter,
3178 .config_intf = rt2800pci_config_intf, 1540 .config_intf = rt2800_config_intf,
3179 .config_erp = rt2800pci_config_erp, 1541 .config_erp = rt2800_config_erp,
3180 .config_ant = rt2800pci_config_ant, 1542 .config_ant = rt2800_config_ant,
3181 .config = rt2800pci_config, 1543 .config = rt2800_config,
3182}; 1544};
3183 1545
3184static const struct data_queue_desc rt2800pci_queue_rx = { 1546static const struct data_queue_desc rt2800pci_queue_rx = {
@@ -3213,9 +1575,9 @@ static const struct rt2x00_ops rt2800pci_ops = {
3213 .tx = &rt2800pci_queue_tx, 1575 .tx = &rt2800pci_queue_tx,
3214 .bcn = &rt2800pci_queue_bcn, 1576 .bcn = &rt2800pci_queue_bcn,
3215 .lib = &rt2800pci_rt2x00_ops, 1577 .lib = &rt2800pci_rt2x00_ops,
3216 .hw = &rt2800pci_mac80211_ops, 1578 .hw = &rt2800_mac80211_ops,
3217#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1579#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3218 .debugfs = &rt2800pci_rt2x00debug, 1580 .debugfs = &rt2800_rt2x00debug,
3219#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1581#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3220}; 1582};
3221 1583
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
index 856908815221..1dbf13270cda 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.h
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -28,61 +28,6 @@
28#define RT2800PCI_H 28#define RT2800PCI_H
29 29
30/* 30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * RT2860 version
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Default offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * PCI registers. 31 * PCI registers.
87 */ 32 */
88 33
@@ -102,215 +47,6 @@
102#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 47#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
103 48
104/* 49/*
105 * INT_SOURCE_CSR: Interrupt source register.
106 * Write one to clear corresponding bit.
107 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
108 */
109#define INT_SOURCE_CSR 0x0200
110#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
111#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
112#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
113#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
114#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
115#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
116#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
117#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
118#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
119#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
120#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
121#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
122#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
123#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
124#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
125#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
126#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
127#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
128
129/*
130 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
131 */
132#define INT_MASK_CSR 0x0204
133#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
134#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
135#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
136#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
137#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
138#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
139#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
140#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
141#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
142#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
143#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
144#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
145#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
146#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
147#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
148#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
149#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
150#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
151
152/*
153 * WPDMA_GLO_CFG
154 */
155#define WPDMA_GLO_CFG 0x0208
156#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
157#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
158#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
159#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
160#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
161#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
162#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
163#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
164#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
165
166/*
167 * WPDMA_RST_IDX
168 */
169#define WPDMA_RST_IDX 0x020c
170#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
171#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
172#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
173#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
174#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
175#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
176#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
177
178/*
179 * DELAY_INT_CFG
180 */
181#define DELAY_INT_CFG 0x0210
182#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
183#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
184#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
185#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
186#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
187#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
188
189/*
190 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
191 * AIFSN0: AC_BE
192 * AIFSN1: AC_BK
193 * AIFSN1: AC_VI
194 * AIFSN1: AC_VO
195 */
196#define WMM_AIFSN_CFG 0x0214
197#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
198#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
199#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
200#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
201
202/*
203 * WMM_CWMIN_CSR: CWmin for each EDCA AC
204 * CWMIN0: AC_BE
205 * CWMIN1: AC_BK
206 * CWMIN1: AC_VI
207 * CWMIN1: AC_VO
208 */
209#define WMM_CWMIN_CFG 0x0218
210#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
211#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
212#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
213#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
214
215/*
216 * WMM_CWMAX_CSR: CWmax for each EDCA AC
217 * CWMAX0: AC_BE
218 * CWMAX1: AC_BK
219 * CWMAX1: AC_VI
220 * CWMAX1: AC_VO
221 */
222#define WMM_CWMAX_CFG 0x021c
223#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
224#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
225#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
226#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
227
228/*
229 * AC_TXOP0: AC_BK/AC_BE TXOP register
230 * AC0TXOP: AC_BK in unit of 32us
231 * AC1TXOP: AC_BE in unit of 32us
232 */
233#define WMM_TXOP0_CFG 0x0220
234#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
235#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
236
237/*
238 * AC_TXOP1: AC_VO/AC_VI TXOP register
239 * AC2TXOP: AC_VI in unit of 32us
240 * AC3TXOP: AC_VO in unit of 32us
241 */
242#define WMM_TXOP1_CFG 0x0224
243#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
244#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
245
246/*
247 * GPIO_CTRL_CFG:
248 */
249#define GPIO_CTRL_CFG 0x0228
250#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
251#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
252#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
253#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
254#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
255#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
256#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
257#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
258#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
259
260/*
261 * MCU_CMD_CFG
262 */
263#define MCU_CMD_CFG 0x022c
264
265/*
266 * AC_BK register offsets
267 */
268#define TX_BASE_PTR0 0x0230
269#define TX_MAX_CNT0 0x0234
270#define TX_CTX_IDX0 0x0238
271#define TX_DTX_IDX0 0x023c
272
273/*
274 * AC_BE register offsets
275 */
276#define TX_BASE_PTR1 0x0240
277#define TX_MAX_CNT1 0x0244
278#define TX_CTX_IDX1 0x0248
279#define TX_DTX_IDX1 0x024c
280
281/*
282 * AC_VI register offsets
283 */
284#define TX_BASE_PTR2 0x0250
285#define TX_MAX_CNT2 0x0254
286#define TX_CTX_IDX2 0x0258
287#define TX_DTX_IDX2 0x025c
288
289/*
290 * AC_VO register offsets
291 */
292#define TX_BASE_PTR3 0x0260
293#define TX_MAX_CNT3 0x0264
294#define TX_CTX_IDX3 0x0268
295#define TX_DTX_IDX3 0x026c
296
297/*
298 * HCCA register offsets
299 */
300#define TX_BASE_PTR4 0x0270
301#define TX_MAX_CNT4 0x0274
302#define TX_CTX_IDX4 0x0278
303#define TX_DTX_IDX4 0x027c
304
305/*
306 * MGMT register offsets
307 */
308#define TX_BASE_PTR5 0x0280
309#define TX_MAX_CNT5 0x0284
310#define TX_CTX_IDX5 0x0288
311#define TX_DTX_IDX5 0x028c
312
313/*
314 * Queue register offset macros 50 * Queue register offset macros
315 */ 51 */
316#define TX_QUEUE_REG_OFFSET 0x10 52#define TX_QUEUE_REG_OFFSET 0x10
@@ -320,72 +56,6 @@
320#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET) 56#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
321 57
322/* 58/*
323 * RX register offsets
324 */
325#define RX_BASE_PTR 0x0290
326#define RX_MAX_CNT 0x0294
327#define RX_CRX_IDX 0x0298
328#define RX_DRX_IDX 0x029c
329
330/*
331 * PBF_SYS_CTRL
332 * HOST_RAM_WRITE: enable Host program ram write selection
333 */
334#define PBF_SYS_CTRL 0x0400
335#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
336#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
337
338/*
339 * HOST-MCU shared memory
340 */
341#define HOST_CMD_CSR 0x0404
342#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
343
344/*
345 * PBF registers
346 * Most are for debug. Driver doesn't touch PBF register.
347 */
348#define PBF_CFG 0x0408
349#define PBF_MAX_PCNT 0x040c
350#define PBF_CTRL 0x0410
351#define PBF_INT_STA 0x0414
352#define PBF_INT_ENA 0x0418
353
354/*
355 * BCN_OFFSET0:
356 */
357#define BCN_OFFSET0 0x042c
358#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
359#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
360#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
361#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
362
363/*
364 * BCN_OFFSET1:
365 */
366#define BCN_OFFSET1 0x0430
367#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
368#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
369#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
370#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
371
372/*
373 * PBF registers
374 * Most are for debug. Driver doesn't touch PBF register.
375 */
376#define TXRXQ_PCNT 0x0438
377#define PBF_DBG 0x043c
378
379/*
380 * RF registers
381 */
382#define RF_CSR_CFG 0x0500
383#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
384#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
385#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
386#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
387
388/*
389 * EFUSE_CSR: RT3090 EEPROM 59 * EFUSE_CSR: RT3090 EEPROM
390 */ 60 */
391#define EFUSE_CTRL 0x0580 61#define EFUSE_CTRL 0x0580
@@ -414,1360 +84,16 @@
414#define EFUSE_DATA3 0x059c 84#define EFUSE_DATA3 0x059c
415 85
416/* 86/*
417 * MAC Control/Status Registers(CSR).
418 * Some values are set in TU, whereas 1 TU == 1024 us.
419 */
420
421/*
422 * MAC_CSR0: ASIC revision number.
423 * ASIC_REV: 0
424 * ASIC_VER: 2860
425 */
426#define MAC_CSR0 0x1000
427#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
428#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
429
430/*
431 * MAC_SYS_CTRL:
432 */
433#define MAC_SYS_CTRL 0x1004
434#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
435#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
436#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
437#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
438#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
439#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
440#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
441#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
442
443/*
444 * MAC_ADDR_DW0: STA MAC register 0
445 */
446#define MAC_ADDR_DW0 0x1008
447#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
448#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
449#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
450#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
451
452/*
453 * MAC_ADDR_DW1: STA MAC register 1
454 * UNICAST_TO_ME_MASK:
455 * Used to mask off bits from byte 5 of the MAC address
456 * to determine the UNICAST_TO_ME bit for RX frames.
457 * The full mask is complemented by BSS_ID_MASK:
458 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
459 */
460#define MAC_ADDR_DW1 0x100c
461#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
462#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
463#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
464
465/*
466 * MAC_BSSID_DW0: BSSID register 0
467 */
468#define MAC_BSSID_DW0 0x1010
469#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
470#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
471#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
472#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
473
474/*
475 * MAC_BSSID_DW1: BSSID register 1
476 * BSS_ID_MASK:
477 * 0: 1-BSSID mode (BSS index = 0)
478 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
479 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
480 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
481 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
482 * BSSID. This will make sure that those bits will be ignored
483 * when determining the MY_BSS of RX frames.
484 */
485#define MAC_BSSID_DW1 0x1014
486#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
487#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
488#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
489#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
490
491/*
492 * MAX_LEN_CFG: Maximum frame length register.
493 * MAX_MPDU: rt2860b max 16k bytes
494 * MAX_PSDU: Maximum PSDU length
495 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
496 */
497#define MAX_LEN_CFG 0x1018
498#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
499#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
500#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
501#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
502
503/*
504 * BBP_CSR_CFG: BBP serial control register
505 * VALUE: Register value to program into BBP
506 * REG_NUM: Selected BBP register
507 * READ_CONTROL: 0 write BBP, 1 read BBP
508 * BUSY: ASIC is busy executing BBP commands
509 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
510 * BBP_RW_MODE: 0 serial, 1 paralell
511 */
512#define BBP_CSR_CFG 0x101c
513#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
514#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
515#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
516#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
517#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
518#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
519
520/*
521 * RF_CSR_CFG0: RF control register
522 * REGID_AND_VALUE: Register value to program into RF
523 * BITWIDTH: Selected RF register
524 * STANDBYMODE: 0 high when standby, 1 low when standby
525 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
526 * BUSY: ASIC is busy executing RF commands
527 */
528#define RF_CSR_CFG0 0x1020
529#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
530#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
531#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
532#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
533#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
534#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
535
536/*
537 * RF_CSR_CFG1: RF control register
538 * REGID_AND_VALUE: Register value to program into RF
539 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
540 * 0: 3 system clock cycle (37.5usec)
541 * 1: 5 system clock cycle (62.5usec)
542 */
543#define RF_CSR_CFG1 0x1024
544#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
545#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
546
547/*
548 * RF_CSR_CFG2: RF control register
549 * VALUE: Register value to program into RF
550 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
551 * 0: 3 system clock cycle (37.5usec)
552 * 1: 5 system clock cycle (62.5usec)
553 */
554#define RF_CSR_CFG2 0x1028
555#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
556
557/*
558 * LED_CFG: LED control
559 * color LED's:
560 * 0: off
561 * 1: blinking upon TX2
562 * 2: periodic slow blinking
563 * 3: always on
564 * LED polarity:
565 * 0: active low
566 * 1: active high
567 */
568#define LED_CFG 0x102c
569#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
570#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
571#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
572#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
573#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
574#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
575#define LED_CFG_LED_POLAR FIELD32(0x40000000)
576
577/*
578 * XIFS_TIME_CFG: MAC timing
579 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
580 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
581 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
582 * when MAC doesn't reference BBP signal BBRXEND
583 * EIFS: unit 1us
584 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
585 *
586 */
587#define XIFS_TIME_CFG 0x1100
588#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
589#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
590#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
591#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
592#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
593
594/*
595 * BKOFF_SLOT_CFG:
596 */
597#define BKOFF_SLOT_CFG 0x1104
598#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
599#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
600
601/*
602 * NAV_TIME_CFG:
603 */
604#define NAV_TIME_CFG 0x1108
605#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
606#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
607#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
608#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
609
610/*
611 * CH_TIME_CFG: count as channel busy
612 */
613#define CH_TIME_CFG 0x110c
614
615/*
616 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
617 */
618#define PBF_LIFE_TIMER 0x1110
619
620/*
621 * BCN_TIME_CFG:
622 * BEACON_INTERVAL: in unit of 1/16 TU
623 * TSF_TICKING: Enable TSF auto counting
624 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
625 * BEACON_GEN: Enable beacon generator
626 */
627#define BCN_TIME_CFG 0x1114
628#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
629#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
630#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
631#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
632#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
633#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
634
635/*
636 * TBTT_SYNC_CFG:
637 */
638#define TBTT_SYNC_CFG 0x1118
639
640/*
641 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
642 */
643#define TSF_TIMER_DW0 0x111c
644#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
645
646/*
647 * TSF_TIMER_DW1: Local msb TSF timer, read-only
648 */
649#define TSF_TIMER_DW1 0x1120
650#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
651
652/*
653 * TBTT_TIMER: TImer remains till next TBTT, read-only
654 */
655#define TBTT_TIMER 0x1124
656
657/*
658 * INT_TIMER_CFG:
659 */
660#define INT_TIMER_CFG 0x1128
661
662/*
663 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
664 */
665#define INT_TIMER_EN 0x112c
666
667/*
668 * CH_IDLE_STA: channel idle time
669 */
670#define CH_IDLE_STA 0x1130
671
672/*
673 * CH_BUSY_STA: channel busy time
674 */
675#define CH_BUSY_STA 0x1134
676
677/*
678 * MAC_STATUS_CFG:
679 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
680 * if 1 or higher one of the 2 registers is busy.
681 */
682#define MAC_STATUS_CFG 0x1200
683#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
684
685/*
686 * PWR_PIN_CFG:
687 */
688#define PWR_PIN_CFG 0x1204
689
690/*
691 * AUTOWAKEUP_CFG: Manual power control / status register
692 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
693 * AUTOWAKE: 0:sleep, 1:awake
694 */
695#define AUTOWAKEUP_CFG 0x1208
696#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
697#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
698#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
699
700/*
701 * EDCA_AC0_CFG:
702 */
703#define EDCA_AC0_CFG 0x1300
704#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
705#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
706#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
707#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
708
709/*
710 * EDCA_AC1_CFG:
711 */
712#define EDCA_AC1_CFG 0x1304
713#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
714#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
715#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
716#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
717
718/*
719 * EDCA_AC2_CFG:
720 */
721#define EDCA_AC2_CFG 0x1308
722#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
723#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
724#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
725#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
726
727/*
728 * EDCA_AC3_CFG:
729 */
730#define EDCA_AC3_CFG 0x130c
731#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
732#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
733#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
734#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
735
736/*
737 * EDCA_TID_AC_MAP:
738 */
739#define EDCA_TID_AC_MAP 0x1310
740
741/*
742 * TX_PWR_CFG_0:
743 */
744#define TX_PWR_CFG_0 0x1314
745#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
746#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
747#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
748#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
749#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
750#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
751#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
752#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
753
754/*
755 * TX_PWR_CFG_1:
756 */
757#define TX_PWR_CFG_1 0x1318
758#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
759#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
760#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
761#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
762#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
763#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
764#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
765#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
766
767/*
768 * TX_PWR_CFG_2:
769 */
770#define TX_PWR_CFG_2 0x131c
771#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
772#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
773#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
774#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
775#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
776#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
777#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
778#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
779
780/*
781 * TX_PWR_CFG_3:
782 */
783#define TX_PWR_CFG_3 0x1320
784#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
785#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
786#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
787#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
788#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
789#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
790#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
791#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
792
793/*
794 * TX_PWR_CFG_4:
795 */
796#define TX_PWR_CFG_4 0x1324
797#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
798#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
799#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
800#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
801
802/*
803 * TX_PIN_CFG:
804 */
805#define TX_PIN_CFG 0x1328
806#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
807#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
808#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
809#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
810#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
811#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
812#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
813#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
814#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
815#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
816#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
817#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
818#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
819#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
820#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
821#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
822#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
823#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
824#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
825#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
826
827/*
828 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
829 */
830#define TX_BAND_CFG 0x132c
831#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
832#define TX_BAND_CFG_A FIELD32(0x00000002)
833#define TX_BAND_CFG_BG FIELD32(0x00000004)
834
835/*
836 * TX_SW_CFG0:
837 */
838#define TX_SW_CFG0 0x1330
839
840/*
841 * TX_SW_CFG1:
842 */
843#define TX_SW_CFG1 0x1334
844
845/*
846 * TX_SW_CFG2:
847 */
848#define TX_SW_CFG2 0x1338
849
850/*
851 * TXOP_THRES_CFG:
852 */
853#define TXOP_THRES_CFG 0x133c
854
855/*
856 * TXOP_CTRL_CFG:
857 */
858#define TXOP_CTRL_CFG 0x1340
859
860/*
861 * TX_RTS_CFG:
862 * RTS_THRES: unit:byte
863 * RTS_FBK_EN: enable rts rate fallback
864 */
865#define TX_RTS_CFG 0x1344
866#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
867#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
868#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
869
870/*
871 * TX_TIMEOUT_CFG:
872 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
873 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
874 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
875 * it is recommended that:
876 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
877 */
878#define TX_TIMEOUT_CFG 0x1348
879#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
880#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
881#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
882
883/*
884 * TX_RTY_CFG:
885 * SHORT_RTY_LIMIT: short retry limit
886 * LONG_RTY_LIMIT: long retry limit
887 * LONG_RTY_THRE: Long retry threshoold
888 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
889 * 0:expired by retry limit, 1: expired by mpdu life timer
890 * AGG_RTY_MODE: Aggregate MPDU retry mode
891 * 0:expired by retry limit, 1: expired by mpdu life timer
892 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
893 */
894#define TX_RTY_CFG 0x134c
895#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
896#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
897#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
898#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
899#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
900#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
901
902/*
903 * TX_LINK_CFG:
904 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
905 * MFB_ENABLE: TX apply remote MFB 1:enable
906 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
907 * 0: not apply remote remote unsolicit (MFS=7)
908 * TX_MRQ_EN: MCS request TX enable
909 * TX_RDG_EN: RDG TX enable
910 * TX_CF_ACK_EN: Piggyback CF-ACK enable
911 * REMOTE_MFB: remote MCS feedback
912 * REMOTE_MFS: remote MCS feedback sequence number
913 */
914#define TX_LINK_CFG 0x1350
915#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
916#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
917#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
918#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
919#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
920#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
921#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
922#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
923
924/*
925 * HT_FBK_CFG0:
926 */
927#define HT_FBK_CFG0 0x1354
928#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
929#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
930#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
931#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
932#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
933#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
934#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
935#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
936
937/*
938 * HT_FBK_CFG1:
939 */
940#define HT_FBK_CFG1 0x1358
941#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
942#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
943#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
944#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
945#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
946#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
947#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
948#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
949
950/*
951 * LG_FBK_CFG0:
952 */
953#define LG_FBK_CFG0 0x135c
954#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
955#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
956#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
957#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
958#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
959#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
960#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
961#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
962
963/*
964 * LG_FBK_CFG1:
965 */
966#define LG_FBK_CFG1 0x1360
967#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
968#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
969#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
970#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
971
972/*
973 * CCK_PROT_CFG: CCK Protection
974 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
975 * PROTECT_CTRL: Protection control frame type for CCK TX
976 * 0:none, 1:RTS/CTS, 2:CTS-to-self
977 * PROTECT_NAV: TXOP protection type for CCK TX
978 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
979 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
980 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
981 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
982 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
983 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
984 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
985 * RTS_TH_EN: RTS threshold enable on CCK TX
986 */
987#define CCK_PROT_CFG 0x1364
988#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
989#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
990#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
991#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
992#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
993#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
994#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
995#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
996#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
997#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
998
999/*
1000 * OFDM_PROT_CFG: OFDM Protection
1001 */
1002#define OFDM_PROT_CFG 0x1368
1003#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1004#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1005#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1006#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1007#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1008#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1009#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1010#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1011#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1012#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1013
1014/*
1015 * MM20_PROT_CFG: MM20 Protection
1016 */
1017#define MM20_PROT_CFG 0x136c
1018#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1019#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1020#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1021#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1022#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1023#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1024#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1025#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1026#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1027#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1028
1029/*
1030 * MM40_PROT_CFG: MM40 Protection
1031 */
1032#define MM40_PROT_CFG 0x1370
1033#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1034#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1035#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1036#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1037#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1038#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1039#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1040#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1041#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1042#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1043
1044/*
1045 * GF20_PROT_CFG: GF20 Protection
1046 */
1047#define GF20_PROT_CFG 0x1374
1048#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1049#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1050#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1051#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1052#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1053#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1054#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1055#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1056#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1057#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1058
1059/*
1060 * GF40_PROT_CFG: GF40 Protection
1061 */
1062#define GF40_PROT_CFG 0x1378
1063#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1064#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1065#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1066#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1067#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1068#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1069#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1070#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1071#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1072#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1073
1074/*
1075 * EXP_CTS_TIME:
1076 */
1077#define EXP_CTS_TIME 0x137c
1078
1079/*
1080 * EXP_ACK_TIME:
1081 */
1082#define EXP_ACK_TIME 0x1380
1083
1084/*
1085 * RX_FILTER_CFG: RX configuration register.
1086 */
1087#define RX_FILTER_CFG 0x1400
1088#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1089#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1090#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1091#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1092#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1093#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1094#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1095#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1096#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1097#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1098#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1099#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1100#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1101#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1102#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1103#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1104#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1105
1106/*
1107 * AUTO_RSP_CFG:
1108 * AUTORESPONDER: 0: disable, 1: enable
1109 * BAC_ACK_POLICY: 0:long, 1:short preamble
1110 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1111 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1112 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1113 * DUAL_CTS_EN: Power bit value in control frame
1114 * ACK_CTS_PSM_BIT:Power bit value in control frame
1115 */
1116#define AUTO_RSP_CFG 0x1404
1117#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1118#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1119#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1120#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1121#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1122#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1123#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1124
1125/*
1126 * LEGACY_BASIC_RATE:
1127 */
1128#define LEGACY_BASIC_RATE 0x1408
1129
1130/*
1131 * HT_BASIC_RATE:
1132 */
1133#define HT_BASIC_RATE 0x140c
1134
1135/*
1136 * HT_CTRL_CFG:
1137 */
1138#define HT_CTRL_CFG 0x1410
1139
1140/*
1141 * SIFS_COST_CFG:
1142 */
1143#define SIFS_COST_CFG 0x1414
1144
1145/*
1146 * RX_PARSER_CFG:
1147 * Set NAV for all received frames
1148 */
1149#define RX_PARSER_CFG 0x1418
1150
1151/*
1152 * TX_SEC_CNT0:
1153 */
1154#define TX_SEC_CNT0 0x1500
1155
1156/*
1157 * RX_SEC_CNT0:
1158 */
1159#define RX_SEC_CNT0 0x1504
1160
1161/*
1162 * CCMP_FC_MUTE:
1163 */
1164#define CCMP_FC_MUTE 0x1508
1165
1166/*
1167 * TXOP_HLDR_ADDR0:
1168 */
1169#define TXOP_HLDR_ADDR0 0x1600
1170
1171/*
1172 * TXOP_HLDR_ADDR1:
1173 */
1174#define TXOP_HLDR_ADDR1 0x1604
1175
1176/*
1177 * TXOP_HLDR_ET:
1178 */
1179#define TXOP_HLDR_ET 0x1608
1180
1181/*
1182 * QOS_CFPOLL_RA_DW0:
1183 */
1184#define QOS_CFPOLL_RA_DW0 0x160c
1185
1186/*
1187 * QOS_CFPOLL_RA_DW1:
1188 */
1189#define QOS_CFPOLL_RA_DW1 0x1610
1190
1191/*
1192 * QOS_CFPOLL_QC:
1193 */
1194#define QOS_CFPOLL_QC 0x1614
1195
1196/*
1197 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1198 */
1199#define RX_STA_CNT0 0x1700
1200#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1201#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1202
1203/*
1204 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1205 */
1206#define RX_STA_CNT1 0x1704
1207#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1208#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1209
1210/*
1211 * RX_STA_CNT2:
1212 */
1213#define RX_STA_CNT2 0x1708
1214#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1215#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1216
1217/*
1218 * TX_STA_CNT0: TX Beacon count
1219 */
1220#define TX_STA_CNT0 0x170c
1221#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1222#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1223
1224/*
1225 * TX_STA_CNT1: TX tx count
1226 */
1227#define TX_STA_CNT1 0x1710
1228#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1229#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1230
1231/*
1232 * TX_STA_CNT2: TX tx count
1233 */
1234#define TX_STA_CNT2 0x1714
1235#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1236#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1237
1238/*
1239 * TX_STA_FIFO: TX Result for specific PID status fifo register
1240 */
1241#define TX_STA_FIFO 0x1718
1242#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1243#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1244#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1245#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1246#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1247#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1248#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1249#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1250
1251/*
1252 * TX_AGG_CNT: Debug counter
1253 */
1254#define TX_AGG_CNT 0x171c
1255#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1256#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1257
1258/*
1259 * TX_AGG_CNT0:
1260 */
1261#define TX_AGG_CNT0 0x1720
1262#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1263#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1264
1265/*
1266 * TX_AGG_CNT1:
1267 */
1268#define TX_AGG_CNT1 0x1724
1269#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1270#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1271
1272/*
1273 * TX_AGG_CNT2:
1274 */
1275#define TX_AGG_CNT2 0x1728
1276#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1277#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1278
1279/*
1280 * TX_AGG_CNT3:
1281 */
1282#define TX_AGG_CNT3 0x172c
1283#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1284#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1285
1286/*
1287 * TX_AGG_CNT4:
1288 */
1289#define TX_AGG_CNT4 0x1730
1290#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1291#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1292
1293/*
1294 * TX_AGG_CNT5:
1295 */
1296#define TX_AGG_CNT5 0x1734
1297#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1298#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1299
1300/*
1301 * TX_AGG_CNT6:
1302 */
1303#define TX_AGG_CNT6 0x1738
1304#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1305#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1306
1307/*
1308 * TX_AGG_CNT7:
1309 */
1310#define TX_AGG_CNT7 0x173c
1311#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1312#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1313
1314/*
1315 * MPDU_DENSITY_CNT:
1316 * TX_ZERO_DEL: TX zero length delimiter count
1317 * RX_ZERO_DEL: RX zero length delimiter count
1318 */
1319#define MPDU_DENSITY_CNT 0x1740
1320#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1321#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1322
1323/*
1324 * Security key table memory.
1325 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1326 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1327 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1328 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1329 * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry
1330 * SHARED_KEY_MODE_BASE: 4 bits * 32-entry
1331 */
1332#define MAC_WCID_BASE 0x1800
1333#define PAIRWISE_KEY_TABLE_BASE 0x4000
1334#define MAC_IVEIV_TABLE_BASE 0x6000
1335#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1336#define SHARED_KEY_TABLE_BASE 0x6c00
1337#define SHARED_KEY_MODE_BASE 0x7000
1338
1339#define MAC_WCID_ENTRY(__idx) \
1340 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1341#define PAIRWISE_KEY_ENTRY(__idx) \
1342 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1343#define MAC_IVEIV_ENTRY(__idx) \
1344 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1345#define MAC_WCID_ATTR_ENTRY(__idx) \
1346 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1347#define SHARED_KEY_ENTRY(__idx) \
1348 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1349#define SHARED_KEY_MODE_ENTRY(__idx) \
1350 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1351
1352struct mac_wcid_entry {
1353 u8 mac[6];
1354 u8 reserved[2];
1355} __attribute__ ((packed));
1356
1357struct hw_key_entry {
1358 u8 key[16];
1359 u8 tx_mic[8];
1360 u8 rx_mic[8];
1361} __attribute__ ((packed));
1362
1363struct mac_iveiv_entry {
1364 u8 iv[8];
1365} __attribute__ ((packed));
1366
1367/*
1368 * MAC_WCID_ATTRIBUTE:
1369 */
1370#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1371#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1372#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1373#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1374
1375/*
1376 * SHARED_KEY_MODE:
1377 */
1378#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1379#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1380#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1381#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1382#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1383#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1384#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1385#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1386
1387/*
1388 * HOST-MCU communication
1389 */
1390
1391/*
1392 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1393 */
1394#define H2M_MAILBOX_CSR 0x7010
1395#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1396#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1397#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1398#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1399
1400/*
1401 * H2M_MAILBOX_CID:
1402 */
1403#define H2M_MAILBOX_CID 0x7014
1404#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1405#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1406#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1407#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1408
1409/*
1410 * H2M_MAILBOX_STATUS:
1411 */
1412#define H2M_MAILBOX_STATUS 0x701c
1413
1414/*
1415 * H2M_INT_SRC:
1416 */
1417#define H2M_INT_SRC 0x7024
1418
1419/*
1420 * H2M_BBP_AGENT:
1421 */
1422#define H2M_BBP_AGENT 0x7028
1423
1424/*
1425 * MCU_LEDCS: LED control for MCU Mailbox.
1426 */
1427#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1428#define MCU_LEDCS_POLARITY FIELD8(0x01)
1429
1430/*
1431 * HW_CS_CTS_BASE:
1432 * Carrier-sense CTS frame base address.
1433 * It's where mac stores carrier-sense frame for carrier-sense function.
1434 */
1435#define HW_CS_CTS_BASE 0x7700
1436
1437/*
1438 * HW_DFS_CTS_BASE:
1439 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1440 */
1441#define HW_DFS_CTS_BASE 0x7780
1442
1443/*
1444 * TXRX control registers - base address 0x3000
1445 */
1446
1447/*
1448 * TXRX_CSR1:
1449 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1450 */
1451#define TXRX_CSR1 0x77d0
1452
1453/*
1454 * HW_DEBUG_SETTING_BASE:
1455 * since NULL frame won't be that long (256 byte)
1456 * We steal 16 tail bytes to save debugging settings
1457 */
1458#define HW_DEBUG_SETTING_BASE 0x77f0
1459#define HW_DEBUG_SETTING_BASE2 0x7770
1460
1461/*
1462 * HW_BEACON_BASE
1463 * In order to support maximum 8 MBSS and its maximum length
1464 * is 512 bytes for each beacon
1465 * Three section discontinue memory segments will be used.
1466 * 1. The original region for BCN 0~3
1467 * 2. Extract memory from FCE table for BCN 4~5
1468 * 3. Extract memory from Pair-wise key table for BCN 6~7
1469 * It occupied those memory of wcid 238~253 for BCN 6
1470 * and wcid 222~237 for BCN 7
1471 *
1472 * IMPORTANT NOTE: Not sure why legacy driver does this,
1473 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1474 */
1475#define HW_BEACON_BASE0 0x7800
1476#define HW_BEACON_BASE1 0x7a00
1477#define HW_BEACON_BASE2 0x7c00
1478#define HW_BEACON_BASE3 0x7e00
1479#define HW_BEACON_BASE4 0x7200
1480#define HW_BEACON_BASE5 0x7400
1481#define HW_BEACON_BASE6 0x5dc0
1482#define HW_BEACON_BASE7 0x5bc0
1483
1484#define HW_BEACON_OFFSET(__index) \
1485 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1486 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1487 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1488
1489/*
1490 * 8051 firmware image. 87 * 8051 firmware image.
1491 */ 88 */
1492#define FIRMWARE_RT2860 "rt2860.bin" 89#define FIRMWARE_RT2860 "rt2860.bin"
1493#define FIRMWARE_IMAGE_BASE 0x2000 90#define FIRMWARE_IMAGE_BASE 0x2000
1494 91
1495/* 92/*
1496 * BBP registers.
1497 * The wordsize of the BBP is 8 bits.
1498 */
1499
1500/*
1501 * BBP 1: TX Antenna
1502 */
1503#define BBP1_TX_POWER FIELD8(0x07)
1504#define BBP1_TX_ANTENNA FIELD8(0x18)
1505
1506/*
1507 * BBP 3: RX Antenna
1508 */
1509#define BBP3_RX_ANTENNA FIELD8(0x18)
1510#define BBP3_HT40_PLUS FIELD8(0x20)
1511
1512/*
1513 * BBP 4: Bandwidth
1514 */
1515#define BBP4_TX_BF FIELD8(0x01)
1516#define BBP4_BANDWIDTH FIELD8(0x18)
1517
1518/*
1519 * RFCSR registers
1520 * The wordsize of the RFCSR is 8 bits.
1521 */
1522
1523/*
1524 * RFCSR 6:
1525 */
1526#define RFCSR6_R FIELD8(0x03)
1527
1528/*
1529 * RFCSR 7:
1530 */
1531#define RFCSR7_RF_TUNING FIELD8(0x01)
1532
1533/*
1534 * RFCSR 12:
1535 */
1536#define RFCSR12_TX_POWER FIELD8(0x1f)
1537
1538/*
1539 * RFCSR 22:
1540 */
1541#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1542
1543/*
1544 * RFCSR 23:
1545 */
1546#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1547
1548/*
1549 * RFCSR 30:
1550 */
1551#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1552
1553/*
1554 * RF registers
1555 */
1556
1557/*
1558 * RF 2
1559 */
1560#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1561#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1562#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1563
1564/*
1565 * RF 3
1566 */
1567#define RF3_TXPOWER_G FIELD32(0x00003e00)
1568#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1569#define RF3_TXPOWER_A FIELD32(0x00003c00)
1570
1571/*
1572 * RF 4
1573 */
1574#define RF4_TXPOWER_G FIELD32(0x000007c0)
1575#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1576#define RF4_TXPOWER_A FIELD32(0x00000780)
1577#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1578#define RF4_HT40 FIELD32(0x00200000)
1579
1580/*
1581 * EEPROM content.
1582 * The wordsize of the EEPROM is 16 bits.
1583 */
1584
1585/*
1586 * EEPROM Version
1587 */
1588#define EEPROM_VERSION 0x0001
1589#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1590#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1591
1592/*
1593 * HW MAC address.
1594 */
1595#define EEPROM_MAC_ADDR_0 0x0002
1596#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1597#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1598#define EEPROM_MAC_ADDR_1 0x0003
1599#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1600#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1601#define EEPROM_MAC_ADDR_2 0x0004
1602#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1603#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1604
1605/*
1606 * EEPROM ANTENNA config
1607 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1608 * TXPATH: 1: 1T, 2: 2T
1609 */
1610#define EEPROM_ANTENNA 0x001a
1611#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1612#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1613#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1614
1615/*
1616 * EEPROM NIC config
1617 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1618 */
1619#define EEPROM_NIC 0x001b
1620#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1621#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1622#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1623#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1624#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1625#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1626#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1627#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1628#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1629#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1630
1631/*
1632 * EEPROM frequency
1633 */
1634#define EEPROM_FREQ 0x001d
1635#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1636#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1637#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1638
1639/*
1640 * EEPROM LED
1641 * POLARITY_RDY_G: Polarity RDY_G setting.
1642 * POLARITY_RDY_A: Polarity RDY_A setting.
1643 * POLARITY_ACT: Polarity ACT setting.
1644 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1645 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1646 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1647 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1648 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1649 * LED_MODE: Led mode.
1650 */
1651#define EEPROM_LED1 0x001e
1652#define EEPROM_LED2 0x001f
1653#define EEPROM_LED3 0x0020
1654#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1655#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1656#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1657#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1658#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1659#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1660#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1661#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1662#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1663
1664/*
1665 * EEPROM LNA
1666 */
1667#define EEPROM_LNA 0x0022
1668#define EEPROM_LNA_BG FIELD16(0x00ff)
1669#define EEPROM_LNA_A0 FIELD16(0xff00)
1670
1671/*
1672 * EEPROM RSSI BG offset
1673 */
1674#define EEPROM_RSSI_BG 0x0023
1675#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1676#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1677
1678/*
1679 * EEPROM RSSI BG2 offset
1680 */
1681#define EEPROM_RSSI_BG2 0x0024
1682#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1683#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1684
1685/*
1686 * EEPROM RSSI A offset
1687 */
1688#define EEPROM_RSSI_A 0x0025
1689#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1690#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1691
1692/*
1693 * EEPROM RSSI A2 offset
1694 */
1695#define EEPROM_RSSI_A2 0x0026
1696#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1697#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1698
1699/*
1700 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1701 * This is delta in 40MHZ.
1702 * VALUE: Tx Power dalta value (MAX=4)
1703 * TYPE: 1: Plus the delta value, 0: minus the delta value
1704 * TXPOWER: Enable:
1705 */
1706#define EEPROM_TXPOWER_DELTA 0x0028
1707#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1708#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1709#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1710
1711/*
1712 * EEPROM TXPOWER 802.11BG
1713 */
1714#define EEPROM_TXPOWER_BG1 0x0029
1715#define EEPROM_TXPOWER_BG2 0x0030
1716#define EEPROM_TXPOWER_BG_SIZE 7
1717#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1718#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1719
1720/*
1721 * EEPROM TXPOWER 802.11A
1722 */
1723#define EEPROM_TXPOWER_A1 0x003c
1724#define EEPROM_TXPOWER_A2 0x0053
1725#define EEPROM_TXPOWER_A_SIZE 6
1726#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1727#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1728
1729/*
1730 * EEPROM TXpower byrate: 20MHZ power
1731 */
1732#define EEPROM_TXPOWER_BYRATE 0x006f
1733
1734/*
1735 * EEPROM BBP.
1736 */
1737#define EEPROM_BBP_START 0x0078
1738#define EEPROM_BBP_SIZE 16
1739#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1740#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1741
1742/*
1743 * MCU mailbox commands.
1744 */
1745#define MCU_SLEEP 0x30
1746#define MCU_WAKEUP 0x31
1747#define MCU_RADIO_OFF 0x35
1748#define MCU_CURRENT 0x36
1749#define MCU_LED 0x50
1750#define MCU_LED_STRENGTH 0x51
1751#define MCU_LED_1 0x52
1752#define MCU_LED_2 0x53
1753#define MCU_LED_3 0x54
1754#define MCU_RADAR 0x60
1755#define MCU_BOOT_SIGNAL 0x72
1756#define MCU_BBP_SIGNAL 0x80
1757#define MCU_POWER_SAVE 0x83
1758
1759/*
1760 * MCU mailbox tokens
1761 */
1762#define TOKEN_WAKUP 3
1763
1764/*
1765 * DMA descriptor defines. 93 * DMA descriptor defines.
1766 */ 94 */
1767#define TXD_DESC_SIZE ( 4 * sizeof(__le32) ) 95#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1768#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1769#define RXD_DESC_SIZE ( 4 * sizeof(__le32) ) 96#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
1770#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1771 97
1772/* 98/*
1773 * TX descriptor format for TX, PRIO and Beacon Ring. 99 * TX descriptor format for TX, PRIO and Beacon Ring.
@@ -1806,52 +132,6 @@ struct mac_iveiv_entry {
1806#define TXD_W3_ICO FIELD32(0x80000000) 132#define TXD_W3_ICO FIELD32(0x80000000)
1807 133
1808/* 134/*
1809 * TX WI structure
1810 */
1811
1812/*
1813 * Word0
1814 * FRAG: 1 To inform TKIP engine this is a fragment.
1815 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1816 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1817 * BW: Channel bandwidth 20MHz or 40 MHz
1818 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1819 */
1820#define TXWI_W0_FRAG FIELD32(0x00000001)
1821#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1822#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1823#define TXWI_W0_TS FIELD32(0x00000008)
1824#define TXWI_W0_AMPDU FIELD32(0x00000010)
1825#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1826#define TXWI_W0_TX_OP FIELD32(0x00000300)
1827#define TXWI_W0_MCS FIELD32(0x007f0000)
1828#define TXWI_W0_BW FIELD32(0x00800000)
1829#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1830#define TXWI_W0_STBC FIELD32(0x06000000)
1831#define TXWI_W0_IFS FIELD32(0x08000000)
1832#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1833
1834/*
1835 * Word1
1836 */
1837#define TXWI_W1_ACK FIELD32(0x00000001)
1838#define TXWI_W1_NSEQ FIELD32(0x00000002)
1839#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1840#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1841#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1842#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1843
1844/*
1845 * Word2
1846 */
1847#define TXWI_W2_IV FIELD32(0xffffffff)
1848
1849/*
1850 * Word3
1851 */
1852#define TXWI_W3_EIV FIELD32(0xffffffff)
1853
1854/*
1855 * RX descriptor format for RX Ring. 135 * RX descriptor format for RX Ring.
1856 */ 136 */
1857 137
@@ -1897,64 +177,4 @@ struct mac_iveiv_entry {
1897#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000) 177#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
1898#define RXD_W3_PLCP_RSSI FIELD32(0x00040000) 178#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
1899 179
1900/*
1901 * RX WI structure
1902 */
1903
1904/*
1905 * Word0
1906 */
1907#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1908#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1909#define RXWI_W0_BSSID FIELD32(0x00001c00)
1910#define RXWI_W0_UDF FIELD32(0x0000e000)
1911#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1912#define RXWI_W0_TID FIELD32(0xf0000000)
1913
1914/*
1915 * Word1
1916 */
1917#define RXWI_W1_FRAG FIELD32(0x0000000f)
1918#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1919#define RXWI_W1_MCS FIELD32(0x007f0000)
1920#define RXWI_W1_BW FIELD32(0x00800000)
1921#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1922#define RXWI_W1_STBC FIELD32(0x06000000)
1923#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1924
1925/*
1926 * Word2
1927 */
1928#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1929#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1930#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1931
1932/*
1933 * Word3
1934 */
1935#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1936#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1937
1938/*
1939 * Macros for converting txpower from EEPROM to mac80211 value
1940 * and from mac80211 value to register value.
1941 */
1942#define MIN_G_TXPOWER 0
1943#define MIN_A_TXPOWER -7
1944#define MAX_G_TXPOWER 31
1945#define MAX_A_TXPOWER 15
1946#define DEFAULT_TXPOWER 5
1947
1948#define TXPOWER_G_FROM_DEV(__txpower) \
1949 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1950
1951#define TXPOWER_G_TO_DEV(__txpower) \
1952 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1953
1954#define TXPOWER_A_FROM_DEV(__txpower) \
1955 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1956
1957#define TXPOWER_A_TO_DEV(__txpower) \
1958 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1959
1960#endif /* RT2800PCI_H */ 180#endif /* RT2800PCI_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 9fe770f7d7bb..ce2e893856c1 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -34,6 +34,8 @@
34 34
35#include "rt2x00.h" 35#include "rt2x00.h"
36#include "rt2x00usb.h" 36#include "rt2x00usb.h"
37#include "rt2800lib.h"
38#include "rt2800.h"
37#include "rt2800usb.h" 39#include "rt2800usb.h"
38 40
39/* 41/*
@@ -44,1027 +46,6 @@ module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 46MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45 47
46/* 48/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the new data into the register.
80 */
81 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82 reg = 0;
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89 }
90
91 mutex_unlock(&rt2x00dev->csr_mutex);
92}
93
94static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95 const unsigned int word, u8 *value)
96{
97 u32 reg;
98
99 mutex_lock(&rt2x00dev->csr_mutex);
100
101 /*
102 * Wait until the BBP becomes available, afterwards we
103 * can safely write the read request into the register.
104 * After the data has been written, we wait until hardware
105 * returns the correct value, if at any time the register
106 * doesn't become available in time, reg will be 0xffffffff
107 * which means we return 0xff to the caller.
108 */
109 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 reg = 0;
111 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117 WAIT_FOR_BBP(rt2x00dev, &reg);
118 }
119
120 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122 mutex_unlock(&rt2x00dev->csr_mutex);
123}
124
125static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->csr_mutex);
131
132 /*
133 * Wait until the RFCSR becomes available, afterwards we
134 * can safely write the new data into the register.
135 */
136 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137 reg = 0;
138 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144 }
145
146 mutex_unlock(&rt2x00dev->csr_mutex);
147}
148
149static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150 const unsigned int word, u8 *value)
151{
152 u32 reg;
153
154 mutex_lock(&rt2x00dev->csr_mutex);
155
156 /*
157 * Wait until the RFCSR becomes available, afterwards we
158 * can safely write the read request into the register.
159 * After the data has been written, we wait until hardware
160 * returns the correct value, if at any time the register
161 * doesn't become available in time, reg will be 0xffffffff
162 * which means we return 0xff to the caller.
163 */
164 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165 reg = 0;
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173 }
174
175 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177 mutex_unlock(&rt2x00dev->csr_mutex);
178}
179
180static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181 const unsigned int word, const u32 value)
182{
183 u32 reg;
184
185 mutex_lock(&rt2x00dev->csr_mutex);
186
187 /*
188 * Wait until the RF becomes available, afterwards we
189 * can safely write the new data into the register.
190 */
191 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199 rt2x00_rf_write(rt2x00dev, word, value);
200 }
201
202 mutex_unlock(&rt2x00dev->csr_mutex);
203}
204
205static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206 const u8 command, const u8 token,
207 const u8 arg0, const u8 arg1)
208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the MCU becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224 reg = 0;
225 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
233static const struct rt2x00debug rt2800usb_rt2x00debug = {
234 .owner = THIS_MODULE,
235 .csr = {
236 .read = rt2x00usb_register_read,
237 .write = rt2x00usb_register_write,
238 .flags = RT2X00DEBUGFS_OFFSET,
239 .word_base = CSR_REG_BASE,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_base = EEPROM_BASE,
247 .word_size = sizeof(u16),
248 .word_count = EEPROM_SIZE / sizeof(u16),
249 },
250 .bbp = {
251 .read = rt2800usb_bbp_read,
252 .write = rt2800usb_bbp_write,
253 .word_base = BBP_BASE,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt2800usb_rf_write,
260 .word_base = RF_BASE,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
268{
269 u32 reg;
270
271 rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
272 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
273}
274
275#ifdef CONFIG_RT2X00_LIB_LEDS
276static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
277 enum led_brightness brightness)
278{
279 struct rt2x00_led *led =
280 container_of(led_cdev, struct rt2x00_led, led_dev);
281 unsigned int enabled = brightness != LED_OFF;
282 unsigned int bg_mode =
283 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
284 unsigned int polarity =
285 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
286 EEPROM_FREQ_LED_POLARITY);
287 unsigned int ledmode =
288 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
289 EEPROM_FREQ_LED_MODE);
290
291 if (led->type == LED_TYPE_RADIO) {
292 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
293 enabled ? 0x20 : 0);
294 } else if (led->type == LED_TYPE_ASSOC) {
295 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
296 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
297 } else if (led->type == LED_TYPE_QUALITY) {
298 /*
299 * The brightness is divided into 6 levels (0 - 5),
300 * The specs tell us the following levels:
301 * 0, 1 ,3, 7, 15, 31
302 * to determine the level in a simple way we can simply
303 * work with bitshifting:
304 * (1 << level) - 1
305 */
306 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
307 (1 << brightness / (LED_FULL / 6)) - 1,
308 polarity);
309 }
310}
311
312static int rt2800usb_blink_set(struct led_classdev *led_cdev,
313 unsigned long *delay_on,
314 unsigned long *delay_off)
315{
316 struct rt2x00_led *led =
317 container_of(led_cdev, struct rt2x00_led, led_dev);
318 u32 reg;
319
320 rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
321 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
322 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
323 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
324 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
325 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
326 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
327 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
328 rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
329
330 return 0;
331}
332
333static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
334 struct rt2x00_led *led,
335 enum led_type type)
336{
337 led->rt2x00dev = rt2x00dev;
338 led->type = type;
339 led->led_dev.brightness_set = rt2800usb_brightness_set;
340 led->led_dev.blink_set = rt2800usb_blink_set;
341 led->flags = LED_INITIALIZED;
342}
343#endif /* CONFIG_RT2X00_LIB_LEDS */
344
345/*
346 * Configuration handlers.
347 */
348static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
349 struct rt2x00lib_crypto *crypto,
350 struct ieee80211_key_conf *key)
351{
352 struct mac_wcid_entry wcid_entry;
353 struct mac_iveiv_entry iveiv_entry;
354 u32 offset;
355 u32 reg;
356
357 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
358
359 rt2x00usb_register_read(rt2x00dev, offset, &reg);
360 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
361 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
362 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
363 (crypto->cmd == SET_KEY) * crypto->cipher);
364 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
365 (crypto->cmd == SET_KEY) * crypto->bssidx);
366 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
367 rt2x00usb_register_write(rt2x00dev, offset, reg);
368
369 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
370
371 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
372 if ((crypto->cipher == CIPHER_TKIP) ||
373 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
374 (crypto->cipher == CIPHER_AES))
375 iveiv_entry.iv[3] |= 0x20;
376 iveiv_entry.iv[3] |= key->keyidx << 6;
377 rt2x00usb_register_multiwrite(rt2x00dev, offset,
378 &iveiv_entry, sizeof(iveiv_entry));
379
380 offset = MAC_WCID_ENTRY(key->hw_key_idx);
381
382 memset(&wcid_entry, 0, sizeof(wcid_entry));
383 if (crypto->cmd == SET_KEY)
384 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
385 rt2x00usb_register_multiwrite(rt2x00dev, offset,
386 &wcid_entry, sizeof(wcid_entry));
387}
388
389static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
390 struct rt2x00lib_crypto *crypto,
391 struct ieee80211_key_conf *key)
392{
393 struct hw_key_entry key_entry;
394 struct rt2x00_field32 field;
395 int timeout;
396 u32 offset;
397 u32 reg;
398
399 if (crypto->cmd == SET_KEY) {
400 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
401
402 memcpy(key_entry.key, crypto->key,
403 sizeof(key_entry.key));
404 memcpy(key_entry.tx_mic, crypto->tx_mic,
405 sizeof(key_entry.tx_mic));
406 memcpy(key_entry.rx_mic, crypto->rx_mic,
407 sizeof(key_entry.rx_mic));
408
409 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
410 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
411 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
412 USB_VENDOR_REQUEST_OUT,
413 offset, &key_entry,
414 sizeof(key_entry),
415 timeout);
416 }
417
418 /*
419 * The cipher types are stored over multiple registers
420 * starting with SHARED_KEY_MODE_BASE each word will have
421 * 32 bits and contains the cipher types for 2 bssidx each.
422 * Using the correct defines correctly will cause overhead,
423 * so just calculate the correct offset.
424 */
425 field.bit_offset = 4 * (key->hw_key_idx % 8);
426 field.bit_mask = 0x7 << field.bit_offset;
427
428 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
429
430 rt2x00usb_register_read(rt2x00dev, offset, &reg);
431 rt2x00_set_field32(&reg, field,
432 (crypto->cmd == SET_KEY) * crypto->cipher);
433 rt2x00usb_register_write(rt2x00dev, offset, reg);
434
435 /*
436 * Update WCID information
437 */
438 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
439
440 return 0;
441}
442
443static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
444 struct rt2x00lib_crypto *crypto,
445 struct ieee80211_key_conf *key)
446{
447 struct hw_key_entry key_entry;
448 int timeout;
449 u32 offset;
450
451 if (crypto->cmd == SET_KEY) {
452 /*
453 * 1 pairwise key is possible per AID, this means that the AID
454 * equals our hw_key_idx. Make sure the WCID starts _after_ the
455 * last possible shared key entry.
456 */
457 if (crypto->aid > (256 - 32))
458 return -ENOSPC;
459
460 key->hw_key_idx = 32 + crypto->aid;
461
462 memcpy(key_entry.key, crypto->key,
463 sizeof(key_entry.key));
464 memcpy(key_entry.tx_mic, crypto->tx_mic,
465 sizeof(key_entry.tx_mic));
466 memcpy(key_entry.rx_mic, crypto->rx_mic,
467 sizeof(key_entry.rx_mic));
468
469 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
470 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
471 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
472 USB_VENDOR_REQUEST_OUT,
473 offset, &key_entry,
474 sizeof(key_entry),
475 timeout);
476 }
477
478 /*
479 * Update WCID information
480 */
481 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
482
483 return 0;
484}
485
486static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
487 const unsigned int filter_flags)
488{
489 u32 reg;
490
491 /*
492 * Start configuration steps.
493 * Note that the version error will always be dropped
494 * and broadcast frames will always be accepted since
495 * there is no filter for it at this time.
496 */
497 rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
498 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
499 !(filter_flags & FIF_FCSFAIL));
500 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
501 !(filter_flags & FIF_PLCPFAIL));
502 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
503 !(filter_flags & FIF_PROMISC_IN_BSS));
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
505 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
507 !(filter_flags & FIF_ALLMULTI));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
511 !(filter_flags & FIF_CONTROL));
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
513 !(filter_flags & FIF_CONTROL));
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
515 !(filter_flags & FIF_CONTROL));
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
521 !(filter_flags & FIF_PSPOLL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
523 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
527}
528
529static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
530 struct rt2x00_intf *intf,
531 struct rt2x00intf_conf *conf,
532 const unsigned int flags)
533{
534 unsigned int beacon_base;
535 u32 reg;
536
537 if (flags & CONFIG_UPDATE_TYPE) {
538 /*
539 * Clear current synchronisation setup.
540 * For the Beacon base registers we only need to clear
541 * the first byte since that byte contains the VALID and OWNER
542 * bits which (when set to 0) will invalidate the entire beacon.
543 */
544 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
545 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
546
547 /*
548 * Enable synchronisation.
549 */
550 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
551 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
552 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
553 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
554 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
555 }
556
557 if (flags & CONFIG_UPDATE_MAC) {
558 reg = le32_to_cpu(conf->mac[1]);
559 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
560 conf->mac[1] = cpu_to_le32(reg);
561
562 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
563 conf->mac, sizeof(conf->mac));
564 }
565
566 if (flags & CONFIG_UPDATE_BSSID) {
567 reg = le32_to_cpu(conf->bssid[1]);
568 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
569 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
570 conf->bssid[1] = cpu_to_le32(reg);
571
572 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
573 conf->bssid, sizeof(conf->bssid));
574 }
575}
576
577static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
578 struct rt2x00lib_erp *erp)
579{
580 u32 reg;
581
582 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
583 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
584 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
585
586 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
587 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
588 !!erp->short_preamble);
589 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
590 !!erp->short_preamble);
591 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
592
593 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
594 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
595 erp->cts_protection ? 2 : 0);
596 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
597
598 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
599 erp->basic_rates);
600 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
601
602 rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
603 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
604 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
605 rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
606
607 rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
608 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
609 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
610 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
611 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
612 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
613 rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
614
615 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
616 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
617 erp->beacon_int * 16);
618 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
619}
620
621static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
622 struct antenna_setup *ant)
623{
624 u8 r1;
625 u8 r3;
626
627 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
628 rt2800usb_bbp_read(rt2x00dev, 3, &r3);
629
630 /*
631 * Configure the TX antenna.
632 */
633 switch ((int)ant->tx) {
634 case 1:
635 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
636 break;
637 case 2:
638 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
639 break;
640 case 3:
641 /* Do nothing */
642 break;
643 }
644
645 /*
646 * Configure the RX antenna.
647 */
648 switch ((int)ant->rx) {
649 case 1:
650 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
651 break;
652 case 2:
653 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
654 break;
655 case 3:
656 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
657 break;
658 }
659
660 rt2800usb_bbp_write(rt2x00dev, 3, r3);
661 rt2800usb_bbp_write(rt2x00dev, 1, r1);
662}
663
664static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
665 struct rt2x00lib_conf *libconf)
666{
667 u16 eeprom;
668 short lna_gain;
669
670 if (libconf->rf.channel <= 14) {
671 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
672 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
673 } else if (libconf->rf.channel <= 64) {
674 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
676 } else if (libconf->rf.channel <= 128) {
677 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
678 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
679 } else {
680 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
681 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
682 }
683
684 rt2x00dev->lna_gain = lna_gain;
685}
686
687static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
688 struct ieee80211_conf *conf,
689 struct rf_channel *rf,
690 struct channel_info *info)
691{
692 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
693
694 if (rt2x00dev->default_ant.tx == 1)
695 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
696
697 if (rt2x00dev->default_ant.rx == 1) {
698 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
699 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
700 } else if (rt2x00dev->default_ant.rx == 2)
701 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
702
703 if (rf->channel > 14) {
704 /*
705 * When TX power is below 0, we should increase it by 7 to
706 * make it a positive value (Minumum value is -7).
707 * However this means that values between 0 and 7 have
708 * double meaning, and we should set a 7DBm boost flag.
709 */
710 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
711 (info->tx_power1 >= 0));
712
713 if (info->tx_power1 < 0)
714 info->tx_power1 += 7;
715
716 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
717 TXPOWER_A_TO_DEV(info->tx_power1));
718
719 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
720 (info->tx_power2 >= 0));
721
722 if (info->tx_power2 < 0)
723 info->tx_power2 += 7;
724
725 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
726 TXPOWER_A_TO_DEV(info->tx_power2));
727 } else {
728 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
729 TXPOWER_G_TO_DEV(info->tx_power1));
730 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
731 TXPOWER_G_TO_DEV(info->tx_power2));
732 }
733
734 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
735
736 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
737 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
738 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
739 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
740
741 udelay(200);
742
743 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
744 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
745 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
746 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
747
748 udelay(200);
749
750 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
751 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
752 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
753 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
754}
755
756static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
757 struct ieee80211_conf *conf,
758 struct rf_channel *rf,
759 struct channel_info *info)
760{
761 u8 rfcsr;
762
763 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
764 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
765
766 rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
767 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
768 rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
769
770 rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
771 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
772 TXPOWER_G_TO_DEV(info->tx_power1));
773 rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
774
775 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
776 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
777 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
778
779 rt2800usb_rfcsr_write(rt2x00dev, 24,
780 rt2x00dev->calibration[conf_is_ht40(conf)]);
781
782 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
783 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
784 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
785}
786
787static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
788 struct ieee80211_conf *conf,
789 struct rf_channel *rf,
790 struct channel_info *info)
791{
792 u32 reg;
793 unsigned int tx_pin;
794 u8 bbp;
795
796 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
797 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
798 else
799 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
800
801 /*
802 * Change BBP settings
803 */
804 rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
805 rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
806 rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
807 rt2800usb_bbp_write(rt2x00dev, 86, 0);
808
809 if (rf->channel <= 14) {
810 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
811 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
812 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
813 } else {
814 rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
815 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
816 }
817 } else {
818 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
819
820 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
821 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
822 else
823 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
824 }
825
826 rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
827 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
828 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
829 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
830 rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
831
832 tx_pin = 0;
833
834 /* Turn on unused PA or LNA when not using 1T or 1R */
835 if (rt2x00dev->default_ant.tx != 1) {
836 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
837 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
838 }
839
840 /* Turn on unused PA or LNA when not using 1T or 1R */
841 if (rt2x00dev->default_ant.rx != 1) {
842 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
843 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
844 }
845
846 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
848 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
849 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
852
853 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
854
855 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
856 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
857 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
858
859 rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
860 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
861 rt2800usb_bbp_write(rt2x00dev, 3, bbp);
862
863 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
864 if (conf_is_ht40(conf)) {
865 rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
866 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
867 rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
868 } else {
869 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
870 rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
871 rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
872 }
873 }
874
875 msleep(1);
876}
877
878static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
879 const int txpower)
880{
881 u32 reg;
882 u32 value = TXPOWER_G_TO_DEV(txpower);
883 u8 r1;
884
885 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
886 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
887 rt2800usb_bbp_write(rt2x00dev, 1, r1);
888
889 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
890 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
891 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
892 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
893 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
894 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
895 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
896 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
897 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
898 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
899
900 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
906 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
909 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
910
911 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
917 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
920 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
921
922 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
931 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
932
933 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
938 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
939}
940
941static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 u32 reg;
945
946 rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
947 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
948 libconf->conf->short_frame_max_tx_count);
949 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
950 libconf->conf->long_frame_max_tx_count);
951 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
952 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
953 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
954 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
955 rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
956}
957
958static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
959 struct rt2x00lib_conf *libconf)
960{
961 enum dev_state state =
962 (libconf->conf->flags & IEEE80211_CONF_PS) ?
963 STATE_SLEEP : STATE_AWAKE;
964 u32 reg;
965
966 if (state == STATE_SLEEP) {
967 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
968
969 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
970 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
971 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
972 libconf->conf->listen_interval - 1);
973 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
974 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
975
976 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
977 } else {
978 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
979
980 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
982 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
983 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
984 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
985 }
986}
987
988static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
989 struct rt2x00lib_conf *libconf,
990 const unsigned int flags)
991{
992 /* Always recalculate LNA gain before changing configuration */
993 rt2800usb_config_lna_gain(rt2x00dev, libconf);
994
995 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
996 rt2800usb_config_channel(rt2x00dev, libconf->conf,
997 &libconf->rf, &libconf->channel);
998 if (flags & IEEE80211_CONF_CHANGE_POWER)
999 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1000 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1001 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1002 if (flags & IEEE80211_CONF_CHANGE_PS)
1003 rt2800usb_config_ps(rt2x00dev, libconf);
1004}
1005
1006/*
1007 * Link tuning
1008 */
1009static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1010 struct link_qual *qual)
1011{
1012 u32 reg;
1013
1014 /*
1015 * Update FCS error count from register.
1016 */
1017 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1018 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1019}
1020
1021static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1022{
1023 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1024 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1025 return 0x1c + (2 * rt2x00dev->lna_gain);
1026 else
1027 return 0x2e + rt2x00dev->lna_gain;
1028 }
1029
1030 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1031 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1032 else
1033 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1034}
1035
1036static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1037 struct link_qual *qual, u8 vgc_level)
1038{
1039 if (qual->vgc_level != vgc_level) {
1040 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1041 qual->vgc_level = vgc_level;
1042 qual->vgc_level_reg = vgc_level;
1043 }
1044}
1045
1046static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1047 struct link_qual *qual)
1048{
1049 rt2800usb_set_vgc(rt2x00dev, qual,
1050 rt2800usb_get_default_vgc(rt2x00dev));
1051}
1052
1053static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1054 struct link_qual *qual, const u32 count)
1055{
1056 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1057 return;
1058
1059 /*
1060 * When RSSI is better then -80 increase VGC level with 0x10
1061 */
1062 rt2800usb_set_vgc(rt2x00dev, qual,
1063 rt2800usb_get_default_vgc(rt2x00dev) +
1064 ((qual->rssi > -80) * 0x10));
1065}
1066
1067/*
1068 * Firmware functions 49 * Firmware functions
1069 */ 50 */
1070static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) 51static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1172,7 +153,7 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1172 * Wait for stable hardware. 153 * Wait for stable hardware.
1173 */ 154 */
1174 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 155 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1175 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 156 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1176 if (reg && reg != ~0) 157 if (reg && reg != ~0)
1177 break; 158 break;
1178 msleep(1); 159 msleep(1);
@@ -1192,8 +173,8 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1192 data + offset, length, 173 data + offset, length,
1193 REGISTER_TIMEOUT32(length)); 174 REGISTER_TIMEOUT32(length));
1194 175
1195 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 176 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1196 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 177 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1197 178
1198 /* 179 /*
1199 * Send firmware request to device to load firmware, 180 * Send firmware request to device to load firmware,
@@ -1208,18 +189,18 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1208 } 189 }
1209 190
1210 msleep(10); 191 msleep(10);
1211 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 192 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1212 193
1213 /* 194 /*
1214 * Send signal to firmware during boot time. 195 * Send signal to firmware during boot time.
1215 */ 196 */
1216 rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); 197 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1217 198
1218 if ((chipset == 0x3070) || 199 if ((chipset == 0x3070) ||
1219 (chipset == 0x3071) || 200 (chipset == 0x3071) ||
1220 (chipset == 0x3572)) { 201 (chipset == 0x3572)) {
1221 udelay(200); 202 udelay(200);
1222 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0); 203 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1223 udelay(10); 204 udelay(10);
1224 } 205 }
1225 206
@@ -1227,7 +208,7 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1227 * Wait for device to stabilize. 208 * Wait for device to stabilize.
1228 */ 209 */
1229 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 210 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1230 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 211 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1231 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 212 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1232 break; 213 break;
1233 msleep(1); 214 msleep(1);
@@ -1241,536 +222,14 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1241 /* 222 /*
1242 * Initialize firmware. 223 * Initialize firmware.
1243 */ 224 */
1244 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 225 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1245 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 226 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1246 msleep(1); 227 msleep(1);
1247 228
1248 return 0; 229 return 0;
1249} 230}
1250 231
1251/* 232/*
1252 * Initialization functions.
1253 */
1254static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1255{
1256 u32 reg;
1257 unsigned int i;
1258
1259 /*
1260 * Wait untill BBP and RF are ready.
1261 */
1262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1263 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1264 if (reg && reg != ~0)
1265 break;
1266 msleep(1);
1267 }
1268
1269 if (i == REGISTER_BUSY_COUNT) {
1270 ERROR(rt2x00dev, "Unstable hardware.\n");
1271 return -EBUSY;
1272 }
1273
1274 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1275 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1276
1277 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1278 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1279 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1280 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1281
1282 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1283
1284 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1285 USB_MODE_RESET, REGISTER_TIMEOUT);
1286
1287 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1288
1289 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1290 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1291 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1292 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1293 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1294 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1295
1296 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1297 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1298 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1299 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1300 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1301 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1302
1303 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1304 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1305
1306 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1307
1308 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1309 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1310 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1311 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1312 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1313 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1314 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1315 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1316
1317 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1318 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1319 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1320 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1321 } else {
1322 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1323 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1324 }
1325
1326 rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1327 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1328 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1329 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1330 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1331 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1332 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1333 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1334 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1335 rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1336
1337 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1338 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1339 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1340 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1341
1342 rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1343 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1344 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1345 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1346 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1347 else
1348 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1349 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1350 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1351 rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1352
1353 rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1354
1355 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1356 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1357 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1358 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1359 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1360 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1361 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1362
1363 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1364 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1365 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1366 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1367 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1368 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1369 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1370 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1371 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1372 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1373 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1374
1375 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1376 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1377 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1378 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1379 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1380 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1381 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1382 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1383 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1384 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1385 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1386
1387 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1388 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1389 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1390 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1391 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1392 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1393 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1394 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1395 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1396 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1397 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1398
1399 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1400 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1401 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1402 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1403 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1404 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1405 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1406 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1407 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1408 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1409 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1410
1411 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1412 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1413 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1414 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1415 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1416 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1417 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1418 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1419 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1420 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1421 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1422
1423 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1424 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1425 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1426 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1427 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1428 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1429 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1430 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1431 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1432 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1433 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1434
1435 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1436
1437 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1438 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1439 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1440 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1441 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1442 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1443 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1444 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1445 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1446 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1447 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1448
1449 rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1450 rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1451
1452 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1453 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1454 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1455 IEEE80211_MAX_RTS_THRESHOLD);
1456 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1457 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1458
1459 rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1460 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1461
1462 /*
1463 * ASIC will keep garbage value after boot, clear encryption keys.
1464 */
1465 for (i = 0; i < 4; i++)
1466 rt2x00usb_register_write(rt2x00dev,
1467 SHARED_KEY_MODE_ENTRY(i), 0);
1468
1469 for (i = 0; i < 256; i++) {
1470 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1471 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1472 wcid, sizeof(wcid));
1473
1474 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1475 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1476 }
1477
1478 /*
1479 * Clear all beacons
1480 * For the Beacon base registers we only need to clear
1481 * the first byte since that byte contains the VALID and OWNER
1482 * bits which (when set to 0) will invalidate the entire beacon.
1483 */
1484 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1485 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1486 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1487 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1488 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1489 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1490 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1491 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1492
1493 rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1494 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1495 rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1496
1497 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1498 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1499 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1500 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1501 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1502 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1503 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1504 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1505 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1506 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1507
1508 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1509 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1510 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1511 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1512 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1513 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1514 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1515 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1516 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1517 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1518
1519 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1520 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1521 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1522 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1523 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1524 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1525 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1526 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1527 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1528 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1529
1530 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1531 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1532 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1533 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1534 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1535 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1536
1537 /*
1538 * We must clear the error counters.
1539 * These registers are cleared on read,
1540 * so we may pass a useless variable to store the value.
1541 */
1542 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1543 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1544 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1545 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1546 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1547 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1548
1549 return 0;
1550}
1551
1552static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1553{
1554 unsigned int i;
1555 u32 reg;
1556
1557 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1558 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1559 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1560 return 0;
1561
1562 udelay(REGISTER_BUSY_DELAY);
1563 }
1564
1565 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1566 return -EACCES;
1567}
1568
1569static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1570{
1571 unsigned int i;
1572 u8 value;
1573
1574 /*
1575 * BBP was enabled after firmware was loaded,
1576 * but we need to reactivate it now.
1577 */
1578 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1579 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1580 msleep(1);
1581
1582 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1583 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1584 if ((value != 0xff) && (value != 0x00))
1585 return 0;
1586 udelay(REGISTER_BUSY_DELAY);
1587 }
1588
1589 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1590 return -EACCES;
1591}
1592
1593static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1594{
1595 unsigned int i;
1596 u16 eeprom;
1597 u8 reg_id;
1598 u8 value;
1599
1600 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1601 rt2800usb_wait_bbp_ready(rt2x00dev)))
1602 return -EACCES;
1603
1604 rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1605 rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1606 rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1607 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1608 rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1609 rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1610 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1611 rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1612 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1613 rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1614 rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1615 rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1616 rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1617 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1618
1619 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1620 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1621 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1622 }
1623
1624 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1625 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1626 }
1627
1628 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1629 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1630 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1631 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1632 }
1633
1634 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1635 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1636
1637 if (eeprom != 0xffff && eeprom != 0x0000) {
1638 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1639 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1640 rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1641 }
1642 }
1643
1644 return 0;
1645}
1646
1647static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1648 bool bw40, u8 rfcsr24, u8 filter_target)
1649{
1650 unsigned int i;
1651 u8 bbp;
1652 u8 rfcsr;
1653 u8 passband;
1654 u8 stopband;
1655 u8 overtuned = 0;
1656
1657 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1658
1659 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1660 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1661 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1662
1663 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1664 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1665 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1666
1667 /*
1668 * Set power & frequency of passband test tone
1669 */
1670 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1671
1672 for (i = 0; i < 100; i++) {
1673 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1674 msleep(1);
1675
1676 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1677 if (passband)
1678 break;
1679 }
1680
1681 /*
1682 * Set power & frequency of stopband test tone
1683 */
1684 rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1685
1686 for (i = 0; i < 100; i++) {
1687 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1688 msleep(1);
1689
1690 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1691
1692 if ((passband - stopband) <= filter_target) {
1693 rfcsr24++;
1694 overtuned += ((passband - stopband) == filter_target);
1695 } else
1696 break;
1697
1698 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1699 }
1700
1701 rfcsr24 -= !!overtuned;
1702
1703 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1704 return rfcsr24;
1705}
1706
1707static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1708{
1709 u8 rfcsr;
1710 u8 bbp;
1711
1712 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1713 return 0;
1714
1715 /*
1716 * Init RF calibration.
1717 */
1718 rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1719 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1720 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1721 msleep(1);
1722 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1723 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1724
1725 rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1726 rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1727 rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1728 rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1729 rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1730 rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1731 rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1732 rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1733 rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1734 rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1735 rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1736 rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1737 rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1738 rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1739 rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1740 rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1741 rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1742 rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1743 rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1744 rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1745
1746 /*
1747 * Set RX Filter calibration for 20MHz and 40MHz
1748 */
1749 rt2x00dev->calibration[0] =
1750 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1751 rt2x00dev->calibration[1] =
1752 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1753
1754 /*
1755 * Set back to initial state
1756 */
1757 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1758
1759 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1760 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1761 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1762
1763 /*
1764 * set BBP back to BW20
1765 */
1766 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1767 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1768 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1769
1770 return 0;
1771}
1772
1773/*
1774 * Device state switch handlers. 233 * Device state switch handlers.
1775 */ 234 */
1776static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev, 235static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
@@ -1778,11 +237,11 @@ static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1778{ 237{
1779 u32 reg; 238 u32 reg;
1780 239
1781 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 240 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1782 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 241 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1783 (state == STATE_RADIO_RX_ON) || 242 (state == STATE_RADIO_RX_ON) ||
1784 (state == STATE_RADIO_RX_ON_LINK)); 243 (state == STATE_RADIO_RX_ON_LINK));
1785 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 244 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1786} 245}
1787 246
1788static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 247static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
@@ -1791,7 +250,7 @@ static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1791 u32 reg; 250 u32 reg;
1792 251
1793 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 252 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1794 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 253 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1795 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 254 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1796 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 255 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1797 return 0; 256 return 0;
@@ -1812,25 +271,25 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1812 * Initialize all registers. 271 * Initialize all registers.
1813 */ 272 */
1814 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) || 273 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1815 rt2800usb_init_registers(rt2x00dev) || 274 rt2800_init_registers(rt2x00dev) ||
1816 rt2800usb_init_bbp(rt2x00dev) || 275 rt2800_init_bbp(rt2x00dev) ||
1817 rt2800usb_init_rfcsr(rt2x00dev))) 276 rt2800_init_rfcsr(rt2x00dev)))
1818 return -EIO; 277 return -EIO;
1819 278
1820 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 279 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1821 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 280 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1822 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 281 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1823 282
1824 udelay(50); 283 udelay(50);
1825 284
1826 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1827 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 286 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1828 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 287 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1829 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 288 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1830 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 289 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1831 290
1832 291
1833 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg); 292 rt2800_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1834 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0); 293 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1835 /* Don't use bulk in aggregation when working with USB 1.1 */ 294 /* Don't use bulk in aggregation when working with USB 1.1 */
1836 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN, 295 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
@@ -1844,26 +303,26 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1844 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3); 303 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1845 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1); 304 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1846 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1); 305 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1847 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg); 306 rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
1848 307
1849 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 308 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1850 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 309 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1851 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 310 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1852 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 311 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1853 312
1854 /* 313 /*
1855 * Initialize LED control 314 * Initialize LED control
1856 */ 315 */
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); 316 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1858 rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff, 317 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1859 word & 0xff, (word >> 8) & 0xff); 318 word & 0xff, (word >> 8) & 0xff);
1860 319
1861 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 320 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1862 rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff, 321 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1863 word & 0xff, (word >> 8) & 0xff); 322 word & 0xff, (word >> 8) & 0xff);
1864 323
1865 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); 324 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1866 rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff, 325 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1867 word & 0xff, (word >> 8) & 0xff); 326 word & 0xff, (word >> 8) & 0xff);
1868 327
1869 return 0; 328 return 0;
@@ -1873,14 +332,14 @@ static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1873{ 332{
1874 u32 reg; 333 u32 reg;
1875 334
1876 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 335 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1877 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 336 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1878 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 337 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1879 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 338 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1880 339
1881 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 340 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1882 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0); 341 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1883 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0); 342 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
1884 343
1885 /* Wait for DMA, ignore error */ 344 /* Wait for DMA, ignore error */
1886 rt2800usb_wait_wpdma_ready(rt2x00dev); 345 rt2800usb_wait_wpdma_ready(rt2x00dev);
@@ -1892,9 +351,9 @@ static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1892 enum dev_state state) 351 enum dev_state state)
1893{ 352{
1894 if (state == STATE_AWAKE) 353 if (state == STATE_AWAKE)
1895 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); 354 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1896 else 355 else
1897 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 356 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1898 357
1899 return 0; 358 return 0;
1900} 359}
@@ -2048,9 +507,9 @@ static void rt2800usb_write_beacon(struct queue_entry *entry)
2048 * Disable beaconing while we are reloading the beacon data, 507 * Disable beaconing while we are reloading the beacon data,
2049 * otherwise we might be sending out invalid data. 508 * otherwise we might be sending out invalid data.
2050 */ 509 */
2051 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 510 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2052 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 511 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2053 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); 512 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2054 513
2055 /* 514 /*
2056 * Write entire beacon with descriptor to register. 515 * Write entire beacon with descriptor to register.
@@ -2093,12 +552,12 @@ static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2093 return; 552 return;
2094 } 553 }
2095 554
2096 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2097 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 556 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2098 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2099 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 558 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2100 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 559 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2101 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg); 560 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2102 } 561 }
2103} 562}
2104 563
@@ -2124,7 +583,7 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2124 */ 583 */
2125 memcpy(skbdesc->desc, rxd, skbdesc->desc_len); 584 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2126 rxd = (__le32 *)skbdesc->desc; 585 rxd = (__le32 *)skbdesc->desc;
2127 rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)]; 586 rxwi = &rxd[RXINFO_DESC_SIZE / sizeof(__le32)];
2128 587
2129 /* 588 /*
2130 * It is now safe to read the descriptor on all architectures. 589 * It is now safe to read the descriptor on all architectures.
@@ -2326,7 +785,7 @@ static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2326 * Identify RF chipset. 785 * Identify RF chipset.
2327 */ 786 */
2328 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 787 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2329 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 788 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2330 rt2x00_set_chip(rt2x00dev, RT2870, value, reg); 789 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2331 790
2332 /* 791 /*
@@ -2385,9 +844,9 @@ static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2385 * Store led settings, for correct led behaviour. 844 * Store led settings, for correct led behaviour.
2386 */ 845 */
2387#ifdef CONFIG_RT2X00_LIB_LEDS 846#ifdef CONFIG_RT2X00_LIB_LEDS
2388 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 847 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2389 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 848 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2390 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 849 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2391 850
2392 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, 851 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2393 &rt2x00dev->led_mcu_reg); 852 &rt2x00dev->led_mcu_reg);
@@ -2600,10 +1059,25 @@ static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2600 return 0; 1059 return 0;
2601} 1060}
2602 1061
1062static const struct rt2800_ops rt2800usb_rt2800_ops = {
1063 .register_read = rt2x00usb_register_read,
1064 .register_write = rt2x00usb_register_write,
1065 .register_write_lock = rt2x00usb_register_write_lock,
1066
1067 .register_multiread = rt2x00usb_register_multiread,
1068 .register_multiwrite = rt2x00usb_register_multiwrite,
1069
1070 .regbusy_read = rt2x00usb_regbusy_read,
1071};
1072
2603static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev) 1073static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2604{ 1074{
2605 int retval; 1075 int retval;
2606 1076
1077 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_USB);
1078
1079 rt2x00dev->priv = (void *)&rt2800usb_rt2800_ops;
1080
2607 /* 1081 /*
2608 * Allocate eeprom data. 1082 * Allocate eeprom data.
2609 */ 1083 */
@@ -2645,162 +1119,6 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2645 return 0; 1119 return 0;
2646} 1120}
2647 1121
2648/*
2649 * IEEE80211 stack callback functions.
2650 */
2651static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2652 u32 *iv32, u16 *iv16)
2653{
2654 struct rt2x00_dev *rt2x00dev = hw->priv;
2655 struct mac_iveiv_entry iveiv_entry;
2656 u32 offset;
2657
2658 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2659 rt2x00usb_register_multiread(rt2x00dev, offset,
2660 &iveiv_entry, sizeof(iveiv_entry));
2661
2662 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2663 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2664}
2665
2666static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2667{
2668 struct rt2x00_dev *rt2x00dev = hw->priv;
2669 u32 reg;
2670 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2671
2672 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2673 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2674 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2675
2676 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2677 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2678 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2679
2680 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2681 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2682 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2683
2684 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2685 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2686 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2687
2688 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2689 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2690 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2691
2692 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2693 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2694 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2695
2696 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2697 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2698 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2699
2700 return 0;
2701}
2702
2703static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2704 const struct ieee80211_tx_queue_params *params)
2705{
2706 struct rt2x00_dev *rt2x00dev = hw->priv;
2707 struct data_queue *queue;
2708 struct rt2x00_field32 field;
2709 int retval;
2710 u32 reg;
2711 u32 offset;
2712
2713 /*
2714 * First pass the configuration through rt2x00lib, that will
2715 * update the queue settings and validate the input. After that
2716 * we are free to update the registers based on the value
2717 * in the queue parameter.
2718 */
2719 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2720 if (retval)
2721 return retval;
2722
2723 /*
2724 * We only need to perform additional register initialization
2725 * for WMM queues/
2726 */
2727 if (queue_idx >= 4)
2728 return 0;
2729
2730 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2731
2732 /* Update WMM TXOP register */
2733 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2734 field.bit_offset = (queue_idx & 1) * 16;
2735 field.bit_mask = 0xffff << field.bit_offset;
2736
2737 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2738 rt2x00_set_field32(&reg, field, queue->txop);
2739 rt2x00usb_register_write(rt2x00dev, offset, reg);
2740
2741 /* Update WMM registers */
2742 field.bit_offset = queue_idx * 4;
2743 field.bit_mask = 0xf << field.bit_offset;
2744
2745 rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2746 rt2x00_set_field32(&reg, field, queue->aifs);
2747 rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2748
2749 rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2750 rt2x00_set_field32(&reg, field, queue->cw_min);
2751 rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2752
2753 rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2754 rt2x00_set_field32(&reg, field, queue->cw_max);
2755 rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2756
2757 /* Update EDCA registers */
2758 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2759
2760 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2761 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2762 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2763 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2764 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2765 rt2x00usb_register_write(rt2x00dev, offset, reg);
2766
2767 return 0;
2768}
2769
2770static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2771{
2772 struct rt2x00_dev *rt2x00dev = hw->priv;
2773 u64 tsf;
2774 u32 reg;
2775
2776 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2777 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2778 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2779 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2780
2781 return tsf;
2782}
2783
2784static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2785 .tx = rt2x00mac_tx,
2786 .start = rt2x00mac_start,
2787 .stop = rt2x00mac_stop,
2788 .add_interface = rt2x00mac_add_interface,
2789 .remove_interface = rt2x00mac_remove_interface,
2790 .config = rt2x00mac_config,
2791 .configure_filter = rt2x00mac_configure_filter,
2792 .set_tim = rt2x00mac_set_tim,
2793 .set_key = rt2x00mac_set_key,
2794 .get_stats = rt2x00mac_get_stats,
2795 .get_tkip_seq = rt2800usb_get_tkip_seq,
2796 .set_rts_threshold = rt2800usb_set_rts_threshold,
2797 .bss_info_changed = rt2x00mac_bss_info_changed,
2798 .conf_tx = rt2800usb_conf_tx,
2799 .get_tx_stats = rt2x00mac_get_tx_stats,
2800 .get_tsf = rt2800usb_get_tsf,
2801 .rfkill_poll = rt2x00mac_rfkill_poll,
2802};
2803
2804static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = { 1122static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2805 .probe_hw = rt2800usb_probe_hw, 1123 .probe_hw = rt2800usb_probe_hw,
2806 .get_firmware_name = rt2800usb_get_firmware_name, 1124 .get_firmware_name = rt2800usb_get_firmware_name,
@@ -2810,10 +1128,10 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2810 .uninitialize = rt2x00usb_uninitialize, 1128 .uninitialize = rt2x00usb_uninitialize,
2811 .clear_entry = rt2x00usb_clear_entry, 1129 .clear_entry = rt2x00usb_clear_entry,
2812 .set_device_state = rt2800usb_set_device_state, 1130 .set_device_state = rt2800usb_set_device_state,
2813 .rfkill_poll = rt2800usb_rfkill_poll, 1131 .rfkill_poll = rt2800_rfkill_poll,
2814 .link_stats = rt2800usb_link_stats, 1132 .link_stats = rt2800_link_stats,
2815 .reset_tuner = rt2800usb_reset_tuner, 1133 .reset_tuner = rt2800_reset_tuner,
2816 .link_tuner = rt2800usb_link_tuner, 1134 .link_tuner = rt2800_link_tuner,
2817 .write_tx_desc = rt2800usb_write_tx_desc, 1135 .write_tx_desc = rt2800usb_write_tx_desc,
2818 .write_tx_data = rt2x00usb_write_tx_data, 1136 .write_tx_data = rt2x00usb_write_tx_data,
2819 .write_beacon = rt2800usb_write_beacon, 1137 .write_beacon = rt2800usb_write_beacon,
@@ -2821,19 +1139,19 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2821 .kick_tx_queue = rt2800usb_kick_tx_queue, 1139 .kick_tx_queue = rt2800usb_kick_tx_queue,
2822 .kill_tx_queue = rt2x00usb_kill_tx_queue, 1140 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2823 .fill_rxdone = rt2800usb_fill_rxdone, 1141 .fill_rxdone = rt2800usb_fill_rxdone,
2824 .config_shared_key = rt2800usb_config_shared_key, 1142 .config_shared_key = rt2800_config_shared_key,
2825 .config_pairwise_key = rt2800usb_config_pairwise_key, 1143 .config_pairwise_key = rt2800_config_pairwise_key,
2826 .config_filter = rt2800usb_config_filter, 1144 .config_filter = rt2800_config_filter,
2827 .config_intf = rt2800usb_config_intf, 1145 .config_intf = rt2800_config_intf,
2828 .config_erp = rt2800usb_config_erp, 1146 .config_erp = rt2800_config_erp,
2829 .config_ant = rt2800usb_config_ant, 1147 .config_ant = rt2800_config_ant,
2830 .config = rt2800usb_config, 1148 .config = rt2800_config,
2831}; 1149};
2832 1150
2833static const struct data_queue_desc rt2800usb_queue_rx = { 1151static const struct data_queue_desc rt2800usb_queue_rx = {
2834 .entry_num = RX_ENTRIES, 1152 .entry_num = RX_ENTRIES,
2835 .data_size = AGGREGATION_SIZE, 1153 .data_size = AGGREGATION_SIZE,
2836 .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE, 1154 .desc_size = RXINFO_DESC_SIZE + RXWI_DESC_SIZE,
2837 .priv_size = sizeof(struct queue_entry_priv_usb), 1155 .priv_size = sizeof(struct queue_entry_priv_usb),
2838}; 1156};
2839 1157
@@ -2862,9 +1180,9 @@ static const struct rt2x00_ops rt2800usb_ops = {
2862 .tx = &rt2800usb_queue_tx, 1180 .tx = &rt2800usb_queue_tx,
2863 .bcn = &rt2800usb_queue_bcn, 1181 .bcn = &rt2800usb_queue_bcn,
2864 .lib = &rt2800usb_rt2x00_ops, 1182 .lib = &rt2800usb_rt2x00_ops,
2865 .hw = &rt2800usb_mac80211_ops, 1183 .hw = &rt2800_mac80211_ops,
2866#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1184#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2867 .debugfs = &rt2800usb_rt2x00debug, 1185 .debugfs = &rt2800_rt2x00debug,
2868#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1186#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2869}; 1187};
2870 1188
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
index 4d9991c9a51c..c9d7d40ee5fb 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.h
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -28,288 +28,10 @@
28#define RT2800USB_H 28#define RT2800USB_H
29 29
30/* 30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 * RF3021 2.4G 1T2R
40 * RF3022 2.4G 2T2R
41 * RF3052 2.4G 2T2R
42 */
43#define RF2820 0x0001
44#define RF2850 0x0002
45#define RF2720 0x0003
46#define RF2750 0x0004
47#define RF3020 0x0005
48#define RF2020 0x0006
49#define RF3021 0x0007
50#define RF3022 0x0008
51#define RF3052 0x0009
52
53/*
54 * RT2870 version
55 */
56#define RT2860C_VERSION 0x28600100
57#define RT2860D_VERSION 0x28600101
58#define RT2880E_VERSION 0x28720200
59#define RT2883_VERSION 0x28830300
60#define RT3070_VERSION 0x30700200
61
62/*
63 * Signal information.
64 * Defaul offset is required for RSSI <-> dBm conversion.
65 */
66#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
67
68/*
69 * Register layout information.
70 */
71#define CSR_REG_BASE 0x1000
72#define CSR_REG_SIZE 0x0800
73#define EEPROM_BASE 0x0000
74#define EEPROM_SIZE 0x0110
75#define BBP_BASE 0x0000
76#define BBP_SIZE 0x0080
77#define RF_BASE 0x0004
78#define RF_SIZE 0x0010
79
80/*
81 * Number of TX queues.
82 */
83#define NUM_TX_QUEUES 4
84
85/*
86 * USB registers. 31 * USB registers.
87 */ 32 */
88 33
89/* 34/*
90 * HOST-MCU shared memory
91 */
92#define HOST_CMD_CSR 0x0404
93#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
94
95/*
96 * INT_SOURCE_CSR: Interrupt source register.
97 * Write one to clear corresponding bit.
98 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
99 */
100#define INT_SOURCE_CSR 0x0200
101#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
102#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
103#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
104#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
105#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
106#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
107#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
108#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
109#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
110#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
111#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
112#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
113#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
114#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
115#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
116#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
117#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
118#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
119
120/*
121 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
122 */
123#define INT_MASK_CSR 0x0204
124#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
125#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
126#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
127#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
128#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
129#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
130#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
131#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
132#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
133#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
134#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
135#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
136#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
137#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
138#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
139#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
140#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
141#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
142
143/*
144 * WPDMA_GLO_CFG
145 */
146#define WPDMA_GLO_CFG 0x0208
147#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
148#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
149#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
150#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
151#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
152#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
153#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
154#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
155#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
156
157/*
158 * WPDMA_RST_IDX
159 */
160#define WPDMA_RST_IDX 0x020c
161#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
162#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
163#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
164#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
165#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
166#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
167#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
168
169/*
170 * DELAY_INT_CFG
171 */
172#define DELAY_INT_CFG 0x0210
173#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
174#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
175#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
176#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
177#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
178#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
179
180/*
181 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
182 * AIFSN0: AC_BE
183 * AIFSN1: AC_BK
184 * AIFSN1: AC_VI
185 * AIFSN1: AC_VO
186 */
187#define WMM_AIFSN_CFG 0x0214
188#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
189#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
190#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
191#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
192
193/*
194 * WMM_CWMIN_CSR: CWmin for each EDCA AC
195 * CWMIN0: AC_BE
196 * CWMIN1: AC_BK
197 * CWMIN1: AC_VI
198 * CWMIN1: AC_VO
199 */
200#define WMM_CWMIN_CFG 0x0218
201#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
202#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
203#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
204#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
205
206/*
207 * WMM_CWMAX_CSR: CWmax for each EDCA AC
208 * CWMAX0: AC_BE
209 * CWMAX1: AC_BK
210 * CWMAX1: AC_VI
211 * CWMAX1: AC_VO
212 */
213#define WMM_CWMAX_CFG 0x021c
214#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
215#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
216#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
217#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
218
219/*
220 * AC_TXOP0: AC_BK/AC_BE TXOP register
221 * AC0TXOP: AC_BK in unit of 32us
222 * AC1TXOP: AC_BE in unit of 32us
223 */
224#define WMM_TXOP0_CFG 0x0220
225#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
226#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
227
228/*
229 * AC_TXOP1: AC_VO/AC_VI TXOP register
230 * AC2TXOP: AC_VI in unit of 32us
231 * AC3TXOP: AC_VO in unit of 32us
232 */
233#define WMM_TXOP1_CFG 0x0224
234#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
235#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
236
237/*
238 * GPIO_CTRL_CFG:
239 */
240#define GPIO_CTRL_CFG 0x0228
241#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
242#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
243#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
244#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
245#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
246#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
247#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
248#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
249#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
250
251/*
252 * MCU_CMD_CFG
253 */
254#define MCU_CMD_CFG 0x022c
255
256/*
257 * AC_BK register offsets
258 */
259#define TX_BASE_PTR0 0x0230
260#define TX_MAX_CNT0 0x0234
261#define TX_CTX_IDX0 0x0238
262#define TX_DTX_IDX0 0x023c
263
264/*
265 * AC_BE register offsets
266 */
267#define TX_BASE_PTR1 0x0240
268#define TX_MAX_CNT1 0x0244
269#define TX_CTX_IDX1 0x0248
270#define TX_DTX_IDX1 0x024c
271
272/*
273 * AC_VI register offsets
274 */
275#define TX_BASE_PTR2 0x0250
276#define TX_MAX_CNT2 0x0254
277#define TX_CTX_IDX2 0x0258
278#define TX_DTX_IDX2 0x025c
279
280/*
281 * AC_VO register offsets
282 */
283#define TX_BASE_PTR3 0x0260
284#define TX_MAX_CNT3 0x0264
285#define TX_CTX_IDX3 0x0268
286#define TX_DTX_IDX3 0x026c
287
288/*
289 * HCCA register offsets
290 */
291#define TX_BASE_PTR4 0x0270
292#define TX_MAX_CNT4 0x0274
293#define TX_CTX_IDX4 0x0278
294#define TX_DTX_IDX4 0x027c
295
296/*
297 * MGMT register offsets
298 */
299#define TX_BASE_PTR5 0x0280
300#define TX_MAX_CNT5 0x0284
301#define TX_CTX_IDX5 0x0288
302#define TX_DTX_IDX5 0x028c
303
304/*
305 * RX register offsets
306 */
307#define RX_BASE_PTR 0x0290
308#define RX_MAX_CNT 0x0294
309#define RX_CRX_IDX 0x0298
310#define RX_DRX_IDX 0x029c
311
312/*
313 * USB_DMA_CFG 35 * USB_DMA_CFG
314 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. 36 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
315 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. 37 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
@@ -343,1448 +65,16 @@
343#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff) 65#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
344 66
345/* 67/*
346 * PBF_SYS_CTRL
347 * HOST_RAM_WRITE: enable Host program ram write selection
348 */
349#define PBF_SYS_CTRL 0x0400
350#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
351#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
352
353/*
354 * PBF registers
355 * Most are for debug. Driver doesn't touch PBF register.
356 */
357#define PBF_CFG 0x0408
358#define PBF_MAX_PCNT 0x040c
359#define PBF_CTRL 0x0410
360#define PBF_INT_STA 0x0414
361#define PBF_INT_ENA 0x0418
362
363/*
364 * BCN_OFFSET0:
365 */
366#define BCN_OFFSET0 0x042c
367#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
368#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
369#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
370#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
371
372/*
373 * BCN_OFFSET1:
374 */
375#define BCN_OFFSET1 0x0430
376#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
377#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
378#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
379#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
380
381/*
382 * PBF registers
383 * Most are for debug. Driver doesn't touch PBF register.
384 */
385#define TXRXQ_PCNT 0x0438
386#define PBF_DBG 0x043c
387
388/*
389 * RF registers
390 */
391#define RF_CSR_CFG 0x0500
392#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
393#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
394#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
395#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
396
397/*
398 * MAC Control/Status Registers(CSR).
399 * Some values are set in TU, whereas 1 TU == 1024 us.
400 */
401
402/*
403 * MAC_CSR0: ASIC revision number.
404 * ASIC_REV: 0
405 * ASIC_VER: 2870
406 */
407#define MAC_CSR0 0x1000
408#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
409#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
410
411/*
412 * MAC_SYS_CTRL:
413 */
414#define MAC_SYS_CTRL 0x1004
415#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
416#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
417#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
418#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
419#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
420#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
421#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
422#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
423
424/*
425 * MAC_ADDR_DW0: STA MAC register 0
426 */
427#define MAC_ADDR_DW0 0x1008
428#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
429#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
430#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
431#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
432
433/*
434 * MAC_ADDR_DW1: STA MAC register 1
435 * UNICAST_TO_ME_MASK:
436 * Used to mask off bits from byte 5 of the MAC address
437 * to determine the UNICAST_TO_ME bit for RX frames.
438 * The full mask is complemented by BSS_ID_MASK:
439 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
440 */
441#define MAC_ADDR_DW1 0x100c
442#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
443#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
444#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
445
446/*
447 * MAC_BSSID_DW0: BSSID register 0
448 */
449#define MAC_BSSID_DW0 0x1010
450#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
451#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
452#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
453#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
454
455/*
456 * MAC_BSSID_DW1: BSSID register 1
457 * BSS_ID_MASK:
458 * 0: 1-BSSID mode (BSS index = 0)
459 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
460 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
461 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
462 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
463 * BSSID. This will make sure that those bits will be ignored
464 * when determining the MY_BSS of RX frames.
465 */
466#define MAC_BSSID_DW1 0x1014
467#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
468#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
469#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
470#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
471
472/*
473 * MAX_LEN_CFG: Maximum frame length register.
474 * MAX_MPDU: rt2860b max 16k bytes
475 * MAX_PSDU: Maximum PSDU length
476 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
477 */
478#define MAX_LEN_CFG 0x1018
479#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
480#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
481#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
482#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
483
484/*
485 * BBP_CSR_CFG: BBP serial control register
486 * VALUE: Register value to program into BBP
487 * REG_NUM: Selected BBP register
488 * READ_CONTROL: 0 write BBP, 1 read BBP
489 * BUSY: ASIC is busy executing BBP commands
490 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
491 * BBP_RW_MODE: 0 serial, 1 paralell
492 */
493#define BBP_CSR_CFG 0x101c
494#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
495#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
496#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
497#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
498#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
499#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
500
501/*
502 * RF_CSR_CFG0: RF control register
503 * REGID_AND_VALUE: Register value to program into RF
504 * BITWIDTH: Selected RF register
505 * STANDBYMODE: 0 high when standby, 1 low when standby
506 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
507 * BUSY: ASIC is busy executing RF commands
508 */
509#define RF_CSR_CFG0 0x1020
510#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
511#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
512#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
513#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
514#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
515#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
516
517/*
518 * RF_CSR_CFG1: RF control register
519 * REGID_AND_VALUE: Register value to program into RF
520 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
521 * 0: 3 system clock cycle (37.5usec)
522 * 1: 5 system clock cycle (62.5usec)
523 */
524#define RF_CSR_CFG1 0x1024
525#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
526#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
527
528/*
529 * RF_CSR_CFG2: RF control register
530 * VALUE: Register value to program into RF
531 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
532 * 0: 3 system clock cycle (37.5usec)
533 * 1: 5 system clock cycle (62.5usec)
534 */
535#define RF_CSR_CFG2 0x1028
536#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
537
538/*
539 * LED_CFG: LED control
540 * color LED's:
541 * 0: off
542 * 1: blinking upon TX2
543 * 2: periodic slow blinking
544 * 3: always on
545 * LED polarity:
546 * 0: active low
547 * 1: active high
548 */
549#define LED_CFG 0x102c
550#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
551#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
552#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
553#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
554#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
555#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
556#define LED_CFG_LED_POLAR FIELD32(0x40000000)
557
558/*
559 * XIFS_TIME_CFG: MAC timing
560 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
561 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
562 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
563 * when MAC doesn't reference BBP signal BBRXEND
564 * EIFS: unit 1us
565 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
566 *
567 */
568#define XIFS_TIME_CFG 0x1100
569#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
570#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
571#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
572#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
573#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
574
575/*
576 * BKOFF_SLOT_CFG:
577 */
578#define BKOFF_SLOT_CFG 0x1104
579#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
580#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
581
582/*
583 * NAV_TIME_CFG:
584 */
585#define NAV_TIME_CFG 0x1108
586#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
587#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
588#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
589#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
590
591/*
592 * CH_TIME_CFG: count as channel busy
593 */
594#define CH_TIME_CFG 0x110c
595
596/*
597 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
598 */
599#define PBF_LIFE_TIMER 0x1110
600
601/*
602 * BCN_TIME_CFG:
603 * BEACON_INTERVAL: in unit of 1/16 TU
604 * TSF_TICKING: Enable TSF auto counting
605 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
606 * BEACON_GEN: Enable beacon generator
607 */
608#define BCN_TIME_CFG 0x1114
609#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
610#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
611#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
612#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
613#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
614#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
615
616/*
617 * TBTT_SYNC_CFG:
618 */
619#define TBTT_SYNC_CFG 0x1118
620
621/*
622 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
623 */
624#define TSF_TIMER_DW0 0x111c
625#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
626
627/*
628 * TSF_TIMER_DW1: Local msb TSF timer, read-only
629 */
630#define TSF_TIMER_DW1 0x1120
631#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
632
633/*
634 * TBTT_TIMER: TImer remains till next TBTT, read-only
635 */
636#define TBTT_TIMER 0x1124
637
638/*
639 * INT_TIMER_CFG:
640 */
641#define INT_TIMER_CFG 0x1128
642
643/*
644 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
645 */
646#define INT_TIMER_EN 0x112c
647
648/*
649 * CH_IDLE_STA: channel idle time
650 */
651#define CH_IDLE_STA 0x1130
652
653/*
654 * CH_BUSY_STA: channel busy time
655 */
656#define CH_BUSY_STA 0x1134
657
658/*
659 * MAC_STATUS_CFG:
660 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
661 * if 1 or higher one of the 2 registers is busy.
662 */
663#define MAC_STATUS_CFG 0x1200
664#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
665
666/*
667 * PWR_PIN_CFG:
668 */
669#define PWR_PIN_CFG 0x1204
670
671/*
672 * AUTOWAKEUP_CFG: Manual power control / status register
673 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
674 * AUTOWAKE: 0:sleep, 1:awake
675 */
676#define AUTOWAKEUP_CFG 0x1208
677#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
678#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
679#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
680
681/*
682 * EDCA_AC0_CFG:
683 */
684#define EDCA_AC0_CFG 0x1300
685#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
686#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
687#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
688#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
689
690/*
691 * EDCA_AC1_CFG:
692 */
693#define EDCA_AC1_CFG 0x1304
694#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
695#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
696#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
697#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
698
699/*
700 * EDCA_AC2_CFG:
701 */
702#define EDCA_AC2_CFG 0x1308
703#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
704#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
705#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
706#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
707
708/*
709 * EDCA_AC3_CFG:
710 */
711#define EDCA_AC3_CFG 0x130c
712#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
713#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
714#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
715#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
716
717/*
718 * EDCA_TID_AC_MAP:
719 */
720#define EDCA_TID_AC_MAP 0x1310
721
722/*
723 * TX_PWR_CFG_0:
724 */
725#define TX_PWR_CFG_0 0x1314
726#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
727#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
728#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
729#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
730#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
731#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
732#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
733#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
734
735/*
736 * TX_PWR_CFG_1:
737 */
738#define TX_PWR_CFG_1 0x1318
739#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
740#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
741#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
742#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
743#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
744#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
745#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
746#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
747
748/*
749 * TX_PWR_CFG_2:
750 */
751#define TX_PWR_CFG_2 0x131c
752#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
753#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
754#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
755#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
756#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
757#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
758#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
759#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
760
761/*
762 * TX_PWR_CFG_3:
763 */
764#define TX_PWR_CFG_3 0x1320
765#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
766#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
767#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
768#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
769#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
770#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
771#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
772#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
773
774/*
775 * TX_PWR_CFG_4:
776 */
777#define TX_PWR_CFG_4 0x1324
778#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
779#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
780#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
781#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
782
783/*
784 * TX_PIN_CFG:
785 */
786#define TX_PIN_CFG 0x1328
787#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
788#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
789#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
790#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
791#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
792#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
793#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
794#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
795#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
796#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
797#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
798#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
799#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
800#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
801#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
802#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
803#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
804#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
805#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
806#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
807
808/*
809 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
810 */
811#define TX_BAND_CFG 0x132c
812#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
813#define TX_BAND_CFG_A FIELD32(0x00000002)
814#define TX_BAND_CFG_BG FIELD32(0x00000004)
815
816/*
817 * TX_SW_CFG0:
818 */
819#define TX_SW_CFG0 0x1330
820
821/*
822 * TX_SW_CFG1:
823 */
824#define TX_SW_CFG1 0x1334
825
826/*
827 * TX_SW_CFG2:
828 */
829#define TX_SW_CFG2 0x1338
830
831/*
832 * TXOP_THRES_CFG:
833 */
834#define TXOP_THRES_CFG 0x133c
835
836/*
837 * TXOP_CTRL_CFG:
838 */
839#define TXOP_CTRL_CFG 0x1340
840
841/*
842 * TX_RTS_CFG:
843 * RTS_THRES: unit:byte
844 * RTS_FBK_EN: enable rts rate fallback
845 */
846#define TX_RTS_CFG 0x1344
847#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
848#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
849#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
850
851/*
852 * TX_TIMEOUT_CFG:
853 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
854 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
855 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
856 * it is recommended that:
857 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
858 */
859#define TX_TIMEOUT_CFG 0x1348
860#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
861#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
862#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
863
864/*
865 * TX_RTY_CFG:
866 * SHORT_RTY_LIMIT: short retry limit
867 * LONG_RTY_LIMIT: long retry limit
868 * LONG_RTY_THRE: Long retry threshoold
869 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
870 * 0:expired by retry limit, 1: expired by mpdu life timer
871 * AGG_RTY_MODE: Aggregate MPDU retry mode
872 * 0:expired by retry limit, 1: expired by mpdu life timer
873 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
874 */
875#define TX_RTY_CFG 0x134c
876#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
877#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
878#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
879#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
880#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
881#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
882
883/*
884 * TX_LINK_CFG:
885 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
886 * MFB_ENABLE: TX apply remote MFB 1:enable
887 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
888 * 0: not apply remote remote unsolicit (MFS=7)
889 * TX_MRQ_EN: MCS request TX enable
890 * TX_RDG_EN: RDG TX enable
891 * TX_CF_ACK_EN: Piggyback CF-ACK enable
892 * REMOTE_MFB: remote MCS feedback
893 * REMOTE_MFS: remote MCS feedback sequence number
894 */
895#define TX_LINK_CFG 0x1350
896#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
897#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
898#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
899#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
900#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
901#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
902#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
903#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
904
905/*
906 * HT_FBK_CFG0:
907 */
908#define HT_FBK_CFG0 0x1354
909#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
910#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
911#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
912#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
913#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
914#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
915#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
916#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
917
918/*
919 * HT_FBK_CFG1:
920 */
921#define HT_FBK_CFG1 0x1358
922#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
923#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
924#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
925#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
926#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
927#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
928#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
929#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
930
931/*
932 * LG_FBK_CFG0:
933 */
934#define LG_FBK_CFG0 0x135c
935#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
936#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
937#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
938#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
939#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
940#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
941#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
942#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
943
944/*
945 * LG_FBK_CFG1:
946 */
947#define LG_FBK_CFG1 0x1360
948#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
949#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
950#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
951#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
952
953/*
954 * CCK_PROT_CFG: CCK Protection
955 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
956 * PROTECT_CTRL: Protection control frame type for CCK TX
957 * 0:none, 1:RTS/CTS, 2:CTS-to-self
958 * PROTECT_NAV: TXOP protection type for CCK TX
959 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
960 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
961 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
962 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
963 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
964 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
965 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
966 * RTS_TH_EN: RTS threshold enable on CCK TX
967 */
968#define CCK_PROT_CFG 0x1364
969#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
970#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
971#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
972#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
973#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
974#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
975#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
976#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
977#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
978#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
979
980/*
981 * OFDM_PROT_CFG: OFDM Protection
982 */
983#define OFDM_PROT_CFG 0x1368
984#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
985#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
986#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
987#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
988#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
989#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
990#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
991#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
992#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
993#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
994
995/*
996 * MM20_PROT_CFG: MM20 Protection
997 */
998#define MM20_PROT_CFG 0x136c
999#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1000#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1001#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1002#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1003#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1004#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1005#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1006#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1007#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1008#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1009
1010/*
1011 * MM40_PROT_CFG: MM40 Protection
1012 */
1013#define MM40_PROT_CFG 0x1370
1014#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1015#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1016#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1017#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1018#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1019#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1020#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1021#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1022#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1023#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1024
1025/*
1026 * GF20_PROT_CFG: GF20 Protection
1027 */
1028#define GF20_PROT_CFG 0x1374
1029#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1030#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1031#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1032#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1033#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1034#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1035#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1036#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1037#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1038#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1039
1040/*
1041 * GF40_PROT_CFG: GF40 Protection
1042 */
1043#define GF40_PROT_CFG 0x1378
1044#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1045#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1046#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1047#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1048#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1049#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1050#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1051#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1052#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1053#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1054
1055/*
1056 * EXP_CTS_TIME:
1057 */
1058#define EXP_CTS_TIME 0x137c
1059
1060/*
1061 * EXP_ACK_TIME:
1062 */
1063#define EXP_ACK_TIME 0x1380
1064
1065/*
1066 * RX_FILTER_CFG: RX configuration register.
1067 */
1068#define RX_FILTER_CFG 0x1400
1069#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1070#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1071#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1072#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1073#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1074#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1075#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1076#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1077#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1078#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1079#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1080#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1081#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1082#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1083#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1084#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1085#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1086
1087/*
1088 * AUTO_RSP_CFG:
1089 * AUTORESPONDER: 0: disable, 1: enable
1090 * BAC_ACK_POLICY: 0:long, 1:short preamble
1091 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1092 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1093 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1094 * DUAL_CTS_EN: Power bit value in control frame
1095 * ACK_CTS_PSM_BIT:Power bit value in control frame
1096 */
1097#define AUTO_RSP_CFG 0x1404
1098#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1099#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1100#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1101#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1102#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1103#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1104#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1105
1106/*
1107 * LEGACY_BASIC_RATE:
1108 */
1109#define LEGACY_BASIC_RATE 0x1408
1110
1111/*
1112 * HT_BASIC_RATE:
1113 */
1114#define HT_BASIC_RATE 0x140c
1115
1116/*
1117 * HT_CTRL_CFG:
1118 */
1119#define HT_CTRL_CFG 0x1410
1120
1121/*
1122 * SIFS_COST_CFG:
1123 */
1124#define SIFS_COST_CFG 0x1414
1125
1126/*
1127 * RX_PARSER_CFG:
1128 * Set NAV for all received frames
1129 */
1130#define RX_PARSER_CFG 0x1418
1131
1132/*
1133 * TX_SEC_CNT0:
1134 */
1135#define TX_SEC_CNT0 0x1500
1136
1137/*
1138 * RX_SEC_CNT0:
1139 */
1140#define RX_SEC_CNT0 0x1504
1141
1142/*
1143 * CCMP_FC_MUTE:
1144 */
1145#define CCMP_FC_MUTE 0x1508
1146
1147/*
1148 * TXOP_HLDR_ADDR0:
1149 */
1150#define TXOP_HLDR_ADDR0 0x1600
1151
1152/*
1153 * TXOP_HLDR_ADDR1:
1154 */
1155#define TXOP_HLDR_ADDR1 0x1604
1156
1157/*
1158 * TXOP_HLDR_ET:
1159 */
1160#define TXOP_HLDR_ET 0x1608
1161
1162/*
1163 * QOS_CFPOLL_RA_DW0:
1164 */
1165#define QOS_CFPOLL_RA_DW0 0x160c
1166
1167/*
1168 * QOS_CFPOLL_RA_DW1:
1169 */
1170#define QOS_CFPOLL_RA_DW1 0x1610
1171
1172/*
1173 * QOS_CFPOLL_QC:
1174 */
1175#define QOS_CFPOLL_QC 0x1614
1176
1177/*
1178 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1179 */
1180#define RX_STA_CNT0 0x1700
1181#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1182#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1183
1184/*
1185 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1186 */
1187#define RX_STA_CNT1 0x1704
1188#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1189#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1190
1191/*
1192 * RX_STA_CNT2:
1193 */
1194#define RX_STA_CNT2 0x1708
1195#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1196#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1197
1198/*
1199 * TX_STA_CNT0: TX Beacon count
1200 */
1201#define TX_STA_CNT0 0x170c
1202#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1203#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1204
1205/*
1206 * TX_STA_CNT1: TX tx count
1207 */
1208#define TX_STA_CNT1 0x1710
1209#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1210#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1211
1212/*
1213 * TX_STA_CNT2: TX tx count
1214 */
1215#define TX_STA_CNT2 0x1714
1216#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1217#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1218
1219/*
1220 * TX_STA_FIFO: TX Result for specific PID status fifo register
1221 */
1222#define TX_STA_FIFO 0x1718
1223#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1224#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1225#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1226#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1227#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1228#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1229#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1230
1231/*
1232 * TX_AGG_CNT: Debug counter
1233 */
1234#define TX_AGG_CNT 0x171c
1235#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1236#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1237
1238/*
1239 * TX_AGG_CNT0:
1240 */
1241#define TX_AGG_CNT0 0x1720
1242#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1243#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1244
1245/*
1246 * TX_AGG_CNT1:
1247 */
1248#define TX_AGG_CNT1 0x1724
1249#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1250#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1251
1252/*
1253 * TX_AGG_CNT2:
1254 */
1255#define TX_AGG_CNT2 0x1728
1256#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1257#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1258
1259/*
1260 * TX_AGG_CNT3:
1261 */
1262#define TX_AGG_CNT3 0x172c
1263#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1264#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1265
1266/*
1267 * TX_AGG_CNT4:
1268 */
1269#define TX_AGG_CNT4 0x1730
1270#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1271#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1272
1273/*
1274 * TX_AGG_CNT5:
1275 */
1276#define TX_AGG_CNT5 0x1734
1277#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1278#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1279
1280/*
1281 * TX_AGG_CNT6:
1282 */
1283#define TX_AGG_CNT6 0x1738
1284#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1285#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1286
1287/*
1288 * TX_AGG_CNT7:
1289 */
1290#define TX_AGG_CNT7 0x173c
1291#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1292#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1293
1294/*
1295 * MPDU_DENSITY_CNT:
1296 * TX_ZERO_DEL: TX zero length delimiter count
1297 * RX_ZERO_DEL: RX zero length delimiter count
1298 */
1299#define MPDU_DENSITY_CNT 0x1740
1300#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1301#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1302
1303/*
1304 * Security key table memory.
1305 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1306 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1307 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1308 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1309 * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry
1310 * SHARED_KEY_MODE_BASE: 4 bits * 32-entry
1311 */
1312#define MAC_WCID_BASE 0x1800
1313#define PAIRWISE_KEY_TABLE_BASE 0x4000
1314#define MAC_IVEIV_TABLE_BASE 0x6000
1315#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1316#define SHARED_KEY_TABLE_BASE 0x6c00
1317#define SHARED_KEY_MODE_BASE 0x7000
1318
1319#define MAC_WCID_ENTRY(__idx) \
1320 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1321#define PAIRWISE_KEY_ENTRY(__idx) \
1322 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1323#define MAC_IVEIV_ENTRY(__idx) \
1324 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1325#define MAC_WCID_ATTR_ENTRY(__idx) \
1326 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1327#define SHARED_KEY_ENTRY(__idx) \
1328 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1329#define SHARED_KEY_MODE_ENTRY(__idx) \
1330 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1331
1332struct mac_wcid_entry {
1333 u8 mac[6];
1334 u8 reserved[2];
1335} __attribute__ ((packed));
1336
1337struct hw_key_entry {
1338 u8 key[16];
1339 u8 tx_mic[8];
1340 u8 rx_mic[8];
1341} __attribute__ ((packed));
1342
1343struct mac_iveiv_entry {
1344 u8 iv[8];
1345} __attribute__ ((packed));
1346
1347/*
1348 * MAC_WCID_ATTRIBUTE:
1349 */
1350#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1351#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1352#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1353#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1354
1355/*
1356 * SHARED_KEY_MODE:
1357 */
1358#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1359#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1360#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1361#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1362#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1363#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1364#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1365#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1366
1367/*
1368 * HOST-MCU communication
1369 */
1370
1371/*
1372 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1373 */
1374#define H2M_MAILBOX_CSR 0x7010
1375#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1376#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1377#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1378#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1379
1380/*
1381 * H2M_MAILBOX_CID:
1382 */
1383#define H2M_MAILBOX_CID 0x7014
1384#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1385#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1386#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1387#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1388
1389/*
1390 * H2M_MAILBOX_STATUS:
1391 */
1392#define H2M_MAILBOX_STATUS 0x701c
1393
1394/*
1395 * H2M_INT_SRC:
1396 */
1397#define H2M_INT_SRC 0x7024
1398
1399/*
1400 * H2M_BBP_AGENT:
1401 */
1402#define H2M_BBP_AGENT 0x7028
1403
1404/*
1405 * MCU_LEDCS: LED control for MCU Mailbox.
1406 */
1407#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1408#define MCU_LEDCS_POLARITY FIELD8(0x01)
1409
1410/*
1411 * HW_CS_CTS_BASE:
1412 * Carrier-sense CTS frame base address.
1413 * It's where mac stores carrier-sense frame for carrier-sense function.
1414 */
1415#define HW_CS_CTS_BASE 0x7700
1416
1417/*
1418 * HW_DFS_CTS_BASE:
1419 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1420 */
1421#define HW_DFS_CTS_BASE 0x7780
1422
1423/*
1424 * TXRX control registers - base address 0x3000
1425 */
1426
1427/*
1428 * TXRX_CSR1:
1429 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1430 */
1431#define TXRX_CSR1 0x77d0
1432
1433/*
1434 * HW_DEBUG_SETTING_BASE:
1435 * since NULL frame won't be that long (256 byte)
1436 * We steal 16 tail bytes to save debugging settings
1437 */
1438#define HW_DEBUG_SETTING_BASE 0x77f0
1439#define HW_DEBUG_SETTING_BASE2 0x7770
1440
1441/*
1442 * HW_BEACON_BASE
1443 * In order to support maximum 8 MBSS and its maximum length
1444 * is 512 bytes for each beacon
1445 * Three section discontinue memory segments will be used.
1446 * 1. The original region for BCN 0~3
1447 * 2. Extract memory from FCE table for BCN 4~5
1448 * 3. Extract memory from Pair-wise key table for BCN 6~7
1449 * It occupied those memory of wcid 238~253 for BCN 6
1450 * and wcid 222~237 for BCN 7
1451 *
1452 * IMPORTANT NOTE: Not sure why legacy driver does this,
1453 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1454 */
1455#define HW_BEACON_BASE0 0x7800
1456#define HW_BEACON_BASE1 0x7a00
1457#define HW_BEACON_BASE2 0x7c00
1458#define HW_BEACON_BASE3 0x7e00
1459#define HW_BEACON_BASE4 0x7200
1460#define HW_BEACON_BASE5 0x7400
1461#define HW_BEACON_BASE6 0x5dc0
1462#define HW_BEACON_BASE7 0x5bc0
1463
1464#define HW_BEACON_OFFSET(__index) \
1465 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1466 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1467 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1468
1469/*
1470 * 8051 firmware image. 68 * 8051 firmware image.
1471 */ 69 */
1472#define FIRMWARE_RT2870 "rt2870.bin" 70#define FIRMWARE_RT2870 "rt2870.bin"
1473#define FIRMWARE_IMAGE_BASE 0x3000 71#define FIRMWARE_IMAGE_BASE 0x3000
1474 72
1475/* 73/*
1476 * BBP registers.
1477 * The wordsize of the BBP is 8 bits.
1478 */
1479
1480/*
1481 * BBP 1: TX Antenna
1482 */
1483#define BBP1_TX_POWER FIELD8(0x07)
1484#define BBP1_TX_ANTENNA FIELD8(0x18)
1485
1486/*
1487 * BBP 3: RX Antenna
1488 */
1489#define BBP3_RX_ANTENNA FIELD8(0x18)
1490#define BBP3_HT40_PLUS FIELD8(0x20)
1491
1492/*
1493 * BBP 4: Bandwidth
1494 */
1495#define BBP4_TX_BF FIELD8(0x01)
1496#define BBP4_BANDWIDTH FIELD8(0x18)
1497
1498/*
1499 * RFCSR registers
1500 * The wordsize of the RFCSR is 8 bits.
1501 */
1502
1503/*
1504 * RFCSR 6:
1505 */
1506#define RFCSR6_R FIELD8(0x03)
1507
1508/*
1509 * RFCSR 7:
1510 */
1511#define RFCSR7_RF_TUNING FIELD8(0x01)
1512
1513/*
1514 * RFCSR 12:
1515 */
1516#define RFCSR12_TX_POWER FIELD8(0x1f)
1517
1518/*
1519 * RFCSR 22:
1520 */
1521#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1522
1523/*
1524 * RFCSR 23:
1525 */
1526#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1527
1528/*
1529 * RFCSR 30:
1530 */
1531#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1532
1533/*
1534 * RF registers
1535 */
1536
1537/*
1538 * RF 2
1539 */
1540#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1541#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1542#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1543
1544/*
1545 * RF 3
1546 */
1547#define RF3_TXPOWER_G FIELD32(0x00003e00)
1548#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1549#define RF3_TXPOWER_A FIELD32(0x00003c00)
1550
1551/*
1552 * RF 4
1553 */
1554#define RF4_TXPOWER_G FIELD32(0x000007c0)
1555#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1556#define RF4_TXPOWER_A FIELD32(0x00000780)
1557#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1558#define RF4_HT40 FIELD32(0x00200000)
1559
1560/*
1561 * EEPROM content.
1562 * The wordsize of the EEPROM is 16 bits.
1563 */
1564
1565/*
1566 * EEPROM Version
1567 */
1568#define EEPROM_VERSION 0x0001
1569#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1570#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1571
1572/*
1573 * HW MAC address.
1574 */
1575#define EEPROM_MAC_ADDR_0 0x0002
1576#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1577#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1578#define EEPROM_MAC_ADDR_1 0x0003
1579#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1580#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1581#define EEPROM_MAC_ADDR_2 0x0004
1582#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1583#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1584
1585/*
1586 * EEPROM ANTENNA config
1587 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1588 * TXPATH: 1: 1T, 2: 2T
1589 */
1590#define EEPROM_ANTENNA 0x001a
1591#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1592#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1593#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1594
1595/*
1596 * EEPROM NIC config
1597 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1598 */
1599#define EEPROM_NIC 0x001b
1600#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1601#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1602#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1603#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1604#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1605#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1606#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1607#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1608#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1609#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1610
1611/*
1612 * EEPROM frequency
1613 */
1614#define EEPROM_FREQ 0x001d
1615#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1616#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1617#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1618
1619/*
1620 * EEPROM LED
1621 * POLARITY_RDY_G: Polarity RDY_G setting.
1622 * POLARITY_RDY_A: Polarity RDY_A setting.
1623 * POLARITY_ACT: Polarity ACT setting.
1624 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1625 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1626 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1627 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1628 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1629 * LED_MODE: Led mode.
1630 */
1631#define EEPROM_LED1 0x001e
1632#define EEPROM_LED2 0x001f
1633#define EEPROM_LED3 0x0020
1634#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1635#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1636#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1637#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1638#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1639#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1640#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1641#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1642#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1643
1644/*
1645 * EEPROM LNA
1646 */
1647#define EEPROM_LNA 0x0022
1648#define EEPROM_LNA_BG FIELD16(0x00ff)
1649#define EEPROM_LNA_A0 FIELD16(0xff00)
1650
1651/*
1652 * EEPROM RSSI BG offset
1653 */
1654#define EEPROM_RSSI_BG 0x0023
1655#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1656#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1657
1658/*
1659 * EEPROM RSSI BG2 offset
1660 */
1661#define EEPROM_RSSI_BG2 0x0024
1662#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1663#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1664
1665/*
1666 * EEPROM RSSI A offset
1667 */
1668#define EEPROM_RSSI_A 0x0025
1669#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1670#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1671
1672/*
1673 * EEPROM RSSI A2 offset
1674 */
1675#define EEPROM_RSSI_A2 0x0026
1676#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1677#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1678
1679/*
1680 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1681 * This is delta in 40MHZ.
1682 * VALUE: Tx Power dalta value (MAX=4)
1683 * TYPE: 1: Plus the delta value, 0: minus the delta value
1684 * TXPOWER: Enable:
1685 */
1686#define EEPROM_TXPOWER_DELTA 0x0028
1687#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1688#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1689#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1690
1691/*
1692 * EEPROM TXPOWER 802.11BG
1693 */
1694#define EEPROM_TXPOWER_BG1 0x0029
1695#define EEPROM_TXPOWER_BG2 0x0030
1696#define EEPROM_TXPOWER_BG_SIZE 7
1697#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1698#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1699
1700/*
1701 * EEPROM TXPOWER 802.11A
1702 */
1703#define EEPROM_TXPOWER_A1 0x003c
1704#define EEPROM_TXPOWER_A2 0x0053
1705#define EEPROM_TXPOWER_A_SIZE 6
1706#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1707#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1708
1709/*
1710 * EEPROM TXpower byrate: 20MHZ power
1711 */
1712#define EEPROM_TXPOWER_BYRATE 0x006f
1713
1714/*
1715 * EEPROM BBP.
1716 */
1717#define EEPROM_BBP_START 0x0078
1718#define EEPROM_BBP_SIZE 16
1719#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1720#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1721
1722/*
1723 * MCU mailbox commands.
1724 */
1725#define MCU_SLEEP 0x30
1726#define MCU_WAKEUP 0x31
1727#define MCU_RADIO_OFF 0x35
1728#define MCU_CURRENT 0x36
1729#define MCU_LED 0x50
1730#define MCU_LED_STRENGTH 0x51
1731#define MCU_LED_1 0x52
1732#define MCU_LED_2 0x53
1733#define MCU_LED_3 0x54
1734#define MCU_RADAR 0x60
1735#define MCU_BOOT_SIGNAL 0x72
1736#define MCU_BBP_SIGNAL 0x80
1737#define MCU_POWER_SAVE 0x83
1738
1739/*
1740 * MCU mailbox tokens
1741 */
1742#define TOKEN_WAKUP 3
1743
1744/*
1745 * DMA descriptor defines. 74 * DMA descriptor defines.
1746 */ 75 */
1747#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1748#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 76#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1749#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) 77#define RXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1750#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1751#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1752
1753/*
1754 * TX descriptor format for TX, PRIO and Beacon Ring.
1755 */
1756
1757/*
1758 * Word0
1759 */
1760#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
1761
1762/*
1763 * Word1
1764 */
1765#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
1766#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
1767#define TXD_W1_BURST FIELD32(0x00008000)
1768#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
1769#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
1770#define TXD_W1_DMA_DONE FIELD32(0x80000000)
1771
1772/*
1773 * Word2
1774 */
1775#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
1776
1777/*
1778 * Word3
1779 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1780 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1781 * 0:MGMT, 1:HCCA 2:EDCA
1782 */
1783#define TXD_W3_WIV FIELD32(0x01000000)
1784#define TXD_W3_QSEL FIELD32(0x06000000)
1785#define TXD_W3_TCO FIELD32(0x20000000)
1786#define TXD_W3_UCO FIELD32(0x40000000)
1787#define TXD_W3_ICO FIELD32(0x80000000)
1788 78
1789/* 79/*
1790 * TX Info structure 80 * TX Info structure
@@ -1807,52 +97,6 @@ struct mac_iveiv_entry {
1807#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000) 97#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
1808 98
1809/* 99/*
1810 * TX WI structure
1811 */
1812
1813/*
1814 * Word0
1815 * FRAG: 1 To inform TKIP engine this is a fragment.
1816 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1817 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1818 * BW: Channel bandwidth 20MHz or 40 MHz
1819 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1820 */
1821#define TXWI_W0_FRAG FIELD32(0x00000001)
1822#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1823#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1824#define TXWI_W0_TS FIELD32(0x00000008)
1825#define TXWI_W0_AMPDU FIELD32(0x00000010)
1826#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1827#define TXWI_W0_TX_OP FIELD32(0x00000300)
1828#define TXWI_W0_MCS FIELD32(0x007f0000)
1829#define TXWI_W0_BW FIELD32(0x00800000)
1830#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1831#define TXWI_W0_STBC FIELD32(0x06000000)
1832#define TXWI_W0_IFS FIELD32(0x08000000)
1833#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1834
1835/*
1836 * Word1
1837 */
1838#define TXWI_W1_ACK FIELD32(0x00000001)
1839#define TXWI_W1_NSEQ FIELD32(0x00000002)
1840#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1841#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1842#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1843#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1844
1845/*
1846 * Word2
1847 */
1848#define TXWI_W2_IV FIELD32(0xffffffff)
1849
1850/*
1851 * Word3
1852 */
1853#define TXWI_W3_EIV FIELD32(0xffffffff)
1854
1855/*
1856 * RX descriptor format for RX Ring. 100 * RX descriptor format for RX Ring.
1857 */ 101 */
1858 102
@@ -1888,64 +132,4 @@ struct mac_iveiv_entry {
1888#define RXD_W0_LAST_AMSDU FIELD32(0x00080000) 132#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
1889#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000) 133#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
1890 134
1891/*
1892 * RX WI structure
1893 */
1894
1895/*
1896 * Word0
1897 */
1898#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1899#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1900#define RXWI_W0_BSSID FIELD32(0x00001c00)
1901#define RXWI_W0_UDF FIELD32(0x0000e000)
1902#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1903#define RXWI_W0_TID FIELD32(0xf0000000)
1904
1905/*
1906 * Word1
1907 */
1908#define RXWI_W1_FRAG FIELD32(0x0000000f)
1909#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1910#define RXWI_W1_MCS FIELD32(0x007f0000)
1911#define RXWI_W1_BW FIELD32(0x00800000)
1912#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1913#define RXWI_W1_STBC FIELD32(0x06000000)
1914#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1915
1916/*
1917 * Word2
1918 */
1919#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1920#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1921#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1922
1923/*
1924 * Word3
1925 */
1926#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1927#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1928
1929/*
1930 * Macros for converting txpower from EEPROM to mac80211 value
1931 * and from mac80211 value to register value.
1932 */
1933#define MIN_G_TXPOWER 0
1934#define MIN_A_TXPOWER -7
1935#define MAX_G_TXPOWER 31
1936#define MAX_A_TXPOWER 15
1937#define DEFAULT_TXPOWER 5
1938
1939#define TXPOWER_G_FROM_DEV(__txpower) \
1940 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1941
1942#define TXPOWER_G_TO_DEV(__txpower) \
1943 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1944
1945#define TXPOWER_A_FROM_DEV(__txpower) \
1946 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1947
1948#define TXPOWER_A_TO_DEV(__txpower) \
1949 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1950
1951#endif /* RT2800USB_H */ 135#endif /* RT2800USB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 196de8ab8153..c83dbaefd57a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -144,6 +144,11 @@ struct avg_val {
144 int avg_weight; 144 int avg_weight;
145}; 145};
146 146
147enum rt2x00_chip_intf {
148 RT2X00_CHIP_INTF_PCI,
149 RT2X00_CHIP_INTF_USB,
150};
151
147/* 152/*
148 * Chipset identification 153 * Chipset identification
149 * The chipset on the device is composed of a RT and RF chip. 154 * The chipset on the device is composed of a RT and RF chip.
@@ -169,6 +174,8 @@ struct rt2x00_chip {
169 174
170 u16 rf; 175 u16 rf;
171 u32 rev; 176 u32 rev;
177
178 enum rt2x00_chip_intf intf;
172}; 179};
173 180
174/* 181/*
@@ -842,9 +849,23 @@ struct rt2x00_dev {
842 * Firmware image. 849 * Firmware image.
843 */ 850 */
844 const struct firmware *fw; 851 const struct firmware *fw;
852
853 /*
854 * Driver specific data.
855 */
856 void *priv;
845}; 857};
846 858
847/* 859/*
860 * Register defines.
861 * Some registers require multiple attempts before success,
862 * in those cases REGISTER_BUSY_COUNT attempts should be
863 * taken with a REGISTER_BUSY_DELAY interval.
864 */
865#define REGISTER_BUSY_COUNT 5
866#define REGISTER_BUSY_DELAY 100
867
868/*
848 * Generic RF access. 869 * Generic RF access.
849 * The RF is being accessed by word index. 870 * The RF is being accessed by word index.
850 */ 871 */
@@ -932,6 +953,28 @@ static inline bool rt2x00_check_rev(const struct rt2x00_chip *chipset,
932 return ((chipset->rev & mask) == rev); 953 return ((chipset->rev & mask) == rev);
933} 954}
934 955
956static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
957 enum rt2x00_chip_intf intf)
958{
959 rt2x00dev->chip.intf = intf;
960}
961
962static inline bool rt2x00_intf(const struct rt2x00_chip *chipset,
963 enum rt2x00_chip_intf intf)
964{
965 return (chipset->intf == intf);
966}
967
968static inline bool rt2x00_intf_is_pci(struct rt2x00_dev *rt2x00dev)
969{
970 return rt2x00_intf(&rt2x00dev->chip, RT2X00_CHIP_INTF_PCI);
971}
972
973static inline bool rt2x00_intf_is_usb(struct rt2x00_dev *rt2x00dev)
974{
975 return rt2x00_intf(&rt2x00dev->chip, RT2X00_CHIP_INTF_USB);
976}
977
935/** 978/**
936 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes. 979 * rt2x00queue_map_txskb - Map a skb into DMA for TX purposes.
937 * @rt2x00dev: Pointer to &struct rt2x00_dev. 980 * @rt2x00dev: Pointer to &struct rt2x00_dev.
diff --git a/drivers/net/wireless/rt2x00/rt2x00leds.h b/drivers/net/wireless/rt2x00/rt2x00leds.h
index 1046977e6a12..8e03c045e037 100644
--- a/drivers/net/wireless/rt2x00/rt2x00leds.h
+++ b/drivers/net/wireless/rt2x00/rt2x00leds.h
@@ -33,8 +33,6 @@ enum led_type {
33 LED_TYPE_QUALITY, 33 LED_TYPE_QUALITY,
34}; 34};
35 35
36#ifdef CONFIG_RT2X00_LIB_LEDS
37
38struct rt2x00_led { 36struct rt2x00_led {
39 struct rt2x00_dev *rt2x00dev; 37 struct rt2x00_dev *rt2x00dev;
40 struct led_classdev led_dev; 38 struct led_classdev led_dev;
@@ -45,6 +43,4 @@ struct rt2x00_led {
45#define LED_REGISTERED ( 1 << 1 ) 43#define LED_REGISTERED ( 1 << 1 )
46}; 44};
47 45
48#endif /* CONFIG_RT2X00_LIB_LEDS */
49
50#endif /* RT2X00LEDS_H */ 46#endif /* RT2X00LEDS_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index 15a12487e04b..ae33eebe9a6f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -35,15 +35,6 @@
35#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops) 35#define PCI_DEVICE_DATA(__ops) .driver_data = (kernel_ulong_t)(__ops)
36 36
37/* 37/*
38 * Register defines.
39 * Some registers require multiple attempts before success,
40 * in those cases REGISTER_BUSY_COUNT attempts should be
41 * taken with a REGISTER_BUSY_DELAY interval.
42 */
43#define REGISTER_BUSY_COUNT 5
44#define REGISTER_BUSY_DELAY 100
45
46/*
47 * Register access. 38 * Register access.
48 */ 39 */
49static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev, 40static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,
@@ -53,10 +44,9 @@ static inline void rt2x00pci_register_read(struct rt2x00_dev *rt2x00dev,
53 *value = readl(rt2x00dev->csr.base + offset); 44 *value = readl(rt2x00dev->csr.base + offset);
54} 45}
55 46
56static inline void 47static inline void rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev,
57rt2x00pci_register_multiread(struct rt2x00_dev *rt2x00dev, 48 const unsigned int offset,
58 const unsigned int offset, 49 void *value, const u32 length)
59 void *value, const u16 length)
60{ 50{
61 memcpy_fromio(value, rt2x00dev->csr.base + offset, length); 51 memcpy_fromio(value, rt2x00dev->csr.base + offset, length);
62} 52}
@@ -68,10 +58,10 @@ static inline void rt2x00pci_register_write(struct rt2x00_dev *rt2x00dev,
68 writel(value, rt2x00dev->csr.base + offset); 58 writel(value, rt2x00dev->csr.base + offset);
69} 59}
70 60
71static inline void 61static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
72rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev, 62 const unsigned int offset,
73 const unsigned int offset, 63 const void *value,
74 const void *value, const u16 length) 64 const u32 length)
75{ 65{
76 memcpy_toio(rt2x00dev->csr.base + offset, value, length); 66 memcpy_toio(rt2x00dev->csr.base + offset, value, length);
77} 67}
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index f02b48a90593..c9cbdaa1073f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -160,7 +160,7 @@ EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_large_buff);
160 160
161int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev, 161int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
162 const unsigned int offset, 162 const unsigned int offset,
163 struct rt2x00_field32 field, 163 const struct rt2x00_field32 field,
164 u32 *reg) 164 u32 *reg)
165{ 165{
166 unsigned int i; 166 unsigned int i;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index bd2d59c85f1b..9943e428bc21 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -39,17 +39,11 @@
39#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops) 39#define USB_DEVICE_DATA(__ops) .driver_info = (kernel_ulong_t)(__ops)
40 40
41/* 41/*
42 * Register defines.
43 * Some registers require multiple attempts before success,
44 * in those cases REGISTER_BUSY_COUNT attempts should be
45 * taken with a REGISTER_BUSY_DELAY interval.
46 * For USB vendor requests we need to pass a timeout 42 * For USB vendor requests we need to pass a timeout
47 * time in ms, for this we use the REGISTER_TIMEOUT, 43 * time in ms, for this we use the REGISTER_TIMEOUT,
48 * however when loading firmware a higher value is 44 * however when loading firmware a higher value is
49 * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE. 45 * required. In that case we use the REGISTER_TIMEOUT_FIRMWARE.
50 */ 46 */
51#define REGISTER_BUSY_COUNT 5
52#define REGISTER_BUSY_DELAY 100
53#define REGISTER_TIMEOUT 500 47#define REGISTER_TIMEOUT 500
54#define REGISTER_TIMEOUT_FIRMWARE 1000 48#define REGISTER_TIMEOUT_FIRMWARE 1000
55 49
@@ -232,7 +226,7 @@ static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev,
232} 226}
233 227
234/** 228/**
235 * rt2x00usb_regbusy_read - Read 32bit register word 229 * rt2x00usb_register_read - Read 32bit register word
236 * @rt2x00dev: Device pointer, see &struct rt2x00_dev. 230 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
237 * @offset: Register offset 231 * @offset: Register offset
238 * @value: Pointer to where register contents should be stored 232 * @value: Pointer to where register contents should be stored
@@ -340,12 +334,13 @@ static inline void rt2x00usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
340 * through rt2x00usb_vendor_request_buff(). 334 * through rt2x00usb_vendor_request_buff().
341 */ 335 */
342static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev, 336static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
343 const unsigned int offset, 337 const unsigned int offset,
344 void *value, const u32 length) 338 const void *value,
339 const u32 length)
345{ 340{
346 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, 341 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
347 USB_VENDOR_REQUEST_OUT, offset, 342 USB_VENDOR_REQUEST_OUT, offset,
348 value, length, 343 (void *)value, length,
349 REGISTER_TIMEOUT32(length)); 344 REGISTER_TIMEOUT32(length));
350} 345}
351 346
@@ -364,7 +359,7 @@ static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
364 */ 359 */
365int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev, 360int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
366 const unsigned int offset, 361 const unsigned int offset,
367 struct rt2x00_field32 field, 362 const struct rt2x00_field32 field,
368 u32 *reg); 363 u32 *reg);
369 364
370/* 365/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 21:00:25 -0500