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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-15 12:40:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-15 12:40:05 -0400
commit2ed0e21b30b53d3a94e204196e523e6c8f732b56 (patch)
treede2635426477d86338a9469ce09ba0626052288f /drivers/net/wireless/rt2x00
parent0fa213310cd8fa7a51071cdcf130e26fa56e9549 (diff)
parent9cbc1cb8cd46ce1f7645b9de249b2ce8460129bb (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1244 commits) pkt_sched: Rename PSCHED_US2NS and PSCHED_NS2US ipv4: Fix fib_trie rebalancing Bluetooth: Fix issue with uninitialized nsh.type in DTL-1 driver Bluetooth: Fix Kconfig issue with RFKILL integration PIM-SM: namespace changes ipv4: update ARPD help text net: use a deferred timer in rt_check_expire ieee802154: fix kconfig bool/tristate muckup bonding: initialization rework bonding: use is_zero_ether_addr bonding: network device names are case sensative bonding: elminate bad refcount code bonding: fix style issues bonding: fix destructor bonding: remove bonding read/write semaphore bonding: initialize before registration bonding: bond_create always called with default parameters x_tables: Convert printk to pr_err netfilter: conntrack: optional reliable conntrack event delivery list_nulls: add hlist_nulls_add_head and hlist_nulls_del ...
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig17
-rw-r--r--drivers/net/wireless/rt2x00/Makefile2
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c35
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c35
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c22
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c3078
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h1945
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h57
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00config.c9
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00crypto.c89
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c134
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00ht.c69
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00lib.h65
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00link.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c88
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c16
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c48
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h53
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c38
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.h6
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c34
21 files changed, 5548 insertions, 294 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 1ae11c7f17af..8aab3e6754bd 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -77,6 +77,20 @@ config RT73USB
77 77
78 When compiled as a module, this driver will be called rt73usb. 78 When compiled as a module, this driver will be called rt73usb.
79 79
80config RT2800USB
81 tristate "Ralink rt2800 (USB) support"
82 depends on USB
83 select RT2X00_LIB_USB
84 select RT2X00_LIB_HT
85 select RT2X00_LIB_FIRMWARE
86 select RT2X00_LIB_CRYPTO
87 select CRC_CCITT
88 ---help---
89 This adds support for rt2800 wireless chipset family.
90 Supported chips: RT2770, RT2870 & RT3070.
91
92 When compiled as a module, this driver will be called "rt2800usb.ko".
93
80config RT2X00_LIB_PCI 94config RT2X00_LIB_PCI
81 tristate 95 tristate
82 select RT2X00_LIB 96 select RT2X00_LIB
@@ -88,6 +102,9 @@ config RT2X00_LIB_USB
88config RT2X00_LIB 102config RT2X00_LIB
89 tristate 103 tristate
90 104
105config RT2X00_LIB_HT
106 boolean
107
91config RT2X00_LIB_FIRMWARE 108config RT2X00_LIB_FIRMWARE
92 boolean 109 boolean
93 select FW_LOADER 110 select FW_LOADER
diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
index f22d808d8c51..bfc7226f0afe 100644
--- a/drivers/net/wireless/rt2x00/Makefile
+++ b/drivers/net/wireless/rt2x00/Makefile
@@ -8,6 +8,7 @@ rt2x00lib-$(CONFIG_RT2X00_LIB_CRYPTO) += rt2x00crypto.o
8rt2x00lib-$(CONFIG_RT2X00_LIB_RFKILL) += rt2x00rfkill.o 8rt2x00lib-$(CONFIG_RT2X00_LIB_RFKILL) += rt2x00rfkill.o
9rt2x00lib-$(CONFIG_RT2X00_LIB_FIRMWARE) += rt2x00firmware.o 9rt2x00lib-$(CONFIG_RT2X00_LIB_FIRMWARE) += rt2x00firmware.o
10rt2x00lib-$(CONFIG_RT2X00_LIB_LEDS) += rt2x00leds.o 10rt2x00lib-$(CONFIG_RT2X00_LIB_LEDS) += rt2x00leds.o
11rt2x00lib-$(CONFIG_RT2X00_LIB_HT) += rt2x00ht.o
11 12
12obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o 13obj-$(CONFIG_RT2X00_LIB) += rt2x00lib.o
13obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o 14obj-$(CONFIG_RT2X00_LIB_PCI) += rt2x00pci.o
@@ -17,3 +18,4 @@ obj-$(CONFIG_RT2500PCI) += rt2500pci.o
17obj-$(CONFIG_RT61PCI) += rt61pci.o 18obj-$(CONFIG_RT61PCI) += rt61pci.o
18obj-$(CONFIG_RT2500USB) += rt2500usb.o 19obj-$(CONFIG_RT2500USB) += rt2500usb.o
19obj-$(CONFIG_RT73USB) += rt73usb.o 20obj-$(CONFIG_RT73USB) += rt73usb.o
21obj-$(CONFIG_RT2800USB) += rt2800usb.o
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 0f08773328c6..435f945fe64d 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -335,10 +335,11 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
335 preamble_mask = erp->short_preamble << 3; 335 preamble_mask = erp->short_preamble << 3;
336 336
337 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 337 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
338 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 338 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, erp->ack_timeout);
339 erp->ack_timeout);
340 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 339 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
341 erp->ack_consume_time); 340 erp->ack_consume_time);
341 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
342 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
342 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 343 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
343 344
344 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 345 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
@@ -371,6 +372,11 @@ static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
371 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 372 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
372 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 373 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
373 374
375 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
376 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
377 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
378 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
379
374 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 380 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
375 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 381 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
376 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 382 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
@@ -503,24 +509,6 @@ static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
503 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 509 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
504} 510}
505 511
506static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
507 struct rt2x00lib_conf *libconf)
508{
509 u32 reg;
510
511 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
512 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
513 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
514 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
515
516 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
517 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
518 libconf->conf->beacon_int * 16);
519 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
520 libconf->conf->beacon_int * 16);
521 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
522}
523
524static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev, 512static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
525 struct rt2x00lib_conf *libconf) 513 struct rt2x00lib_conf *libconf)
526{ 514{
@@ -532,7 +520,7 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
532 if (state == STATE_SLEEP) { 520 if (state == STATE_SLEEP) {
533 rt2x00pci_register_read(rt2x00dev, CSR20, &reg); 521 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
534 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN, 522 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
535 (libconf->conf->beacon_int - 20) * 16); 523 (rt2x00dev->beacon_int - 20) * 16);
536 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP, 524 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
537 libconf->conf->listen_interval - 1); 525 libconf->conf->listen_interval - 1);
538 526
@@ -558,8 +546,6 @@ static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
558 libconf->conf->power_level); 546 libconf->conf->power_level);
559 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 547 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
560 rt2400pci_config_retry_limit(rt2x00dev, libconf); 548 rt2400pci_config_retry_limit(rt2x00dev, libconf);
561 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
562 rt2400pci_config_duration(rt2x00dev, libconf);
563 if (flags & IEEE80211_CONF_CHANGE_PS) 549 if (flags & IEEE80211_CONF_CHANGE_PS)
564 rt2400pci_config_ps(rt2x00dev, libconf); 550 rt2400pci_config_ps(rt2x00dev, libconf);
565} 551}
@@ -1361,7 +1347,7 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1361 */ 1347 */
1362 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1348 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1363 rt2x00pci_register_read(rt2x00dev, CSR0, &reg); 1349 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1364 rt2x00_set_chip(rt2x00dev, RT2460, value, reg); 1350 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1365 1351
1366 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) && 1352 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1367 !rt2x00_rf(&rt2x00dev->chip, RF2421)) { 1353 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
@@ -1580,7 +1566,6 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1580 .add_interface = rt2x00mac_add_interface, 1566 .add_interface = rt2x00mac_add_interface,
1581 .remove_interface = rt2x00mac_remove_interface, 1567 .remove_interface = rt2x00mac_remove_interface,
1582 .config = rt2x00mac_config, 1568 .config = rt2x00mac_config,
1583 .config_interface = rt2x00mac_config_interface,
1584 .configure_filter = rt2x00mac_configure_filter, 1569 .configure_filter = rt2x00mac_configure_filter,
1585 .get_stats = rt2x00mac_get_stats, 1570 .get_stats = rt2x00mac_get_stats,
1586 .bss_info_changed = rt2x00mac_bss_info_changed, 1571 .bss_info_changed = rt2x00mac_bss_info_changed,
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 276a8232aaa0..08b30d01e67d 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -341,10 +341,11 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
341 preamble_mask = erp->short_preamble << 3; 341 preamble_mask = erp->short_preamble << 3;
342 342
343 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 343 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
344 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 344 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, erp->ack_timeout);
345 erp->ack_timeout);
346 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 345 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
347 erp->ack_consume_time); 346 erp->ack_consume_time);
347 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
348 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
348 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 349 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
349 350
350 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 351 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
@@ -377,6 +378,11 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
377 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 378 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
378 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 379 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
379 380
381 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
382 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16);
383 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16);
384 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
385
380 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 386 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
381 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 387 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
382 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 388 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
@@ -552,24 +558,6 @@ static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
552 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 558 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
553} 559}
554 560
555static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
556 struct rt2x00lib_conf *libconf)
557{
558 u32 reg;
559
560 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
561 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
562 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
563 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
564
565 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
566 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
567 libconf->conf->beacon_int * 16);
568 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
569 libconf->conf->beacon_int * 16);
570 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
571}
572
573static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev, 561static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
574 struct rt2x00lib_conf *libconf) 562 struct rt2x00lib_conf *libconf)
575{ 563{
@@ -581,7 +569,7 @@ static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
581 if (state == STATE_SLEEP) { 569 if (state == STATE_SLEEP) {
582 rt2x00pci_register_read(rt2x00dev, CSR20, &reg); 570 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
583 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN, 571 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
584 (libconf->conf->beacon_int - 20) * 16); 572 (rt2x00dev->beacon_int - 20) * 16);
585 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP, 573 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
586 libconf->conf->listen_interval - 1); 574 libconf->conf->listen_interval - 1);
587 575
@@ -609,8 +597,6 @@ static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
609 libconf->conf->power_level); 597 libconf->conf->power_level);
610 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 598 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
611 rt2500pci_config_retry_limit(rt2x00dev, libconf); 599 rt2500pci_config_retry_limit(rt2x00dev, libconf);
612 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
613 rt2500pci_config_duration(rt2x00dev, libconf);
614 if (flags & IEEE80211_CONF_CHANGE_PS) 600 if (flags & IEEE80211_CONF_CHANGE_PS)
615 rt2500pci_config_ps(rt2x00dev, libconf); 601 rt2500pci_config_ps(rt2x00dev, libconf);
616} 602}
@@ -1525,7 +1511,7 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1525 */ 1511 */
1526 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1512 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1527 rt2x00pci_register_read(rt2x00dev, CSR0, &reg); 1513 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1528 rt2x00_set_chip(rt2x00dev, RT2560, value, reg); 1514 rt2x00_set_chip_rf(rt2x00dev, value, reg);
1529 1515
1530 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) && 1516 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1531 !rt2x00_rf(&rt2x00dev->chip, RF2523) && 1517 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
@@ -1879,7 +1865,6 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1879 .add_interface = rt2x00mac_add_interface, 1865 .add_interface = rt2x00mac_add_interface,
1880 .remove_interface = rt2x00mac_remove_interface, 1866 .remove_interface = rt2x00mac_remove_interface,
1881 .config = rt2x00mac_config, 1867 .config = rt2x00mac_config,
1882 .config_interface = rt2x00mac_config_interface,
1883 .configure_filter = rt2x00mac_configure_filter, 1868 .configure_filter = rt2x00mac_configure_filter,
1884 .get_stats = rt2x00mac_get_stats, 1869 .get_stats = rt2x00mac_get_stats,
1885 .bss_info_changed = rt2x00mac_bss_info_changed, 1870 .bss_info_changed = rt2x00mac_bss_info_changed,
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 9e630e70fc97..66daf68ff0ee 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -503,6 +503,10 @@ static void rt2500usb_config_erp(struct rt2x00_dev *rt2x00dev,
503 503
504 rt2500usb_register_write(rt2x00dev, TXRX_CSR11, erp->basic_rates); 504 rt2500usb_register_write(rt2x00dev, TXRX_CSR11, erp->basic_rates);
505 505
506 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
507 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL, erp->beacon_int * 4);
508 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
509
506 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time); 510 rt2500usb_register_write(rt2x00dev, MAC_CSR10, erp->slot_time);
507 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs); 511 rt2500usb_register_write(rt2x00dev, MAC_CSR11, erp->sifs);
508 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs); 512 rt2500usb_register_write(rt2x00dev, MAC_CSR12, erp->eifs);
@@ -632,17 +636,6 @@ static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev,
632 rt2500usb_rf_write(rt2x00dev, 3, rf3); 636 rt2500usb_rf_write(rt2x00dev, 3, rf3);
633} 637}
634 638
635static void rt2500usb_config_duration(struct rt2x00_dev *rt2x00dev,
636 struct rt2x00lib_conf *libconf)
637{
638 u16 reg;
639
640 rt2500usb_register_read(rt2x00dev, TXRX_CSR18, &reg);
641 rt2x00_set_field16(&reg, TXRX_CSR18_INTERVAL,
642 libconf->conf->beacon_int * 4);
643 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
644}
645
646static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev, 639static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
647 struct rt2x00lib_conf *libconf) 640 struct rt2x00lib_conf *libconf)
648{ 641{
@@ -654,7 +647,7 @@ static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
654 if (state == STATE_SLEEP) { 647 if (state == STATE_SLEEP) {
655 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg); 648 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
656 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON, 649 rt2x00_set_field16(&reg, MAC_CSR18_DELAY_AFTER_BEACON,
657 libconf->conf->beacon_int - 20); 650 rt2x00dev->beacon_int - 20);
658 rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP, 651 rt2x00_set_field16(&reg, MAC_CSR18_BEACONS_BEFORE_WAKEUP,
659 libconf->conf->listen_interval - 1); 652 libconf->conf->listen_interval - 1);
660 653
@@ -680,8 +673,6 @@ static void rt2500usb_config(struct rt2x00_dev *rt2x00dev,
680 !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) 673 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
681 rt2500usb_config_txpower(rt2x00dev, 674 rt2500usb_config_txpower(rt2x00dev,
682 libconf->conf->power_level); 675 libconf->conf->power_level);
683 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
684 rt2500usb_config_duration(rt2x00dev, libconf);
685 if (flags & IEEE80211_CONF_CHANGE_PS) 676 if (flags & IEEE80211_CONF_CHANGE_PS)
686 rt2500usb_config_ps(rt2x00dev, libconf); 677 rt2500usb_config_ps(rt2x00dev, libconf);
687} 678}
@@ -1559,7 +1550,7 @@ static int rt2500usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1559 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1550 rt2500usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1560 rt2x00_set_chip(rt2x00dev, RT2570, value, reg); 1551 rt2x00_set_chip(rt2x00dev, RT2570, value, reg);
1561 1552
1562 if (!rt2x00_check_rev(&rt2x00dev->chip, 0)) { 1553 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x000ffff0, 0)) {
1563 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 1554 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1564 return -ENODEV; 1555 return -ENODEV;
1565 } 1556 }
@@ -1908,7 +1899,6 @@ static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1908 .add_interface = rt2x00mac_add_interface, 1899 .add_interface = rt2x00mac_add_interface,
1909 .remove_interface = rt2x00mac_remove_interface, 1900 .remove_interface = rt2x00mac_remove_interface,
1910 .config = rt2x00mac_config, 1901 .config = rt2x00mac_config,
1911 .config_interface = rt2x00mac_config_interface,
1912 .configure_filter = rt2x00mac_configure_filter, 1902 .configure_filter = rt2x00mac_configure_filter,
1913 .set_key = rt2x00mac_set_key, 1903 .set_key = rt2x00mac_set_key,
1914 .get_stats = rt2x00mac_get_stats, 1904 .get_stats = rt2x00mac_get_stats,
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
new file mode 100644
index 000000000000..37561667925b
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -0,0 +1,3078 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800usb
23 Abstract: rt2800usb device specific routines.
24 Supported chipsets: RT2800U.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt2800usb.h"
38
39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 1;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the new data into the register.
80 */
81 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82 reg = 0;
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89 }
90
91 mutex_unlock(&rt2x00dev->csr_mutex);
92}
93
94static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95 const unsigned int word, u8 *value)
96{
97 u32 reg;
98
99 mutex_lock(&rt2x00dev->csr_mutex);
100
101 /*
102 * Wait until the BBP becomes available, afterwards we
103 * can safely write the read request into the register.
104 * After the data has been written, we wait until hardware
105 * returns the correct value, if at any time the register
106 * doesn't become available in time, reg will be 0xffffffff
107 * which means we return 0xff to the caller.
108 */
109 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 reg = 0;
111 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117 WAIT_FOR_BBP(rt2x00dev, &reg);
118 }
119
120 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122 mutex_unlock(&rt2x00dev->csr_mutex);
123}
124
125static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->csr_mutex);
131
132 /*
133 * Wait until the RFCSR becomes available, afterwards we
134 * can safely write the new data into the register.
135 */
136 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137 reg = 0;
138 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144 }
145
146 mutex_unlock(&rt2x00dev->csr_mutex);
147}
148
149static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150 const unsigned int word, u8 *value)
151{
152 u32 reg;
153
154 mutex_lock(&rt2x00dev->csr_mutex);
155
156 /*
157 * Wait until the RFCSR becomes available, afterwards we
158 * can safely write the read request into the register.
159 * After the data has been written, we wait until hardware
160 * returns the correct value, if at any time the register
161 * doesn't become available in time, reg will be 0xffffffff
162 * which means we return 0xff to the caller.
163 */
164 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165 reg = 0;
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173 }
174
175 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177 mutex_unlock(&rt2x00dev->csr_mutex);
178}
179
180static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181 const unsigned int word, const u32 value)
182{
183 u32 reg;
184
185 mutex_lock(&rt2x00dev->csr_mutex);
186
187 /*
188 * Wait until the RF becomes available, afterwards we
189 * can safely write the new data into the register.
190 */
191 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199 rt2x00_rf_write(rt2x00dev, word, value);
200 }
201
202 mutex_unlock(&rt2x00dev->csr_mutex);
203}
204
205static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206 const u8 command, const u8 token,
207 const u8 arg0, const u8 arg1)
208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the MCU becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224 reg = 0;
225 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
233static const struct rt2x00debug rt2800usb_rt2x00debug = {
234 .owner = THIS_MODULE,
235 .csr = {
236 .read = rt2x00usb_register_read,
237 .write = rt2x00usb_register_write,
238 .flags = RT2X00DEBUGFS_OFFSET,
239 .word_base = CSR_REG_BASE,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_base = EEPROM_BASE,
247 .word_size = sizeof(u16),
248 .word_count = EEPROM_SIZE / sizeof(u16),
249 },
250 .bbp = {
251 .read = rt2800usb_bbp_read,
252 .write = rt2800usb_bbp_write,
253 .word_base = BBP_BASE,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt2800usb_rf_write,
260 .word_base = RF_BASE,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267#ifdef CONFIG_RT2X00_LIB_RFKILL
268static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269{
270 u32 reg;
271
272 rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
273 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
274}
275#else
276#define rt2800usb_rfkill_poll NULL
277#endif /* CONFIG_RT2X00_LIB_RFKILL */
278
279#ifdef CONFIG_RT2X00_LIB_LEDS
280static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int bg_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
288 unsigned int polarity =
289 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
290 EEPROM_FREQ_LED_POLARITY);
291 unsigned int ledmode =
292 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
293 EEPROM_FREQ_LED_MODE);
294
295 if (led->type == LED_TYPE_RADIO) {
296 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
297 enabled ? 0x20 : 0);
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
300 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
301 } else if (led->type == LED_TYPE_QUALITY) {
302 /*
303 * The brightness is divided into 6 levels (0 - 5),
304 * The specs tell us the following levels:
305 * 0, 1 ,3, 7, 15, 31
306 * to determine the level in a simple way we can simply
307 * work with bitshifting:
308 * (1 << level) - 1
309 */
310 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
311 (1 << brightness / (LED_FULL / 6)) - 1,
312 polarity);
313 }
314}
315
316static int rt2800usb_blink_set(struct led_classdev *led_cdev,
317 unsigned long *delay_on,
318 unsigned long *delay_off)
319{
320 struct rt2x00_led *led =
321 container_of(led_cdev, struct rt2x00_led, led_dev);
322 u32 reg;
323
324 rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
325 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
326 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
327 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
328 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
329 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
330 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
331 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
332 rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
333
334 return 0;
335}
336
337static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
338 struct rt2x00_led *led,
339 enum led_type type)
340{
341 led->rt2x00dev = rt2x00dev;
342 led->type = type;
343 led->led_dev.brightness_set = rt2800usb_brightness_set;
344 led->led_dev.blink_set = rt2800usb_blink_set;
345 led->flags = LED_INITIALIZED;
346}
347#endif /* CONFIG_RT2X00_LIB_LEDS */
348
349/*
350 * Configuration handlers.
351 */
352static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
353 struct rt2x00lib_crypto *crypto,
354 struct ieee80211_key_conf *key)
355{
356 struct mac_wcid_entry wcid_entry;
357 struct mac_iveiv_entry iveiv_entry;
358 u32 offset;
359 u32 reg;
360
361 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
362
363 rt2x00usb_register_read(rt2x00dev, offset, &reg);
364 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
365 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
366 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
367 (crypto->cmd == SET_KEY) * crypto->cipher);
368 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
369 (crypto->cmd == SET_KEY) * crypto->bssidx);
370 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
371 rt2x00usb_register_write(rt2x00dev, offset, reg);
372
373 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
374
375 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
376 if ((crypto->cipher == CIPHER_TKIP) ||
377 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
378 (crypto->cipher == CIPHER_AES))
379 iveiv_entry.iv[3] |= 0x20;
380 iveiv_entry.iv[3] |= key->keyidx << 6;
381 rt2x00usb_register_multiwrite(rt2x00dev, offset,
382 &iveiv_entry, sizeof(iveiv_entry));
383
384 offset = MAC_WCID_ENTRY(key->hw_key_idx);
385
386 memset(&wcid_entry, 0, sizeof(wcid_entry));
387 if (crypto->cmd == SET_KEY)
388 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
389 rt2x00usb_register_multiwrite(rt2x00dev, offset,
390 &wcid_entry, sizeof(wcid_entry));
391}
392
393static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
394 struct rt2x00lib_crypto *crypto,
395 struct ieee80211_key_conf *key)
396{
397 struct hw_key_entry key_entry;
398 struct rt2x00_field32 field;
399 int timeout;
400 u32 offset;
401 u32 reg;
402
403 if (crypto->cmd == SET_KEY) {
404 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
405
406 memcpy(key_entry.key, crypto->key,
407 sizeof(key_entry.key));
408 memcpy(key_entry.tx_mic, crypto->tx_mic,
409 sizeof(key_entry.tx_mic));
410 memcpy(key_entry.rx_mic, crypto->rx_mic,
411 sizeof(key_entry.rx_mic));
412
413 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
414 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
415 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
416 USB_VENDOR_REQUEST_OUT,
417 offset, &key_entry,
418 sizeof(key_entry),
419 timeout);
420 }
421
422 /*
423 * The cipher types are stored over multiple registers
424 * starting with SHARED_KEY_MODE_BASE each word will have
425 * 32 bits and contains the cipher types for 2 bssidx each.
426 * Using the correct defines correctly will cause overhead,
427 * so just calculate the correct offset.
428 */
429 field.bit_offset = 4 * (key->hw_key_idx % 8);
430 field.bit_mask = 0x7 << field.bit_offset;
431
432 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
433
434 rt2x00usb_register_read(rt2x00dev, offset, &reg);
435 rt2x00_set_field32(&reg, field,
436 (crypto->cmd == SET_KEY) * crypto->cipher);
437 rt2x00usb_register_write(rt2x00dev, offset, reg);
438
439 /*
440 * Update WCID information
441 */
442 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
443
444 return 0;
445}
446
447static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
448 struct rt2x00lib_crypto *crypto,
449 struct ieee80211_key_conf *key)
450{
451 struct hw_key_entry key_entry;
452 int timeout;
453 u32 offset;
454
455 if (crypto->cmd == SET_KEY) {
456 /*
457 * 1 pairwise key is possible per AID, this means that the AID
458 * equals our hw_key_idx. Make sure the WCID starts _after_ the
459 * last possible shared key entry.
460 */
461 if (crypto->aid > (256 - 32))
462 return -ENOSPC;
463
464 key->hw_key_idx = 32 + crypto->aid;
465
466 memcpy(key_entry.key, crypto->key,
467 sizeof(key_entry.key));
468 memcpy(key_entry.tx_mic, crypto->tx_mic,
469 sizeof(key_entry.tx_mic));
470 memcpy(key_entry.rx_mic, crypto->rx_mic,
471 sizeof(key_entry.rx_mic));
472
473 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
474 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
475 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
476 USB_VENDOR_REQUEST_OUT,
477 offset, &key_entry,
478 sizeof(key_entry),
479 timeout);
480 }
481
482 /*
483 * Update WCID information
484 */
485 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
486
487 return 0;
488}
489
490static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
491 const unsigned int filter_flags)
492{
493 u32 reg;
494
495 /*
496 * Start configuration steps.
497 * Note that the version error will always be dropped
498 * and broadcast frames will always be accepted since
499 * there is no filter for it at this time.
500 */
501 rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
502 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
503 !(filter_flags & FIF_FCSFAIL));
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
505 !(filter_flags & FIF_PLCPFAIL));
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
507 !(filter_flags & FIF_PROMISC_IN_BSS));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
511 !(filter_flags & FIF_ALLMULTI));
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
513 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
515 !(filter_flags & FIF_CONTROL));
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
521 !(filter_flags & FIF_CONTROL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
523 !(filter_flags & FIF_CONTROL));
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
529 !(filter_flags & FIF_CONTROL));
530 rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
531}
532
533static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
534 struct rt2x00_intf *intf,
535 struct rt2x00intf_conf *conf,
536 const unsigned int flags)
537{
538 unsigned int beacon_base;
539 u32 reg;
540
541 if (flags & CONFIG_UPDATE_TYPE) {
542 /*
543 * Clear current synchronisation setup.
544 * For the Beacon base registers we only need to clear
545 * the first byte since that byte contains the VALID and OWNER
546 * bits which (when set to 0) will invalidate the entire beacon.
547 */
548 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
549 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
550
551 /*
552 * Enable synchronisation.
553 */
554 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
555 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
558 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
559 }
560
561 if (flags & CONFIG_UPDATE_MAC) {
562 reg = le32_to_cpu(conf->mac[1]);
563 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
564 conf->mac[1] = cpu_to_le32(reg);
565
566 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
567 conf->mac, sizeof(conf->mac));
568 }
569
570 if (flags & CONFIG_UPDATE_BSSID) {
571 reg = le32_to_cpu(conf->bssid[1]);
572 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
573 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
574 conf->bssid[1] = cpu_to_le32(reg);
575
576 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
577 conf->bssid, sizeof(conf->bssid));
578 }
579}
580
581static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
582 struct rt2x00lib_erp *erp)
583{
584 u32 reg;
585
586 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
587 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
588 DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
589 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
590
591 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
592 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
593 !!erp->short_preamble);
594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
595 !!erp->short_preamble);
596 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
597
598 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
599 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
600 erp->cts_protection ? 2 : 0);
601 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
602
603 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
604 erp->basic_rates);
605 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
606
607 rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
608 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
609 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
610 rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
611
612 rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
613 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
614 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
615 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
616 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
617 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
618 rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
619
620 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
621 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
622 erp->beacon_int * 16);
623 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
624}
625
626static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
627 struct antenna_setup *ant)
628{
629 u8 r1;
630 u8 r3;
631
632 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
633 rt2800usb_bbp_read(rt2x00dev, 3, &r3);
634
635 /*
636 * Configure the TX antenna.
637 */
638 switch ((int)ant->tx) {
639 case 1:
640 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
641 break;
642 case 2:
643 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
644 break;
645 case 3:
646 /* Do nothing */
647 break;
648 }
649
650 /*
651 * Configure the RX antenna.
652 */
653 switch ((int)ant->rx) {
654 case 1:
655 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
656 break;
657 case 2:
658 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
659 break;
660 case 3:
661 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
662 break;
663 }
664
665 rt2800usb_bbp_write(rt2x00dev, 3, r3);
666 rt2800usb_bbp_write(rt2x00dev, 1, r1);
667}
668
669static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
670 struct rt2x00lib_conf *libconf)
671{
672 u16 eeprom;
673 short lna_gain;
674
675 if (libconf->rf.channel <= 14) {
676 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
677 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
678 } else if (libconf->rf.channel <= 64) {
679 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
680 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
681 } else if (libconf->rf.channel <= 128) {
682 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
683 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
684 } else {
685 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
686 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
687 }
688
689 rt2x00dev->lna_gain = lna_gain;
690}
691
692static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
693 struct ieee80211_conf *conf,
694 struct rf_channel *rf,
695 struct channel_info *info)
696{
697 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
698
699 if (rt2x00dev->default_ant.tx == 1)
700 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
701
702 if (rt2x00dev->default_ant.rx == 1) {
703 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
704 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
705 } else if (rt2x00dev->default_ant.rx == 2)
706 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
707
708 if (rf->channel > 14) {
709 /*
710 * When TX power is below 0, we should increase it by 7 to
711 * make it a positive value (Minumum value is -7).
712 * However this means that values between 0 and 7 have
713 * double meaning, and we should set a 7DBm boost flag.
714 */
715 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
716 (info->tx_power1 >= 0));
717
718 if (info->tx_power1 < 0)
719 info->tx_power1 += 7;
720
721 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
722 TXPOWER_A_TO_DEV(info->tx_power1));
723
724 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
725 (info->tx_power2 >= 0));
726
727 if (info->tx_power2 < 0)
728 info->tx_power2 += 7;
729
730 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
731 TXPOWER_A_TO_DEV(info->tx_power2));
732 } else {
733 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
734 TXPOWER_G_TO_DEV(info->tx_power1));
735 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
736 TXPOWER_G_TO_DEV(info->tx_power2));
737 }
738
739 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
740
741 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
742 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
743 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
744 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
745
746 udelay(200);
747
748 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
749 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
750 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
751 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
752
753 udelay(200);
754
755 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
756 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
757 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
758 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
759}
760
761static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
762 struct ieee80211_conf *conf,
763 struct rf_channel *rf,
764 struct channel_info *info)
765{
766 u8 rfcsr;
767
768 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
769 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
770
771 rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
772 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
773 rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
774
775 rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
776 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
777 TXPOWER_G_TO_DEV(info->tx_power1));
778 rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
779
780 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
781 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
782 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
783
784 rt2800usb_rfcsr_write(rt2x00dev, 24,
785 rt2x00dev->calibration[conf_is_ht40(conf)]);
786
787 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
788 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
789 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
790}
791
792static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
793 struct ieee80211_conf *conf,
794 struct rf_channel *rf,
795 struct channel_info *info)
796{
797 u32 reg;
798 unsigned int tx_pin;
799 u8 bbp;
800
801 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
802 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
803 else
804 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
805
806 /*
807 * Change BBP settings
808 */
809 rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
810 rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
811 rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
812 rt2800usb_bbp_write(rt2x00dev, 86, 0);
813
814 if (rf->channel <= 14) {
815 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
816 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
817 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
818 } else {
819 rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
820 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
821 }
822 } else {
823 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
824
825 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
826 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
827 else
828 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
829 }
830
831 rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
832 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
833 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
834 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
835 rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
836
837 tx_pin = 0;
838
839 /* Turn on unused PA or LNA when not using 1T or 1R */
840 if (rt2x00dev->default_ant.tx != 1) {
841 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
842 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
843 }
844
845 /* Turn on unused PA or LNA when not using 1T or 1R */
846 if (rt2x00dev->default_ant.rx != 1) {
847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
848 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
849 }
850
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
852 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
853 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
854 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
855 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
856 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
857
858 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
859
860 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
861 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
862 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
863
864 rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
865 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
866 rt2800usb_bbp_write(rt2x00dev, 3, bbp);
867
868 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
869 if (conf_is_ht40(conf)) {
870 rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
871 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
872 rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
873 } else {
874 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
875 rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
876 rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
877 }
878 }
879
880 msleep(1);
881}
882
883static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
884 const int txpower)
885{
886 u32 reg;
887 u32 value = TXPOWER_G_TO_DEV(txpower);
888 u8 r1;
889
890 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
891 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
892 rt2800usb_bbp_write(rt2x00dev, 1, r1);
893
894 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
895 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
896 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
897 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
898 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
899 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
900 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
903 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
904
905 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
906 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
909 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
910 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
911 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
914 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
915
916 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
917 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
920 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
921 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
922 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
925 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
926
927 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
931 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
932 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
933 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
936 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
937
938 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
939 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
940 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
941 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
942 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
943 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
944}
945
946static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
947 struct rt2x00lib_conf *libconf)
948{
949 u32 reg;
950
951 rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
952 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
953 libconf->conf->short_frame_max_tx_count);
954 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
955 libconf->conf->long_frame_max_tx_count);
956 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
957 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
958 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
959 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
960 rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
961}
962
963static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
964 struct rt2x00lib_conf *libconf)
965{
966 enum dev_state state =
967 (libconf->conf->flags & IEEE80211_CONF_PS) ?
968 STATE_SLEEP : STATE_AWAKE;
969 u32 reg;
970
971 if (state == STATE_SLEEP) {
972 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
973
974 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
975 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
976 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
977 libconf->conf->listen_interval - 1);
978 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
979 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
980
981 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
982 } else {
983 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
984
985 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
986 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
987 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
988 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
989 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
990 }
991}
992
993static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
994 struct rt2x00lib_conf *libconf,
995 const unsigned int flags)
996{
997 /* Always recalculate LNA gain before changing configuration */
998 rt2800usb_config_lna_gain(rt2x00dev, libconf);
999
1000 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1001 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1002 &libconf->rf, &libconf->channel);
1003 if (flags & IEEE80211_CONF_CHANGE_POWER)
1004 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1005 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1006 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1007 if (flags & IEEE80211_CONF_CHANGE_PS)
1008 rt2800usb_config_ps(rt2x00dev, libconf);
1009}
1010
1011/*
1012 * Link tuning
1013 */
1014static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1015 struct link_qual *qual)
1016{
1017 u32 reg;
1018
1019 /*
1020 * Update FCS error count from register.
1021 */
1022 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1023 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1024}
1025
1026static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1027{
1028 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1029 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1030 return 0x1c + (2 * rt2x00dev->lna_gain);
1031 else
1032 return 0x2e + rt2x00dev->lna_gain;
1033 }
1034
1035 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1036 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1037 else
1038 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1039}
1040
1041static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1042 struct link_qual *qual, u8 vgc_level)
1043{
1044 if (qual->vgc_level != vgc_level) {
1045 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1046 qual->vgc_level = vgc_level;
1047 qual->vgc_level_reg = vgc_level;
1048 }
1049}
1050
1051static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1052 struct link_qual *qual)
1053{
1054 rt2800usb_set_vgc(rt2x00dev, qual,
1055 rt2800usb_get_default_vgc(rt2x00dev));
1056}
1057
1058static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1059 struct link_qual *qual, const u32 count)
1060{
1061 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1062 return;
1063
1064 /*
1065 * When RSSI is better then -80 increase VGC level with 0x10
1066 */
1067 rt2800usb_set_vgc(rt2x00dev, qual,
1068 rt2800usb_get_default_vgc(rt2x00dev) +
1069 ((qual->rssi > -80) * 0x10));
1070}
1071
1072/*
1073 * Firmware functions
1074 */
1075static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1076{
1077 return FIRMWARE_RT2870;
1078}
1079
1080static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1081{
1082 u16 fw_crc;
1083 u16 crc;
1084
1085 /*
1086 * The last 2 bytes in the firmware array are the crc checksum itself,
1087 * this means that we should never pass those 2 bytes to the crc
1088 * algorithm.
1089 */
1090 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1091
1092 /*
1093 * Use the crc ccitt algorithm.
1094 * This will return the same value as the legacy driver which
1095 * used bit ordering reversion on the both the firmware bytes
1096 * before input input as well as on the final output.
1097 * Obviously using crc ccitt directly is much more efficient.
1098 */
1099 crc = crc_ccitt(~0, data, len - 2);
1100
1101 /*
1102 * There is a small difference between the crc-itu-t + bitrev and
1103 * the crc-ccitt crc calculation. In the latter method the 2 bytes
1104 * will be swapped, use swab16 to convert the crc to the correct
1105 * value.
1106 */
1107 crc = swab16(crc);
1108
1109 return fw_crc == crc;
1110}
1111
1112static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1113 const u8 *data, const size_t len)
1114{
1115 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1116 size_t offset = 0;
1117
1118 /*
1119 * Firmware files:
1120 * There are 2 variations of the rt2870 firmware.
1121 * a) size: 4kb
1122 * b) size: 8kb
1123 * Note that (b) contains 2 seperate firmware blobs of 4k
1124 * within the file. The first blob is the same firmware as (a),
1125 * but the second blob is for the additional chipsets.
1126 */
1127 if (len != 4096 && len != 8192)
1128 return FW_BAD_LENGTH;
1129
1130 /*
1131 * Check if we need the upper 4kb firmware data or not.
1132 */
1133 if ((len == 4096) &&
1134 (chipset != 0x2860) &&
1135 (chipset != 0x2872) &&
1136 (chipset != 0x3070))
1137 return FW_BAD_VERSION;
1138
1139 /*
1140 * 8kb firmware files must be checked as if it were
1141 * 2 seperate firmware files.
1142 */
1143 while (offset < len) {
1144 if (!rt2800usb_check_crc(data + offset, 4096))
1145 return FW_BAD_CRC;
1146
1147 offset += 4096;
1148 }
1149
1150 return FW_OK;
1151}
1152
1153static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1154 const u8 *data, const size_t len)
1155{
1156 unsigned int i;
1157 int status;
1158 u32 reg;
1159 u32 offset;
1160 u32 length;
1161 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1162
1163 /*
1164 * Check which section of the firmware we need.
1165 */
1166 if ((chipset == 0x2860) ||
1167 (chipset == 0x2872) ||
1168 (chipset == 0x3070)) {
1169 offset = 0;
1170 length = 4096;
1171 } else {
1172 offset = 4096;
1173 length = 4096;
1174 }
1175
1176 /*
1177 * Wait for stable hardware.
1178 */
1179 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1180 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1181 if (reg && reg != ~0)
1182 break;
1183 msleep(1);
1184 }
1185
1186 if (i == REGISTER_BUSY_COUNT) {
1187 ERROR(rt2x00dev, "Unstable hardware.\n");
1188 return -EBUSY;
1189 }
1190
1191 /*
1192 * Write firmware to device.
1193 */
1194 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1195 USB_VENDOR_REQUEST_OUT,
1196 FIRMWARE_IMAGE_BASE,
1197 data + offset, length,
1198 REGISTER_TIMEOUT32(length));
1199
1200 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1201 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1202
1203 /*
1204 * Send firmware request to device to load firmware,
1205 * we need to specify a long timeout time.
1206 */
1207 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1208 0, USB_MODE_FIRMWARE,
1209 REGISTER_TIMEOUT_FIRMWARE);
1210 if (status < 0) {
1211 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1212 return status;
1213 }
1214
1215 msleep(10);
1216 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1217
1218 /*
1219 * Send signal to firmware during boot time.
1220 */
1221 rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1222
1223 if ((chipset == 0x3070) ||
1224 (chipset == 0x3071) ||
1225 (chipset == 0x3572)) {
1226 udelay(200);
1227 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1228 udelay(10);
1229 }
1230
1231 /*
1232 * Wait for device to stabilize.
1233 */
1234 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1235 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1236 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1237 break;
1238 msleep(1);
1239 }
1240
1241 if (i == REGISTER_BUSY_COUNT) {
1242 ERROR(rt2x00dev, "PBF system register not ready.\n");
1243 return -EBUSY;
1244 }
1245
1246 /*
1247 * Initialize firmware.
1248 */
1249 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1250 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1251 msleep(1);
1252
1253 return 0;
1254}
1255
1256/*
1257 * Initialization functions.
1258 */
1259static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1260{
1261 u32 reg;
1262 unsigned int i;
1263
1264 /*
1265 * Wait untill BBP and RF are ready.
1266 */
1267 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1268 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1269 if (reg && reg != ~0)
1270 break;
1271 msleep(1);
1272 }
1273
1274 if (i == REGISTER_BUSY_COUNT) {
1275 ERROR(rt2x00dev, "Unstable hardware.\n");
1276 return -EBUSY;
1277 }
1278
1279 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1280 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1281
1282 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1283 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1284 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1285 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1286
1287 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1288
1289 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1290 USB_MODE_RESET, REGISTER_TIMEOUT);
1291
1292 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1293
1294 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1295 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1296 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1297 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1298 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1299 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1300
1301 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1302 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1303 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1304 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1305 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1306 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1307
1308 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1309 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1310
1311 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1312
1313 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1314 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1315 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1316 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1317 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1318 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1319 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1320 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1321
1322 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1323 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1324 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1325 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1326 } else {
1327 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1328 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1329 }
1330
1331 rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1332 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1333 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1334 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1335 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1336 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1337 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1338 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1339 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1340 rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1341
1342 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1343 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1344 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1345 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1346
1347 rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1348 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1349 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1350 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1351 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1352 else
1353 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1354 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1355 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1356 rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1357
1358 rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1359
1360 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1361 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1362 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1363 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1364 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1365 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1366 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1367
1368 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1369 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1370 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1371 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1372 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1373 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1374 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1375 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1376 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1377 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1378 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1379
1380 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1381 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1382 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1383 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1384 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1385 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1386 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1387 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1388 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1389 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1390 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1391
1392 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1393 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1394 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1395 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1396 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1397 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1398 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1399 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1400 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1401 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1402 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1403
1404 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1405 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1406 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1407 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1408 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1409 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1410 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1411 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1412 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1413 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1414 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1415
1416 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1417 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1418 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1419 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1420 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1421 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1422 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1423 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1424 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1425 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1426 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1427
1428 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1429 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1430 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1431 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1432 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1433 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1434 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1435 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1436 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1437 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1438 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1439
1440 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1441
1442 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1443 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1444 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1445 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1446 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1447 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1448 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1449 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1450 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1451 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1452 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1453
1454 rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1455 rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1456
1457 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1458 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1459 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1460 IEEE80211_MAX_RTS_THRESHOLD);
1461 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1462 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1463
1464 rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1465 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1466
1467 /*
1468 * ASIC will keep garbage value after boot, clear encryption keys.
1469 */
1470 for (i = 0; i < 256; i++) {
1471 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1472 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1473 wcid, sizeof(wcid));
1474
1475 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1476 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1477 }
1478
1479 for (i = 0; i < 16; i++)
1480 rt2x00usb_register_write(rt2x00dev,
1481 SHARED_KEY_MODE_ENTRY(i), 0);
1482
1483 /*
1484 * Clear all beacons
1485 * For the Beacon base registers we only need to clear
1486 * the first byte since that byte contains the VALID and OWNER
1487 * bits which (when set to 0) will invalidate the entire beacon.
1488 */
1489 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1490 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1491 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1492 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1493 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1494 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1495 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1496 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1497
1498 rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1499 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1500 rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1501
1502 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1503 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1504 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1505 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1506 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1507 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1508 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1509 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1510 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1511 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1512
1513 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1514 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1515 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1516 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1517 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1518 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1519 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1520 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1521 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1522 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1523
1524 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1525 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1526 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1527 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1528 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1529 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1530 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1531 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1532 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1533 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1534
1535 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1536 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1537 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1538 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1539 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1540 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1541
1542 /*
1543 * We must clear the error counters.
1544 * These registers are cleared on read,
1545 * so we may pass a useless variable to store the value.
1546 */
1547 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1548 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1549 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1550 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1551 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1552 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1553
1554 return 0;
1555}
1556
1557static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1558{
1559 unsigned int i;
1560 u32 reg;
1561
1562 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1563 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1564 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1565 return 0;
1566
1567 udelay(REGISTER_BUSY_DELAY);
1568 }
1569
1570 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1571 return -EACCES;
1572}
1573
1574static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1575{
1576 unsigned int i;
1577 u8 value;
1578
1579 /*
1580 * BBP was enabled after firmware was loaded,
1581 * but we need to reactivate it now.
1582 */
1583 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1584 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1585 msleep(1);
1586
1587 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1588 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1589 if ((value != 0xff) && (value != 0x00))
1590 return 0;
1591 udelay(REGISTER_BUSY_DELAY);
1592 }
1593
1594 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1595 return -EACCES;
1596}
1597
1598static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1599{
1600 unsigned int i;
1601 u16 eeprom;
1602 u8 reg_id;
1603 u8 value;
1604
1605 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1606 rt2800usb_wait_bbp_ready(rt2x00dev)))
1607 return -EACCES;
1608
1609 rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1610 rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1611 rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1612 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1613 rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1614 rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1615 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1616 rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1617 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1618 rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1619 rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1620 rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1621 rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1622 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1623
1624 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1625 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1626 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1627 }
1628
1629 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1630 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1631 }
1632
1633 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1634 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1635 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1636 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1637 }
1638
1639 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1640 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1641
1642 if (eeprom != 0xffff && eeprom != 0x0000) {
1643 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1644 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1645 rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1646 }
1647 }
1648
1649 return 0;
1650}
1651
1652static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1653 bool bw40, u8 rfcsr24, u8 filter_target)
1654{
1655 unsigned int i;
1656 u8 bbp;
1657 u8 rfcsr;
1658 u8 passband;
1659 u8 stopband;
1660 u8 overtuned = 0;
1661
1662 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1663
1664 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1665 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1666 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1667
1668 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1669 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1670 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1671
1672 /*
1673 * Set power & frequency of passband test tone
1674 */
1675 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1676
1677 for (i = 0; i < 100; i++) {
1678 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1679 msleep(1);
1680
1681 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1682 if (passband)
1683 break;
1684 }
1685
1686 /*
1687 * Set power & frequency of stopband test tone
1688 */
1689 rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1690
1691 for (i = 0; i < 100; i++) {
1692 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1693 msleep(1);
1694
1695 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1696
1697 if ((passband - stopband) <= filter_target) {
1698 rfcsr24++;
1699 overtuned += ((passband - stopband) == filter_target);
1700 } else
1701 break;
1702
1703 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1704 }
1705
1706 rfcsr24 -= !!overtuned;
1707
1708 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1709 return rfcsr24;
1710}
1711
1712static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1713{
1714 u8 rfcsr;
1715 u8 bbp;
1716
1717 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1718 return 0;
1719
1720 /*
1721 * Init RF calibration.
1722 */
1723 rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1724 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1725 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1726 msleep(1);
1727 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1728 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1729
1730 rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1731 rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1732 rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1733 rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1734 rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1735 rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1736 rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1737 rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1738 rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1739 rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1740 rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1741 rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1742 rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1743 rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1744 rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1745 rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1746 rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1747 rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1748 rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1749 rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1750
1751 /*
1752 * Set RX Filter calibration for 20MHz and 40MHz
1753 */
1754 rt2x00dev->calibration[0] =
1755 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1756 rt2x00dev->calibration[1] =
1757 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1758
1759 /*
1760 * Set back to initial state
1761 */
1762 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1763
1764 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1765 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1766 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1767
1768 /*
1769 * set BBP back to BW20
1770 */
1771 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1772 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1773 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1774
1775 return 0;
1776}
1777
1778/*
1779 * Device state switch handlers.
1780 */
1781static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1782 enum dev_state state)
1783{
1784 u32 reg;
1785
1786 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1787 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1788 (state == STATE_RADIO_RX_ON) ||
1789 (state == STATE_RADIO_RX_ON_LINK));
1790 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1791}
1792
1793static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1794{
1795 unsigned int i;
1796 u32 reg;
1797
1798 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1799 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1800 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1801 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1802 return 0;
1803
1804 msleep(1);
1805 }
1806
1807 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1808 return -EACCES;
1809}
1810
1811static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1812{
1813 u32 reg;
1814 u16 word;
1815
1816 /*
1817 * Initialize all registers.
1818 */
1819 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1820 rt2800usb_init_registers(rt2x00dev) ||
1821 rt2800usb_init_bbp(rt2x00dev) ||
1822 rt2800usb_init_rfcsr(rt2x00dev)))
1823 return -EIO;
1824
1825 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1826 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1827 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1828
1829 udelay(50);
1830
1831 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1832 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1833 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1834 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1835 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1836
1837
1838 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1839 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1840 /* Don't use bulk in aggregation when working with USB 1.1 */
1841 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1842 (rt2x00dev->rx->usb_maxpacket == 512));
1843 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1844 /*
1845 * Total room for RX frames in kilobytes, PBF might still exceed
1846 * this limit so reduce the number to prevent errors.
1847 */
1848 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1849 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1850 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1851 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1852 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1853
1854 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1855 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1856 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1857 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1858
1859 /*
1860 * Initialize LED control
1861 */
1862 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1863 rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1864 word & 0xff, (word >> 8) & 0xff);
1865
1866 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1867 rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1868 word & 0xff, (word >> 8) & 0xff);
1869
1870 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1871 rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1872 word & 0xff, (word >> 8) & 0xff);
1873
1874 return 0;
1875}
1876
1877static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1878{
1879 u32 reg;
1880
1881 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1882 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1883 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1884 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1885
1886 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1887 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1888 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1889
1890 /* Wait for DMA, ignore error */
1891 rt2800usb_wait_wpdma_ready(rt2x00dev);
1892
1893 rt2x00usb_disable_radio(rt2x00dev);
1894}
1895
1896static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1897 enum dev_state state)
1898{
1899 if (state == STATE_AWAKE)
1900 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1901 else
1902 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1903
1904 return 0;
1905}
1906
1907static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1908 enum dev_state state)
1909{
1910 int retval = 0;
1911
1912 switch (state) {
1913 case STATE_RADIO_ON:
1914 /*
1915 * Before the radio can be enabled, the device first has
1916 * to be woken up. After that it needs a bit of time
1917 * to be fully awake and the radio can be enabled.
1918 */
1919 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1920 msleep(1);
1921 retval = rt2800usb_enable_radio(rt2x00dev);
1922 break;
1923 case STATE_RADIO_OFF:
1924 /*
1925 * After the radio has been disablee, the device should
1926 * be put to sleep for powersaving.
1927 */
1928 rt2800usb_disable_radio(rt2x00dev);
1929 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1930 break;
1931 case STATE_RADIO_RX_ON:
1932 case STATE_RADIO_RX_ON_LINK:
1933 case STATE_RADIO_RX_OFF:
1934 case STATE_RADIO_RX_OFF_LINK:
1935 rt2800usb_toggle_rx(rt2x00dev, state);
1936 break;
1937 case STATE_RADIO_IRQ_ON:
1938 case STATE_RADIO_IRQ_OFF:
1939 /* No support, but no error either */
1940 break;
1941 case STATE_DEEP_SLEEP:
1942 case STATE_SLEEP:
1943 case STATE_STANDBY:
1944 case STATE_AWAKE:
1945 retval = rt2800usb_set_state(rt2x00dev, state);
1946 break;
1947 default:
1948 retval = -ENOTSUPP;
1949 break;
1950 }
1951
1952 if (unlikely(retval))
1953 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1954 state, retval);
1955
1956 return retval;
1957}
1958
1959/*
1960 * TX descriptor initialization
1961 */
1962static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1963 struct sk_buff *skb,
1964 struct txentry_desc *txdesc)
1965{
1966 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1967 __le32 *txi = skbdesc->desc;
1968 __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1969 u32 word;
1970
1971 /*
1972 * Initialize TX Info descriptor
1973 */
1974 rt2x00_desc_read(txwi, 0, &word);
1975 rt2x00_set_field32(&word, TXWI_W0_FRAG,
1976 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1977 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1978 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1979 rt2x00_set_field32(&word, TXWI_W0_TS,
1980 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1981 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1982 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1983 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1984 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1985 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1986 rt2x00_set_field32(&word, TXWI_W0_BW,
1987 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1988 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1989 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1990 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1991 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1992 rt2x00_desc_write(txwi, 0, word);
1993
1994 rt2x00_desc_read(txwi, 1, &word);
1995 rt2x00_set_field32(&word, TXWI_W1_ACK,
1996 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1997 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1998 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1999 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2000 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2001 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2002 txdesc->key_idx : 0xff);
2003 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2004 skb->len - txdesc->l2pad);
2005 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2006 skbdesc->entry->entry_idx);
2007 rt2x00_desc_write(txwi, 1, word);
2008
2009 /*
2010 * Always write 0 to IV/EIV fields, hardware will insert the IV
2011 * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2012 * When TXINFO_W0_WIV is set to 1 it will use the IV data
2013 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2014 * crypto entry in the registers should be used to encrypt the frame.
2015 */
2016 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2017 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2018
2019 /*
2020 * Initialize TX descriptor
2021 */
2022 rt2x00_desc_read(txi, 0, &word);
2023 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2024 skb->len + TXWI_DESC_SIZE);
2025 rt2x00_set_field32(&word, TXINFO_W0_WIV,
2026 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2027 rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2028 rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2029 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2030 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2031 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2032 rt2x00_desc_write(txi, 0, word);
2033}
2034
2035/*
2036 * TX data initialization
2037 */
2038static void rt2800usb_write_beacon(struct queue_entry *entry)
2039{
2040 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2041 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2042 unsigned int beacon_base;
2043 u32 reg;
2044
2045 /*
2046 * Add the descriptor in front of the skb.
2047 */
2048 skb_push(entry->skb, entry->queue->desc_size);
2049 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2050 skbdesc->desc = entry->skb->data;
2051
2052 /*
2053 * Disable beaconing while we are reloading the beacon data,
2054 * otherwise we might be sending out invalid data.
2055 */
2056 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2057 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2058 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2059 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2060 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2061
2062 /*
2063 * Write entire beacon with descriptor to register.
2064 */
2065 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2066 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2067 USB_VENDOR_REQUEST_OUT, beacon_base,
2068 entry->skb->data, entry->skb->len,
2069 REGISTER_TIMEOUT32(entry->skb->len));
2070
2071 /*
2072 * Clean up the beacon skb.
2073 */
2074 dev_kfree_skb(entry->skb);
2075 entry->skb = NULL;
2076}
2077
2078static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2079{
2080 int length;
2081
2082 /*
2083 * The length _must_ include 4 bytes padding,
2084 * it should always be multiple of 4,
2085 * but it must _not_ be a multiple of the USB packet size.
2086 */
2087 length = roundup(entry->skb->len + 4, 4);
2088 length += (4 * !(length % entry->queue->usb_maxpacket));
2089
2090 return length;
2091}
2092
2093static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2094 const enum data_queue_qid queue)
2095{
2096 u32 reg;
2097
2098 if (queue != QID_BEACON) {
2099 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2100 return;
2101 }
2102
2103 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2104 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2105 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2106 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2107 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2108 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2109 }
2110}
2111
2112/*
2113 * RX control handlers
2114 */
2115static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2116 struct rxdone_entry_desc *rxdesc)
2117{
2118 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2119 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2120 __le32 *rxd = (__le32 *)entry->skb->data;
2121 __le32 *rxwi;
2122 u32 rxd0;
2123 u32 rxwi0;
2124 u32 rxwi1;
2125 u32 rxwi2;
2126 u32 rxwi3;
2127
2128 /*
2129 * Copy descriptor to the skbdesc->desc buffer, making it safe from
2130 * moving of frame data in rt2x00usb.
2131 */
2132 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2133 rxd = (__le32 *)skbdesc->desc;
2134 rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2135
2136 /*
2137 * It is now safe to read the descriptor on all architectures.
2138 */
2139 rt2x00_desc_read(rxd, 0, &rxd0);
2140 rt2x00_desc_read(rxwi, 0, &rxwi0);
2141 rt2x00_desc_read(rxwi, 1, &rxwi1);
2142 rt2x00_desc_read(rxwi, 2, &rxwi2);
2143 rt2x00_desc_read(rxwi, 3, &rxwi3);
2144
2145 if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2146 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2147
2148 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2149 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2150 rxdesc->cipher_status =
2151 rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2152 }
2153
2154 if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2155 /*
2156 * Hardware has stripped IV/EIV data from 802.11 frame during
2157 * decryption. Unfortunately the descriptor doesn't contain
2158 * any fields with the EIV/IV data either, so they can't
2159 * be restored by rt2x00lib.
2160 */
2161 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2162
2163 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2164 rxdesc->flags |= RX_FLAG_DECRYPTED;
2165 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2166 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2167 }
2168
2169 if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2170 rxdesc->dev_flags |= RXDONE_MY_BSS;
2171
2172 if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD))
2173 rxdesc->dev_flags |= RXDONE_L2PAD;
2174
2175 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2176 rxdesc->flags |= RX_FLAG_SHORT_GI;
2177
2178 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2179 rxdesc->flags |= RX_FLAG_40MHZ;
2180
2181 /*
2182 * Detect RX rate, always use MCS as signal type.
2183 */
2184 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2185 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2186 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2187
2188 /*
2189 * Mask of 0x8 bit to remove the short preamble flag.
2190 */
2191 if (rxdesc->rate_mode == RATE_MODE_CCK)
2192 rxdesc->signal &= ~0x8;
2193
2194 rxdesc->rssi =
2195 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2196 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2197
2198 rxdesc->noise =
2199 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2200 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2201
2202 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2203
2204 /*
2205 * Remove RXWI descriptor from start of buffer.
2206 */
2207 skb_pull(entry->skb, skbdesc->desc_len);
2208 skb_trim(entry->skb, rxdesc->size);
2209}
2210
2211/*
2212 * Device probe functions.
2213 */
2214static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2215{
2216 u16 word;
2217 u8 *mac;
2218 u8 default_lna_gain;
2219
2220 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2221
2222 /*
2223 * Start validation of the data that has been read.
2224 */
2225 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2226 if (!is_valid_ether_addr(mac)) {
2227 DECLARE_MAC_BUF(macbuf);
2228
2229 random_ether_addr(mac);
2230 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2231 }
2232
2233 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2234 if (word == 0xffff) {
2235 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2236 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2237 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2238 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2239 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2240 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2241 /*
2242 * There is a max of 2 RX streams for RT2870 series
2243 */
2244 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2245 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2246 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2247 }
2248
2249 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2250 if (word == 0xffff) {
2251 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2252 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2253 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2254 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2255 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2256 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2257 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2258 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2259 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2260 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2261 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2262 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2263 }
2264
2265 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2266 if ((word & 0x00ff) == 0x00ff) {
2267 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2268 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2269 LED_MODE_TXRX_ACTIVITY);
2270 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2271 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2272 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2273 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2274 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2275 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2276 }
2277
2278 /*
2279 * During the LNA validation we are going to use
2280 * lna0 as correct value. Note that EEPROM_LNA
2281 * is never validated.
2282 */
2283 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2284 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2285
2286 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2287 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2288 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2289 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2290 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2291 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2292
2293 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2294 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2295 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2296 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2297 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2298 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2299 default_lna_gain);
2300 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2301
2302 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2303 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2304 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2305 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2306 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2307 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2308
2309 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2310 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2311 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2312 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2313 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2314 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2315 default_lna_gain);
2316 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2317
2318 return 0;
2319}
2320
2321static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2322{
2323 u32 reg;
2324 u16 value;
2325 u16 eeprom;
2326
2327 /*
2328 * Read EEPROM word for configuration.
2329 */
2330 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2331
2332 /*
2333 * Identify RF chipset.
2334 */
2335 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2336 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2337 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2338
2339 /*
2340 * The check for rt2860 is not a typo, some rt2870 hardware
2341 * identifies itself as rt2860 in the CSR register.
2342 */
2343 if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2344 !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2345 !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2346 !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2347 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2348 return -ENODEV;
2349 }
2350
2351 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2352 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2353 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2354 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2355 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2356 !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2357 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2358 return -ENODEV;
2359 }
2360
2361 /*
2362 * Identify default antenna configuration.
2363 */
2364 rt2x00dev->default_ant.tx =
2365 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2366 rt2x00dev->default_ant.rx =
2367 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2368
2369 /*
2370 * Read frequency offset and RF programming sequence.
2371 */
2372 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2373 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2374
2375 /*
2376 * Read external LNA informations.
2377 */
2378 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2379
2380 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2381 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2382 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2383 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2384
2385 /*
2386 * Detect if this device has an hardware controlled radio.
2387 */
2388#ifdef CONFIG_RT2X00_LIB_RFKILL
2389 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2390 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2391#endif /* CONFIG_RT2X00_LIB_RFKILL */
2392
2393 /*
2394 * Store led settings, for correct led behaviour.
2395 */
2396#ifdef CONFIG_RT2X00_LIB_LEDS
2397 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2398 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2399 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2400
2401 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2402 &rt2x00dev->led_mcu_reg);
2403#endif /* CONFIG_RT2X00_LIB_LEDS */
2404
2405 return 0;
2406}
2407
2408/*
2409 * RF value list for rt2870
2410 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2411 */
2412static const struct rf_channel rf_vals[] = {
2413 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2414 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2415 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2416 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2417 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2418 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2419 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2420 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2421 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2422 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2423 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2424 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2425 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2426 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2427
2428 /* 802.11 UNI / HyperLan 2 */
2429 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2430 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2431 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2432 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2433 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2434 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2435 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2436 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2437 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2438 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2439 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2440 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2441
2442 /* 802.11 HyperLan 2 */
2443 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2444 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2445 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2446 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2447 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2448 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2449 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2450 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2451 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2452 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2453 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2454 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2455 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2456 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2457 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2458 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2459
2460 /* 802.11 UNII */
2461 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2462 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2463 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2464 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2465 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2466 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2467 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2468 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2469 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2470 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2471 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2472
2473 /* 802.11 Japan */
2474 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2475 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2476 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2477 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2478 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2479 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2480 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2481};
2482
2483/*
2484 * RF value list for rt3070
2485 * Supports: 2.4 GHz
2486 */
2487static const struct rf_channel rf_vals_3070[] = {
2488 {1, 241, 2, 2 },
2489 {2, 241, 2, 7 },
2490 {3, 242, 2, 2 },
2491 {4, 242, 2, 7 },
2492 {5, 243, 2, 2 },
2493 {6, 243, 2, 7 },
2494 {7, 244, 2, 2 },
2495 {8, 244, 2, 7 },
2496 {9, 245, 2, 2 },
2497 {10, 245, 2, 7 },
2498 {11, 246, 2, 2 },
2499 {12, 246, 2, 7 },
2500 {13, 247, 2, 2 },
2501 {14, 248, 2, 4 },
2502};
2503
2504static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2505{
2506 struct hw_mode_spec *spec = &rt2x00dev->spec;
2507 struct channel_info *info;
2508 char *tx_power1;
2509 char *tx_power2;
2510 unsigned int i;
2511 u16 eeprom;
2512
2513 /*
2514 * Initialize all hw fields.
2515 */
2516 rt2x00dev->hw->flags =
2517 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2518 IEEE80211_HW_SIGNAL_DBM |
2519 IEEE80211_HW_SUPPORTS_PS |
2520 IEEE80211_HW_PS_NULLFUNC_STACK;
2521 rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2522
2523 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2524 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2525 rt2x00_eeprom_addr(rt2x00dev,
2526 EEPROM_MAC_ADDR_0));
2527
2528 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2529
2530 /*
2531 * Initialize HT information.
2532 */
2533 spec->ht.ht_supported = true;
2534 spec->ht.cap =
2535 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2536 IEEE80211_HT_CAP_GRN_FLD |
2537 IEEE80211_HT_CAP_SGI_20 |
2538 IEEE80211_HT_CAP_SGI_40 |
2539 IEEE80211_HT_CAP_TX_STBC |
2540 IEEE80211_HT_CAP_RX_STBC |
2541 IEEE80211_HT_CAP_PSMP_SUPPORT;
2542 spec->ht.ampdu_factor = 3;
2543 spec->ht.ampdu_density = 4;
2544 spec->ht.mcs.tx_params =
2545 IEEE80211_HT_MCS_TX_DEFINED |
2546 IEEE80211_HT_MCS_TX_RX_DIFF |
2547 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2548 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2549
2550 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2551 case 3:
2552 spec->ht.mcs.rx_mask[2] = 0xff;
2553 case 2:
2554 spec->ht.mcs.rx_mask[1] = 0xff;
2555 case 1:
2556 spec->ht.mcs.rx_mask[0] = 0xff;
2557 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2558 break;
2559 }
2560
2561 /*
2562 * Initialize hw_mode information.
2563 */
2564 spec->supported_bands = SUPPORT_BAND_2GHZ;
2565 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2566
2567 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2568 rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2569 spec->num_channels = 14;
2570 spec->channels = rf_vals;
2571 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2572 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2573 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2574 spec->num_channels = ARRAY_SIZE(rf_vals);
2575 spec->channels = rf_vals;
2576 } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2577 rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2578 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2579 spec->channels = rf_vals_3070;
2580 }
2581
2582 /*
2583 * Create channel information array
2584 */
2585 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2586 if (!info)
2587 return -ENOMEM;
2588
2589 spec->channels_info = info;
2590
2591 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2592 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2593
2594 for (i = 0; i < 14; i++) {
2595 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2596 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2597 }
2598
2599 if (spec->num_channels > 14) {
2600 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2601 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2602
2603 for (i = 14; i < spec->num_channels; i++) {
2604 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2605 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2606 }
2607 }
2608
2609 return 0;
2610}
2611
2612static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2613{
2614 int retval;
2615
2616 /*
2617 * Allocate eeprom data.
2618 */
2619 retval = rt2800usb_validate_eeprom(rt2x00dev);
2620 if (retval)
2621 return retval;
2622
2623 retval = rt2800usb_init_eeprom(rt2x00dev);
2624 if (retval)
2625 return retval;
2626
2627 /*
2628 * Initialize hw specifications.
2629 */
2630 retval = rt2800usb_probe_hw_mode(rt2x00dev);
2631 if (retval)
2632 return retval;
2633
2634 /*
2635 * This device requires firmware.
2636 */
2637 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2638 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2639 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2640 if (!modparam_nohwcrypt)
2641 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2642
2643 /*
2644 * Set the rssi offset.
2645 */
2646 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2647
2648 return 0;
2649}
2650
2651/*
2652 * IEEE80211 stack callback functions.
2653 */
2654static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2655 u32 *iv32, u16 *iv16)
2656{
2657 struct rt2x00_dev *rt2x00dev = hw->priv;
2658 struct mac_iveiv_entry iveiv_entry;
2659 u32 offset;
2660
2661 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2662 rt2x00usb_register_multiread(rt2x00dev, offset,
2663 &iveiv_entry, sizeof(iveiv_entry));
2664
2665 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2666 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2667}
2668
2669static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2670{
2671 struct rt2x00_dev *rt2x00dev = hw->priv;
2672 u32 reg;
2673 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2674
2675 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2676 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2677 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2678
2679 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2680 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2681 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2682
2683 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2684 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2685 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2686
2687 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2688 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2689 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2690
2691 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2692 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2693 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2694
2695 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2696 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2697 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2698
2699 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2700 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2701 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2702
2703 return 0;
2704}
2705
2706static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2707 const struct ieee80211_tx_queue_params *params)
2708{
2709 struct rt2x00_dev *rt2x00dev = hw->priv;
2710 struct data_queue *queue;
2711 struct rt2x00_field32 field;
2712 int retval;
2713 u32 reg;
2714 u32 offset;
2715
2716 /*
2717 * First pass the configuration through rt2x00lib, that will
2718 * update the queue settings and validate the input. After that
2719 * we are free to update the registers based on the value
2720 * in the queue parameter.
2721 */
2722 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2723 if (retval)
2724 return retval;
2725
2726 /*
2727 * We only need to perform additional register initialization
2728 * for WMM queues/
2729 */
2730 if (queue_idx >= 4)
2731 return 0;
2732
2733 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2734
2735 /* Update WMM TXOP register */
2736 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2737 field.bit_offset = (queue_idx & 1) * 16;
2738 field.bit_mask = 0xffff << field.bit_offset;
2739
2740 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2741 rt2x00_set_field32(&reg, field, queue->txop);
2742 rt2x00usb_register_write(rt2x00dev, offset, reg);
2743
2744 /* Update WMM registers */
2745 field.bit_offset = queue_idx * 4;
2746 field.bit_mask = 0xf << field.bit_offset;
2747
2748 rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2749 rt2x00_set_field32(&reg, field, queue->aifs);
2750 rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2751
2752 rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2753 rt2x00_set_field32(&reg, field, queue->cw_min);
2754 rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2755
2756 rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2757 rt2x00_set_field32(&reg, field, queue->cw_max);
2758 rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2759
2760 /* Update EDCA registers */
2761 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2762
2763 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2764 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2765 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2766 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2767 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2768 rt2x00usb_register_write(rt2x00dev, offset, reg);
2769
2770 return 0;
2771}
2772
2773static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2774{
2775 struct rt2x00_dev *rt2x00dev = hw->priv;
2776 u64 tsf;
2777 u32 reg;
2778
2779 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2780 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2781 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2782 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2783
2784 return tsf;
2785}
2786
2787static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2788 .tx = rt2x00mac_tx,
2789 .start = rt2x00mac_start,
2790 .stop = rt2x00mac_stop,
2791 .add_interface = rt2x00mac_add_interface,
2792 .remove_interface = rt2x00mac_remove_interface,
2793 .config = rt2x00mac_config,
2794 .configure_filter = rt2x00mac_configure_filter,
2795 .set_key = rt2x00mac_set_key,
2796 .get_stats = rt2x00mac_get_stats,
2797 .get_tkip_seq = rt2800usb_get_tkip_seq,
2798 .set_rts_threshold = rt2800usb_set_rts_threshold,
2799 .bss_info_changed = rt2x00mac_bss_info_changed,
2800 .conf_tx = rt2800usb_conf_tx,
2801 .get_tx_stats = rt2x00mac_get_tx_stats,
2802 .get_tsf = rt2800usb_get_tsf,
2803};
2804
2805static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2806 .probe_hw = rt2800usb_probe_hw,
2807 .get_firmware_name = rt2800usb_get_firmware_name,
2808 .check_firmware = rt2800usb_check_firmware,
2809 .load_firmware = rt2800usb_load_firmware,
2810 .initialize = rt2x00usb_initialize,
2811 .uninitialize = rt2x00usb_uninitialize,
2812 .clear_entry = rt2x00usb_clear_entry,
2813 .set_device_state = rt2800usb_set_device_state,
2814 .rfkill_poll = rt2800usb_rfkill_poll,
2815 .link_stats = rt2800usb_link_stats,
2816 .reset_tuner = rt2800usb_reset_tuner,
2817 .link_tuner = rt2800usb_link_tuner,
2818 .write_tx_desc = rt2800usb_write_tx_desc,
2819 .write_tx_data = rt2x00usb_write_tx_data,
2820 .write_beacon = rt2800usb_write_beacon,
2821 .get_tx_data_len = rt2800usb_get_tx_data_len,
2822 .kick_tx_queue = rt2800usb_kick_tx_queue,
2823 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2824 .fill_rxdone = rt2800usb_fill_rxdone,
2825 .config_shared_key = rt2800usb_config_shared_key,
2826 .config_pairwise_key = rt2800usb_config_pairwise_key,
2827 .config_filter = rt2800usb_config_filter,
2828 .config_intf = rt2800usb_config_intf,
2829 .config_erp = rt2800usb_config_erp,
2830 .config_ant = rt2800usb_config_ant,
2831 .config = rt2800usb_config,
2832};
2833
2834static const struct data_queue_desc rt2800usb_queue_rx = {
2835 .entry_num = RX_ENTRIES,
2836 .data_size = AGGREGATION_SIZE,
2837 .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2838 .priv_size = sizeof(struct queue_entry_priv_usb),
2839};
2840
2841static const struct data_queue_desc rt2800usb_queue_tx = {
2842 .entry_num = TX_ENTRIES,
2843 .data_size = AGGREGATION_SIZE,
2844 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2845 .priv_size = sizeof(struct queue_entry_priv_usb),
2846};
2847
2848static const struct data_queue_desc rt2800usb_queue_bcn = {
2849 .entry_num = 8 * BEACON_ENTRIES,
2850 .data_size = MGMT_FRAME_SIZE,
2851 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2852 .priv_size = sizeof(struct queue_entry_priv_usb),
2853};
2854
2855static const struct rt2x00_ops rt2800usb_ops = {
2856 .name = KBUILD_MODNAME,
2857 .max_sta_intf = 1,
2858 .max_ap_intf = 8,
2859 .eeprom_size = EEPROM_SIZE,
2860 .rf_size = RF_SIZE,
2861 .tx_queues = NUM_TX_QUEUES,
2862 .rx = &rt2800usb_queue_rx,
2863 .tx = &rt2800usb_queue_tx,
2864 .bcn = &rt2800usb_queue_bcn,
2865 .lib = &rt2800usb_rt2x00_ops,
2866 .hw = &rt2800usb_mac80211_ops,
2867#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2868 .debugfs = &rt2800usb_rt2x00debug,
2869#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2870};
2871
2872/*
2873 * rt2800usb module information.
2874 */
2875static struct usb_device_id rt2800usb_device_table[] = {
2876 /* Abocom */
2877 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2878 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2879 { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2880 { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2881 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2882 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2883 /* AirTies */
2884 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2885 /* Amigo */
2886 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2887 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2888 /* Amit */
2889 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2890 /* ASUS */
2891 { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2892 { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2893 { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2894 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2895 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2896 /* AzureWave */
2897 { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2898 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2899 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2900 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2901 /* Belkin */
2902 { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2903 { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2906 /* Buffalo */
2907 { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 /* Conceptronic */
2910 { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2912 { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2913 { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2915 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2917 { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2918 { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2919 { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2920 /* Corega */
2921 { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2922 { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2923 { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2926 /* D-Link */
2927 { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2930 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2931 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2933 { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2934 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2935 /* Edimax */
2936 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2939 /* Encore */
2940 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2941 /* EnGenius */
2942 { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2943 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2945 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2946 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2948 /* Gemtek */
2949 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2950 /* Gigabyte */
2951 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2953 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2954 /* Hawking */
2955 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2957 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2958 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2959 /* I-O DATA */
2960 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2961 /* LevelOne */
2962 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2964 /* Linksys */
2965 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2966 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2967 { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2968 /* Logitec */
2969 { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2971 { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2972 /* Motorola */
2973 { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2974 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2975 /* Ovislink */
2976 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2977 /* Pegatron */
2978 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2979 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2980 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2981 /* Philips */
2982 { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2983 /* Planex */
2984 { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2985 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2986 { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2987 /* Qcom */
2988 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2989 /* Quanta */
2990 { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2991 /* Ralink */
2992 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
2993 { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2994 { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2995 { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2997 { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3001 /* Samsung */
3002 { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3003 /* Siemens */
3004 { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3005 /* Sitecom */
3006 { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3007 { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3008 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3010 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3013 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3016 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3017 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3018 /* SMC */
3019 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3020 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3021 { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3022 { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3023 { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3024 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3025 { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3026 { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3027 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3028 /* Sparklan */
3029 { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3030 /* Sweex */
3031 { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3032 { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3033 { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3034 /* U-Media*/
3035 { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3036 /* ZCOM */
3037 { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3038 { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3039 /* Zinwell */
3040 { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3041 { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3042 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3043 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3044 /* Zyxel */
3045 { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3046 { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3047 { 0, }
3048};
3049
3050MODULE_AUTHOR(DRV_PROJECT);
3051MODULE_VERSION(DRV_VERSION);
3052MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3053MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3054MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3055MODULE_FIRMWARE(FIRMWARE_RT2870);
3056MODULE_LICENSE("GPL");
3057
3058static struct usb_driver rt2800usb_driver = {
3059 .name = KBUILD_MODNAME,
3060 .id_table = rt2800usb_device_table,
3061 .probe = rt2x00usb_probe,
3062 .disconnect = rt2x00usb_disconnect,
3063 .suspend = rt2x00usb_suspend,
3064 .resume = rt2x00usb_resume,
3065};
3066
3067static int __init rt2800usb_init(void)
3068{
3069 return usb_register(&rt2800usb_driver);
3070}
3071
3072static void __exit rt2800usb_exit(void)
3073{
3074 usb_deregister(&rt2800usb_driver);
3075}
3076
3077module_init(rt2800usb_init);
3078module_exit(rt2800usb_exit);
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
new file mode 100644
index 000000000000..61a8be61d3f5
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -0,0 +1,1945 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800usb
23 Abstract: Data structures and registers for the rt2800usb module.
24 Supported chipsets: RT2800U.
25 */
26
27#ifndef RT2800USB_H
28#define RT2800USB_H
29
30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 */
40#define RF2820 0x0001
41#define RF2850 0x0002
42#define RF2720 0x0003
43#define RF2750 0x0004
44#define RF3020 0x0005
45#define RF2020 0x0006
46
47/*
48 * RT2870 version
49 */
50#define RT2860C_VERSION 0x28600100
51#define RT2860D_VERSION 0x28600101
52#define RT2880E_VERSION 0x28720200
53#define RT2883_VERSION 0x28830300
54#define RT3070_VERSION 0x30700200
55
56/*
57 * Signal information.
58 * Defaul offset is required for RSSI <-> dBm conversion.
59 */
60#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
61
62/*
63 * Register layout information.
64 */
65#define CSR_REG_BASE 0x1000
66#define CSR_REG_SIZE 0x0800
67#define EEPROM_BASE 0x0000
68#define EEPROM_SIZE 0x0110
69#define BBP_BASE 0x0000
70#define BBP_SIZE 0x0080
71#define RF_BASE 0x0004
72#define RF_SIZE 0x0010
73
74/*
75 * Number of TX queues.
76 */
77#define NUM_TX_QUEUES 4
78
79/*
80 * USB registers.
81 */
82
83/*
84 * HOST-MCU shared memory
85 */
86#define HOST_CMD_CSR 0x0404
87#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
88
89/*
90 * INT_SOURCE_CSR: Interrupt source register.
91 * Write one to clear corresponding bit.
92 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
93 */
94#define INT_SOURCE_CSR 0x0200
95#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
96#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
97#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
98#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
99#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
100#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
101#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
102#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
103#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
104#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
105#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
106#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
107#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
108#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
109#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
110#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
111#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
112#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
113
114/*
115 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
116 */
117#define INT_MASK_CSR 0x0204
118#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
119#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
120#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
121#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
122#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
123#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
124#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
125#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
126#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
127#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
128#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
129#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
130#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
131#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
132#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
133#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
134#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
135#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
136
137/*
138 * WPDMA_GLO_CFG
139 */
140#define WPDMA_GLO_CFG 0x0208
141#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
142#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
143#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
144#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
145#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
146#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
147#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
148#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
149#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
150
151/*
152 * WPDMA_RST_IDX
153 */
154#define WPDMA_RST_IDX 0x020c
155#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
156#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
157#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
158#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
159#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
160#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
161#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
162
163/*
164 * DELAY_INT_CFG
165 */
166#define DELAY_INT_CFG 0x0210
167#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
168#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
169#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
170#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
171#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
172#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
173
174/*
175 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
176 * AIFSN0: AC_BE
177 * AIFSN1: AC_BK
178 * AIFSN1: AC_VI
179 * AIFSN1: AC_VO
180 */
181#define WMM_AIFSN_CFG 0x0214
182#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
183#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
184#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
185#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
186
187/*
188 * WMM_CWMIN_CSR: CWmin for each EDCA AC
189 * CWMIN0: AC_BE
190 * CWMIN1: AC_BK
191 * CWMIN1: AC_VI
192 * CWMIN1: AC_VO
193 */
194#define WMM_CWMIN_CFG 0x0218
195#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
196#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
197#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
198#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
199
200/*
201 * WMM_CWMAX_CSR: CWmax for each EDCA AC
202 * CWMAX0: AC_BE
203 * CWMAX1: AC_BK
204 * CWMAX1: AC_VI
205 * CWMAX1: AC_VO
206 */
207#define WMM_CWMAX_CFG 0x021c
208#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
209#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
210#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
211#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
212
213/*
214 * AC_TXOP0: AC_BK/AC_BE TXOP register
215 * AC0TXOP: AC_BK in unit of 32us
216 * AC1TXOP: AC_BE in unit of 32us
217 */
218#define WMM_TXOP0_CFG 0x0220
219#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
220#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
221
222/*
223 * AC_TXOP1: AC_VO/AC_VI TXOP register
224 * AC2TXOP: AC_VI in unit of 32us
225 * AC3TXOP: AC_VO in unit of 32us
226 */
227#define WMM_TXOP1_CFG 0x0224
228#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
229#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
230
231/*
232 * GPIO_CTRL_CFG:
233 */
234#define GPIO_CTRL_CFG 0x0228
235#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
236#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
237#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
238#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
239#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
240#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
241#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
242#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
243#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
244
245/*
246 * MCU_CMD_CFG
247 */
248#define MCU_CMD_CFG 0x022c
249
250/*
251 * AC_BK register offsets
252 */
253#define TX_BASE_PTR0 0x0230
254#define TX_MAX_CNT0 0x0234
255#define TX_CTX_IDX0 0x0238
256#define TX_DTX_IDX0 0x023c
257
258/*
259 * AC_BE register offsets
260 */
261#define TX_BASE_PTR1 0x0240
262#define TX_MAX_CNT1 0x0244
263#define TX_CTX_IDX1 0x0248
264#define TX_DTX_IDX1 0x024c
265
266/*
267 * AC_VI register offsets
268 */
269#define TX_BASE_PTR2 0x0250
270#define TX_MAX_CNT2 0x0254
271#define TX_CTX_IDX2 0x0258
272#define TX_DTX_IDX2 0x025c
273
274/*
275 * AC_VO register offsets
276 */
277#define TX_BASE_PTR3 0x0260
278#define TX_MAX_CNT3 0x0264
279#define TX_CTX_IDX3 0x0268
280#define TX_DTX_IDX3 0x026c
281
282/*
283 * HCCA register offsets
284 */
285#define TX_BASE_PTR4 0x0270
286#define TX_MAX_CNT4 0x0274
287#define TX_CTX_IDX4 0x0278
288#define TX_DTX_IDX4 0x027c
289
290/*
291 * MGMT register offsets
292 */
293#define TX_BASE_PTR5 0x0280
294#define TX_MAX_CNT5 0x0284
295#define TX_CTX_IDX5 0x0288
296#define TX_DTX_IDX5 0x028c
297
298/*
299 * RX register offsets
300 */
301#define RX_BASE_PTR 0x0290
302#define RX_MAX_CNT 0x0294
303#define RX_CRX_IDX 0x0298
304#define RX_DRX_IDX 0x029c
305
306/*
307 * USB_DMA_CFG
308 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
309 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
310 * PHY_CLEAR: phy watch dog enable.
311 * TX_CLEAR: Clear USB DMA TX path.
312 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
313 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
314 * RX_BULK_EN: Enable USB DMA Rx.
315 * TX_BULK_EN: Enable USB DMA Tx.
316 * EP_OUT_VALID: OUT endpoint data valid.
317 * RX_BUSY: USB DMA RX FSM busy.
318 * TX_BUSY: USB DMA TX FSM busy.
319 */
320#define USB_DMA_CFG 0x02a0
321#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
322#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
323#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
324#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
325#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
326#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
327#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
328#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
329#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
330#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
331#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
332
333/*
334 * USB_CYC_CFG
335 */
336#define USB_CYC_CFG 0x02a4
337#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
338
339/*
340 * PBF_SYS_CTRL
341 * HOST_RAM_WRITE: enable Host program ram write selection
342 */
343#define PBF_SYS_CTRL 0x0400
344#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
345#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
346
347/*
348 * PBF registers
349 * Most are for debug. Driver doesn't touch PBF register.
350 */
351#define PBF_CFG 0x0408
352#define PBF_MAX_PCNT 0x040c
353#define PBF_CTRL 0x0410
354#define PBF_INT_STA 0x0414
355#define PBF_INT_ENA 0x0418
356
357/*
358 * BCN_OFFSET0:
359 */
360#define BCN_OFFSET0 0x042c
361#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
362#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
363#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
364#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
365
366/*
367 * BCN_OFFSET1:
368 */
369#define BCN_OFFSET1 0x0430
370#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
371#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
372#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
373#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
374
375/*
376 * PBF registers
377 * Most are for debug. Driver doesn't touch PBF register.
378 */
379#define TXRXQ_PCNT 0x0438
380#define PBF_DBG 0x043c
381
382/*
383 * RF registers
384 */
385#define RF_CSR_CFG 0x0500
386#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
387#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
388#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
389#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
390
391/*
392 * MAC Control/Status Registers(CSR).
393 * Some values are set in TU, whereas 1 TU == 1024 us.
394 */
395
396/*
397 * MAC_CSR0: ASIC revision number.
398 * ASIC_REV: 0
399 * ASIC_VER: 2870
400 */
401#define MAC_CSR0 0x1000
402#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
403#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
404
405/*
406 * MAC_SYS_CTRL:
407 */
408#define MAC_SYS_CTRL 0x1004
409#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
410#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
411#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
412#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
413#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
414#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
415#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
416#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
417
418/*
419 * MAC_ADDR_DW0: STA MAC register 0
420 */
421#define MAC_ADDR_DW0 0x1008
422#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
423#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
424#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
425#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
426
427/*
428 * MAC_ADDR_DW1: STA MAC register 1
429 * UNICAST_TO_ME_MASK:
430 * Used to mask off bits from byte 5 of the MAC address
431 * to determine the UNICAST_TO_ME bit for RX frames.
432 * The full mask is complemented by BSS_ID_MASK:
433 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
434 */
435#define MAC_ADDR_DW1 0x100c
436#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
437#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
438#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
439
440/*
441 * MAC_BSSID_DW0: BSSID register 0
442 */
443#define MAC_BSSID_DW0 0x1010
444#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
445#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
446#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
447#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
448
449/*
450 * MAC_BSSID_DW1: BSSID register 1
451 * BSS_ID_MASK:
452 * 0: 1-BSSID mode (BSS index = 0)
453 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
454 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
455 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
456 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
457 * BSSID. This will make sure that those bits will be ignored
458 * when determining the MY_BSS of RX frames.
459 */
460#define MAC_BSSID_DW1 0x1014
461#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
462#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
463#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
464#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
465
466/*
467 * MAX_LEN_CFG: Maximum frame length register.
468 * MAX_MPDU: rt2860b max 16k bytes
469 * MAX_PSDU: Maximum PSDU length
470 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
471 */
472#define MAX_LEN_CFG 0x1018
473#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
474#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
475#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
476#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
477
478/*
479 * BBP_CSR_CFG: BBP serial control register
480 * VALUE: Register value to program into BBP
481 * REG_NUM: Selected BBP register
482 * READ_CONTROL: 0 write BBP, 1 read BBP
483 * BUSY: ASIC is busy executing BBP commands
484 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
485 * BBP_RW_MODE: 0 serial, 1 paralell
486 */
487#define BBP_CSR_CFG 0x101c
488#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
489#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
490#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
491#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
492#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
493#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
494
495/*
496 * RF_CSR_CFG0: RF control register
497 * REGID_AND_VALUE: Register value to program into RF
498 * BITWIDTH: Selected RF register
499 * STANDBYMODE: 0 high when standby, 1 low when standby
500 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
501 * BUSY: ASIC is busy executing RF commands
502 */
503#define RF_CSR_CFG0 0x1020
504#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
505#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
506#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
507#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
508#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
509#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
510
511/*
512 * RF_CSR_CFG1: RF control register
513 * REGID_AND_VALUE: Register value to program into RF
514 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
515 * 0: 3 system clock cycle (37.5usec)
516 * 1: 5 system clock cycle (62.5usec)
517 */
518#define RF_CSR_CFG1 0x1024
519#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
520#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
521
522/*
523 * RF_CSR_CFG2: RF control register
524 * VALUE: Register value to program into RF
525 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
526 * 0: 3 system clock cycle (37.5usec)
527 * 1: 5 system clock cycle (62.5usec)
528 */
529#define RF_CSR_CFG2 0x1028
530#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
531
532/*
533 * LED_CFG: LED control
534 * color LED's:
535 * 0: off
536 * 1: blinking upon TX2
537 * 2: periodic slow blinking
538 * 3: always on
539 * LED polarity:
540 * 0: active low
541 * 1: active high
542 */
543#define LED_CFG 0x102c
544#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
545#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
546#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
547#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
548#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
549#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
550#define LED_CFG_LED_POLAR FIELD32(0x40000000)
551
552/*
553 * XIFS_TIME_CFG: MAC timing
554 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
555 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
556 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
557 * when MAC doesn't reference BBP signal BBRXEND
558 * EIFS: unit 1us
559 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
560 *
561 */
562#define XIFS_TIME_CFG 0x1100
563#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
564#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
565#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
566#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
567#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
568
569/*
570 * BKOFF_SLOT_CFG:
571 */
572#define BKOFF_SLOT_CFG 0x1104
573#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
574#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
575
576/*
577 * NAV_TIME_CFG:
578 */
579#define NAV_TIME_CFG 0x1108
580#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
581#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
582#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
583#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
584
585/*
586 * CH_TIME_CFG: count as channel busy
587 */
588#define CH_TIME_CFG 0x110c
589
590/*
591 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
592 */
593#define PBF_LIFE_TIMER 0x1110
594
595/*
596 * BCN_TIME_CFG:
597 * BEACON_INTERVAL: in unit of 1/16 TU
598 * TSF_TICKING: Enable TSF auto counting
599 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
600 * BEACON_GEN: Enable beacon generator
601 */
602#define BCN_TIME_CFG 0x1114
603#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
604#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
605#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
606#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
607#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
608#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
609
610/*
611 * TBTT_SYNC_CFG:
612 */
613#define TBTT_SYNC_CFG 0x1118
614
615/*
616 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
617 */
618#define TSF_TIMER_DW0 0x111c
619#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
620
621/*
622 * TSF_TIMER_DW1: Local msb TSF timer, read-only
623 */
624#define TSF_TIMER_DW1 0x1120
625#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
626
627/*
628 * TBTT_TIMER: TImer remains till next TBTT, read-only
629 */
630#define TBTT_TIMER 0x1124
631
632/*
633 * INT_TIMER_CFG:
634 */
635#define INT_TIMER_CFG 0x1128
636
637/*
638 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
639 */
640#define INT_TIMER_EN 0x112c
641
642/*
643 * CH_IDLE_STA: channel idle time
644 */
645#define CH_IDLE_STA 0x1130
646
647/*
648 * CH_BUSY_STA: channel busy time
649 */
650#define CH_BUSY_STA 0x1134
651
652/*
653 * MAC_STATUS_CFG:
654 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
655 * if 1 or higher one of the 2 registers is busy.
656 */
657#define MAC_STATUS_CFG 0x1200
658#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
659
660/*
661 * PWR_PIN_CFG:
662 */
663#define PWR_PIN_CFG 0x1204
664
665/*
666 * AUTOWAKEUP_CFG: Manual power control / status register
667 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
668 * AUTOWAKE: 0:sleep, 1:awake
669 */
670#define AUTOWAKEUP_CFG 0x1208
671#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
672#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
673#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
674
675/*
676 * EDCA_AC0_CFG:
677 */
678#define EDCA_AC0_CFG 0x1300
679#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
680#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
681#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
682#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
683
684/*
685 * EDCA_AC1_CFG:
686 */
687#define EDCA_AC1_CFG 0x1304
688#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
689#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
690#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
691#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
692
693/*
694 * EDCA_AC2_CFG:
695 */
696#define EDCA_AC2_CFG 0x1308
697#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
698#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
699#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
700#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
701
702/*
703 * EDCA_AC3_CFG:
704 */
705#define EDCA_AC3_CFG 0x130c
706#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
707#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
708#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
709#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
710
711/*
712 * EDCA_TID_AC_MAP:
713 */
714#define EDCA_TID_AC_MAP 0x1310
715
716/*
717 * TX_PWR_CFG_0:
718 */
719#define TX_PWR_CFG_0 0x1314
720#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
721#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
722#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
723#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
724#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
725#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
726#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
727#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
728
729/*
730 * TX_PWR_CFG_1:
731 */
732#define TX_PWR_CFG_1 0x1318
733#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
734#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
735#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
736#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
737#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
738#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
739#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
740#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
741
742/*
743 * TX_PWR_CFG_2:
744 */
745#define TX_PWR_CFG_2 0x131c
746#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
747#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
748#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
749#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
750#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
751#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
752#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
753#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
754
755/*
756 * TX_PWR_CFG_3:
757 */
758#define TX_PWR_CFG_3 0x1320
759#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
760#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
761#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
762#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
763#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
764#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
765#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
766#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
767
768/*
769 * TX_PWR_CFG_4:
770 */
771#define TX_PWR_CFG_4 0x1324
772#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
773#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
774#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
775#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
776
777/*
778 * TX_PIN_CFG:
779 */
780#define TX_PIN_CFG 0x1328
781#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
782#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
783#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
784#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
785#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
786#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
787#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
788#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
789#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
790#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
791#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
792#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
793#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
794#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
795#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
796#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
797#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
798#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
799#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
800#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
801
802/*
803 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
804 */
805#define TX_BAND_CFG 0x132c
806#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
807#define TX_BAND_CFG_A FIELD32(0x00000002)
808#define TX_BAND_CFG_BG FIELD32(0x00000004)
809
810/*
811 * TX_SW_CFG0:
812 */
813#define TX_SW_CFG0 0x1330
814
815/*
816 * TX_SW_CFG1:
817 */
818#define TX_SW_CFG1 0x1334
819
820/*
821 * TX_SW_CFG2:
822 */
823#define TX_SW_CFG2 0x1338
824
825/*
826 * TXOP_THRES_CFG:
827 */
828#define TXOP_THRES_CFG 0x133c
829
830/*
831 * TXOP_CTRL_CFG:
832 */
833#define TXOP_CTRL_CFG 0x1340
834
835/*
836 * TX_RTS_CFG:
837 * RTS_THRES: unit:byte
838 * RTS_FBK_EN: enable rts rate fallback
839 */
840#define TX_RTS_CFG 0x1344
841#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
842#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
843#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
844
845/*
846 * TX_TIMEOUT_CFG:
847 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
848 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
849 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
850 * it is recommended that:
851 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
852 */
853#define TX_TIMEOUT_CFG 0x1348
854#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
855#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
856#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
857
858/*
859 * TX_RTY_CFG:
860 * SHORT_RTY_LIMIT: short retry limit
861 * LONG_RTY_LIMIT: long retry limit
862 * LONG_RTY_THRE: Long retry threshoold
863 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
864 * 0:expired by retry limit, 1: expired by mpdu life timer
865 * AGG_RTY_MODE: Aggregate MPDU retry mode
866 * 0:expired by retry limit, 1: expired by mpdu life timer
867 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
868 */
869#define TX_RTY_CFG 0x134c
870#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
871#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
872#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
873#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
874#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
875#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
876
877/*
878 * TX_LINK_CFG:
879 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
880 * MFB_ENABLE: TX apply remote MFB 1:enable
881 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
882 * 0: not apply remote remote unsolicit (MFS=7)
883 * TX_MRQ_EN: MCS request TX enable
884 * TX_RDG_EN: RDG TX enable
885 * TX_CF_ACK_EN: Piggyback CF-ACK enable
886 * REMOTE_MFB: remote MCS feedback
887 * REMOTE_MFS: remote MCS feedback sequence number
888 */
889#define TX_LINK_CFG 0x1350
890#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
891#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
892#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
893#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
894#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
895#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
896#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
897#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
898
899/*
900 * HT_FBK_CFG0:
901 */
902#define HT_FBK_CFG0 0x1354
903#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
904#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
905#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
906#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
907#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
908#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
909#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
910#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
911
912/*
913 * HT_FBK_CFG1:
914 */
915#define HT_FBK_CFG1 0x1358
916#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
917#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
918#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
919#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
920#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
921#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
922#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
923#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
924
925/*
926 * LG_FBK_CFG0:
927 */
928#define LG_FBK_CFG0 0x135c
929#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
930#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
931#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
932#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
933#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
934#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
935#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
936#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
937
938/*
939 * LG_FBK_CFG1:
940 */
941#define LG_FBK_CFG1 0x1360
942#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
943#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
944#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
945#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
946
947/*
948 * CCK_PROT_CFG: CCK Protection
949 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
950 * PROTECT_CTRL: Protection control frame type for CCK TX
951 * 0:none, 1:RTS/CTS, 2:CTS-to-self
952 * PROTECT_NAV: TXOP protection type for CCK TX
953 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
954 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
955 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
956 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
957 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
958 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
959 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
960 * RTS_TH_EN: RTS threshold enable on CCK TX
961 */
962#define CCK_PROT_CFG 0x1364
963#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
964#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
965#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
966#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
967#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
968#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
969#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
970#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
971#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
972#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
973
974/*
975 * OFDM_PROT_CFG: OFDM Protection
976 */
977#define OFDM_PROT_CFG 0x1368
978#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
979#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
980#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
981#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
982#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
983#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
984#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
985#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
986#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
987#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
988
989/*
990 * MM20_PROT_CFG: MM20 Protection
991 */
992#define MM20_PROT_CFG 0x136c
993#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
994#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
995#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
996#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
997#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
998#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
999#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1000#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1001#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1002#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1003
1004/*
1005 * MM40_PROT_CFG: MM40 Protection
1006 */
1007#define MM40_PROT_CFG 0x1370
1008#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1009#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1010#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1011#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1012#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1013#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1014#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1015#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1016#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1017#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1018
1019/*
1020 * GF20_PROT_CFG: GF20 Protection
1021 */
1022#define GF20_PROT_CFG 0x1374
1023#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1024#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1025#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1026#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1027#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1028#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1029#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1030#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1031#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1032#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1033
1034/*
1035 * GF40_PROT_CFG: GF40 Protection
1036 */
1037#define GF40_PROT_CFG 0x1378
1038#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1039#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1040#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1041#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1042#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1043#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1044#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1045#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1046#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1047#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1048
1049/*
1050 * EXP_CTS_TIME:
1051 */
1052#define EXP_CTS_TIME 0x137c
1053
1054/*
1055 * EXP_ACK_TIME:
1056 */
1057#define EXP_ACK_TIME 0x1380
1058
1059/*
1060 * RX_FILTER_CFG: RX configuration register.
1061 */
1062#define RX_FILTER_CFG 0x1400
1063#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1064#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1065#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1066#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1067#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1068#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1069#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1070#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1071#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1072#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1073#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1074#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1075#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1076#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1077#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1078#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1079#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1080
1081/*
1082 * AUTO_RSP_CFG:
1083 * AUTORESPONDER: 0: disable, 1: enable
1084 * BAC_ACK_POLICY: 0:long, 1:short preamble
1085 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1086 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1087 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1088 * DUAL_CTS_EN: Power bit value in control frame
1089 * ACK_CTS_PSM_BIT:Power bit value in control frame
1090 */
1091#define AUTO_RSP_CFG 0x1404
1092#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1093#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1094#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1095#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1096#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1097#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1098#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1099
1100/*
1101 * LEGACY_BASIC_RATE:
1102 */
1103#define LEGACY_BASIC_RATE 0x1408
1104
1105/*
1106 * HT_BASIC_RATE:
1107 */
1108#define HT_BASIC_RATE 0x140c
1109
1110/*
1111 * HT_CTRL_CFG:
1112 */
1113#define HT_CTRL_CFG 0x1410
1114
1115/*
1116 * SIFS_COST_CFG:
1117 */
1118#define SIFS_COST_CFG 0x1414
1119
1120/*
1121 * RX_PARSER_CFG:
1122 * Set NAV for all received frames
1123 */
1124#define RX_PARSER_CFG 0x1418
1125
1126/*
1127 * TX_SEC_CNT0:
1128 */
1129#define TX_SEC_CNT0 0x1500
1130
1131/*
1132 * RX_SEC_CNT0:
1133 */
1134#define RX_SEC_CNT0 0x1504
1135
1136/*
1137 * CCMP_FC_MUTE:
1138 */
1139#define CCMP_FC_MUTE 0x1508
1140
1141/*
1142 * TXOP_HLDR_ADDR0:
1143 */
1144#define TXOP_HLDR_ADDR0 0x1600
1145
1146/*
1147 * TXOP_HLDR_ADDR1:
1148 */
1149#define TXOP_HLDR_ADDR1 0x1604
1150
1151/*
1152 * TXOP_HLDR_ET:
1153 */
1154#define TXOP_HLDR_ET 0x1608
1155
1156/*
1157 * QOS_CFPOLL_RA_DW0:
1158 */
1159#define QOS_CFPOLL_RA_DW0 0x160c
1160
1161/*
1162 * QOS_CFPOLL_RA_DW1:
1163 */
1164#define QOS_CFPOLL_RA_DW1 0x1610
1165
1166/*
1167 * QOS_CFPOLL_QC:
1168 */
1169#define QOS_CFPOLL_QC 0x1614
1170
1171/*
1172 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1173 */
1174#define RX_STA_CNT0 0x1700
1175#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1176#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1177
1178/*
1179 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1180 */
1181#define RX_STA_CNT1 0x1704
1182#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1183#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1184
1185/*
1186 * RX_STA_CNT2:
1187 */
1188#define RX_STA_CNT2 0x1708
1189#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1190#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1191
1192/*
1193 * TX_STA_CNT0: TX Beacon count
1194 */
1195#define TX_STA_CNT0 0x170c
1196#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1197#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1198
1199/*
1200 * TX_STA_CNT1: TX tx count
1201 */
1202#define TX_STA_CNT1 0x1710
1203#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1204#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1205
1206/*
1207 * TX_STA_CNT2: TX tx count
1208 */
1209#define TX_STA_CNT2 0x1714
1210#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1211#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1212
1213/*
1214 * TX_STA_FIFO: TX Result for specific PID status fifo register
1215 */
1216#define TX_STA_FIFO 0x1718
1217#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1218#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1219#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1220#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1221#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1222#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1223#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1224
1225/*
1226 * TX_AGG_CNT: Debug counter
1227 */
1228#define TX_AGG_CNT 0x171c
1229#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1230#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1231
1232/*
1233 * TX_AGG_CNT0:
1234 */
1235#define TX_AGG_CNT0 0x1720
1236#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1237#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1238
1239/*
1240 * TX_AGG_CNT1:
1241 */
1242#define TX_AGG_CNT1 0x1724
1243#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1244#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1245
1246/*
1247 * TX_AGG_CNT2:
1248 */
1249#define TX_AGG_CNT2 0x1728
1250#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1251#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1252
1253/*
1254 * TX_AGG_CNT3:
1255 */
1256#define TX_AGG_CNT3 0x172c
1257#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1258#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1259
1260/*
1261 * TX_AGG_CNT4:
1262 */
1263#define TX_AGG_CNT4 0x1730
1264#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1265#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1266
1267/*
1268 * TX_AGG_CNT5:
1269 */
1270#define TX_AGG_CNT5 0x1734
1271#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1272#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1273
1274/*
1275 * TX_AGG_CNT6:
1276 */
1277#define TX_AGG_CNT6 0x1738
1278#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1279#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1280
1281/*
1282 * TX_AGG_CNT7:
1283 */
1284#define TX_AGG_CNT7 0x173c
1285#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1286#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1287
1288/*
1289 * MPDU_DENSITY_CNT:
1290 * TX_ZERO_DEL: TX zero length delimiter count
1291 * RX_ZERO_DEL: RX zero length delimiter count
1292 */
1293#define MPDU_DENSITY_CNT 0x1740
1294#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1295#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1296
1297/*
1298 * Security key table memory.
1299 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1300 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1301 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1302 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1303 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1304 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1305 */
1306#define MAC_WCID_BASE 0x1800
1307#define PAIRWISE_KEY_TABLE_BASE 0x4000
1308#define MAC_IVEIV_TABLE_BASE 0x6000
1309#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1310#define SHARED_KEY_TABLE_BASE 0x6c00
1311#define SHARED_KEY_MODE_BASE 0x7000
1312
1313#define MAC_WCID_ENTRY(__idx) \
1314 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1315#define PAIRWISE_KEY_ENTRY(__idx) \
1316 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1317#define MAC_IVEIV_ENTRY(__idx) \
1318 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1319#define MAC_WCID_ATTR_ENTRY(__idx) \
1320 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1321#define SHARED_KEY_ENTRY(__idx) \
1322 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1323#define SHARED_KEY_MODE_ENTRY(__idx) \
1324 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1325
1326struct mac_wcid_entry {
1327 u8 mac[6];
1328 u8 reserved[2];
1329} __attribute__ ((packed));
1330
1331struct hw_key_entry {
1332 u8 key[16];
1333 u8 tx_mic[8];
1334 u8 rx_mic[8];
1335} __attribute__ ((packed));
1336
1337struct mac_iveiv_entry {
1338 u8 iv[8];
1339} __attribute__ ((packed));
1340
1341/*
1342 * MAC_WCID_ATTRIBUTE:
1343 */
1344#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1345#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1346#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1347#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1348
1349/*
1350 * SHARED_KEY_MODE:
1351 */
1352#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1353#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1354#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1355#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1356#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1357#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1358#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1359#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1360
1361/*
1362 * HOST-MCU communication
1363 */
1364
1365/*
1366 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1367 */
1368#define H2M_MAILBOX_CSR 0x7010
1369#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1370#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1371#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1372#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1373
1374/*
1375 * H2M_MAILBOX_CID:
1376 */
1377#define H2M_MAILBOX_CID 0x7014
1378#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1379#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1380#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1381#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1382
1383/*
1384 * H2M_MAILBOX_STATUS:
1385 */
1386#define H2M_MAILBOX_STATUS 0x701c
1387
1388/*
1389 * H2M_INT_SRC:
1390 */
1391#define H2M_INT_SRC 0x7024
1392
1393/*
1394 * H2M_BBP_AGENT:
1395 */
1396#define H2M_BBP_AGENT 0x7028
1397
1398/*
1399 * MCU_LEDCS: LED control for MCU Mailbox.
1400 */
1401#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1402#define MCU_LEDCS_POLARITY FIELD8(0x01)
1403
1404/*
1405 * HW_CS_CTS_BASE:
1406 * Carrier-sense CTS frame base address.
1407 * It's where mac stores carrier-sense frame for carrier-sense function.
1408 */
1409#define HW_CS_CTS_BASE 0x7700
1410
1411/*
1412 * HW_DFS_CTS_BASE:
1413 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1414 */
1415#define HW_DFS_CTS_BASE 0x7780
1416
1417/*
1418 * TXRX control registers - base address 0x3000
1419 */
1420
1421/*
1422 * TXRX_CSR1:
1423 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1424 */
1425#define TXRX_CSR1 0x77d0
1426
1427/*
1428 * HW_DEBUG_SETTING_BASE:
1429 * since NULL frame won't be that long (256 byte)
1430 * We steal 16 tail bytes to save debugging settings
1431 */
1432#define HW_DEBUG_SETTING_BASE 0x77f0
1433#define HW_DEBUG_SETTING_BASE2 0x7770
1434
1435/*
1436 * HW_BEACON_BASE
1437 * In order to support maximum 8 MBSS and its maximum length
1438 * is 512 bytes for each beacon
1439 * Three section discontinue memory segments will be used.
1440 * 1. The original region for BCN 0~3
1441 * 2. Extract memory from FCE table for BCN 4~5
1442 * 3. Extract memory from Pair-wise key table for BCN 6~7
1443 * It occupied those memory of wcid 238~253 for BCN 6
1444 * and wcid 222~237 for BCN 7
1445 *
1446 * IMPORTANT NOTE: Not sure why legacy driver does this,
1447 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1448 */
1449#define HW_BEACON_BASE0 0x7800
1450#define HW_BEACON_BASE1 0x7a00
1451#define HW_BEACON_BASE2 0x7c00
1452#define HW_BEACON_BASE3 0x7e00
1453#define HW_BEACON_BASE4 0x7200
1454#define HW_BEACON_BASE5 0x7400
1455#define HW_BEACON_BASE6 0x5dc0
1456#define HW_BEACON_BASE7 0x5bc0
1457
1458#define HW_BEACON_OFFSET(__index) \
1459 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1460 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1461 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1462
1463/*
1464 * 8051 firmware image.
1465 */
1466#define FIRMWARE_RT2870 "rt2870.bin"
1467#define FIRMWARE_IMAGE_BASE 0x3000
1468
1469/*
1470 * BBP registers.
1471 * The wordsize of the BBP is 8 bits.
1472 */
1473
1474/*
1475 * BBP 1: TX Antenna
1476 */
1477#define BBP1_TX_POWER FIELD8(0x07)
1478#define BBP1_TX_ANTENNA FIELD8(0x18)
1479
1480/*
1481 * BBP 3: RX Antenna
1482 */
1483#define BBP3_RX_ANTENNA FIELD8(0x18)
1484#define BBP3_HT40_PLUS FIELD8(0x20)
1485
1486/*
1487 * BBP 4: Bandwidth
1488 */
1489#define BBP4_TX_BF FIELD8(0x01)
1490#define BBP4_BANDWIDTH FIELD8(0x18)
1491
1492/*
1493 * RFCSR registers
1494 * The wordsize of the RFCSR is 8 bits.
1495 */
1496
1497/*
1498 * RFCSR 6:
1499 */
1500#define RFCSR6_R FIELD8(0x03)
1501
1502/*
1503 * RFCSR 7:
1504 */
1505#define RFCSR7_RF_TUNING FIELD8(0x01)
1506
1507/*
1508 * RFCSR 12:
1509 */
1510#define RFCSR12_TX_POWER FIELD8(0x1f)
1511
1512/*
1513 * RFCSR 22:
1514 */
1515#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1516
1517/*
1518 * RFCSR 23:
1519 */
1520#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1521
1522/*
1523 * RFCSR 30:
1524 */
1525#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1526
1527/*
1528 * RF registers
1529 */
1530
1531/*
1532 * RF 2
1533 */
1534#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1535#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1536#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1537
1538/*
1539 * RF 3
1540 */
1541#define RF3_TXPOWER_G FIELD32(0x00003e00)
1542#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1543#define RF3_TXPOWER_A FIELD32(0x00003c00)
1544
1545/*
1546 * RF 4
1547 */
1548#define RF4_TXPOWER_G FIELD32(0x000007c0)
1549#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1550#define RF4_TXPOWER_A FIELD32(0x00000780)
1551#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1552#define RF4_HT40 FIELD32(0x00200000)
1553
1554/*
1555 * EEPROM content.
1556 * The wordsize of the EEPROM is 16 bits.
1557 */
1558
1559/*
1560 * EEPROM Version
1561 */
1562#define EEPROM_VERSION 0x0001
1563#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1564#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1565
1566/*
1567 * HW MAC address.
1568 */
1569#define EEPROM_MAC_ADDR_0 0x0002
1570#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1571#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1572#define EEPROM_MAC_ADDR_1 0x0003
1573#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1574#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1575#define EEPROM_MAC_ADDR_2 0x0004
1576#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1577#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1578
1579/*
1580 * EEPROM ANTENNA config
1581 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1582 * TXPATH: 1: 1T, 2: 2T
1583 */
1584#define EEPROM_ANTENNA 0x001a
1585#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1586#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1587#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1588
1589/*
1590 * EEPROM NIC config
1591 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1592 */
1593#define EEPROM_NIC 0x001b
1594#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1595#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1596#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1597#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1598#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1599#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1600#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1601#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1602#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1603#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1604
1605/*
1606 * EEPROM frequency
1607 */
1608#define EEPROM_FREQ 0x001d
1609#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1610#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1611#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1612
1613/*
1614 * EEPROM LED
1615 * POLARITY_RDY_G: Polarity RDY_G setting.
1616 * POLARITY_RDY_A: Polarity RDY_A setting.
1617 * POLARITY_ACT: Polarity ACT setting.
1618 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1619 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1620 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1621 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1622 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1623 * LED_MODE: Led mode.
1624 */
1625#define EEPROM_LED1 0x001e
1626#define EEPROM_LED2 0x001f
1627#define EEPROM_LED3 0x0020
1628#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1629#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1630#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1631#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1632#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1633#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1634#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1635#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1636#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1637
1638/*
1639 * EEPROM LNA
1640 */
1641#define EEPROM_LNA 0x0022
1642#define EEPROM_LNA_BG FIELD16(0x00ff)
1643#define EEPROM_LNA_A0 FIELD16(0xff00)
1644
1645/*
1646 * EEPROM RSSI BG offset
1647 */
1648#define EEPROM_RSSI_BG 0x0023
1649#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1650#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1651
1652/*
1653 * EEPROM RSSI BG2 offset
1654 */
1655#define EEPROM_RSSI_BG2 0x0024
1656#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1657#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1658
1659/*
1660 * EEPROM RSSI A offset
1661 */
1662#define EEPROM_RSSI_A 0x0025
1663#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1664#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1665
1666/*
1667 * EEPROM RSSI A2 offset
1668 */
1669#define EEPROM_RSSI_A2 0x0026
1670#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1671#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1672
1673/*
1674 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1675 * This is delta in 40MHZ.
1676 * VALUE: Tx Power dalta value (MAX=4)
1677 * TYPE: 1: Plus the delta value, 0: minus the delta value
1678 * TXPOWER: Enable:
1679 */
1680#define EEPROM_TXPOWER_DELTA 0x0028
1681#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1682#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1683#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1684
1685/*
1686 * EEPROM TXPOWER 802.11BG
1687 */
1688#define EEPROM_TXPOWER_BG1 0x0029
1689#define EEPROM_TXPOWER_BG2 0x0030
1690#define EEPROM_TXPOWER_BG_SIZE 7
1691#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1692#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1693
1694/*
1695 * EEPROM TXPOWER 802.11A
1696 */
1697#define EEPROM_TXPOWER_A1 0x003c
1698#define EEPROM_TXPOWER_A2 0x0053
1699#define EEPROM_TXPOWER_A_SIZE 6
1700#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1701#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1702
1703/*
1704 * EEPROM TXpower byrate: 20MHZ power
1705 */
1706#define EEPROM_TXPOWER_BYRATE 0x006f
1707
1708/*
1709 * EEPROM BBP.
1710 */
1711#define EEPROM_BBP_START 0x0078
1712#define EEPROM_BBP_SIZE 16
1713#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1714#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1715
1716/*
1717 * MCU mailbox commands.
1718 */
1719#define MCU_SLEEP 0x30
1720#define MCU_WAKEUP 0x31
1721#define MCU_RADIO_OFF 0x35
1722#define MCU_CURRENT 0x36
1723#define MCU_LED 0x50
1724#define MCU_LED_STRENGTH 0x51
1725#define MCU_LED_1 0x52
1726#define MCU_LED_2 0x53
1727#define MCU_LED_3 0x54
1728#define MCU_RADAR 0x60
1729#define MCU_BOOT_SIGNAL 0x72
1730#define MCU_BBP_SIGNAL 0x80
1731#define MCU_POWER_SAVE 0x83
1732
1733/*
1734 * MCU mailbox tokens
1735 */
1736#define TOKEN_WAKUP 3
1737
1738/*
1739 * DMA descriptor defines.
1740 */
1741#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1742#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1743#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1744#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1745#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1746
1747/*
1748 * TX descriptor format for TX, PRIO and Beacon Ring.
1749 */
1750
1751/*
1752 * Word0
1753 */
1754#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
1755
1756/*
1757 * Word1
1758 */
1759#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
1760#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
1761#define TXD_W1_BURST FIELD32(0x00008000)
1762#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
1763#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
1764#define TXD_W1_DMA_DONE FIELD32(0x80000000)
1765
1766/*
1767 * Word2
1768 */
1769#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
1770
1771/*
1772 * Word3
1773 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1774 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1775 * 0:MGMT, 1:HCCA 2:EDCA
1776 */
1777#define TXD_W3_WIV FIELD32(0x01000000)
1778#define TXD_W3_QSEL FIELD32(0x06000000)
1779#define TXD_W3_TCO FIELD32(0x20000000)
1780#define TXD_W3_UCO FIELD32(0x40000000)
1781#define TXD_W3_ICO FIELD32(0x80000000)
1782
1783/*
1784 * TX Info structure
1785 */
1786
1787/*
1788 * Word0
1789 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1790 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1791 * 0:MGMT, 1:HCCA 2:EDCA
1792 * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
1793 * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
1794 * Force USB DMA transmit frame from current selected endpoint
1795 */
1796#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
1797#define TXINFO_W0_WIV FIELD32(0x01000000)
1798#define TXINFO_W0_QSEL FIELD32(0x06000000)
1799#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
1800#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
1801#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
1802
1803/*
1804 * TX WI structure
1805 */
1806
1807/*
1808 * Word0
1809 * FRAG: 1 To inform TKIP engine this is a fragment.
1810 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1811 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1812 * BW: Channel bandwidth 20MHz or 40 MHz
1813 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1814 */
1815#define TXWI_W0_FRAG FIELD32(0x00000001)
1816#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1817#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1818#define TXWI_W0_TS FIELD32(0x00000008)
1819#define TXWI_W0_AMPDU FIELD32(0x00000010)
1820#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1821#define TXWI_W0_TX_OP FIELD32(0x00000300)
1822#define TXWI_W0_MCS FIELD32(0x007f0000)
1823#define TXWI_W0_BW FIELD32(0x00800000)
1824#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1825#define TXWI_W0_STBC FIELD32(0x06000000)
1826#define TXWI_W0_IFS FIELD32(0x08000000)
1827#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1828
1829/*
1830 * Word1
1831 */
1832#define TXWI_W1_ACK FIELD32(0x00000001)
1833#define TXWI_W1_NSEQ FIELD32(0x00000002)
1834#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1835#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1836#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1837#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1838
1839/*
1840 * Word2
1841 */
1842#define TXWI_W2_IV FIELD32(0xffffffff)
1843
1844/*
1845 * Word3
1846 */
1847#define TXWI_W3_EIV FIELD32(0xffffffff)
1848
1849/*
1850 * RX descriptor format for RX Ring.
1851 */
1852
1853/*
1854 * Word0
1855 * UNICAST_TO_ME: This RX frame is unicast to me.
1856 * MULTICAST: This is a multicast frame.
1857 * BROADCAST: This is a broadcast frame.
1858 * MY_BSS: this frame belongs to the same BSSID.
1859 * CRC_ERROR: CRC error.
1860 * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
1861 * AMSDU: rx with 802.3 header, not 802.11 header.
1862 */
1863
1864#define RXD_W0_BA FIELD32(0x00000001)
1865#define RXD_W0_DATA FIELD32(0x00000002)
1866#define RXD_W0_NULLDATA FIELD32(0x00000004)
1867#define RXD_W0_FRAG FIELD32(0x00000008)
1868#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
1869#define RXD_W0_MULTICAST FIELD32(0x00000020)
1870#define RXD_W0_BROADCAST FIELD32(0x00000040)
1871#define RXD_W0_MY_BSS FIELD32(0x00000080)
1872#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
1873#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
1874#define RXD_W0_AMSDU FIELD32(0x00000800)
1875#define RXD_W0_HTC FIELD32(0x00001000)
1876#define RXD_W0_RSSI FIELD32(0x00002000)
1877#define RXD_W0_L2PAD FIELD32(0x00004000)
1878#define RXD_W0_AMPDU FIELD32(0x00008000)
1879#define RXD_W0_DECRYPTED FIELD32(0x00010000)
1880#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
1881#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
1882#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
1883#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
1884
1885/*
1886 * RX WI structure
1887 */
1888
1889/*
1890 * Word0
1891 */
1892#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1893#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1894#define RXWI_W0_BSSID FIELD32(0x00001c00)
1895#define RXWI_W0_UDF FIELD32(0x0000e000)
1896#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1897#define RXWI_W0_TID FIELD32(0xf0000000)
1898
1899/*
1900 * Word1
1901 */
1902#define RXWI_W1_FRAG FIELD32(0x0000000f)
1903#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1904#define RXWI_W1_MCS FIELD32(0x007f0000)
1905#define RXWI_W1_BW FIELD32(0x00800000)
1906#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1907#define RXWI_W1_STBC FIELD32(0x06000000)
1908#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1909
1910/*
1911 * Word2
1912 */
1913#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1914#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1915#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1916
1917/*
1918 * Word3
1919 */
1920#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1921#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1922
1923/*
1924 * Macro's for converting txpower from EEPROM to mac80211 value
1925 * and from mac80211 value to register value.
1926 */
1927#define MIN_G_TXPOWER 0
1928#define MIN_A_TXPOWER -7
1929#define MAX_G_TXPOWER 31
1930#define MAX_A_TXPOWER 15
1931#define DEFAULT_TXPOWER 5
1932
1933#define TXPOWER_G_FROM_DEV(__txpower) \
1934 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1935
1936#define TXPOWER_G_TO_DEV(__txpower) \
1937 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1938
1939#define TXPOWER_A_FROM_DEV(__txpower) \
1940 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1941
1942#define TXPOWER_A_TO_DEV(__txpower) \
1943 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1944
1945#endif /* RT2800USB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 84bd6f19acb0..a498dde024e1 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -103,6 +103,15 @@
103#define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate)) 103#define GET_DURATION_RES(__size, __rate)(((__size) * 8 * 10) % (__rate))
104 104
105/* 105/*
106 * Determine the alignment requirement,
107 * to make sure the 802.11 payload is padded to a 4-byte boundrary
108 * we must determine the address of the payload and calculate the
109 * amount of bytes needed to move the data.
110 */
111#define ALIGN_SIZE(__skb, __header) \
112 ( ((unsigned long)((__skb)->data + (__header))) & 3 )
113
114/*
106 * Standard timing and size defines. 115 * Standard timing and size defines.
107 * These values should follow the ieee80211 specifications. 116 * These values should follow the ieee80211 specifications.
108 */ 117 */
@@ -138,6 +147,7 @@ struct rt2x00_chip {
138#define RT2561 0x0302 147#define RT2561 0x0302
139#define RT2661 0x0401 148#define RT2661 0x0401
140#define RT2571 0x1300 149#define RT2571 0x1300
150#define RT2870 0x1600
141 151
142 u16 rf; 152 u16 rf;
143 u32 rev; 153 u32 rev;
@@ -357,6 +367,7 @@ static inline struct rt2x00_intf* vif_to_intf(struct ieee80211_vif *vif)
357 * for @tx_power_a, @tx_power_bg and @channels. 367 * for @tx_power_a, @tx_power_bg and @channels.
358 * @channels: Device/chipset specific channel values (See &struct rf_channel). 368 * @channels: Device/chipset specific channel values (See &struct rf_channel).
359 * @channels_info: Additional information for channels (See &struct channel_info). 369 * @channels_info: Additional information for channels (See &struct channel_info).
370 * @ht: Driver HT Capabilities (See &ieee80211_sta_ht_cap).
360 */ 371 */
361struct hw_mode_spec { 372struct hw_mode_spec {
362 unsigned int supported_bands; 373 unsigned int supported_bands;
@@ -370,6 +381,8 @@ struct hw_mode_spec {
370 unsigned int num_channels; 381 unsigned int num_channels;
371 const struct rf_channel *channels; 382 const struct rf_channel *channels;
372 const struct channel_info *channels_info; 383 const struct channel_info *channels_info;
384
385 struct ieee80211_sta_ht_cap ht;
373}; 386};
374 387
375/* 388/*
@@ -404,6 +417,8 @@ struct rt2x00lib_erp {
404 short pifs; 417 short pifs;
405 short difs; 418 short difs;
406 short eifs; 419 short eifs;
420
421 u16 beacon_int;
407}; 422};
408 423
409/* 424/*
@@ -590,6 +605,7 @@ enum rt2x00_flags {
590 DRIVER_REQUIRE_SCHEDULED, 605 DRIVER_REQUIRE_SCHEDULED,
591 DRIVER_REQUIRE_DMA, 606 DRIVER_REQUIRE_DMA,
592 DRIVER_REQUIRE_COPY_IV, 607 DRIVER_REQUIRE_COPY_IV,
608 DRIVER_REQUIRE_L2PAD,
593 609
594 /* 610 /*
595 * Driver features 611 * Driver features
@@ -606,6 +622,7 @@ enum rt2x00_flags {
606 CONFIG_EXTERNAL_LNA_BG, 622 CONFIG_EXTERNAL_LNA_BG,
607 CONFIG_DOUBLE_ANTENNA, 623 CONFIG_DOUBLE_ANTENNA,
608 CONFIG_DISABLE_LINK_TUNING, 624 CONFIG_DISABLE_LINK_TUNING,
625 CONFIG_CHANNEL_HT40,
609}; 626};
610 627
611/* 628/*
@@ -672,6 +689,12 @@ struct rt2x00_dev {
672 unsigned long flags; 689 unsigned long flags;
673 690
674 /* 691 /*
692 * Device information, Bus IRQ and name (PCI, SoC)
693 */
694 int irq;
695 const char *name;
696
697 /*
675 * Chipset identification. 698 * Chipset identification.
676 */ 699 */
677 struct rt2x00_chip chip; 700 struct rt2x00_chip chip;
@@ -772,6 +795,18 @@ struct rt2x00_dev {
772 u8 freq_offset; 795 u8 freq_offset;
773 796
774 /* 797 /*
798 * Calibration information (for rt2800usb & rt2800pci).
799 * [0] -> BW20
800 * [1] -> BW40
801 */
802 u8 calibration[2];
803
804 /*
805 * Beacon interval.
806 */
807 u16 beacon_int;
808
809 /*
775 * Low level statistics which will have 810 * Low level statistics which will have
776 * to be kept up to date while device is running. 811 * to be kept up to date while device is running.
777 */ 812 */
@@ -860,6 +895,18 @@ static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
860 rt2x00dev->chip.rev = rev; 895 rt2x00dev->chip.rev = rev;
861} 896}
862 897
898static inline void rt2x00_set_chip_rt(struct rt2x00_dev *rt2x00dev,
899 const u16 rt)
900{
901 rt2x00dev->chip.rt = rt;
902}
903
904static inline void rt2x00_set_chip_rf(struct rt2x00_dev *rt2x00dev,
905 const u16 rf, const u32 rev)
906{
907 rt2x00_set_chip(rt2x00dev, rt2x00dev->chip.rt, rf, rev);
908}
909
863static inline char rt2x00_rt(const struct rt2x00_chip *chipset, const u16 chip) 910static inline char rt2x00_rt(const struct rt2x00_chip *chipset, const u16 chip)
864{ 911{
865 return (chipset->rt == chip); 912 return (chipset->rt == chip);
@@ -875,11 +922,10 @@ static inline u32 rt2x00_rev(const struct rt2x00_chip *chipset)
875 return chipset->rev; 922 return chipset->rev;
876} 923}
877 924
878static inline u16 rt2x00_check_rev(const struct rt2x00_chip *chipset, 925static inline bool rt2x00_check_rev(const struct rt2x00_chip *chipset,
879 const u32 rev) 926 const u32 mask, const u32 rev)
880{ 927{
881 return (((chipset->rev & 0xffff0) == rev) && 928 return ((chipset->rev & mask) == rev);
882 !!(chipset->rev & 0x0000f));
883} 929}
884 930
885/** 931/**
@@ -925,9 +971,6 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
925void rt2x00mac_remove_interface(struct ieee80211_hw *hw, 971void rt2x00mac_remove_interface(struct ieee80211_hw *hw,
926 struct ieee80211_if_init_conf *conf); 972 struct ieee80211_if_init_conf *conf);
927int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed); 973int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed);
928int rt2x00mac_config_interface(struct ieee80211_hw *hw,
929 struct ieee80211_vif *vif,
930 struct ieee80211_if_conf *conf);
931void rt2x00mac_configure_filter(struct ieee80211_hw *hw, 974void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
932 unsigned int changed_flags, 975 unsigned int changed_flags,
933 unsigned int *total_flags, 976 unsigned int *total_flags,
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c
index 9c2f5517af2a..3e019a12df2e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00config.c
+++ b/drivers/net/wireless/rt2x00/rt2x00config.c
@@ -106,6 +106,10 @@ void rt2x00lib_config_erp(struct rt2x00_dev *rt2x00dev,
106 } 106 }
107 107
108 erp.basic_rates = bss_conf->basic_rates; 108 erp.basic_rates = bss_conf->basic_rates;
109 erp.beacon_int = bss_conf->beacon_int;
110
111 /* Update global beacon interval time, this is needed for PS support */
112 rt2x00dev->beacon_int = bss_conf->beacon_int;
109 113
110 rt2x00dev->ops->lib->config_erp(rt2x00dev, &erp); 114 rt2x00dev->ops->lib->config_erp(rt2x00dev, &erp);
111} 115}
@@ -173,6 +177,11 @@ void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
173 libconf.conf = conf; 177 libconf.conf = conf;
174 178
175 if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL) { 179 if (ieee80211_flags & IEEE80211_CONF_CHANGE_CHANNEL) {
180 if (conf_is_ht40(conf))
181 __set_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags);
182 else
183 __clear_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags);
184
176 memcpy(&libconf.rf, 185 memcpy(&libconf.rf,
177 &rt2x00dev->spec.channels[conf->channel->hw_value], 186 &rt2x00dev->spec.channels[conf->channel->hw_value],
178 sizeof(libconf.rf)); 187 sizeof(libconf.rf));
diff --git a/drivers/net/wireless/rt2x00/rt2x00crypto.c b/drivers/net/wireless/rt2x00/rt2x00crypto.c
index 0b41845d9543..bc4e81e21841 100644
--- a/drivers/net/wireless/rt2x00/rt2x00crypto.c
+++ b/drivers/net/wireless/rt2x00/rt2x00crypto.c
@@ -33,7 +33,7 @@ enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf *key)
33{ 33{
34 switch (key->alg) { 34 switch (key->alg) {
35 case ALG_WEP: 35 case ALG_WEP:
36 if (key->keylen == LEN_WEP40) 36 if (key->keylen == WLAN_KEY_LEN_WEP40)
37 return CIPHER_WEP64; 37 return CIPHER_WEP64;
38 else 38 else
39 return CIPHER_WEP128; 39 return CIPHER_WEP128;
@@ -65,7 +65,8 @@ void rt2x00crypto_create_tx_descriptor(struct queue_entry *entry,
65 __set_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags); 65 __set_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags);
66 66
67 txdesc->key_idx = hw_key->hw_key_idx; 67 txdesc->key_idx = hw_key->hw_key_idx;
68 txdesc->iv_offset = ieee80211_get_hdrlen_from_skb(entry->skb); 68 txdesc->iv_offset = txdesc->header_length;
69 txdesc->iv_len = hw_key->iv_len;
69 70
70 if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_IV)) 71 if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_IV))
71 __set_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags); 72 __set_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags);
@@ -103,47 +104,44 @@ unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev,
103 return overhead; 104 return overhead;
104} 105}
105 106
106void rt2x00crypto_tx_copy_iv(struct sk_buff *skb, unsigned int iv_len) 107void rt2x00crypto_tx_copy_iv(struct sk_buff *skb, struct txentry_desc *txdesc)
107{ 108{
108 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 109 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
109 unsigned int header_length = ieee80211_get_hdrlen_from_skb(skb);
110 110
111 if (unlikely(!iv_len)) 111 if (unlikely(!txdesc->iv_len))
112 return; 112 return;
113 113
114 /* Copy IV/EIV data */ 114 /* Copy IV/EIV data */
115 memcpy(skbdesc->iv, skb->data + header_length, iv_len); 115 memcpy(skbdesc->iv, skb->data + txdesc->iv_offset, txdesc->iv_len);
116} 116}
117 117
118void rt2x00crypto_tx_remove_iv(struct sk_buff *skb, unsigned int iv_len) 118void rt2x00crypto_tx_remove_iv(struct sk_buff *skb, struct txentry_desc *txdesc)
119{ 119{
120 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 120 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
121 unsigned int header_length = ieee80211_get_hdrlen_from_skb(skb);
122 121
123 if (unlikely(!iv_len)) 122 if (unlikely(!txdesc->iv_len))
124 return; 123 return;
125 124
126 /* Copy IV/EIV data */ 125 /* Copy IV/EIV data */
127 memcpy(skbdesc->iv, skb->data + header_length, iv_len); 126 memcpy(skbdesc->iv, skb->data + txdesc->iv_offset, txdesc->iv_len);
128 127
129 /* Move ieee80211 header */ 128 /* Move ieee80211 header */
130 memmove(skb->data + iv_len, skb->data, header_length); 129 memmove(skb->data + txdesc->iv_len, skb->data, txdesc->iv_offset);
131 130
132 /* Pull buffer to correct size */ 131 /* Pull buffer to correct size */
133 skb_pull(skb, iv_len); 132 skb_pull(skb, txdesc->iv_len);
134 133
135 /* IV/EIV data has officially be stripped */ 134 /* IV/EIV data has officially be stripped */
136 skbdesc->flags |= FRAME_DESC_IV_STRIPPED; 135 skbdesc->flags |= SKBDESC_IV_STRIPPED;
137} 136}
138 137
139void rt2x00crypto_tx_insert_iv(struct sk_buff *skb) 138void rt2x00crypto_tx_insert_iv(struct sk_buff *skb, unsigned int header_length)
140{ 139{
141 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 140 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
142 unsigned int header_length = ieee80211_get_hdrlen_from_skb(skb);
143 const unsigned int iv_len = 141 const unsigned int iv_len =
144 ((!!(skbdesc->iv[0])) * 4) + ((!!(skbdesc->iv[1])) * 4); 142 ((!!(skbdesc->iv[0])) * 4) + ((!!(skbdesc->iv[1])) * 4);
145 143
146 if (!(skbdesc->flags & FRAME_DESC_IV_STRIPPED)) 144 if (!(skbdesc->flags & SKBDESC_IV_STRIPPED))
147 return; 145 return;
148 146
149 skb_push(skb, iv_len); 147 skb_push(skb, iv_len);
@@ -155,14 +153,15 @@ void rt2x00crypto_tx_insert_iv(struct sk_buff *skb)
155 memcpy(skb->data + header_length, skbdesc->iv, iv_len); 153 memcpy(skb->data + header_length, skbdesc->iv, iv_len);
156 154
157 /* IV/EIV data has returned into the frame */ 155 /* IV/EIV data has returned into the frame */
158 skbdesc->flags &= ~FRAME_DESC_IV_STRIPPED; 156 skbdesc->flags &= ~SKBDESC_IV_STRIPPED;
159} 157}
160 158
161void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, unsigned int align, 159void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, bool l2pad,
162 unsigned int header_length, 160 unsigned int header_length,
163 struct rxdone_entry_desc *rxdesc) 161 struct rxdone_entry_desc *rxdesc)
164{ 162{
165 unsigned int payload_len = rxdesc->size - header_length; 163 unsigned int payload_len = rxdesc->size - header_length;
164 unsigned int align = ALIGN_SIZE(skb, header_length);
166 unsigned int iv_len; 165 unsigned int iv_len;
167 unsigned int icv_len; 166 unsigned int icv_len;
168 unsigned int transfer = 0; 167 unsigned int transfer = 0;
@@ -192,32 +191,48 @@ void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, unsigned int align,
192 } 191 }
193 192
194 /* 193 /*
195 * Make room for new data, note that we increase both 194 * Make room for new data. There are 2 possibilities
196 * headsize and tailsize when required. The tailsize is 195 * either the alignment is already present between
197 * only needed when ICV data needs to be inserted and 196 * the 802.11 header and payload. In that case we
198 * the padding is smaller than the ICV data. 197 * we have to move the header less then the iv_len
199 * When alignment requirements is greater than the 198 * since we can use the already available l2pad bytes
200 * ICV data we must trim the skb to the correct size 199 * for the iv data.
201 * because we need to remove the extra bytes. 200 * When the alignment must be added manually we must
201 * move the header more then iv_len since we must
202 * make room for the payload move as well.
202 */ 203 */
203 skb_push(skb, iv_len + align); 204 if (l2pad) {
204 if (align < icv_len) 205 skb_push(skb, iv_len - align);
205 skb_put(skb, icv_len - align); 206 skb_put(skb, icv_len);
206 else if (align > icv_len)
207 skb_trim(skb, rxdesc->size + iv_len + icv_len);
208 207
209 /* Move ieee80211 header */ 208 /* Move ieee80211 header */
210 memmove(skb->data + transfer, 209 memmove(skb->data + transfer,
211 skb->data + transfer + iv_len + align, 210 skb->data + transfer + (iv_len - align),
212 header_length); 211 header_length);
213 transfer += header_length; 212 transfer += header_length;
213 } else {
214 skb_push(skb, iv_len + align);
215 if (align < icv_len)
216 skb_put(skb, icv_len - align);
217 else if (align > icv_len)
218 skb_trim(skb, rxdesc->size + iv_len + icv_len);
219
220 /* Move ieee80211 header */
221 memmove(skb->data + transfer,
222 skb->data + transfer + iv_len + align,
223 header_length);
224 transfer += header_length;
225 }
214 226
215 /* Copy IV/EIV data */ 227 /* Copy IV/EIV data */
216 memcpy(skb->data + transfer, rxdesc->iv, iv_len); 228 memcpy(skb->data + transfer, rxdesc->iv, iv_len);
217 transfer += iv_len; 229 transfer += iv_len;
218 230
219 /* Move payload */ 231 /*
220 if (align) { 232 * Move payload for alignment purposes. Note that
233 * this is only needed when no l2 padding is present.
234 */
235 if (!l2pad) {
221 memmove(skb->data + transfer, 236 memmove(skb->data + transfer,
222 skb->data + transfer + align, 237 skb->data + transfer + align,
223 payload_len); 238 payload_len);
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index 5752aaae906b..57813e72c808 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -227,6 +227,7 @@ void rt2x00lib_txdone(struct queue_entry *entry,
227 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 227 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
228 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 228 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
229 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb); 229 enum data_queue_qid qid = skb_get_queue_mapping(entry->skb);
230 unsigned int header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
230 u8 rate_idx, rate_flags; 231 u8 rate_idx, rate_flags;
231 232
232 /* 233 /*
@@ -235,13 +236,19 @@ void rt2x00lib_txdone(struct queue_entry *entry,
235 rt2x00queue_unmap_skb(rt2x00dev, entry->skb); 236 rt2x00queue_unmap_skb(rt2x00dev, entry->skb);
236 237
237 /* 238 /*
239 * Remove L2 padding which was added during
240 */
241 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags))
242 rt2x00queue_payload_align(entry->skb, true, header_length);
243
244 /*
238 * If the IV/EIV data was stripped from the frame before it was 245 * If the IV/EIV data was stripped from the frame before it was
239 * passed to the hardware, we should now reinsert it again because 246 * passed to the hardware, we should now reinsert it again because
240 * mac80211 will expect the the same data to be present it the 247 * mac80211 will expect the the same data to be present it the
241 * frame as it was passed to us. 248 * frame as it was passed to us.
242 */ 249 */
243 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) 250 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags))
244 rt2x00crypto_tx_insert_iv(entry->skb); 251 rt2x00crypto_tx_insert_iv(entry->skb, header_length);
245 252
246 /* 253 /*
247 * Send frame to debugfs immediately, after this call is completed 254 * Send frame to debugfs immediately, after this call is completed
@@ -253,7 +260,8 @@ void rt2x00lib_txdone(struct queue_entry *entry,
253 * Update TX statistics. 260 * Update TX statistics.
254 */ 261 */
255 rt2x00dev->link.qual.tx_success += 262 rt2x00dev->link.qual.tx_success +=
256 test_bit(TXDONE_SUCCESS, &txdesc->flags); 263 test_bit(TXDONE_SUCCESS, &txdesc->flags) ||
264 test_bit(TXDONE_UNKNOWN, &txdesc->flags);
257 rt2x00dev->link.qual.tx_failed += 265 rt2x00dev->link.qual.tx_failed +=
258 test_bit(TXDONE_FAILURE, &txdesc->flags); 266 test_bit(TXDONE_FAILURE, &txdesc->flags);
259 267
@@ -271,14 +279,16 @@ void rt2x00lib_txdone(struct queue_entry *entry,
271 tx_info->status.rates[1].idx = -1; /* terminate */ 279 tx_info->status.rates[1].idx = -1; /* terminate */
272 280
273 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) { 281 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
274 if (test_bit(TXDONE_SUCCESS, &txdesc->flags)) 282 if (test_bit(TXDONE_SUCCESS, &txdesc->flags) ||
283 test_bit(TXDONE_UNKNOWN, &txdesc->flags))
275 tx_info->flags |= IEEE80211_TX_STAT_ACK; 284 tx_info->flags |= IEEE80211_TX_STAT_ACK;
276 else if (test_bit(TXDONE_FAILURE, &txdesc->flags)) 285 else if (test_bit(TXDONE_FAILURE, &txdesc->flags))
277 rt2x00dev->low_level_stats.dot11ACKFailureCount++; 286 rt2x00dev->low_level_stats.dot11ACKFailureCount++;
278 } 287 }
279 288
280 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 289 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
281 if (test_bit(TXDONE_SUCCESS, &txdesc->flags)) 290 if (test_bit(TXDONE_SUCCESS, &txdesc->flags) ||
291 test_bit(TXDONE_UNKNOWN, &txdesc->flags))
282 rt2x00dev->low_level_stats.dot11RTSSuccessCount++; 292 rt2x00dev->low_level_stats.dot11RTSSuccessCount++;
283 else if (test_bit(TXDONE_FAILURE, &txdesc->flags)) 293 else if (test_bit(TXDONE_FAILURE, &txdesc->flags))
284 rt2x00dev->low_level_stats.dot11RTSFailureCount++; 294 rt2x00dev->low_level_stats.dot11RTSFailureCount++;
@@ -316,19 +326,54 @@ void rt2x00lib_txdone(struct queue_entry *entry,
316} 326}
317EXPORT_SYMBOL_GPL(rt2x00lib_txdone); 327EXPORT_SYMBOL_GPL(rt2x00lib_txdone);
318 328
329static int rt2x00lib_rxdone_read_signal(struct rt2x00_dev *rt2x00dev,
330 struct rxdone_entry_desc *rxdesc)
331{
332 struct ieee80211_supported_band *sband;
333 const struct rt2x00_rate *rate;
334 unsigned int i;
335 int signal;
336 int type;
337
338 /*
339 * For non-HT rates the MCS value needs to contain the
340 * actually used rate modulation (CCK or OFDM).
341 */
342 if (rxdesc->dev_flags & RXDONE_SIGNAL_MCS)
343 signal = RATE_MCS(rxdesc->rate_mode, rxdesc->signal);
344 else
345 signal = rxdesc->signal;
346
347 type = (rxdesc->dev_flags & RXDONE_SIGNAL_MASK);
348
349 sband = &rt2x00dev->bands[rt2x00dev->curr_band];
350 for (i = 0; i < sband->n_bitrates; i++) {
351 rate = rt2x00_get_rate(sband->bitrates[i].hw_value);
352
353 if (((type == RXDONE_SIGNAL_PLCP) &&
354 (rate->plcp == signal)) ||
355 ((type == RXDONE_SIGNAL_BITRATE) &&
356 (rate->bitrate == signal)) ||
357 ((type == RXDONE_SIGNAL_MCS) &&
358 (rate->mcs == signal))) {
359 return i;
360 }
361 }
362
363 WARNING(rt2x00dev, "Frame received with unrecognized signal, "
364 "signal=0x%.4x, type=%d.\n", signal, type);
365 return 0;
366}
367
319void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev, 368void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
320 struct queue_entry *entry) 369 struct queue_entry *entry)
321{ 370{
322 struct rxdone_entry_desc rxdesc; 371 struct rxdone_entry_desc rxdesc;
323 struct sk_buff *skb; 372 struct sk_buff *skb;
324 struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status; 373 struct ieee80211_rx_status *rx_status = &rt2x00dev->rx_status;
325 struct ieee80211_supported_band *sband;
326 const struct rt2x00_rate *rate;
327 unsigned int header_length; 374 unsigned int header_length;
328 unsigned int align; 375 bool l2pad;
329 unsigned int i; 376 int rate_idx;
330 int idx = -1;
331
332 /* 377 /*
333 * Allocate a new sk_buffer. If no new buffer available, drop the 378 * Allocate a new sk_buffer. If no new buffer available, drop the
334 * received frame and reuse the existing buffer. 379 * received frame and reuse the existing buffer.
@@ -348,12 +393,15 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
348 memset(&rxdesc, 0, sizeof(rxdesc)); 393 memset(&rxdesc, 0, sizeof(rxdesc));
349 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc); 394 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
350 395
396 /* Trim buffer to correct size */
397 skb_trim(entry->skb, rxdesc.size);
398
351 /* 399 /*
352 * The data behind the ieee80211 header must be 400 * The data behind the ieee80211 header must be
353 * aligned on a 4 byte boundary. 401 * aligned on a 4 byte boundary.
354 */ 402 */
355 header_length = ieee80211_get_hdrlen_from_skb(entry->skb); 403 header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
356 align = ((unsigned long)(entry->skb->data + header_length)) & 3; 404 l2pad = !!(rxdesc.dev_flags & RXDONE_L2PAD);
357 405
358 /* 406 /*
359 * Hardware might have stripped the IV/EIV/ICV data, 407 * Hardware might have stripped the IV/EIV/ICV data,
@@ -362,40 +410,24 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
362 * in which case we should reinsert the data into the frame. 410 * in which case we should reinsert the data into the frame.
363 */ 411 */
364 if ((rxdesc.dev_flags & RXDONE_CRYPTO_IV) && 412 if ((rxdesc.dev_flags & RXDONE_CRYPTO_IV) &&
365 (rxdesc.flags & RX_FLAG_IV_STRIPPED)) { 413 (rxdesc.flags & RX_FLAG_IV_STRIPPED))
366 rt2x00crypto_rx_insert_iv(entry->skb, align, 414 rt2x00crypto_rx_insert_iv(entry->skb, l2pad, header_length,
367 header_length, &rxdesc); 415 &rxdesc);
368 } else if (align) { 416 else
369 skb_push(entry->skb, align); 417 rt2x00queue_payload_align(entry->skb, l2pad, header_length);
370 /* Move entire frame in 1 command */
371 memmove(entry->skb->data, entry->skb->data + align,
372 rxdesc.size);
373 }
374
375 /* Update data pointers, trim buffer to correct size */
376 skb_trim(entry->skb, rxdesc.size);
377 418
378 /* 419 /*
379 * Update RX statistics. 420 * Check if the frame was received using HT. In that case,
421 * the rate is the MCS index and should be passed to mac80211
422 * directly. Otherwise we need to translate the signal to
423 * the correct bitrate index.
380 */ 424 */
381 sband = &rt2x00dev->bands[rt2x00dev->curr_band]; 425 if (rxdesc.rate_mode == RATE_MODE_CCK ||
382 for (i = 0; i < sband->n_bitrates; i++) { 426 rxdesc.rate_mode == RATE_MODE_OFDM) {
383 rate = rt2x00_get_rate(sband->bitrates[i].hw_value); 427 rate_idx = rt2x00lib_rxdone_read_signal(rt2x00dev, &rxdesc);
384 428 } else {
385 if (((rxdesc.dev_flags & RXDONE_SIGNAL_PLCP) && 429 rxdesc.flags |= RX_FLAG_HT;
386 (rate->plcp == rxdesc.signal)) || 430 rate_idx = rxdesc.signal;
387 ((rxdesc.dev_flags & RXDONE_SIGNAL_BITRATE) &&
388 (rate->bitrate == rxdesc.signal))) {
389 idx = i;
390 break;
391 }
392 }
393
394 if (idx < 0) {
395 WARNING(rt2x00dev, "Frame received with unrecognized signal,"
396 "signal=0x%.2x, type=%d.\n", rxdesc.signal,
397 (rxdesc.dev_flags & RXDONE_SIGNAL_MASK));
398 idx = 0;
399 } 431 }
400 432
401 /* 433 /*
@@ -405,7 +437,7 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
405 rt2x00debug_update_crypto(rt2x00dev, &rxdesc); 437 rt2x00debug_update_crypto(rt2x00dev, &rxdesc);
406 438
407 rx_status->mactime = rxdesc.timestamp; 439 rx_status->mactime = rxdesc.timestamp;
408 rx_status->rate_idx = idx; 440 rx_status->rate_idx = rate_idx;
409 rx_status->qual = rt2x00link_calculate_signal(rt2x00dev, rxdesc.rssi); 441 rx_status->qual = rt2x00link_calculate_signal(rt2x00dev, rxdesc.rssi);
410 rx_status->signal = rxdesc.rssi; 442 rx_status->signal = rxdesc.rssi;
411 rx_status->noise = rxdesc.noise; 443 rx_status->noise = rxdesc.noise;
@@ -440,72 +472,84 @@ const struct rt2x00_rate rt2x00_supported_rates[12] = {
440 .bitrate = 10, 472 .bitrate = 10,
441 .ratemask = BIT(0), 473 .ratemask = BIT(0),
442 .plcp = 0x00, 474 .plcp = 0x00,
475 .mcs = RATE_MCS(RATE_MODE_CCK, 0),
443 }, 476 },
444 { 477 {
445 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE, 478 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
446 .bitrate = 20, 479 .bitrate = 20,
447 .ratemask = BIT(1), 480 .ratemask = BIT(1),
448 .plcp = 0x01, 481 .plcp = 0x01,
482 .mcs = RATE_MCS(RATE_MODE_CCK, 1),
449 }, 483 },
450 { 484 {
451 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE, 485 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
452 .bitrate = 55, 486 .bitrate = 55,
453 .ratemask = BIT(2), 487 .ratemask = BIT(2),
454 .plcp = 0x02, 488 .plcp = 0x02,
489 .mcs = RATE_MCS(RATE_MODE_CCK, 2),
455 }, 490 },
456 { 491 {
457 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE, 492 .flags = DEV_RATE_CCK | DEV_RATE_SHORT_PREAMBLE,
458 .bitrate = 110, 493 .bitrate = 110,
459 .ratemask = BIT(3), 494 .ratemask = BIT(3),
460 .plcp = 0x03, 495 .plcp = 0x03,
496 .mcs = RATE_MCS(RATE_MODE_CCK, 3),
461 }, 497 },
462 { 498 {
463 .flags = DEV_RATE_OFDM, 499 .flags = DEV_RATE_OFDM,
464 .bitrate = 60, 500 .bitrate = 60,
465 .ratemask = BIT(4), 501 .ratemask = BIT(4),
466 .plcp = 0x0b, 502 .plcp = 0x0b,
503 .mcs = RATE_MCS(RATE_MODE_OFDM, 0),
467 }, 504 },
468 { 505 {
469 .flags = DEV_RATE_OFDM, 506 .flags = DEV_RATE_OFDM,
470 .bitrate = 90, 507 .bitrate = 90,
471 .ratemask = BIT(5), 508 .ratemask = BIT(5),
472 .plcp = 0x0f, 509 .plcp = 0x0f,
510 .mcs = RATE_MCS(RATE_MODE_OFDM, 1),
473 }, 511 },
474 { 512 {
475 .flags = DEV_RATE_OFDM, 513 .flags = DEV_RATE_OFDM,
476 .bitrate = 120, 514 .bitrate = 120,
477 .ratemask = BIT(6), 515 .ratemask = BIT(6),
478 .plcp = 0x0a, 516 .plcp = 0x0a,
517 .mcs = RATE_MCS(RATE_MODE_OFDM, 2),
479 }, 518 },
480 { 519 {
481 .flags = DEV_RATE_OFDM, 520 .flags = DEV_RATE_OFDM,
482 .bitrate = 180, 521 .bitrate = 180,
483 .ratemask = BIT(7), 522 .ratemask = BIT(7),
484 .plcp = 0x0e, 523 .plcp = 0x0e,
524 .mcs = RATE_MCS(RATE_MODE_OFDM, 3),
485 }, 525 },
486 { 526 {
487 .flags = DEV_RATE_OFDM, 527 .flags = DEV_RATE_OFDM,
488 .bitrate = 240, 528 .bitrate = 240,
489 .ratemask = BIT(8), 529 .ratemask = BIT(8),
490 .plcp = 0x09, 530 .plcp = 0x09,
531 .mcs = RATE_MCS(RATE_MODE_OFDM, 4),
491 }, 532 },
492 { 533 {
493 .flags = DEV_RATE_OFDM, 534 .flags = DEV_RATE_OFDM,
494 .bitrate = 360, 535 .bitrate = 360,
495 .ratemask = BIT(9), 536 .ratemask = BIT(9),
496 .plcp = 0x0d, 537 .plcp = 0x0d,
538 .mcs = RATE_MCS(RATE_MODE_OFDM, 5),
497 }, 539 },
498 { 540 {
499 .flags = DEV_RATE_OFDM, 541 .flags = DEV_RATE_OFDM,
500 .bitrate = 480, 542 .bitrate = 480,
501 .ratemask = BIT(10), 543 .ratemask = BIT(10),
502 .plcp = 0x08, 544 .plcp = 0x08,
545 .mcs = RATE_MCS(RATE_MODE_OFDM, 6),
503 }, 546 },
504 { 547 {
505 .flags = DEV_RATE_OFDM, 548 .flags = DEV_RATE_OFDM,
506 .bitrate = 540, 549 .bitrate = 540,
507 .ratemask = BIT(11), 550 .ratemask = BIT(11),
508 .plcp = 0x0c, 551 .plcp = 0x0c,
552 .mcs = RATE_MCS(RATE_MODE_OFDM, 7),
509 }, 553 },
510}; 554};
511 555
@@ -581,6 +625,8 @@ static int rt2x00lib_probe_hw_modes(struct rt2x00_dev *rt2x00dev,
581 rt2x00dev->bands[IEEE80211_BAND_2GHZ].bitrates = rates; 625 rt2x00dev->bands[IEEE80211_BAND_2GHZ].bitrates = rates;
582 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 626 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
583 &rt2x00dev->bands[IEEE80211_BAND_2GHZ]; 627 &rt2x00dev->bands[IEEE80211_BAND_2GHZ];
628 memcpy(&rt2x00dev->bands[IEEE80211_BAND_2GHZ].ht_cap,
629 &spec->ht, sizeof(spec->ht));
584 } 630 }
585 631
586 /* 632 /*
@@ -597,6 +643,8 @@ static int rt2x00lib_probe_hw_modes(struct rt2x00_dev *rt2x00dev,
597 rt2x00dev->bands[IEEE80211_BAND_5GHZ].bitrates = &rates[4]; 643 rt2x00dev->bands[IEEE80211_BAND_5GHZ].bitrates = &rates[4];
598 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 644 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
599 &rt2x00dev->bands[IEEE80211_BAND_5GHZ]; 645 &rt2x00dev->bands[IEEE80211_BAND_5GHZ];
646 memcpy(&rt2x00dev->bands[IEEE80211_BAND_5GHZ].ht_cap,
647 &spec->ht, sizeof(spec->ht));
600 } 648 }
601 649
602 return 0; 650 return 0;
diff --git a/drivers/net/wireless/rt2x00/rt2x00ht.c b/drivers/net/wireless/rt2x00/rt2x00ht.c
new file mode 100644
index 000000000000..e3cec839e540
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2x00ht.c
@@ -0,0 +1,69 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2x00lib
23 Abstract: rt2x00 HT specific routines.
24 */
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28
29#include "rt2x00.h"
30#include "rt2x00lib.h"
31
32void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
33 struct txentry_desc *txdesc,
34 const struct rt2x00_rate *hwrate)
35{
36 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
37 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
38
39 if (tx_info->control.sta)
40 txdesc->mpdu_density =
41 tx_info->control.sta->ht_cap.ampdu_density;
42 else
43 txdesc->mpdu_density = 0;
44
45 txdesc->ba_size = 7; /* FIXME: What value is needed? */
46 txdesc->stbc = 0; /* FIXME: What value is needed? */
47
48 txdesc->mcs = rt2x00_get_rate_mcs(hwrate->mcs);
49 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
50 txdesc->mcs |= 0x08;
51
52 /*
53 * Convert flags
54 */
55 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
56 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
57
58 /*
59 * Determine HT Mix/Greenfield rate mode
60 */
61 if (txrate->flags & IEEE80211_TX_RC_MCS)
62 txdesc->rate_mode = RATE_MODE_HT_MIX;
63 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
64 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
65 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
66 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
67 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
68 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
69}
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index d83e3794d340..0bf2715fa93a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -32,8 +32,8 @@
32 * Interval defines 32 * Interval defines
33 * Both the link tuner as the rfkill will be called once per second. 33 * Both the link tuner as the rfkill will be called once per second.
34 */ 34 */
35#define LINK_TUNE_INTERVAL ( round_jiffies_relative(HZ) ) 35#define LINK_TUNE_INTERVAL round_jiffies_relative(HZ)
36#define RFKILL_POLL_INTERVAL ( 1000 ) 36#define RFKILL_POLL_INTERVAL 1000
37 37
38/* 38/*
39 * rt2x00_rate: Per rate device information 39 * rt2x00_rate: Per rate device information
@@ -48,6 +48,7 @@ struct rt2x00_rate {
48 unsigned short ratemask; 48 unsigned short ratemask;
49 49
50 unsigned short plcp; 50 unsigned short plcp;
51 unsigned short mcs;
51}; 52};
52 53
53extern const struct rt2x00_rate rt2x00_supported_rates[12]; 54extern const struct rt2x00_rate rt2x00_supported_rates[12];
@@ -57,6 +58,14 @@ static inline const struct rt2x00_rate *rt2x00_get_rate(const u16 hw_value)
57 return &rt2x00_supported_rates[hw_value & 0xff]; 58 return &rt2x00_supported_rates[hw_value & 0xff];
58} 59}
59 60
61#define RATE_MCS(__mode, __mcs) \
62 ( (((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff) )
63
64static inline int rt2x00_get_rate_mcs(const u16 mcs_value)
65{
66 return (mcs_value & 0x00ff);
67}
68
60/* 69/*
61 * Radio control handlers. 70 * Radio control handlers.
62 */ 71 */
@@ -113,6 +122,23 @@ void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
113void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb); 122void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb);
114 123
115/** 124/**
125 * rt2x00queue_payload_align - Align 802.11 payload to 4-byte boundary
126 * @skb: The skb to align
127 * @l2pad: Should L2 padding be used
128 * @header_length: Length of 802.11 header
129 *
130 * This function prepares the @skb to be send to the device or mac80211.
131 * If @l2pad is set to true padding will occur between the 802.11 header
132 * and payload. Otherwise the padding will be done in front of the 802.11
133 * header.
134 * When @l2pad is set the function will check for the &SKBDESC_L2_PADDED
135 * flag in &skb_frame_desc. If that flag is set, the padding is removed
136 * and the flag cleared. Otherwise the padding is added and the flag is set.
137 */
138void rt2x00queue_payload_align(struct sk_buff *skb,
139 bool l2pad, unsigned int header_length);
140
141/**
116 * rt2x00queue_write_tx_frame - Write TX frame to hardware 142 * rt2x00queue_write_tx_frame - Write TX frame to hardware
117 * @queue: Queue over which the frame should be send 143 * @queue: Queue over which the frame should be send
118 * @skb: The skb to send 144 * @skb: The skb to send
@@ -295,10 +321,12 @@ void rt2x00crypto_create_tx_descriptor(struct queue_entry *entry,
295 struct txentry_desc *txdesc); 321 struct txentry_desc *txdesc);
296unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev, 322unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev,
297 struct sk_buff *skb); 323 struct sk_buff *skb);
298void rt2x00crypto_tx_copy_iv(struct sk_buff *skb, unsigned int iv_len); 324void rt2x00crypto_tx_copy_iv(struct sk_buff *skb,
299void rt2x00crypto_tx_remove_iv(struct sk_buff *skb, unsigned int iv_len); 325 struct txentry_desc *txdesc);
300void rt2x00crypto_tx_insert_iv(struct sk_buff *skb); 326void rt2x00crypto_tx_remove_iv(struct sk_buff *skb,
301void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, unsigned int align, 327 struct txentry_desc *txdesc);
328void rt2x00crypto_tx_insert_iv(struct sk_buff *skb, unsigned int header_length);
329void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, bool l2pad,
302 unsigned int header_length, 330 unsigned int header_length,
303 struct rxdone_entry_desc *rxdesc); 331 struct rxdone_entry_desc *rxdesc);
304#else 332#else
@@ -319,21 +347,21 @@ static inline unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev
319} 347}
320 348
321static inline void rt2x00crypto_tx_copy_iv(struct sk_buff *skb, 349static inline void rt2x00crypto_tx_copy_iv(struct sk_buff *skb,
322 unsigned int iv_len) 350 struct txentry_desc *txdesc)
323{ 351{
324} 352}
325 353
326static inline void rt2x00crypto_tx_remove_iv(struct sk_buff *skb, 354static inline void rt2x00crypto_tx_remove_iv(struct sk_buff *skb,
327 unsigned int iv_len) 355 struct txentry_desc *txdesc)
328{ 356{
329} 357}
330 358
331static inline void rt2x00crypto_tx_insert_iv(struct sk_buff *skb) 359static inline void rt2x00crypto_tx_insert_iv(struct sk_buff *skb,
360 unsigned int header_length)
332{ 361{
333} 362}
334 363
335static inline void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, 364static inline void rt2x00crypto_rx_insert_iv(struct sk_buff *skb, bool l2pad,
336 unsigned int align,
337 unsigned int header_length, 365 unsigned int header_length,
338 struct rxdone_entry_desc *rxdesc) 366 struct rxdone_entry_desc *rxdesc)
339{ 367{
@@ -341,6 +369,21 @@ static inline void rt2x00crypto_rx_insert_iv(struct sk_buff *skb,
341#endif /* CONFIG_RT2X00_LIB_CRYPTO */ 369#endif /* CONFIG_RT2X00_LIB_CRYPTO */
342 370
343/* 371/*
372 * HT handlers.
373 */
374#ifdef CONFIG_RT2X00_LIB_HT
375void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
376 struct txentry_desc *txdesc,
377 const struct rt2x00_rate *hwrate);
378#else
379static inline void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
380 struct txentry_desc *txdesc,
381 const struct rt2x00_rate *hwrate)
382{
383}
384#endif /* CONFIG_RT2X00_LIB_HT */
385
386/*
344 * RFkill handlers. 387 * RFkill handlers.
345 */ 388 */
346#ifdef CONFIG_RT2X00_LIB_RFKILL 389#ifdef CONFIG_RT2X00_LIB_RFKILL
diff --git a/drivers/net/wireless/rt2x00/rt2x00link.c b/drivers/net/wireless/rt2x00/rt2x00link.c
index 7eb5cd7e5f32..eb9b981b9139 100644
--- a/drivers/net/wireless/rt2x00/rt2x00link.c
+++ b/drivers/net/wireless/rt2x00/rt2x00link.c
@@ -387,7 +387,7 @@ void rt2x00link_reset_tuner(struct rt2x00_dev *rt2x00dev, bool antenna)
387 rt2x00link_antenna_reset(rt2x00dev); 387 rt2x00link_antenna_reset(rt2x00dev);
388} 388}
389 389
390void rt2x00link_reset_qual(struct rt2x00_dev *rt2x00dev) 390static void rt2x00link_reset_qual(struct rt2x00_dev *rt2x00dev)
391{ 391{
392 struct link_qual *qual = &rt2x00dev->link.qual; 392 struct link_qual *qual = &rt2x00dev->link.qual;
393 393
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index c41a0b9e473d..c4c06b4e1f08 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -390,56 +390,6 @@ int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed)
390} 390}
391EXPORT_SYMBOL_GPL(rt2x00mac_config); 391EXPORT_SYMBOL_GPL(rt2x00mac_config);
392 392
393int rt2x00mac_config_interface(struct ieee80211_hw *hw,
394 struct ieee80211_vif *vif,
395 struct ieee80211_if_conf *conf)
396{
397 struct rt2x00_dev *rt2x00dev = hw->priv;
398 struct rt2x00_intf *intf = vif_to_intf(vif);
399 int update_bssid = 0;
400 int status = 0;
401
402 /*
403 * Mac80211 might be calling this function while we are trying
404 * to remove the device or perhaps suspending it.
405 */
406 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
407 return 0;
408
409 spin_lock(&intf->lock);
410
411 /*
412 * conf->bssid can be NULL if coming from the internal
413 * beacon update routine.
414 */
415 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
416 update_bssid = 1;
417 memcpy(&intf->bssid, conf->bssid, ETH_ALEN);
418 }
419
420 spin_unlock(&intf->lock);
421
422 /*
423 * Call rt2x00_config_intf() outside of the spinlock context since
424 * the call will sleep for USB drivers. By using the ieee80211_if_conf
425 * values as arguments we make keep access to rt2x00_intf thread safe
426 * even without the lock.
427 */
428 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, NULL,
429 update_bssid ? conf->bssid : NULL);
430
431 /*
432 * Update the beacon.
433 */
434 if (conf->changed & (IEEE80211_IFCC_BEACON |
435 IEEE80211_IFCC_BEACON_ENABLED))
436 status = rt2x00queue_update_beacon(rt2x00dev, vif,
437 conf->enable_beacon);
438
439 return status;
440}
441EXPORT_SYMBOL_GPL(rt2x00mac_config_interface);
442
443void rt2x00mac_configure_filter(struct ieee80211_hw *hw, 393void rt2x00mac_configure_filter(struct ieee80211_hw *hw,
444 unsigned int changed_flags, 394 unsigned int changed_flags,
445 unsigned int *total_flags, 395 unsigned int *total_flags,
@@ -623,6 +573,44 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
623 struct rt2x00_dev *rt2x00dev = hw->priv; 573 struct rt2x00_dev *rt2x00dev = hw->priv;
624 struct rt2x00_intf *intf = vif_to_intf(vif); 574 struct rt2x00_intf *intf = vif_to_intf(vif);
625 unsigned int delayed = 0; 575 unsigned int delayed = 0;
576 int update_bssid = 0;
577
578 /*
579 * Mac80211 might be calling this function while we are trying
580 * to remove the device or perhaps suspending it.
581 */
582 if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
583 return;
584
585 spin_lock(&intf->lock);
586
587 /*
588 * conf->bssid can be NULL if coming from the internal
589 * beacon update routine.
590 */
591 if (changes & BSS_CHANGED_BSSID) {
592 update_bssid = 1;
593 memcpy(&intf->bssid, bss_conf->bssid, ETH_ALEN);
594 }
595
596 spin_unlock(&intf->lock);
597
598 /*
599 * Call rt2x00_config_intf() outside of the spinlock context since
600 * the call will sleep for USB drivers. By using the ieee80211_if_conf
601 * values as arguments we make keep access to rt2x00_intf thread safe
602 * even without the lock.
603 */
604 if (changes & BSS_CHANGED_BSSID)
605 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, NULL,
606 update_bssid ? bss_conf->bssid : NULL);
607
608 /*
609 * Update the beacon.
610 */
611 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED))
612 rt2x00queue_update_beacon(rt2x00dev, vif,
613 bss_conf->enable_beacon);
626 614
627 /* 615 /*
628 * When the association status has changed we must reset the link 616 * When the association status has changed we must reset the link
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 9730b4f8fd26..cdd5154bd4c0 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -170,7 +170,6 @@ static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
170 170
171int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev) 171int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
172{ 172{
173 struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
174 struct data_queue *queue; 173 struct data_queue *queue;
175 int status; 174 int status;
176 175
@@ -186,11 +185,11 @@ int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
186 /* 185 /*
187 * Register interrupt handler. 186 * Register interrupt handler.
188 */ 187 */
189 status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler, 188 status = request_irq(rt2x00dev->irq, rt2x00dev->ops->lib->irq_handler,
190 IRQF_SHARED, pci_name(pci_dev), rt2x00dev); 189 IRQF_SHARED, rt2x00dev->name, rt2x00dev);
191 if (status) { 190 if (status) {
192 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n", 191 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
193 pci_dev->irq, status); 192 rt2x00dev->irq, status);
194 goto exit; 193 goto exit;
195 } 194 }
196 195
@@ -270,6 +269,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
270 struct ieee80211_hw *hw; 269 struct ieee80211_hw *hw;
271 struct rt2x00_dev *rt2x00dev; 270 struct rt2x00_dev *rt2x00dev;
272 int retval; 271 int retval;
272 u16 chip;
273 273
274 retval = pci_request_regions(pci_dev, pci_name(pci_dev)); 274 retval = pci_request_regions(pci_dev, pci_name(pci_dev));
275 if (retval) { 275 if (retval) {
@@ -307,6 +307,14 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
307 rt2x00dev->dev = &pci_dev->dev; 307 rt2x00dev->dev = &pci_dev->dev;
308 rt2x00dev->ops = ops; 308 rt2x00dev->ops = ops;
309 rt2x00dev->hw = hw; 309 rt2x00dev->hw = hw;
310 rt2x00dev->irq = pci_dev->irq;
311 rt2x00dev->name = pci_name(pci_dev);
312
313 /*
314 * Determine RT chipset by reading PCI header.
315 */
316 pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
317 rt2x00_set_chip_rt(rt2x00dev, chip);
310 318
311 retval = rt2x00pci_alloc_reg(rt2x00dev); 319 retval = rt2x00pci_alloc_reg(rt2x00dev);
312 if (retval) 320 if (retval)
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index a5664bd8493e..44e5b3279ca7 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -148,6 +148,35 @@ void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
148 dev_kfree_skb_any(skb); 148 dev_kfree_skb_any(skb);
149} 149}
150 150
151void rt2x00queue_payload_align(struct sk_buff *skb,
152 bool l2pad, unsigned int header_length)
153{
154 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
155 unsigned int frame_length = skb->len;
156 unsigned int align = ALIGN_SIZE(skb, header_length);
157
158 if (!align)
159 return;
160
161 if (l2pad) {
162 if (skbdesc->flags & SKBDESC_L2_PADDED) {
163 /* Remove L2 padding */
164 memmove(skb->data + align, skb->data, header_length);
165 skb_pull(skb, align);
166 skbdesc->flags &= ~SKBDESC_L2_PADDED;
167 } else {
168 /* Add L2 padding */
169 skb_push(skb, align);
170 memmove(skb->data, skb->data + align, header_length);
171 skbdesc->flags |= SKBDESC_L2_PADDED;
172 }
173 } else {
174 /* Generic payload alignment to 4-byte boundary */
175 skb_push(skb, align);
176 memmove(skb->data, skb->data + align, frame_length);
177 }
178}
179
151static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry, 180static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
152 struct txentry_desc *txdesc) 181 struct txentry_desc *txdesc)
153{ 182{
@@ -259,6 +288,12 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
259 txdesc->aifs = entry->queue->aifs; 288 txdesc->aifs = entry->queue->aifs;
260 289
261 /* 290 /*
291 * Header and alignment information.
292 */
293 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
294 txdesc->l2pad = ALIGN_SIZE(entry->skb, txdesc->header_length);
295
296 /*
262 * Check whether this frame is to be acked. 297 * Check whether this frame is to be acked.
263 */ 298 */
264 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) 299 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
@@ -326,6 +361,7 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
326 * Apply TX descriptor handling by components 361 * Apply TX descriptor handling by components
327 */ 362 */
328 rt2x00crypto_create_tx_descriptor(entry, txdesc); 363 rt2x00crypto_create_tx_descriptor(entry, txdesc);
364 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
329 rt2x00queue_create_tx_descriptor_seq(entry, txdesc); 365 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
330 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate); 366 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
331} 367}
@@ -368,7 +404,6 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
368 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX); 404 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
369 struct txentry_desc txdesc; 405 struct txentry_desc txdesc;
370 struct skb_frame_desc *skbdesc; 406 struct skb_frame_desc *skbdesc;
371 unsigned int iv_len = 0;
372 u8 rate_idx, rate_flags; 407 u8 rate_idx, rate_flags;
373 408
374 if (unlikely(rt2x00queue_full(queue))) 409 if (unlikely(rt2x00queue_full(queue)))
@@ -390,9 +425,6 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
390 entry->skb = skb; 425 entry->skb = skb;
391 rt2x00queue_create_tx_descriptor(entry, &txdesc); 426 rt2x00queue_create_tx_descriptor(entry, &txdesc);
392 427
393 if (IEEE80211_SKB_CB(skb)->control.hw_key != NULL)
394 iv_len = IEEE80211_SKB_CB(skb)->control.hw_key->iv_len;
395
396 /* 428 /*
397 * All information is retrieved from the skb->cb array, 429 * All information is retrieved from the skb->cb array,
398 * now we should claim ownership of the driver part of that 430 * now we should claim ownership of the driver part of that
@@ -415,11 +447,15 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
415 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && 447 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
416 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { 448 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) {
417 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags)) 449 if (test_bit(DRIVER_REQUIRE_COPY_IV, &queue->rt2x00dev->flags))
418 rt2x00crypto_tx_copy_iv(skb, iv_len); 450 rt2x00crypto_tx_copy_iv(skb, &txdesc);
419 else 451 else
420 rt2x00crypto_tx_remove_iv(skb, iv_len); 452 rt2x00crypto_tx_remove_iv(skb, &txdesc);
421 } 453 }
422 454
455 if (test_bit(DRIVER_REQUIRE_L2PAD, &queue->rt2x00dev->flags))
456 rt2x00queue_payload_align(entry->skb, true,
457 txdesc.header_length);
458
423 /* 459 /*
424 * It could be possible that the queue was corrupted and this 460 * It could be possible that the queue was corrupted and this
425 * call failed. Since we always return NETDEV_TX_OK to mac80211, 461 * call failed. Since we always return NETDEV_TX_OK to mac80211,
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index 97e2ab08f080..b5e06347c8a7 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -35,9 +35,12 @@
35 * for USB devices this restriction does not apply, but the value of 35 * for USB devices this restriction does not apply, but the value of
36 * 2432 makes sense since it is big enough to contain the maximum fragment 36 * 2432 makes sense since it is big enough to contain the maximum fragment
37 * size according to the ieee802.11 specs. 37 * size according to the ieee802.11 specs.
38 * The aggregation size depends on support from the driver, but should
39 * be something around 3840 bytes.
38 */ 40 */
39#define DATA_FRAME_SIZE 2432 41#define DATA_FRAME_SIZE 2432
40#define MGMT_FRAME_SIZE 256 42#define MGMT_FRAME_SIZE 256
43#define AGGREGATION_SIZE 3840
41 44
42/** 45/**
43 * DOC: Number of entries per queue 46 * DOC: Number of entries per queue
@@ -87,13 +90,16 @@ enum data_queue_qid {
87 * 90 *
88 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX 91 * @SKBDESC_DMA_MAPPED_RX: &skb_dma field has been mapped for RX
89 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX 92 * @SKBDESC_DMA_MAPPED_TX: &skb_dma field has been mapped for TX
90 * @FRAME_DESC_IV_STRIPPED: Frame contained a IV/EIV provided by 93 * @SKBDESC_IV_STRIPPED: Frame contained a IV/EIV provided by
91 * mac80211 but was stripped for processing by the driver. 94 * mac80211 but was stripped for processing by the driver.
95 * @SKBDESC_L2_PADDED: Payload has been padded for 4-byte alignment,
96 * the padded bytes are located between header and payload.
92 */ 97 */
93enum skb_frame_desc_flags { 98enum skb_frame_desc_flags {
94 SKBDESC_DMA_MAPPED_RX = 1 << 0, 99 SKBDESC_DMA_MAPPED_RX = 1 << 0,
95 SKBDESC_DMA_MAPPED_TX = 1 << 1, 100 SKBDESC_DMA_MAPPED_TX = 1 << 1,
96 FRAME_DESC_IV_STRIPPED = 1 << 2, 101 SKBDESC_IV_STRIPPED = 1 << 2,
102 SKBDESC_L2_PADDED = 1 << 3
97}; 103};
98 104
99/** 105/**
@@ -145,16 +151,20 @@ static inline struct skb_frame_desc* get_skb_frame_desc(struct sk_buff *skb)
145 * 151 *
146 * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value. 152 * @RXDONE_SIGNAL_PLCP: Signal field contains the plcp value.
147 * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value. 153 * @RXDONE_SIGNAL_BITRATE: Signal field contains the bitrate value.
154 * @RXDONE_SIGNAL_MCS: Signal field contains the mcs value.
148 * @RXDONE_MY_BSS: Does this frame originate from device's BSS. 155 * @RXDONE_MY_BSS: Does this frame originate from device's BSS.
149 * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data. 156 * @RXDONE_CRYPTO_IV: Driver provided IV/EIV data.
150 * @RXDONE_CRYPTO_ICV: Driver provided ICV data. 157 * @RXDONE_CRYPTO_ICV: Driver provided ICV data.
158 * @RXDONE_L2PAD: 802.11 payload has been padded to 4-byte boundary.
151 */ 159 */
152enum rxdone_entry_desc_flags { 160enum rxdone_entry_desc_flags {
153 RXDONE_SIGNAL_PLCP = 1 << 0, 161 RXDONE_SIGNAL_PLCP = BIT(0),
154 RXDONE_SIGNAL_BITRATE = 1 << 1, 162 RXDONE_SIGNAL_BITRATE = BIT(1),
155 RXDONE_MY_BSS = 1 << 2, 163 RXDONE_SIGNAL_MCS = BIT(2),
156 RXDONE_CRYPTO_IV = 1 << 3, 164 RXDONE_MY_BSS = BIT(3),
157 RXDONE_CRYPTO_ICV = 1 << 4, 165 RXDONE_CRYPTO_IV = BIT(4),
166 RXDONE_CRYPTO_ICV = BIT(5),
167 RXDONE_L2PAD = BIT(6),
158}; 168};
159 169
160/** 170/**
@@ -163,7 +173,7 @@ enum rxdone_entry_desc_flags {
163 * from &rxdone_entry_desc to a signal value type. 173 * from &rxdone_entry_desc to a signal value type.
164 */ 174 */
165#define RXDONE_SIGNAL_MASK \ 175#define RXDONE_SIGNAL_MASK \
166 ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE ) 176 ( RXDONE_SIGNAL_PLCP | RXDONE_SIGNAL_BITRATE | RXDONE_SIGNAL_MCS )
167 177
168/** 178/**
169 * struct rxdone_entry_desc: RX Entry descriptor 179 * struct rxdone_entry_desc: RX Entry descriptor
@@ -177,6 +187,7 @@ enum rxdone_entry_desc_flags {
177 * @size: Data size of the received frame. 187 * @size: Data size of the received frame.
178 * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags). 188 * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
179 * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags). 189 * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
190 * @rate_mode: Rate mode (See @enum rate_modulation).
180 * @cipher: Cipher type used during decryption. 191 * @cipher: Cipher type used during decryption.
181 * @cipher_status: Decryption status. 192 * @cipher_status: Decryption status.
182 * @iv: IV/EIV data used during decryption. 193 * @iv: IV/EIV data used during decryption.
@@ -190,6 +201,7 @@ struct rxdone_entry_desc {
190 int size; 201 int size;
191 int flags; 202 int flags;
192 int dev_flags; 203 int dev_flags;
204 u16 rate_mode;
193 u8 cipher; 205 u8 cipher;
194 u8 cipher_status; 206 u8 cipher_status;
195 207
@@ -243,6 +255,9 @@ struct txdone_entry_desc {
243 * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared). 255 * @ENTRY_TXD_ENCRYPT_PAIRWISE: Use pairwise key table (instead of shared).
244 * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware. 256 * @ENTRY_TXD_ENCRYPT_IV: Generate IV/EIV in hardware.
245 * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware. 257 * @ENTRY_TXD_ENCRYPT_MMIC: Generate MIC in hardware.
258 * @ENTRY_TXD_HT_AMPDU: This frame is part of an AMPDU.
259 * @ENTRY_TXD_HT_BW_40: Use 40MHz Bandwidth.
260 * @ENTRY_TXD_HT_SHORT_GI: Use short GI.
246 */ 261 */
247enum txentry_desc_flags { 262enum txentry_desc_flags {
248 ENTRY_TXD_RTS_FRAME, 263 ENTRY_TXD_RTS_FRAME,
@@ -258,6 +273,9 @@ enum txentry_desc_flags {
258 ENTRY_TXD_ENCRYPT_PAIRWISE, 273 ENTRY_TXD_ENCRYPT_PAIRWISE,
259 ENTRY_TXD_ENCRYPT_IV, 274 ENTRY_TXD_ENCRYPT_IV,
260 ENTRY_TXD_ENCRYPT_MMIC, 275 ENTRY_TXD_ENCRYPT_MMIC,
276 ENTRY_TXD_HT_AMPDU,
277 ENTRY_TXD_HT_BW_40,
278 ENTRY_TXD_HT_SHORT_GI,
261}; 279};
262 280
263/** 281/**
@@ -267,11 +285,17 @@ enum txentry_desc_flags {
267 * 285 *
268 * @flags: Descriptor flags (See &enum queue_entry_flags). 286 * @flags: Descriptor flags (See &enum queue_entry_flags).
269 * @queue: Queue identification (See &enum data_queue_qid). 287 * @queue: Queue identification (See &enum data_queue_qid).
288 * @header_length: Length of 802.11 header.
289 * @l2pad: Amount of padding to align 802.11 payload to 4-byte boundrary.
270 * @length_high: PLCP length high word. 290 * @length_high: PLCP length high word.
271 * @length_low: PLCP length low word. 291 * @length_low: PLCP length low word.
272 * @signal: PLCP signal. 292 * @signal: PLCP signal.
273 * @service: PLCP service. 293 * @service: PLCP service.
294 * @msc: MCS.
295 * @stbc: STBC.
296 * @ba_size: BA size.
274 * @rate_mode: Rate mode (See @enum rate_modulation). 297 * @rate_mode: Rate mode (See @enum rate_modulation).
298 * @mpdu_density: MDPU density.
275 * @retry_limit: Max number of retries. 299 * @retry_limit: Max number of retries.
276 * @aifs: AIFS value. 300 * @aifs: AIFS value.
277 * @ifs: IFS value. 301 * @ifs: IFS value.
@@ -280,18 +304,26 @@ enum txentry_desc_flags {
280 * @cipher: Cipher type used for encryption. 304 * @cipher: Cipher type used for encryption.
281 * @key_idx: Key index used for encryption. 305 * @key_idx: Key index used for encryption.
282 * @iv_offset: Position where IV should be inserted by hardware. 306 * @iv_offset: Position where IV should be inserted by hardware.
307 * @iv_len: Length of IV data.
283 */ 308 */
284struct txentry_desc { 309struct txentry_desc {
285 unsigned long flags; 310 unsigned long flags;
286 311
287 enum data_queue_qid queue; 312 enum data_queue_qid queue;
288 313
314 u16 header_length;
315 u16 l2pad;
316
289 u16 length_high; 317 u16 length_high;
290 u16 length_low; 318 u16 length_low;
291 u16 signal; 319 u16 signal;
292 u16 service; 320 u16 service;
293 321
322 u16 mcs;
323 u16 stbc;
324 u16 ba_size;
294 u16 rate_mode; 325 u16 rate_mode;
326 u16 mpdu_density;
295 327
296 short retry_limit; 328 short retry_limit;
297 short aifs; 329 short aifs;
@@ -302,6 +334,7 @@ struct txentry_desc {
302 enum cipher cipher; 334 enum cipher cipher;
303 u16 key_idx; 335 u16 key_idx;
304 u16 iv_offset; 336 u16 iv_offset;
337 u16 iv_len;
305}; 338};
306 339
307/** 340/**
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 2ca8b7a9722c..49b29ff90c47 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -603,15 +603,22 @@ static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
603 603
604 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg); 604 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
605 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); 605 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
606 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
606 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 607 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
607 608
608 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg); 609 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
610 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
609 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 611 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
610 !!erp->short_preamble); 612 !!erp->short_preamble);
611 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 613 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
612 614
613 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 615 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
614 616
617 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
618 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
619 erp->beacon_int * 16);
620 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
621
615 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg); 622 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
616 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 623 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
617 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg); 624 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
@@ -938,25 +945,6 @@ static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
938 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg); 945 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
939} 946}
940 947
941static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 u32 reg;
945
946 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
947 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
948 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
949
950 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
951 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
952 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
953
954 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
955 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
956 libconf->conf->beacon_int * 16);
957 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
958}
959
960static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, 948static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
961 struct rt2x00lib_conf *libconf) 949 struct rt2x00lib_conf *libconf)
962{ 950{
@@ -968,7 +956,7 @@ static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
968 if (state == STATE_SLEEP) { 956 if (state == STATE_SLEEP) {
969 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg); 957 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
970 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 958 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
971 libconf->conf->beacon_int - 10); 959 rt2x00dev->beacon_int - 10);
972 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 960 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
973 libconf->conf->listen_interval - 1); 961 libconf->conf->listen_interval - 1);
974 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5); 962 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
@@ -1016,8 +1004,6 @@ static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
1016 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); 1004 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1017 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 1005 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1018 rt61pci_config_retry_limit(rt2x00dev, libconf); 1006 rt61pci_config_retry_limit(rt2x00dev, libconf);
1019 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1020 rt61pci_config_duration(rt2x00dev, libconf);
1021 if (flags & IEEE80211_CONF_CHANGE_PS) 1007 if (flags & IEEE80211_CONF_CHANGE_PS)
1022 rt61pci_config_ps(rt2x00dev, libconf); 1008 rt61pci_config_ps(rt2x00dev, libconf);
1023} 1009}
@@ -2308,7 +2294,6 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2308 u32 reg; 2294 u32 reg;
2309 u16 value; 2295 u16 value;
2310 u16 eeprom; 2296 u16 eeprom;
2311 u16 device;
2312 2297
2313 /* 2298 /*
2314 * Read EEPROM word for configuration. 2299 * Read EEPROM word for configuration.
@@ -2317,14 +2302,10 @@ static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2317 2302
2318 /* 2303 /*
2319 * Identify RF chipset. 2304 * Identify RF chipset.
2320 * To determine the RT chip we have to read the
2321 * PCI header of the device.
2322 */ 2305 */
2323 pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2324 PCI_CONFIG_HEADER_DEVICE, &device);
2325 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2306 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2326 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 2307 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2327 rt2x00_set_chip(rt2x00dev, device, value, reg); 2308 rt2x00_set_chip_rf(rt2x00dev, value, reg);
2328 2309
2329 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) && 2310 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2330 !rt2x00_rf(&rt2x00dev->chip, RF5325) && 2311 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
@@ -2740,7 +2721,6 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2740 .add_interface = rt2x00mac_add_interface, 2721 .add_interface = rt2x00mac_add_interface,
2741 .remove_interface = rt2x00mac_remove_interface, 2722 .remove_interface = rt2x00mac_remove_interface,
2742 .config = rt2x00mac_config, 2723 .config = rt2x00mac_config,
2743 .config_interface = rt2x00mac_config_interface,
2744 .configure_filter = rt2x00mac_configure_filter, 2724 .configure_filter = rt2x00mac_configure_filter,
2745 .set_key = rt2x00mac_set_key, 2725 .set_key = rt2x00mac_set_key,
2746 .get_stats = rt2x00mac_get_stats, 2726 .get_stats = rt2x00mac_get_stats,
diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h
index 41e8959919f6..6c71f77c8165 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.h
+++ b/drivers/net/wireless/rt2x00/rt61pci.h
@@ -63,12 +63,6 @@
63 */ 63 */
64 64
65/* 65/*
66 * PCI Configuration Header
67 */
68#define PCI_CONFIG_HEADER_VENDOR 0x0000
69#define PCI_CONFIG_HEADER_DEVICE 0x0002
70
71/*
72 * HOST_CMD_CSR: For HOST to interrupt embedded processor 66 * HOST_CMD_CSR: For HOST to interrupt embedded processor
73 */ 67 */
74#define HOST_CMD_CSR 0x0008 68#define HOST_CMD_CSR 0x0008
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index 853b2b279b64..c18848836f2d 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -566,15 +566,22 @@ static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
566 566
567 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 567 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
568 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); 568 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
569 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
569 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); 570 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
570 571
571 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 572 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
573 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
572 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 574 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
573 !!erp->short_preamble); 575 !!erp->short_preamble);
574 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); 576 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
575 577
576 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 578 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
577 579
580 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
581 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
582 erp->beacon_int * 16);
583 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
584
578 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg); 585 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
579 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 586 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
580 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); 587 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
@@ -834,25 +841,6 @@ static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
834 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); 841 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
835} 842}
836 843
837static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
838 struct rt2x00lib_conf *libconf)
839{
840 u32 reg;
841
842 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
843 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
845
846 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
847 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
848 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
849
850 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
851 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
852 libconf->conf->beacon_int * 16);
853 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
854}
855
856static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev, 844static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
857 struct rt2x00lib_conf *libconf) 845 struct rt2x00lib_conf *libconf)
858{ 846{
@@ -864,7 +852,7 @@ static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
864 if (state == STATE_SLEEP) { 852 if (state == STATE_SLEEP) {
865 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg); 853 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
866 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 854 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
867 libconf->conf->beacon_int - 10); 855 rt2x00dev->beacon_int - 10);
868 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 856 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
869 libconf->conf->listen_interval - 1); 857 libconf->conf->listen_interval - 1);
870 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5); 858 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
@@ -906,8 +894,6 @@ static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
906 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); 894 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
907 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 895 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
908 rt73usb_config_retry_limit(rt2x00dev, libconf); 896 rt73usb_config_retry_limit(rt2x00dev, libconf);
909 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
910 rt73usb_config_duration(rt2x00dev, libconf);
911 if (flags & IEEE80211_CONF_CHANGE_PS) 897 if (flags & IEEE80211_CONF_CHANGE_PS)
912 rt73usb_config_ps(rt2x00dev, libconf); 898 rt73usb_config_ps(rt2x00dev, libconf);
913} 899}
@@ -1846,7 +1832,8 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1846 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1832 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1847 rt2x00_set_chip(rt2x00dev, RT2571, value, reg); 1833 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1848 1834
1849 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) { 1835 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x000ffff0, 0x25730) ||
1836 rt2x00_check_rev(&rt2x00dev->chip, 0x0000000f, 0)) {
1850 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 1837 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1851 return -ENODEV; 1838 return -ENODEV;
1852 } 1839 }
@@ -2259,7 +2246,6 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
2259 .add_interface = rt2x00mac_add_interface, 2246 .add_interface = rt2x00mac_add_interface,
2260 .remove_interface = rt2x00mac_remove_interface, 2247 .remove_interface = rt2x00mac_remove_interface,
2261 .config = rt2x00mac_config, 2248 .config = rt2x00mac_config,
2262 .config_interface = rt2x00mac_config_interface,
2263 .configure_filter = rt2x00mac_configure_filter, 2249 .configure_filter = rt2x00mac_configure_filter,
2264 .set_key = rt2x00mac_set_key, 2250 .set_key = rt2x00mac_set_key,
2265 .get_stats = rt2x00mac_get_stats, 2251 .get_stats = rt2x00mac_get_stats,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 08:26:35 -0500