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authorWoody Hung <Woody.Hung@mediatek.com>2012-06-13 03:01:16 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-06-20 14:41:49 -0400
commita89534edaaa7008992b878680490e9b02a665563 (patch)
tree94b1a8ff42d231e89d40d5434e66dec507585549 /drivers/net/wireless/rt2x00
parent324640e3594e9d824e72e864001a83d003588363 (diff)
rt2x00 : RT3290 chip support v4
This patch support the new chipset rt3290 wifi implementation in rt2x00. It initailize the related mac, bbp and rf register in startup phase. And this patch modify the efuse read/write method for the different efuse data offset of rt3290. Signed-off-by: Woody Hung <Woody.Hung@mediatek.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig8
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h173
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c350
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c82
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.h1
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h1
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c9
7 files changed, 567 insertions, 57 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 299c3879582d..c7548da6573d 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -99,6 +99,14 @@ config RT2800PCI_RT53XX
99 rt2800pci driver. 99 rt2800pci driver.
100 Supported chips: RT5390 100 Supported chips: RT5390
101 101
102config RT2800PCI_RT3290
103 bool "rt2800pci - Include support for rt3290 devices (EXPERIMENTAL)"
104 depends on EXPERIMENTAL
105 default y
106 ---help---
107 This adds support for rt3290 wireless chipset family to the
108 rt2800pci driver.
109 Supported chips: RT3290
102endif 110endif
103 111
104config RT2500USB 112config RT2500USB
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 1ca88cdc6ece..e252e9bafd0e 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -68,6 +68,7 @@
68#define RF3320 0x000b 68#define RF3320 0x000b
69#define RF3322 0x000c 69#define RF3322 0x000c
70#define RF3053 0x000d 70#define RF3053 0x000d
71#define RF3290 0x3290
71#define RF5360 0x5360 72#define RF5360 0x5360
72#define RF5370 0x5370 73#define RF5370 0x5370
73#define RF5372 0x5372 74#define RF5372 0x5372
@@ -117,6 +118,12 @@
117 * Registers. 118 * Registers.
118 */ 119 */
119 120
121
122/*
123 * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
124 */
125#define MAC_CSR0_3290 0x0000
126
120/* 127/*
121 * E2PROM_CSR: PCI EEPROM control register. 128 * E2PROM_CSR: PCI EEPROM control register.
122 * RELOAD: Write 1 to reload eeprom content. 129 * RELOAD: Write 1 to reload eeprom content.
@@ -133,6 +140,150 @@
133#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 140#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
134 141
135/* 142/*
143 * CMB_CTRL_CFG
144 */
145#define CMB_CTRL 0x0020
146#define AUX_OPT_BIT0 FIELD32(0x00000001)
147#define AUX_OPT_BIT1 FIELD32(0x00000002)
148#define AUX_OPT_BIT2 FIELD32(0x00000004)
149#define AUX_OPT_BIT3 FIELD32(0x00000008)
150#define AUX_OPT_BIT4 FIELD32(0x00000010)
151#define AUX_OPT_BIT5 FIELD32(0x00000020)
152#define AUX_OPT_BIT6 FIELD32(0x00000040)
153#define AUX_OPT_BIT7 FIELD32(0x00000080)
154#define AUX_OPT_BIT8 FIELD32(0x00000100)
155#define AUX_OPT_BIT9 FIELD32(0x00000200)
156#define AUX_OPT_BIT10 FIELD32(0x00000400)
157#define AUX_OPT_BIT11 FIELD32(0x00000800)
158#define AUX_OPT_BIT12 FIELD32(0x00001000)
159#define AUX_OPT_BIT13 FIELD32(0x00002000)
160#define AUX_OPT_BIT14 FIELD32(0x00004000)
161#define AUX_OPT_BIT15 FIELD32(0x00008000)
162#define LDO25_LEVEL FIELD32(0x00030000)
163#define LDO25_LARGEA FIELD32(0x00040000)
164#define LDO25_FRC_ON FIELD32(0x00080000)
165#define CMB_RSV FIELD32(0x00300000)
166#define XTAL_RDY FIELD32(0x00400000)
167#define PLL_LD FIELD32(0x00800000)
168#define LDO_CORE_LEVEL FIELD32(0x0F000000)
169#define LDO_BGSEL FIELD32(0x30000000)
170#define LDO3_EN FIELD32(0x40000000)
171#define LDO0_EN FIELD32(0x80000000)
172
173/*
174 * EFUSE_CSR_3290: RT3290 EEPROM
175 */
176#define EFUSE_CTRL_3290 0x0024
177
178/*
179 * EFUSE_DATA3 of 3290
180 */
181#define EFUSE_DATA3_3290 0x0028
182
183/*
184 * EFUSE_DATA2 of 3290
185 */
186#define EFUSE_DATA2_3290 0x002c
187
188/*
189 * EFUSE_DATA1 of 3290
190 */
191#define EFUSE_DATA1_3290 0x0030
192
193/*
194 * EFUSE_DATA0 of 3290
195 */
196#define EFUSE_DATA0_3290 0x0034
197
198/*
199 * OSC_CTRL_CFG
200 * Ring oscillator configuration
201 */
202#define OSC_CTRL 0x0038
203#define OSC_REF_CYCLE FIELD32(0x00001fff)
204#define OSC_RSV FIELD32(0x0000e000)
205#define OSC_CAL_CNT FIELD32(0x0fff0000)
206#define OSC_CAL_ACK FIELD32(0x10000000)
207#define OSC_CLK_32K_VLD FIELD32(0x20000000)
208#define OSC_CAL_REQ FIELD32(0x40000000)
209#define OSC_ROSC_EN FIELD32(0x80000000)
210
211/*
212 * COEX_CFG_0
213 */
214#define COEX_CFG0 0x0040
215#define COEX_CFG_ANT FIELD32(0xff000000)
216/*
217 * COEX_CFG_1
218 */
219#define COEX_CFG1 0x0044
220
221/*
222 * COEX_CFG_2
223 */
224#define COEX_CFG2 0x0048
225#define BT_COEX_CFG1 FIELD32(0xff000000)
226#define BT_COEX_CFG0 FIELD32(0x00ff0000)
227#define WL_COEX_CFG1 FIELD32(0x0000ff00)
228#define WL_COEX_CFG0 FIELD32(0x000000ff)
229/*
230 * PLL_CTRL_CFG
231 * PLL configuration register
232 */
233#define PLL_CTRL 0x0050
234#define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
235#define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
236#define PLL_CONTROL FIELD32(0x00070000)
237#define PLL_LPF_R1 FIELD32(0x00080000)
238#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
239#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
240#define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
241#define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
242#define PLL_LOCK_CTRL FIELD32(0x70000000)
243#define PLL_VBGBK_EN FIELD32(0x80000000)
244
245
246/*
247 * WLAN_CTRL_CFG
248 * RT3290 wlan configuration
249 */
250#define WLAN_FUN_CTRL 0x0080
251#define WLAN_EN FIELD32(0x00000001)
252#define WLAN_CLK_EN FIELD32(0x00000002)
253#define WLAN_RSV1 FIELD32(0x00000004)
254#define WLAN_RESET FIELD32(0x00000008)
255#define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
256#define FRC_WL_ANT_SET FIELD32(0x00000020)
257#define INV_TR_SW0 FIELD32(0x00000040)
258#define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
259#define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
260#define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
261#define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
262#define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
263#define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
264#define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
265#define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
266#define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
267#define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
268#define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
269#define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
270#define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
271#define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
272#define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
273#define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
274#define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
275#define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
276#define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
277#define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
278#define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
279#define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
280#define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
281#define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
282#define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
283#define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
284#define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
285
286/*
136 * AUX_CTRL: Aux/PCI-E related configuration 287 * AUX_CTRL: Aux/PCI-E related configuration
137 */ 288 */
138#define AUX_CTRL 0x10c 289#define AUX_CTRL 0x10c
@@ -1763,9 +1914,11 @@ struct mac_iveiv_entry {
1763/* 1914/*
1764 * BBP 3: RX Antenna 1915 * BBP 3: RX Antenna
1765 */ 1916 */
1766#define BBP3_RX_ADC FIELD8(0x03) 1917#define BBP3_RX_ADC FIELD8(0x03)
1767#define BBP3_RX_ANTENNA FIELD8(0x18) 1918#define BBP3_RX_ANTENNA FIELD8(0x18)
1768#define BBP3_HT40_MINUS FIELD8(0x20) 1919#define BBP3_HT40_MINUS FIELD8(0x20)
1920#define BBP3_ADC_MODE_SWITCH FIELD8(0x40)
1921#define BBP3_ADC_INIT_MODE FIELD8(0x80)
1769 1922
1770/* 1923/*
1771 * BBP 4: Bandwidth 1924 * BBP 4: Bandwidth
@@ -1775,6 +1928,14 @@ struct mac_iveiv_entry {
1775#define BBP4_MAC_IF_CTRL FIELD8(0x40) 1928#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1776 1929
1777/* 1930/*
1931 * BBP 47: Bandwidth
1932 */
1933#define BBP47_TSSI_REPORT_SEL FIELD8(0x03)
1934#define BBP47_TSSI_UPDATE_REQ FIELD8(0x04)
1935#define BBP47_TSSI_TSSI_MODE FIELD8(0x18)
1936#define BBP47_TSSI_ADC6 FIELD8(0x80)
1937
1938/*
1778 * BBP 109 1939 * BBP 109
1779 */ 1940 */
1780#define BBP109_TX0_POWER FIELD8(0x0f) 1941#define BBP109_TX0_POWER FIELD8(0x0f)
@@ -1917,6 +2078,16 @@ struct mac_iveiv_entry {
1917#define RFCSR27_R4 FIELD8(0x40) 2078#define RFCSR27_R4 FIELD8(0x40)
1918 2079
1919/* 2080/*
2081 * RFCSR 29:
2082 */
2083#define RFCSR29_ADC6_TEST FIELD8(0x01)
2084#define RFCSR29_ADC6_INT_TEST FIELD8(0x02)
2085#define RFCSR29_RSSI_RESET FIELD8(0x04)
2086#define RFCSR29_RSSI_ON FIELD8(0x08)
2087#define RFCSR29_RSSI_RIP_CTRL FIELD8(0x30)
2088#define RFCSR29_RSSI_GAIN FIELD8(0xc0)
2089
2090/*
1920 * RFCSR 30: 2091 * RFCSR 30:
1921 */ 2092 */
1922#define RFCSR30_TX_H20M FIELD8(0x02) 2093#define RFCSR30_TX_H20M FIELD8(0x02)
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 4d3747c3010b..068276ee8aff 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -354,16 +354,15 @@ int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
354 * of 4kb. Certain USB chipsets however require different firmware, 354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware 355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length 356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb. 357 * which is a multiple of 4kb. The firmware for rt3290 chip also
358 * have a length which is a multiple of 4kb.
358 */ 359 */
359 if (rt2x00_is_usb(rt2x00dev)) { 360 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
360 fw_len = 4096; 361 fw_len = 4096;
361 multiple = true; 362 else
362 } else {
363 fw_len = 8192; 363 fw_len = 8192;
364 multiple = true;
365 }
366 364
365 multiple = true;
367 /* 366 /*
368 * Validate the firmware length 367 * Validate the firmware length
369 */ 368 */
@@ -415,7 +414,8 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
415 return -EBUSY; 414 return -EBUSY;
416 415
417 if (rt2x00_is_pci(rt2x00dev)) { 416 if (rt2x00_is_pci(rt2x00dev)) {
418 if (rt2x00_rt(rt2x00dev, RT3572) || 417 if (rt2x00_rt(rt2x00dev, RT3290) ||
418 rt2x00_rt(rt2x00dev, RT3572) ||
419 rt2x00_rt(rt2x00dev, RT5390) || 419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) { 420 rt2x00_rt(rt2x00dev, RT5392)) {
421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg); 421 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
@@ -851,8 +851,13 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
851{ 851{
852 u32 reg; 852 u32 reg;
853 853
854 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 854 if (rt2x00_rt(rt2x00dev, RT3290)) {
855 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); 855 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
856 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
857 } else {
858 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
859 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
860 }
856} 861}
857EXPORT_SYMBOL_GPL(rt2800_rfkill_poll); 862EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
858 863
@@ -1935,9 +1940,54 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1935 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 1940 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1936} 1941}
1937 1942
1943#define RT3290_POWER_BOUND 0x27
1944#define RT3290_FREQ_OFFSET_BOUND 0x5f
1938#define RT5390_POWER_BOUND 0x27 1945#define RT5390_POWER_BOUND 0x27
1939#define RT5390_FREQ_OFFSET_BOUND 0x5f 1946#define RT5390_FREQ_OFFSET_BOUND 0x5f
1940 1947
1948static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1949 struct ieee80211_conf *conf,
1950 struct rf_channel *rf,
1951 struct channel_info *info)
1952{
1953 u8 rfcsr;
1954
1955 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1956 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1957 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1958 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1959 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1960
1961 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1962 if (info->default_power1 > RT3290_POWER_BOUND)
1963 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT3290_POWER_BOUND);
1964 else
1965 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1966 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1967
1968 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1969 if (rt2x00dev->freq_offset > RT3290_FREQ_OFFSET_BOUND)
1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1971 RT3290_FREQ_OFFSET_BOUND);
1972 else
1973 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1974 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1975
1976 if (rf->channel <= 14) {
1977 if (rf->channel == 6)
1978 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
1979 else
1980 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
1981
1982 if (rf->channel >= 1 && rf->channel <= 6)
1983 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
1984 else if (rf->channel >= 7 && rf->channel <= 11)
1985 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
1986 else if (rf->channel >= 12 && rf->channel <= 14)
1987 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
1988 }
1989}
1990
1941static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 1991static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1942 struct ieee80211_conf *conf, 1992 struct ieee80211_conf *conf,
1943 struct rf_channel *rf, 1993 struct rf_channel *rf,
@@ -2036,15 +2086,6 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2036 } 2086 }
2037 } 2087 }
2038 } 2088 }
2039
2040 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2041 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2042 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2043 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2044
2045 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2046 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2047 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2048} 2089}
2049 2090
2050static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 2091static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
@@ -2054,7 +2095,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2054{ 2095{
2055 u32 reg; 2096 u32 reg;
2056 unsigned int tx_pin; 2097 unsigned int tx_pin;
2057 u8 bbp; 2098 u8 bbp, rfcsr;
2058 2099
2059 if (rf->channel <= 14) { 2100 if (rf->channel <= 14) {
2060 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1); 2101 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
@@ -2075,6 +2116,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2075 case RF3052: 2116 case RF3052:
2076 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); 2117 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2077 break; 2118 break;
2119 case RF3290:
2120 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2121 break;
2078 case RF5360: 2122 case RF5360:
2079 case RF5370: 2123 case RF5370:
2080 case RF5372: 2124 case RF5372:
@@ -2086,6 +2130,22 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2086 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 2130 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2087 } 2131 }
2088 2132
2133 if (rt2x00_rf(rt2x00dev, RF3290) ||
2134 rt2x00_rf(rt2x00dev, RF5360) ||
2135 rt2x00_rf(rt2x00dev, RF5370) ||
2136 rt2x00_rf(rt2x00dev, RF5372) ||
2137 rt2x00_rf(rt2x00dev, RF5390) ||
2138 rt2x00_rf(rt2x00dev, RF5392)) {
2139 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2140 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2141 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2142 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2143
2144 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2145 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2146 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2147 }
2148
2089 /* 2149 /*
2090 * Change BBP settings 2150 * Change BBP settings
2091 */ 2151 */
@@ -2566,6 +2626,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2566 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); 2626 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2567 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 2627 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2568 break; 2628 break;
2629 case RF3290:
2569 case RF5360: 2630 case RF5360:
2570 case RF5370: 2631 case RF5370:
2571 case RF5372: 2632 case RF5372:
@@ -2701,6 +2762,7 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2701 if (rt2x00_rt(rt2x00dev, RT3070) || 2762 if (rt2x00_rt(rt2x00dev, RT3070) ||
2702 rt2x00_rt(rt2x00dev, RT3071) || 2763 rt2x00_rt(rt2x00dev, RT3071) ||
2703 rt2x00_rt(rt2x00dev, RT3090) || 2764 rt2x00_rt(rt2x00dev, RT3090) ||
2765 rt2x00_rt(rt2x00dev, RT3290) ||
2704 rt2x00_rt(rt2x00dev, RT3390) || 2766 rt2x00_rt(rt2x00dev, RT3390) ||
2705 rt2x00_rt(rt2x00dev, RT5390) || 2767 rt2x00_rt(rt2x00dev, RT5390) ||
2706 rt2x00_rt(rt2x00dev, RT5392)) 2768 rt2x00_rt(rt2x00dev, RT5392))
@@ -2797,10 +2859,54 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2797 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 2859 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2798 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 2860 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2799 2861
2862 if (rt2x00_rt(rt2x00dev, RT3290)) {
2863 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
2864 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
2865 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
2866 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
2867 }
2868
2869 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
2870 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
2871 rt2x00_set_field32(&reg, LDO0_EN, 1);
2872 rt2x00_set_field32(&reg, LDO_BGSEL, 3);
2873 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
2874 }
2875
2876 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
2877 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
2878 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
2879 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
2880 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
2881
2882 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
2883 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
2884 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
2885
2886 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
2887 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
2888 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
2889 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
2890 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
2891 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
2892
2893 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
2894 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
2895 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
2896 }
2897
2800 if (rt2x00_rt(rt2x00dev, RT3071) || 2898 if (rt2x00_rt(rt2x00dev, RT3071) ||
2801 rt2x00_rt(rt2x00dev, RT3090) || 2899 rt2x00_rt(rt2x00dev, RT3090) ||
2900 rt2x00_rt(rt2x00dev, RT3290) ||
2802 rt2x00_rt(rt2x00dev, RT3390)) { 2901 rt2x00_rt(rt2x00dev, RT3390)) {
2803 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2902
2903 if (rt2x00_rt(rt2x00dev, RT3290))
2904 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2905 0x00000404);
2906 else
2907 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2908 0x00000400);
2909
2804 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2910 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2805 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 2911 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2806 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 2912 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
@@ -3209,14 +3315,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3209 rt2800_wait_bbp_ready(rt2x00dev))) 3315 rt2800_wait_bbp_ready(rt2x00dev)))
3210 return -EACCES; 3316 return -EACCES;
3211 3317
3212 if (rt2x00_rt(rt2x00dev, RT5390) || 3318 if (rt2x00_rt(rt2x00dev, RT3290) ||
3213 rt2x00_rt(rt2x00dev, RT5392)) { 3319 rt2x00_rt(rt2x00dev, RT5390) ||
3320 rt2x00_rt(rt2x00dev, RT5392)) {
3214 rt2800_bbp_read(rt2x00dev, 4, &value); 3321 rt2800_bbp_read(rt2x00dev, 4, &value);
3215 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); 3322 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3216 rt2800_bbp_write(rt2x00dev, 4, value); 3323 rt2800_bbp_write(rt2x00dev, 4, value);
3217 } 3324 }
3218 3325
3219 if (rt2800_is_305x_soc(rt2x00dev) || 3326 if (rt2800_is_305x_soc(rt2x00dev) ||
3327 rt2x00_rt(rt2x00dev, RT3290) ||
3220 rt2x00_rt(rt2x00dev, RT3572) || 3328 rt2x00_rt(rt2x00dev, RT3572) ||
3221 rt2x00_rt(rt2x00dev, RT5390) || 3329 rt2x00_rt(rt2x00dev, RT5390) ||
3222 rt2x00_rt(rt2x00dev, RT5392)) 3330 rt2x00_rt(rt2x00dev, RT5392))
@@ -3225,20 +3333,26 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3225 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 3333 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3226 rt2800_bbp_write(rt2x00dev, 66, 0x38); 3334 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3227 3335
3228 if (rt2x00_rt(rt2x00dev, RT5390) || 3336 if (rt2x00_rt(rt2x00dev, RT3290) ||
3229 rt2x00_rt(rt2x00dev, RT5392)) 3337 rt2x00_rt(rt2x00dev, RT5390) ||
3338 rt2x00_rt(rt2x00dev, RT5392))
3230 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3339 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3231 3340
3232 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 3341 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3233 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3342 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3234 rt2800_bbp_write(rt2x00dev, 73, 0x12); 3343 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3235 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3344 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3236 rt2x00_rt(rt2x00dev, RT5392)) { 3345 rt2x00_rt(rt2x00dev, RT5390) ||
3346 rt2x00_rt(rt2x00dev, RT5392)) {
3237 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3347 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3238 rt2800_bbp_write(rt2x00dev, 73, 0x13); 3348 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3239 rt2800_bbp_write(rt2x00dev, 75, 0x46); 3349 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3240 rt2800_bbp_write(rt2x00dev, 76, 0x28); 3350 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3241 rt2800_bbp_write(rt2x00dev, 77, 0x59); 3351
3352 if (rt2x00_rt(rt2x00dev, RT3290))
3353 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3354 else
3355 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3242 } else { 3356 } else {
3243 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3357 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3244 rt2800_bbp_write(rt2x00dev, 73, 0x10); 3358 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -3263,23 +3377,33 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3263 rt2800_bbp_write(rt2x00dev, 81, 0x37); 3377 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3264 } 3378 }
3265 3379
3380 if (rt2x00_rt(rt2x00dev, RT3290)) {
3381 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3382 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3383 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3384 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3385 }
3386
3266 rt2800_bbp_write(rt2x00dev, 82, 0x62); 3387 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3267 if (rt2x00_rt(rt2x00dev, RT5390) || 3388 if (rt2x00_rt(rt2x00dev, RT3290) ||
3268 rt2x00_rt(rt2x00dev, RT5392)) 3389 rt2x00_rt(rt2x00dev, RT5390) ||
3390 rt2x00_rt(rt2x00dev, RT5392))
3269 rt2800_bbp_write(rt2x00dev, 83, 0x7a); 3391 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3270 else 3392 else
3271 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 3393 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3272 3394
3273 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 3395 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3274 rt2800_bbp_write(rt2x00dev, 84, 0x19); 3396 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3275 else if (rt2x00_rt(rt2x00dev, RT5390) || 3397 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3276 rt2x00_rt(rt2x00dev, RT5392)) 3398 rt2x00_rt(rt2x00dev, RT5390) ||
3399 rt2x00_rt(rt2x00dev, RT5392))
3277 rt2800_bbp_write(rt2x00dev, 84, 0x9a); 3400 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3278 else 3401 else
3279 rt2800_bbp_write(rt2x00dev, 84, 0x99); 3402 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3280 3403
3281 if (rt2x00_rt(rt2x00dev, RT5390) || 3404 if (rt2x00_rt(rt2x00dev, RT3290) ||
3282 rt2x00_rt(rt2x00dev, RT5392)) 3405 rt2x00_rt(rt2x00dev, RT5390) ||
3406 rt2x00_rt(rt2x00dev, RT5392))
3283 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3407 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3284 else 3408 else
3285 rt2800_bbp_write(rt2x00dev, 86, 0x00); 3409 rt2800_bbp_write(rt2x00dev, 86, 0x00);
@@ -3289,8 +3413,9 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3289 3413
3290 rt2800_bbp_write(rt2x00dev, 91, 0x04); 3414 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3291 3415
3292 if (rt2x00_rt(rt2x00dev, RT5390) || 3416 if (rt2x00_rt(rt2x00dev, RT3290) ||
3293 rt2x00_rt(rt2x00dev, RT5392)) 3417 rt2x00_rt(rt2x00dev, RT5390) ||
3418 rt2x00_rt(rt2x00dev, RT5392))
3294 rt2800_bbp_write(rt2x00dev, 92, 0x02); 3419 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3295 else 3420 else
3296 rt2800_bbp_write(rt2x00dev, 92, 0x00); 3421 rt2800_bbp_write(rt2x00dev, 92, 0x00);
@@ -3304,6 +3429,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3304 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 3429 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3305 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 3430 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3306 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 3431 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3432 rt2x00_rt(rt2x00dev, RT3290) ||
3307 rt2x00_rt(rt2x00dev, RT3572) || 3433 rt2x00_rt(rt2x00dev, RT3572) ||
3308 rt2x00_rt(rt2x00dev, RT5390) || 3434 rt2x00_rt(rt2x00dev, RT5390) ||
3309 rt2x00_rt(rt2x00dev, RT5392) || 3435 rt2x00_rt(rt2x00dev, RT5392) ||
@@ -3312,27 +3438,32 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3312 else 3438 else
3313 rt2800_bbp_write(rt2x00dev, 103, 0x00); 3439 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3314 3440
3315 if (rt2x00_rt(rt2x00dev, RT5390) || 3441 if (rt2x00_rt(rt2x00dev, RT3290) ||
3316 rt2x00_rt(rt2x00dev, RT5392)) 3442 rt2x00_rt(rt2x00dev, RT5390) ||
3443 rt2x00_rt(rt2x00dev, RT5392))
3317 rt2800_bbp_write(rt2x00dev, 104, 0x92); 3444 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3318 3445
3319 if (rt2800_is_305x_soc(rt2x00dev)) 3446 if (rt2800_is_305x_soc(rt2x00dev))
3320 rt2800_bbp_write(rt2x00dev, 105, 0x01); 3447 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3448 else if (rt2x00_rt(rt2x00dev, RT3290))
3449 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3321 else if (rt2x00_rt(rt2x00dev, RT5390) || 3450 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3322 rt2x00_rt(rt2x00dev, RT5392)) 3451 rt2x00_rt(rt2x00dev, RT5392))
3323 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 3452 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3324 else 3453 else
3325 rt2800_bbp_write(rt2x00dev, 105, 0x05); 3454 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3326 3455
3327 if (rt2x00_rt(rt2x00dev, RT5390)) 3456 if (rt2x00_rt(rt2x00dev, RT3290) ||
3457 rt2x00_rt(rt2x00dev, RT5390))
3328 rt2800_bbp_write(rt2x00dev, 106, 0x03); 3458 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3329 else if (rt2x00_rt(rt2x00dev, RT5392)) 3459 else if (rt2x00_rt(rt2x00dev, RT5392))
3330 rt2800_bbp_write(rt2x00dev, 106, 0x12); 3460 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3331 else 3461 else
3332 rt2800_bbp_write(rt2x00dev, 106, 0x35); 3462 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3333 3463
3334 if (rt2x00_rt(rt2x00dev, RT5390) || 3464 if (rt2x00_rt(rt2x00dev, RT3290) ||
3335 rt2x00_rt(rt2x00dev, RT5392)) 3465 rt2x00_rt(rt2x00dev, RT5390) ||
3466 rt2x00_rt(rt2x00dev, RT5392))
3336 rt2800_bbp_write(rt2x00dev, 128, 0x12); 3467 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3337 3468
3338 if (rt2x00_rt(rt2x00dev, RT5392)) { 3469 if (rt2x00_rt(rt2x00dev, RT5392)) {
@@ -3357,6 +3488,29 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3357 rt2800_bbp_write(rt2x00dev, 138, value); 3488 rt2800_bbp_write(rt2x00dev, 138, value);
3358 } 3489 }
3359 3490
3491 if (rt2x00_rt(rt2x00dev, RT3290)) {
3492 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3493 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3494 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3495 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3496 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3497 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3498 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3499 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3500 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3501 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3502
3503 rt2800_bbp_read(rt2x00dev, 47, &value);
3504 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3505 rt2800_bbp_write(rt2x00dev, 47, value);
3506
3507 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3508 rt2800_bbp_read(rt2x00dev, 3, &value);
3509 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3510 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3511 rt2800_bbp_write(rt2x00dev, 3, value);
3512 }
3513
3360 if (rt2x00_rt(rt2x00dev, RT5390) || 3514 if (rt2x00_rt(rt2x00dev, RT5390) ||
3361 rt2x00_rt(rt2x00dev, RT5392)) { 3515 rt2x00_rt(rt2x00dev, RT5392)) {
3362 int ant, div_mode; 3516 int ant, div_mode;
@@ -3489,6 +3643,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3489 if (!rt2x00_rt(rt2x00dev, RT3070) && 3643 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3490 !rt2x00_rt(rt2x00dev, RT3071) && 3644 !rt2x00_rt(rt2x00dev, RT3071) &&
3491 !rt2x00_rt(rt2x00dev, RT3090) && 3645 !rt2x00_rt(rt2x00dev, RT3090) &&
3646 !rt2x00_rt(rt2x00dev, RT3290) &&
3492 !rt2x00_rt(rt2x00dev, RT3390) && 3647 !rt2x00_rt(rt2x00dev, RT3390) &&
3493 !rt2x00_rt(rt2x00dev, RT3572) && 3648 !rt2x00_rt(rt2x00dev, RT3572) &&
3494 !rt2x00_rt(rt2x00dev, RT5390) && 3649 !rt2x00_rt(rt2x00dev, RT5390) &&
@@ -3499,8 +3654,9 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3499 /* 3654 /*
3500 * Init RF calibration. 3655 * Init RF calibration.
3501 */ 3656 */
3502 if (rt2x00_rt(rt2x00dev, RT5390) || 3657 if (rt2x00_rt(rt2x00dev, RT3290) ||
3503 rt2x00_rt(rt2x00dev, RT5392)) { 3658 rt2x00_rt(rt2x00dev, RT5390) ||
3659 rt2x00_rt(rt2x00dev, RT5392)) {
3504 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 3660 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3505 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 3661 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3506 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 3662 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
@@ -3538,6 +3694,53 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3538 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 3694 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3539 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 3695 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3540 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 3696 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3697 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3698 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3699 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3700 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3701 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3702 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3703 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3704 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3705 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3706 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3707 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3708 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3709 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3710 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3711 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3712 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3713 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3714 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3715 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3716 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3717 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3718 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3719 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3720 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3721 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3722 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3723 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3724 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3725 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3726 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3727 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3728 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3729 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3730 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3731 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3732 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3733 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3734 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3735 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3736 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3737 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3738 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3739 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3740 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3741 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3742 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3743 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3541 } else if (rt2x00_rt(rt2x00dev, RT3390)) { 3744 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3542 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 3745 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3543 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 3746 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
@@ -3946,6 +4149,12 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3946 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 4149 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3947 } 4150 }
3948 4151
4152 if (rt2x00_rt(rt2x00dev, RT3290)) {
4153 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4154 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4155 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4156 }
4157
3949 if (rt2x00_rt(rt2x00dev, RT5390) || 4158 if (rt2x00_rt(rt2x00dev, RT5390) ||
3950 rt2x00_rt(rt2x00dev, RT5392)) { 4159 rt2x00_rt(rt2x00dev, RT5392)) {
3951 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); 4160 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
@@ -4052,9 +4261,14 @@ EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4052int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) 4261int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4053{ 4262{
4054 u32 reg; 4263 u32 reg;
4264 u16 efuse_ctrl_reg;
4055 4265
4056 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg); 4266 if (rt2x00_rt(rt2x00dev, RT3290))
4267 efuse_ctrl_reg = EFUSE_CTRL_3290;
4268 else
4269 efuse_ctrl_reg = EFUSE_CTRL;
4057 4270
4271 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
4058 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); 4272 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4059} 4273}
4060EXPORT_SYMBOL_GPL(rt2800_efuse_detect); 4274EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
@@ -4062,27 +4276,44 @@ EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4062static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) 4276static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4063{ 4277{
4064 u32 reg; 4278 u32 reg;
4065 4279 u16 efuse_ctrl_reg;
4280 u16 efuse_data0_reg;
4281 u16 efuse_data1_reg;
4282 u16 efuse_data2_reg;
4283 u16 efuse_data3_reg;
4284
4285 if (rt2x00_rt(rt2x00dev, RT3290)) {
4286 efuse_ctrl_reg = EFUSE_CTRL_3290;
4287 efuse_data0_reg = EFUSE_DATA0_3290;
4288 efuse_data1_reg = EFUSE_DATA1_3290;
4289 efuse_data2_reg = EFUSE_DATA2_3290;
4290 efuse_data3_reg = EFUSE_DATA3_3290;
4291 } else {
4292 efuse_ctrl_reg = EFUSE_CTRL;
4293 efuse_data0_reg = EFUSE_DATA0;
4294 efuse_data1_reg = EFUSE_DATA1;
4295 efuse_data2_reg = EFUSE_DATA2;
4296 efuse_data3_reg = EFUSE_DATA3;
4297 }
4066 mutex_lock(&rt2x00dev->csr_mutex); 4298 mutex_lock(&rt2x00dev->csr_mutex);
4067 4299
4068 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg); 4300 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
4069 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 4301 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4070 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 4302 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4071 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 4303 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4072 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg); 4304 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
4073 4305
4074 /* Wait until the EEPROM has been loaded */ 4306 /* Wait until the EEPROM has been loaded */
4075 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 4307 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
4076
4077 /* Apparently the data is read from end to start */ 4308 /* Apparently the data is read from end to start */
4078 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg); 4309 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
4079 /* The returned value is in CPU order, but eeprom is le */ 4310 /* The returned value is in CPU order, but eeprom is le */
4080 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); 4311 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4081 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg); 4312 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
4082 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); 4313 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4083 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg); 4314 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
4084 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); 4315 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4085 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg); 4316 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
4086 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); 4317 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4087 4318
4088 mutex_unlock(&rt2x00dev->csr_mutex); 4319 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -4244,9 +4475,14 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4244 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 4475 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4245 * RT53xx: defined in "EEPROM_CHIP_ID" field 4476 * RT53xx: defined in "EEPROM_CHIP_ID" field
4246 */ 4477 */
4247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 4478 if (rt2x00_rt(rt2x00dev, RT3290))
4248 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 || 4479 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4249 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392) 4480 else
4481 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4482
4483 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4484 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4485 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4250 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value); 4486 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4251 else 4487 else
4252 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 4488 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
@@ -4261,6 +4497,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4261 case RT3070: 4497 case RT3070:
4262 case RT3071: 4498 case RT3071:
4263 case RT3090: 4499 case RT3090:
4500 case RT3290:
4264 case RT3390: 4501 case RT3390:
4265 case RT3572: 4502 case RT3572:
4266 case RT5390: 4503 case RT5390:
@@ -4281,6 +4518,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4281 case RF3021: 4518 case RF3021:
4282 case RF3022: 4519 case RF3022:
4283 case RF3052: 4520 case RF3052:
4521 case RF3290:
4284 case RF3320: 4522 case RF3320:
4285 case RF5360: 4523 case RF5360:
4286 case RF5370: 4524 case RF5370:
@@ -4597,6 +4835,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4597 rt2x00_rf(rt2x00dev, RF2020) || 4835 rt2x00_rf(rt2x00dev, RF2020) ||
4598 rt2x00_rf(rt2x00dev, RF3021) || 4836 rt2x00_rf(rt2x00dev, RF3021) ||
4599 rt2x00_rf(rt2x00dev, RF3022) || 4837 rt2x00_rf(rt2x00dev, RF3022) ||
4838 rt2x00_rf(rt2x00dev, RF3290) ||
4600 rt2x00_rf(rt2x00dev, RF3320) || 4839 rt2x00_rf(rt2x00dev, RF3320) ||
4601 rt2x00_rf(rt2x00dev, RF5360) || 4840 rt2x00_rf(rt2x00dev, RF5360) ||
4602 rt2x00_rf(rt2x00dev, RF5370) || 4841 rt2x00_rf(rt2x00dev, RF5370) ||
@@ -4685,6 +4924,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4685 case RF3022: 4924 case RF3022:
4686 case RF3320: 4925 case RF3320:
4687 case RF3052: 4926 case RF3052:
4927 case RF3290:
4688 case RF5360: 4928 case RF5360:
4689 case RF5370: 4929 case RF5370:
4690 case RF5372: 4930 case RF5372:
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 206158b67426..dd436125fe3d 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -280,7 +280,13 @@ static void rt2800pci_stop_queue(struct data_queue *queue)
280 */ 280 */
281static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) 281static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
282{ 282{
283 return FIRMWARE_RT2860; 283 /*
284 * Chip rt3290 use specific 4KB firmware named rt3290.bin.
285 */
286 if (rt2x00_rt(rt2x00dev, RT3290))
287 return FIRMWARE_RT3290;
288 else
289 return FIRMWARE_RT2860;
284} 290}
285 291
286static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev, 292static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
@@ -974,6 +980,66 @@ static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
974 return rt2800_validate_eeprom(rt2x00dev); 980 return rt2800_validate_eeprom(rt2x00dev);
975} 981}
976 982
983static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
984{
985 u32 reg;
986 int i, count;
987
988 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
989 if ((rt2x00_get_field32(reg, WLAN_EN) == 1))
990 return 0;
991
992 rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
993 rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
994 rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
995 rt2x00_set_field32(&reg, WLAN_EN, 1);
996 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
997
998 udelay(REGISTER_BUSY_DELAY);
999
1000 count = 0;
1001 do {
1002 /*
1003 * Check PLL_LD & XTAL_RDY.
1004 */
1005 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1006 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
1007 if ((rt2x00_get_field32(reg, PLL_LD) == 1) &&
1008 (rt2x00_get_field32(reg, XTAL_RDY) == 1))
1009 break;
1010 udelay(REGISTER_BUSY_DELAY);
1011 }
1012
1013 if (i >= REGISTER_BUSY_COUNT) {
1014
1015 if (count >= 10)
1016 return -EIO;
1017
1018 rt2800_register_write(rt2x00dev, 0x58, 0x018);
1019 udelay(REGISTER_BUSY_DELAY);
1020 rt2800_register_write(rt2x00dev, 0x58, 0x418);
1021 udelay(REGISTER_BUSY_DELAY);
1022 rt2800_register_write(rt2x00dev, 0x58, 0x618);
1023 udelay(REGISTER_BUSY_DELAY);
1024 count++;
1025 } else {
1026 count = 0;
1027 }
1028
1029 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1030 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
1031 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
1032 rt2x00_set_field32(&reg, WLAN_RESET, 1);
1033 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
1034 udelay(10);
1035 rt2x00_set_field32(&reg, WLAN_RESET, 0);
1036 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
1037 udelay(10);
1038 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
1039 } while (count != 0);
1040
1041 return 0;
1042}
977static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1043static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
978{ 1044{
979 int retval; 1045 int retval;
@@ -997,6 +1063,17 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
997 return retval; 1063 return retval;
998 1064
999 /* 1065 /*
1066 * In probe phase call rt2800_enable_wlan_rt3290 to enable wlan
1067 * clk for rt3290. That avoid the MCU fail in start phase.
1068 */
1069 if (rt2x00_rt(rt2x00dev, RT3290)) {
1070 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
1071
1072 if (retval)
1073 return retval;
1074 }
1075
1076 /*
1000 * This device has multiple filters for control frames 1077 * This device has multiple filters for control frames
1001 * and has a separate filter for PS Poll frames. 1078 * and has a separate filter for PS Poll frames.
1002 */ 1079 */
@@ -1175,6 +1252,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1175 { PCI_DEVICE(0x1432, 0x7768) }, 1252 { PCI_DEVICE(0x1432, 0x7768) },
1176 { PCI_DEVICE(0x1462, 0x891a) }, 1253 { PCI_DEVICE(0x1462, 0x891a) },
1177 { PCI_DEVICE(0x1a3b, 0x1059) }, 1254 { PCI_DEVICE(0x1a3b, 0x1059) },
1255#ifdef CONFIG_RT2800PCI_RT3290
1256 { PCI_DEVICE(0x1814, 0x3290) },
1257#endif
1178#ifdef CONFIG_RT2800PCI_RT33XX 1258#ifdef CONFIG_RT2800PCI_RT33XX
1179 { PCI_DEVICE(0x1814, 0x3390) }, 1259 { PCI_DEVICE(0x1814, 0x3390) },
1180#endif 1260#endif
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
index 70e050d904c8..ab22a087c50d 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.h
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -47,6 +47,7 @@
47 * 8051 firmware image. 47 * 8051 firmware image.
48 */ 48 */
49#define FIRMWARE_RT2860 "rt2860.bin" 49#define FIRMWARE_RT2860 "rt2860.bin"
50#define FIRMWARE_RT3290 "rt3290.bin"
50#define FIRMWARE_IMAGE_BASE 0x2000 51#define FIRMWARE_IMAGE_BASE 0x2000
51 52
52/* 53/*
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 8f754025b06e..8afb546c2b2d 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -187,6 +187,7 @@ struct rt2x00_chip {
187#define RT3070 0x3070 187#define RT3070 0x3070
188#define RT3071 0x3071 188#define RT3071 0x3071
189#define RT3090 0x3090 /* 2.4GHz PCIe */ 189#define RT3090 0x3090 /* 2.4GHz PCIe */
190#define RT3290 0x3290
190#define RT3390 0x3390 191#define RT3390 0x3390
191#define RT3572 0x3572 192#define RT3572 0x3572
192#define RT3593 0x3593 193#define RT3593 0x3593
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 0a4653a92cab..a0c8caef3b0a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -256,6 +256,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
256 struct ieee80211_hw *hw; 256 struct ieee80211_hw *hw;
257 struct rt2x00_dev *rt2x00dev; 257 struct rt2x00_dev *rt2x00dev;
258 int retval; 258 int retval;
259 u16 chip;
259 260
260 retval = pci_enable_device(pci_dev); 261 retval = pci_enable_device(pci_dev);
261 if (retval) { 262 if (retval) {
@@ -305,6 +306,14 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct rt2x00_ops *ops)
305 if (retval) 306 if (retval)
306 goto exit_free_device; 307 goto exit_free_device;
307 308
309 /*
310 * Because rt3290 chip use different efuse offset to read efuse data.
311 * So before read efuse it need to indicate it is the
312 * rt3290 or not.
313 */
314 pci_read_config_word(pci_dev, PCI_DEVICE_ID, &chip);
315 rt2x00dev->chip.rt = chip;
316
308 retval = rt2x00lib_probe_dev(rt2x00dev); 317 retval = rt2x00lib_probe_dev(rt2x00dev);
309 if (retval) 318 if (retval)
310 goto exit_free_reg; 319 goto exit_free_reg;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-30 13:31:10 -0400