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authorIvo van Doorn <IvDoorn@gmail.com>2009-04-26 09:47:48 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-05-06 15:14:54 -0400
commitd53d9e67b55f6a9fc3f836c5c392eb41ce5676f4 (patch)
tree0a46d3f61b40b390c0fc194b0d6048726a582fac /drivers/net/wireless/rt2x00
parent206eade5a68f7a06adbe7c65e47fd88843ad0546 (diff)
rt2x00: Implement support for rt2800usb
Add support for the rt2800usb chipset. Current problems: * Cannot scan 11n AP's * No TX during first minute after association * Broken Hardware encryption Includes various patches from Mattias, Felix, Xose and Axel. Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com> Signed-off-by: Axel Kollhofer <rain_maker@root-forum.org> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig14
-rw-r--r--drivers/net/wireless/rt2x00/Makefile1
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c3046
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h1934
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h1
5 files changed, 4996 insertions, 0 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 4338c93d5b63..18ee7d6c4028 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -77,6 +77,20 @@ config RT73USB
77 77
78 When compiled as a module, this driver will be called "rt73usb.ko". 78 When compiled as a module, this driver will be called "rt73usb.ko".
79 79
80config RT2800USB
81 tristate "Ralink rt2800 (USB) support"
82 depends on USB
83 select RT2X00_LIB_USB
84 select RT2X00_LIB_HT
85 select RT2X00_LIB_FIRMWARE
86 select RT2X00_LIB_CRYPTO
87 select CRC_CCITT
88 ---help---
89 This adds support for rt2800 wireless chipset family.
90 Supported chips: RT2770, RT2870 & RT3070.
91
92 When compiled as a module, this driver will be called "rt2800usb.ko".
93
80config RT2X00_LIB_PCI 94config RT2X00_LIB_PCI
81 tristate 95 tristate
82 select RT2X00_LIB 96 select RT2X00_LIB
diff --git a/drivers/net/wireless/rt2x00/Makefile b/drivers/net/wireless/rt2x00/Makefile
index 776ec2b8c4e7..bfc7226f0afe 100644
--- a/drivers/net/wireless/rt2x00/Makefile
+++ b/drivers/net/wireless/rt2x00/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_RT2500PCI) += rt2500pci.o
18obj-$(CONFIG_RT61PCI) += rt61pci.o 18obj-$(CONFIG_RT61PCI) += rt61pci.o
19obj-$(CONFIG_RT2500USB) += rt2500usb.o 19obj-$(CONFIG_RT2500USB) += rt2500usb.o
20obj-$(CONFIG_RT73USB) += rt73usb.o 20obj-$(CONFIG_RT73USB) += rt73usb.o
21obj-$(CONFIG_RT2800USB) += rt2800usb.o
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
new file mode 100644
index 000000000000..812912e508cd
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -0,0 +1,3046 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800usb
23 Abstract: rt2800usb device specific routines.
24 Supported chipsets: RT2800U.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt2800usb.h"
38
39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 1;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the new data into the register.
80 */
81 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82 reg = 0;
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89 }
90
91 mutex_unlock(&rt2x00dev->csr_mutex);
92}
93
94static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95 const unsigned int word, u8 *value)
96{
97 u32 reg;
98
99 mutex_lock(&rt2x00dev->csr_mutex);
100
101 /*
102 * Wait until the BBP becomes available, afterwards we
103 * can safely write the read request into the register.
104 * After the data has been written, we wait until hardware
105 * returns the correct value, if at any time the register
106 * doesn't become available in time, reg will be 0xffffffff
107 * which means we return 0xff to the caller.
108 */
109 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 reg = 0;
111 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117 WAIT_FOR_BBP(rt2x00dev, &reg);
118 }
119
120 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122 mutex_unlock(&rt2x00dev->csr_mutex);
123}
124
125static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->csr_mutex);
131
132 /*
133 * Wait until the RFCSR becomes available, afterwards we
134 * can safely write the new data into the register.
135 */
136 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137 reg = 0;
138 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144 }
145
146 mutex_unlock(&rt2x00dev->csr_mutex);
147}
148
149static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150 const unsigned int word, u8 *value)
151{
152 u32 reg;
153
154 mutex_lock(&rt2x00dev->csr_mutex);
155
156 /*
157 * Wait until the RFCSR becomes available, afterwards we
158 * can safely write the read request into the register.
159 * After the data has been written, we wait until hardware
160 * returns the correct value, if at any time the register
161 * doesn't become available in time, reg will be 0xffffffff
162 * which means we return 0xff to the caller.
163 */
164 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165 reg = 0;
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173 }
174
175 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177 mutex_unlock(&rt2x00dev->csr_mutex);
178}
179
180static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181 const unsigned int word, const u32 value)
182{
183 u32 reg;
184
185 mutex_lock(&rt2x00dev->csr_mutex);
186
187 /*
188 * Wait until the RF becomes available, afterwards we
189 * can safely write the new data into the register.
190 */
191 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199 rt2x00_rf_write(rt2x00dev, word, value);
200 }
201
202 mutex_unlock(&rt2x00dev->csr_mutex);
203}
204
205static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206 const u8 command, const u8 token,
207 const u8 arg0, const u8 arg1)
208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the MCU becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224 reg = 0;
225 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
233static const struct rt2x00debug rt2800usb_rt2x00debug = {
234 .owner = THIS_MODULE,
235 .csr = {
236 .read = rt2x00usb_register_read,
237 .write = rt2x00usb_register_write,
238 .flags = RT2X00DEBUGFS_OFFSET,
239 .word_base = CSR_REG_BASE,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_base = EEPROM_BASE,
247 .word_size = sizeof(u16),
248 .word_count = EEPROM_SIZE / sizeof(u16),
249 },
250 .bbp = {
251 .read = rt2800usb_bbp_read,
252 .write = rt2800usb_bbp_write,
253 .word_base = BBP_BASE,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt2800usb_rf_write,
260 .word_base = RF_BASE,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267#ifdef CONFIG_RT2X00_LIB_RFKILL
268static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269{
270 u32 reg;
271
272 rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
273 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
274}
275#else
276#define rt2800usb_rfkill_poll NULL
277#endif /* CONFIG_RT2X00_LIB_RFKILL */
278
279#ifdef CONFIG_RT2X00_LIB_LEDS
280static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int bg_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
288 unsigned int polarity =
289 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
290 EEPROM_FREQ_LED_POLARITY);
291 unsigned int ledmode =
292 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
293 EEPROM_FREQ_LED_MODE);
294
295 if (led->type == LED_TYPE_RADIO) {
296 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
297 enabled ? 0x20 : 0);
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
300 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
301 } else if (led->type == LED_TYPE_QUALITY) {
302 /*
303 * The brightness is divided into 6 levels (0 - 5),
304 * The specs tell us the following levels:
305 * 0, 1 ,3, 7, 15, 31
306 * to determine the level in a simple way we can simply
307 * work with bitshifting:
308 * (1 << level) - 1
309 */
310 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
311 (1 << brightness / (LED_FULL / 6)) - 1,
312 polarity);
313 }
314}
315
316static int rt2800usb_blink_set(struct led_classdev *led_cdev,
317 unsigned long *delay_on,
318 unsigned long *delay_off)
319{
320 struct rt2x00_led *led =
321 container_of(led_cdev, struct rt2x00_led, led_dev);
322 u32 reg;
323
324 rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
325 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
326 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
327 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
328 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
329 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
330 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
331 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
332 rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
333
334 return 0;
335}
336
337static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
338 struct rt2x00_led *led,
339 enum led_type type)
340{
341 led->rt2x00dev = rt2x00dev;
342 led->type = type;
343 led->led_dev.brightness_set = rt2800usb_brightness_set;
344 led->led_dev.blink_set = rt2800usb_blink_set;
345 led->flags = LED_INITIALIZED;
346}
347#endif /* CONFIG_RT2X00_LIB_LEDS */
348
349/*
350 * Configuration handlers.
351 */
352static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
353 struct rt2x00lib_crypto *crypto,
354 struct ieee80211_key_conf *key)
355{
356 struct mac_wcid_entry wcid_entry;
357 struct mac_iveiv_entry iveiv_entry;
358 u32 offset;
359 u32 reg;
360
361 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
362
363 rt2x00usb_register_read(rt2x00dev, offset, &reg);
364 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
365 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
366 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
367 (crypto->cmd == SET_KEY) * crypto->cipher);
368 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
369 (crypto->cmd == SET_KEY) * crypto->bssidx);
370 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
371 rt2x00usb_register_write(rt2x00dev, offset, reg);
372
373 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
374
375 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
376 if ((crypto->cipher == CIPHER_TKIP) ||
377 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
378 (crypto->cipher == CIPHER_AES))
379 iveiv_entry.iv[3] |= 0x20;
380 iveiv_entry.iv[3] |= key->keyidx << 6;
381 rt2x00usb_register_multiwrite(rt2x00dev, offset,
382 &iveiv_entry, sizeof(iveiv_entry));
383
384 offset = MAC_WCID_ENTRY(key->hw_key_idx);
385
386 memset(&wcid_entry, 0, sizeof(wcid_entry));
387 if (crypto->cmd == SET_KEY)
388 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
389 rt2x00usb_register_multiwrite(rt2x00dev, offset,
390 &wcid_entry, sizeof(wcid_entry));
391}
392
393static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
394 struct rt2x00lib_crypto *crypto,
395 struct ieee80211_key_conf *key)
396{
397 struct hw_key_entry key_entry;
398 struct rt2x00_field32 field;
399 int timeout;
400 u32 offset;
401 u32 reg;
402
403 if (crypto->cmd == SET_KEY) {
404 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
405
406 memcpy(key_entry.key, crypto->key,
407 sizeof(key_entry.key));
408 memcpy(key_entry.tx_mic, crypto->tx_mic,
409 sizeof(key_entry.tx_mic));
410 memcpy(key_entry.rx_mic, crypto->rx_mic,
411 sizeof(key_entry.rx_mic));
412
413 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
414 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
415 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
416 USB_VENDOR_REQUEST_OUT,
417 offset, &key_entry,
418 sizeof(key_entry),
419 timeout);
420 }
421
422 /*
423 * The cipher types are stored over multiple registers
424 * starting with SHARED_KEY_MODE_BASE each word will have
425 * 32 bits and contains the cipher types for 2 bssidx each.
426 * Using the correct defines correctly will cause overhead,
427 * so just calculate the correct offset.
428 */
429 field.bit_offset = 4 * (key->hw_key_idx % 8);
430 field.bit_mask = 0x7 << field.bit_offset;
431
432 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
433
434 rt2x00usb_register_read(rt2x00dev, offset, &reg);
435 rt2x00_set_field32(&reg, field,
436 (crypto->cmd == SET_KEY) * crypto->cipher);
437 rt2x00usb_register_write(rt2x00dev, offset, reg);
438
439 /*
440 * Update WCID information
441 */
442 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
443
444 return 0;
445}
446
447static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
448 struct rt2x00lib_crypto *crypto,
449 struct ieee80211_key_conf *key)
450{
451 struct hw_key_entry key_entry;
452 int timeout;
453 u32 offset;
454
455 if (crypto->cmd == SET_KEY) {
456 /*
457 * 1 pairwise key is possible per AID, this means that the AID
458 * equals our hw_key_idx. Make sure the WCID starts _after_ the
459 * last possible shared key entry.
460 */
461 if (crypto->aid > (256 - 32))
462 return -ENOSPC;
463
464 key->hw_key_idx = 32 + crypto->aid;
465
466 memcpy(key_entry.key, crypto->key,
467 sizeof(key_entry.key));
468 memcpy(key_entry.tx_mic, crypto->tx_mic,
469 sizeof(key_entry.tx_mic));
470 memcpy(key_entry.rx_mic, crypto->rx_mic,
471 sizeof(key_entry.rx_mic));
472
473 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
474 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
475 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
476 USB_VENDOR_REQUEST_OUT,
477 offset, &key_entry,
478 sizeof(key_entry),
479 timeout);
480 }
481
482 /*
483 * Update WCID information
484 */
485 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
486
487 return 0;
488}
489
490static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
491 const unsigned int filter_flags)
492{
493 u32 reg;
494
495 /*
496 * Start configuration steps.
497 * Note that the version error will always be dropped
498 * and broadcast frames will always be accepted since
499 * there is no filter for it at this time.
500 */
501 rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
502 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
503 !(filter_flags & FIF_FCSFAIL));
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
505 !(filter_flags & FIF_PLCPFAIL));
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
507 !(filter_flags & FIF_PROMISC_IN_BSS));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
511 !(filter_flags & FIF_ALLMULTI));
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
513 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
515 !(filter_flags & FIF_CONTROL));
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
521 !(filter_flags & FIF_CONTROL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
523 !(filter_flags & FIF_CONTROL));
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
529 !(filter_flags & FIF_CONTROL));
530 rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
531}
532
533static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
534 struct rt2x00_intf *intf,
535 struct rt2x00intf_conf *conf,
536 const unsigned int flags)
537{
538 unsigned int beacon_base;
539 u32 reg;
540
541 if (flags & CONFIG_UPDATE_TYPE) {
542 /*
543 * Clear current synchronisation setup.
544 * For the Beacon base registers we only need to clear
545 * the first byte since that byte contains the VALID and OWNER
546 * bits which (when set to 0) will invalidate the entire beacon.
547 */
548 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
549 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
550
551 /*
552 * Enable synchronisation.
553 */
554 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
555 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
558 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
559 }
560
561 if (flags & CONFIG_UPDATE_MAC) {
562 reg = le32_to_cpu(conf->mac[1]);
563 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
564 conf->mac[1] = cpu_to_le32(reg);
565
566 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
567 conf->mac, sizeof(conf->mac));
568 }
569
570 if (flags & CONFIG_UPDATE_BSSID) {
571 reg = le32_to_cpu(conf->bssid[1]);
572 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
573 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
574 conf->bssid[1] = cpu_to_le32(reg);
575
576 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
577 conf->bssid, sizeof(conf->bssid));
578 }
579}
580
581static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
582 struct rt2x00lib_erp *erp)
583{
584 u32 reg;
585
586 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
587 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
588 DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
589 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
590
591 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
592 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
593 !!erp->short_preamble);
594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
595 !!erp->short_preamble);
596 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
597
598 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
599 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
600 erp->cts_protection ? 2 : 0);
601 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
602
603 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
604 erp->basic_rates);
605 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
606
607 rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
608 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
609 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
610 rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
611
612 rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
613 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
614 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
615 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
616 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
617 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
618 rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
619}
620
621static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
622 struct antenna_setup *ant)
623{
624 u8 r1;
625 u8 r3;
626
627 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
628 rt2800usb_bbp_read(rt2x00dev, 3, &r3);
629
630 /*
631 * Configure the TX antenna.
632 */
633 switch ((int)ant->tx) {
634 case 1:
635 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
636 break;
637 case 2:
638 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
639 break;
640 case 3:
641 /* Do nothing */
642 break;
643 }
644
645 /*
646 * Configure the RX antenna.
647 */
648 switch ((int)ant->rx) {
649 case 1:
650 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
651 break;
652 case 2:
653 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
654 break;
655 case 3:
656 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
657 break;
658 }
659
660 rt2800usb_bbp_write(rt2x00dev, 3, r3);
661 rt2800usb_bbp_write(rt2x00dev, 1, r1);
662}
663
664static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
665 struct rt2x00lib_conf *libconf)
666{
667 u16 eeprom;
668 short lna_gain;
669
670 if (libconf->rf.channel <= 14) {
671 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
672 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
673 } else if (libconf->rf.channel <= 64) {
674 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
676 } else if (libconf->rf.channel <= 128) {
677 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
678 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
679 } else {
680 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
681 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
682 }
683
684 rt2x00dev->lna_gain = lna_gain;
685}
686
687static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
688 struct ieee80211_conf *conf,
689 struct rf_channel *rf,
690 struct channel_info *info)
691{
692 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
693
694 if (rt2x00dev->default_ant.tx == 1)
695 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
696
697 if (rt2x00dev->default_ant.rx == 1) {
698 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
699 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
700 } else if (rt2x00dev->default_ant.rx == 2)
701 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
702
703 if (rf->channel > 14) {
704 /*
705 * When TX power is below 0, we should increase it by 7 to
706 * make it a positive value (Minumum value is -7).
707 * However this means that values between 0 and 7 have
708 * double meaning, and we should set a 7DBm boost flag.
709 */
710 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
711 (info->tx_power1 >= 0));
712
713 if (info->tx_power1 < 0)
714 info->tx_power1 += 7;
715
716 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
717 TXPOWER_A_TO_DEV(info->tx_power1));
718
719 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
720 (info->tx_power2 >= 0));
721
722 if (info->tx_power2 < 0)
723 info->tx_power2 += 7;
724
725 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
726 TXPOWER_A_TO_DEV(info->tx_power2));
727 } else {
728 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
729 TXPOWER_G_TO_DEV(info->tx_power1));
730 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
731 TXPOWER_G_TO_DEV(info->tx_power2));
732 }
733
734 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
735
736 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
737 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
738 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
739 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
740
741 udelay(200);
742
743 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
744 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
745 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
746 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
747
748 udelay(200);
749
750 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
751 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
752 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
753 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
754}
755
756static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
757 struct ieee80211_conf *conf,
758 struct rf_channel *rf,
759 struct channel_info *info)
760{
761 u8 rfcsr;
762
763 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
764 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
765
766 rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
767 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
768 rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
769
770 rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
771 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
772 TXPOWER_G_TO_DEV(info->tx_power1));
773 rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
774
775 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
776 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
777 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
778
779 rt2800usb_rfcsr_write(rt2x00dev, 24,
780 rt2x00dev->calibration[conf_is_ht40(conf)]);
781
782 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
783 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
784 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
785}
786
787static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
788 struct ieee80211_conf *conf,
789 struct rf_channel *rf,
790 struct channel_info *info)
791{
792 u32 reg;
793 unsigned int tx_pin;
794 u8 bbp;
795
796 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
797 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
798 else
799 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
800
801 /*
802 * Change BBP settings
803 */
804 rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
805 rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
806 rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
807 rt2800usb_bbp_write(rt2x00dev, 86, 0);
808
809 if (rf->channel <= 14) {
810 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
811 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
812 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
813 } else {
814 rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
815 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
816 }
817 } else {
818 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
819
820 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
821 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
822 else
823 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
824 }
825
826 rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
827 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
828 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
829 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
830 rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
831
832 tx_pin = 0;
833
834 /* Turn on unused PA or LNA when not using 1T or 1R */
835 if (rt2x00dev->default_ant.tx != 1) {
836 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
837 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
838 }
839
840 /* Turn on unused PA or LNA when not using 1T or 1R */
841 if (rt2x00dev->default_ant.rx != 1) {
842 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
843 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
844 }
845
846 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
848 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
849 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
852
853 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
854
855 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
856 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
857 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
858
859 rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
860 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
861 rt2800usb_bbp_write(rt2x00dev, 3, bbp);
862
863 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
864 if (conf_is_ht40(conf)) {
865 rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
866 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
867 rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
868 } else {
869 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
870 rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
871 rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
872 }
873 }
874
875 msleep(1);
876}
877
878static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
879 const int txpower)
880{
881 u32 reg;
882 u32 value = TXPOWER_G_TO_DEV(txpower);
883 u8 r1;
884
885 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
886 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
887 rt2800usb_bbp_write(rt2x00dev, 1, r1);
888
889 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
890 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
891 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
892 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
893 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
894 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
895 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
896 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
897 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
898 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
899
900 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
906 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
909 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
910
911 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
917 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
920 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
921
922 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
931 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
932
933 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
938 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
939}
940
941static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 u32 reg;
945
946 rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
947 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
948 libconf->conf->short_frame_max_tx_count);
949 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
950 libconf->conf->long_frame_max_tx_count);
951 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
952 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
953 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
954 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
955 rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
956}
957
958static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
959 struct rt2x00lib_conf *libconf)
960{
961 u32 reg;
962
963 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
964 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
965 libconf->conf->beacon_int * 16);
966 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
967}
968
969static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
970 struct rt2x00lib_conf *libconf)
971{
972 enum dev_state state =
973 (libconf->conf->flags & IEEE80211_CONF_PS) ?
974 STATE_SLEEP : STATE_AWAKE;
975 u32 reg;
976
977 if (state == STATE_SLEEP) {
978 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
979
980 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
982 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
983 libconf->conf->listen_interval - 1);
984 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
985 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
986
987 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
988 } else {
989 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
990
991 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
992 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
993 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
994 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
995 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
996 }
997}
998
999static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1000 struct rt2x00lib_conf *libconf,
1001 const unsigned int flags)
1002{
1003 /* Always recalculate LNA gain before changing configuration */
1004 rt2800usb_config_lna_gain(rt2x00dev, libconf);
1005
1006 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1007 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1008 &libconf->rf, &libconf->channel);
1009 if (flags & IEEE80211_CONF_CHANGE_POWER)
1010 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1011 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1012 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1013 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1014 rt2800usb_config_duration(rt2x00dev, libconf);
1015 if (flags & IEEE80211_CONF_CHANGE_PS)
1016 rt2800usb_config_ps(rt2x00dev, libconf);
1017}
1018
1019/*
1020 * Link tuning
1021 */
1022static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1023 struct link_qual *qual)
1024{
1025 u32 reg;
1026
1027 /*
1028 * Update FCS error count from register.
1029 */
1030 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1031 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1032}
1033
1034static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1035{
1036 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1037 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1038 return 0x1c + (2 * rt2x00dev->lna_gain);
1039 else
1040 return 0x2e + rt2x00dev->lna_gain;
1041 }
1042
1043 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1044 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1045 else
1046 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1047}
1048
1049static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1050 struct link_qual *qual, u8 vgc_level)
1051{
1052 if (qual->vgc_level != vgc_level) {
1053 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1054 qual->vgc_level = vgc_level;
1055 qual->vgc_level_reg = vgc_level;
1056 }
1057}
1058
1059static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1060 struct link_qual *qual)
1061{
1062 rt2800usb_set_vgc(rt2x00dev, qual,
1063 rt2800usb_get_default_vgc(rt2x00dev));
1064}
1065
1066static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1067 struct link_qual *qual, const u32 count)
1068{
1069 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1070 return;
1071
1072 /*
1073 * When RSSI is better then -80 increase VGC level with 0x10
1074 */
1075 rt2800usb_set_vgc(rt2x00dev, qual,
1076 rt2800usb_get_default_vgc(rt2x00dev) +
1077 ((qual->rssi > -80) * 0x10));
1078}
1079
1080/*
1081 * Firmware functions
1082 */
1083static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1084{
1085 return FIRMWARE_RT2870;
1086}
1087
1088static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1089{
1090 u16 fw_crc;
1091 u16 crc;
1092
1093 /*
1094 * The last 2 bytes in the firmware array are the crc checksum itself,
1095 * this means that we should never pass those 2 bytes to the crc
1096 * algorithm.
1097 */
1098 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1099
1100 /*
1101 * Use the crc ccitt algorithm.
1102 * This will return the same value as the legacy driver which
1103 * used bit ordering reversion on the both the firmware bytes
1104 * before input input as well as on the final output.
1105 * Obviously using crc ccitt directly is much more efficient.
1106 */
1107 crc = crc_ccitt(~0, data, len - 2);
1108
1109 /*
1110 * There is a small difference between the crc-itu-t + bitrev and
1111 * the crc-ccitt crc calculation. In the latter method the 2 bytes
1112 * will be swapped, use swab16 to convert the crc to the correct
1113 * value.
1114 */
1115 crc = swab16(crc);
1116
1117 return fw_crc == crc;
1118}
1119
1120static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1121 const u8 *data, const size_t len)
1122{
1123 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1124 size_t offset = 0;
1125
1126 /*
1127 * Firmware files:
1128 * There are 2 variations of the rt2870 firmware.
1129 * a) size: 4kb
1130 * b) size: 8kb
1131 * Note that (b) contains 2 seperate firmware blobs of 4k
1132 * within the file. The first blob is the same firmware as (a),
1133 * but the second blob is for the additional chipsets.
1134 */
1135 if (len != 4096 && len != 8192)
1136 return FW_BAD_LENGTH;
1137
1138 /*
1139 * Check if we need the upper 4kb firmware data or not.
1140 */
1141 if ((len == 4096) &&
1142 (chipset != 0x2860) &&
1143 (chipset != 0x2872) &&
1144 (chipset != 0x3070))
1145 return FW_BAD_VERSION;
1146
1147 /*
1148 * 8kb firmware files must be checked as if it were
1149 * 2 seperate firmware files.
1150 */
1151 while (offset < len) {
1152 if (!rt2800usb_check_crc(data + offset, 4096))
1153 return FW_BAD_CRC;
1154
1155 offset += 4096;
1156 }
1157
1158 return FW_OK;
1159}
1160
1161static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1162 const u8 *data, const size_t len)
1163{
1164 unsigned int i;
1165 int status;
1166 u32 reg;
1167 u32 offset;
1168 u32 length;
1169 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1170
1171 /*
1172 * Check which section of the firmware we need.
1173 */
1174 if ((chipset == 0x2860) || (chipset == 0x2872) || (chipset == 0x3070)) {
1175 offset = 0;
1176 length = 4096;
1177 } else {
1178 offset = 4096;
1179 length = 4096;
1180 }
1181
1182 /*
1183 * Wait for stable hardware.
1184 */
1185 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1186 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1187 if (reg && reg != ~0)
1188 break;
1189 msleep(1);
1190 }
1191
1192 if (i == REGISTER_BUSY_COUNT) {
1193 ERROR(rt2x00dev, "Unstable hardware.\n");
1194 return -EBUSY;
1195 }
1196
1197 /*
1198 * Write firmware to device.
1199 */
1200 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1201 USB_VENDOR_REQUEST_OUT,
1202 FIRMWARE_IMAGE_BASE,
1203 data + offset, length,
1204 REGISTER_TIMEOUT32(length));
1205
1206 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1207 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1208
1209 /*
1210 * Send firmware request to device to load firmware,
1211 * we need to specify a long timeout time.
1212 */
1213 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1214 0, USB_MODE_FIRMWARE,
1215 REGISTER_TIMEOUT_FIRMWARE);
1216 if (status < 0) {
1217 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1218 return status;
1219 }
1220
1221 /*
1222 * Wait for device to stabilize.
1223 */
1224 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1225 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1226 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1227 break;
1228 msleep(1);
1229 }
1230
1231 if (i == REGISTER_BUSY_COUNT) {
1232 ERROR(rt2x00dev, "PBF system register not ready.\n");
1233 return -EBUSY;
1234 }
1235
1236 /*
1237 * Initialize firmware.
1238 */
1239 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1240 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1241 msleep(1);
1242
1243 return 0;
1244}
1245
1246/*
1247 * Initialization functions.
1248 */
1249static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1250{
1251 u32 reg;
1252 unsigned int i;
1253
1254 /*
1255 * Wait untill BBP and RF are ready.
1256 */
1257 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1258 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1259 if (reg && reg != ~0)
1260 break;
1261 msleep(1);
1262 }
1263
1264 if (i == REGISTER_BUSY_COUNT) {
1265 ERROR(rt2x00dev, "Unstable hardware.\n");
1266 return -EBUSY;
1267 }
1268
1269 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1270 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1271
1272 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1273 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1274 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1275 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1276
1277 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1278
1279 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1280 USB_MODE_RESET, REGISTER_TIMEOUT);
1281
1282 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1283
1284 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1285 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1286 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1287 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1288 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1289 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1290
1291 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1292 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1293 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1294 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1295 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1296 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1297
1298 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1299 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1300
1301 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1302
1303 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1304 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1305 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1306 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1307 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1308 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1309 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1310 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1311
1312 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1313 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1314 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1315 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1316 } else {
1317 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1318 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1319 }
1320
1321 rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1322 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1323 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1324 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1325 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1326 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1327 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1328 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1329 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1330 rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1331
1332 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1333 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1334 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1335 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1336
1337 rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1338 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1339 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1340 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1341 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1342 else
1343 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1344 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1345 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1346 rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1347
1348 rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1349
1350 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1351 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1352 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1353 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1354 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1355 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1356 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1357
1358 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1359 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1360 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1361 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1362 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1363 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1364 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1365 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1366 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1367 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1368 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1369
1370 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1371 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1372 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1373 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1374 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1375 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1376 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1377 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1378 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1379 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1380 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1381
1382 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1383 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1384 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1385 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1386 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1387 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1388 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1389 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1390 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1391 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1392 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1393
1394 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1395 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1396 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1397 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1398 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1399 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1400 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1401 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1402 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1403 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1404 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1405
1406 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1407 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1408 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1409 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1410 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1411 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1412 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1413 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1414 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1415 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1416 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1417
1418 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1419 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1420 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1421 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1422 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1423 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1424 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1425 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1426 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1427 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1428 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1429
1430 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1431
1432 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1434 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1435 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1436 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1437 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1438 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1439 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1440 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1441 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1442 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1443
1444 rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1445 rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1446
1447 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1448 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1449 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1450 IEEE80211_MAX_RTS_THRESHOLD);
1451 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1452 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1453
1454 rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1455 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1456
1457 /*
1458 * ASIC will keep garbage value after boot, clear encryption keys.
1459 */
1460 for (i = 0; i < 256; i++) {
1461 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1462 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1463 wcid, sizeof(wcid));
1464
1465 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1466 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1467 }
1468
1469 for (i = 0; i < 16; i++)
1470 rt2x00usb_register_write(rt2x00dev,
1471 SHARED_KEY_MODE_ENTRY(i), 0);
1472
1473 /*
1474 * Clear all beacons
1475 * For the Beacon base registers we only need to clear
1476 * the first byte since that byte contains the VALID and OWNER
1477 * bits which (when set to 0) will invalidate the entire beacon.
1478 */
1479 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1480 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1481 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1482 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1483 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1484 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1485 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1486 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1487
1488 rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1489 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1490 rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1491
1492 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1493 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1494 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1495 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1496 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1497 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1498 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1499 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1500 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1501 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1502
1503 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1504 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1505 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1506 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1507 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1508 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1509 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1510 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1511 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1512 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1513
1514 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1515 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1516 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1517 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1518 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1519 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1520 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1521 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1522 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1523 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1524
1525 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1526 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1527 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1528 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1529 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1530 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1531
1532 /*
1533 * We must clear the error counters.
1534 * These registers are cleared on read,
1535 * so we may pass a useless variable to store the value.
1536 */
1537 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1538 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1539 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1540 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1541 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1542 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1543
1544 return 0;
1545}
1546
1547static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1548{
1549 unsigned int i;
1550 u32 reg;
1551
1552 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1553 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1554 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1555 return 0;
1556
1557 udelay(REGISTER_BUSY_DELAY);
1558 }
1559
1560 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1561 return -EACCES;
1562}
1563
1564static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1565{
1566 unsigned int i;
1567 u8 value;
1568
1569 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1570 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1571 if ((value != 0xff) && (value != 0x00))
1572 return 0;
1573 udelay(REGISTER_BUSY_DELAY);
1574 }
1575
1576 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1577 return -EACCES;
1578}
1579
1580static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1581{
1582 unsigned int i;
1583 u16 eeprom;
1584 u8 reg_id;
1585 u8 value;
1586
1587 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1588 rt2800usb_wait_bbp_ready(rt2x00dev)))
1589 return -EACCES;
1590
1591 rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1592 rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1593 rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1594 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1595 rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1596 rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1597 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1598 rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1599 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1600 rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1601 rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1602 rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1603 rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1604 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1605
1606 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1607 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1608 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1609 }
1610
1611 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1612 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1613 }
1614
1615 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1616 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1617 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1618 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1619 }
1620
1621 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1622 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1623
1624 if (eeprom != 0xffff && eeprom != 0x0000) {
1625 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1626 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1627 rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1628 }
1629 }
1630
1631 return 0;
1632}
1633
1634static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1635 bool bw40, u8 rfcsr24, u8 filter_target)
1636{
1637 unsigned int i;
1638 u8 bbp;
1639 u8 rfcsr;
1640 u8 passband;
1641 u8 stopband;
1642 u8 overtuned = 0;
1643
1644 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1645
1646 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1647 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1648 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1649
1650 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1651 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1652 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1653
1654 /*
1655 * Set power & frequency of passband test tone
1656 */
1657 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1658
1659 for (i = 0; i < 100; i++) {
1660 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1661 msleep(1);
1662
1663 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1664 if (passband)
1665 break;
1666 }
1667
1668 /*
1669 * Set power & frequency of stopband test tone
1670 */
1671 rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1672
1673 for (i = 0; i < 100; i++) {
1674 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1675 msleep(1);
1676
1677 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1678
1679 if ((passband - stopband) <= filter_target) {
1680 rfcsr24++;
1681 overtuned += ((passband - stopband) == filter_target);
1682 } else
1683 break;
1684
1685 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1686 }
1687
1688 rfcsr24 -= !!overtuned;
1689
1690 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1691 return rfcsr24;
1692}
1693
1694static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1695{
1696 u8 rfcsr;
1697 u8 bbp;
1698
1699 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1700 return 0;
1701
1702 /*
1703 * Init RF calibration.
1704 */
1705 rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1706 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1707 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1708 msleep(1);
1709 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1710 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1711
1712 rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1713 rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1714 rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1715 rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1716 rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1717 rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1718 rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1719 rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1720 rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1721 rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1722 rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1723 rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1724 rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1725 rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1726 rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1727 rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1728 rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1729 rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1730 rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1731 rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1732
1733 /*
1734 * Set RX Filter calibration for 20MHz and 40MHz
1735 */
1736 rt2x00dev->calibration[0] =
1737 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1738 rt2x00dev->calibration[1] =
1739 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1740
1741 /*
1742 * Set back to initial state
1743 */
1744 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1745
1746 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1747 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1748 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1749
1750 /*
1751 * set BBP back to BW20
1752 */
1753 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1754 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1755 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1756
1757 return 0;
1758}
1759
1760/*
1761 * Device state switch handlers.
1762 */
1763static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1764 enum dev_state state)
1765{
1766 u32 reg;
1767
1768 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1769 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1770 (state == STATE_RADIO_RX_ON) ||
1771 (state == STATE_RADIO_RX_ON_LINK));
1772 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1773}
1774
1775static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1776{
1777 unsigned int i;
1778 u32 reg;
1779
1780 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1781 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1782 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1783 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1784 return 0;
1785
1786 msleep(1);
1787 }
1788
1789 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1790 return -EACCES;
1791}
1792
1793static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1794{
1795 u32 reg;
1796 u16 word;
1797
1798 /*
1799 * Initialize all registers.
1800 */
1801 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1802 rt2800usb_init_registers(rt2x00dev) ||
1803 rt2800usb_init_bbp(rt2x00dev) ||
1804 rt2800usb_init_rfcsr(rt2x00dev)))
1805 return -EIO;
1806
1807 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1808 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1809 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1810
1811 udelay(50);
1812
1813 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1814 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1815 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1816 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1817 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1818
1819
1820 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1821 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1822 /* Don't use bulk in aggregation when working with USB 1.1 */
1823 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1824 (rt2x00dev->rx->usb_maxpacket == 512));
1825 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1826 /* FIXME: Calculate this value based on Aggregation defines */
1827 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT, 21);
1828 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1829 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1830 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1831
1832 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1833 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1834 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1835 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1836
1837 /*
1838 * Send signal to firmware during boot time.
1839 */
1840 rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1841
1842 /*
1843 * Initialize LED control
1844 */
1845 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1846 rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1847 word & 0xff, (word >> 8) & 0xff);
1848
1849 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1850 rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1851 word & 0xff, (word >> 8) & 0xff);
1852
1853 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1854 rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1855 word & 0xff, (word >> 8) & 0xff);
1856
1857 return 0;
1858}
1859
1860static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1861{
1862 u32 reg;
1863
1864 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1865 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1866 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1867 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1868
1869 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1870 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1871 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1872
1873 /* Wait for DMA, ignore error */
1874 rt2800usb_wait_wpdma_ready(rt2x00dev);
1875
1876 rt2x00usb_disable_radio(rt2x00dev);
1877}
1878
1879static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1880 enum dev_state state)
1881{
1882 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1883
1884 if (state == STATE_AWAKE)
1885 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1886 else
1887 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1888
1889 return 0;
1890}
1891
1892static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1893 enum dev_state state)
1894{
1895 int retval = 0;
1896
1897 switch (state) {
1898 case STATE_RADIO_ON:
1899 /*
1900 * Before the radio can be enabled, the device first has
1901 * to be woken up. After that it needs a bit of time
1902 * to be fully awake and the radio can be enabled.
1903 */
1904 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1905 msleep(1);
1906 retval = rt2800usb_enable_radio(rt2x00dev);
1907 break;
1908 case STATE_RADIO_OFF:
1909 /*
1910 * After the radio has been disablee, the device should
1911 * be put to sleep for powersaving.
1912 */
1913 rt2800usb_disable_radio(rt2x00dev);
1914 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1915 break;
1916 case STATE_RADIO_RX_ON:
1917 case STATE_RADIO_RX_ON_LINK:
1918 case STATE_RADIO_RX_OFF:
1919 case STATE_RADIO_RX_OFF_LINK:
1920 rt2800usb_toggle_rx(rt2x00dev, state);
1921 break;
1922 case STATE_RADIO_IRQ_ON:
1923 case STATE_RADIO_IRQ_OFF:
1924 /* No support, but no error either */
1925 break;
1926 case STATE_DEEP_SLEEP:
1927 case STATE_SLEEP:
1928 case STATE_STANDBY:
1929 case STATE_AWAKE:
1930 retval = rt2800usb_set_state(rt2x00dev, state);
1931 break;
1932 default:
1933 retval = -ENOTSUPP;
1934 break;
1935 }
1936
1937 if (unlikely(retval))
1938 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1939 state, retval);
1940
1941 return retval;
1942}
1943
1944/*
1945 * TX descriptor initialization
1946 */
1947static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1948 struct sk_buff *skb,
1949 struct txentry_desc *txdesc)
1950{
1951 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1952 __le32 *txi = skbdesc->desc;
1953 __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1954 u32 word;
1955
1956 /*
1957 * Initialize TX Info descriptor
1958 */
1959 rt2x00_desc_read(txwi, 0, &word);
1960 rt2x00_set_field32(&word, TXWI_W0_FRAG,
1961 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1962 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1963 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1964 rt2x00_set_field32(&word, TXWI_W0_TS,
1965 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1966 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1967 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1968 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1969 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1970 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1971 rt2x00_set_field32(&word, TXWI_W0_BW,
1972 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1973 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1974 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1975 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1976 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1977 rt2x00_desc_write(txwi, 0, word);
1978
1979 rt2x00_desc_read(txwi, 1, &word);
1980 rt2x00_set_field32(&word, TXWI_W1_ACK,
1981 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1982 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1983 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1984 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1985 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1986 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1987 txdesc->key_idx : 0xff);
1988 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
1989 skb->len - txdesc->l2pad);
1990 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1991 skbdesc->entry->entry_idx);
1992 rt2x00_desc_write(txwi, 1, word);
1993
1994 /*
1995 * Always write 0 to IV/EIV fields, hardware will insert the IV
1996 * from the IVEIV register when TXINFO_W0_WIV is set to 0.
1997 * When TXINFO_W0_WIV is set to 1 it will use the IV data
1998 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
1999 * crypto entry in the registers should be used to encrypt the frame.
2000 */
2001 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2002 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2003
2004 /*
2005 * Initialize TX descriptor
2006 */
2007 rt2x00_desc_read(txi, 0, &word);
2008 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2009 skb->len + TXWI_DESC_SIZE);
2010 rt2x00_set_field32(&word, TXINFO_W0_WIV,
2011 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2012 rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2013 rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2014 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2015 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2016 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2017 rt2x00_desc_write(txi, 0, word);
2018}
2019
2020/*
2021 * TX data initialization
2022 */
2023static void rt2800usb_write_beacon(struct queue_entry *entry)
2024{
2025 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2026 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2027 unsigned int beacon_base;
2028 u32 reg;
2029
2030 /*
2031 * Add the descriptor in front of the skb.
2032 */
2033 skb_push(entry->skb, entry->queue->desc_size);
2034 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2035 skbdesc->desc = entry->skb->data;
2036
2037 /*
2038 * Disable beaconing while we are reloading the beacon data,
2039 * otherwise we might be sending out invalid data.
2040 */
2041 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2042 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2043 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2044 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2045 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2046
2047 /*
2048 * Write entire beacon with descriptor to register.
2049 */
2050 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2051 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2052 USB_VENDOR_REQUEST_OUT, beacon_base,
2053 entry->skb->data, entry->skb->len,
2054 REGISTER_TIMEOUT32(entry->skb->len));
2055
2056 /*
2057 * Clean up the beacon skb.
2058 */
2059 dev_kfree_skb(entry->skb);
2060 entry->skb = NULL;
2061}
2062
2063static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2064{
2065 int length;
2066
2067 /*
2068 * The length _must_ include 4 bytes padding,
2069 * it should always be multiple of 4,
2070 * but it must _not_ be a multiple of the USB packet size.
2071 */
2072 length = roundup(entry->skb->len + 4, 4);
2073 length += (4 * !(length % entry->queue->usb_maxpacket));
2074
2075 return length;
2076}
2077
2078static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2079 const enum data_queue_qid queue)
2080{
2081 u32 reg;
2082
2083 if (queue != QID_BEACON) {
2084 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2085 return;
2086 }
2087
2088 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2089 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2090 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2091 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2092 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2093 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2094 }
2095}
2096
2097/*
2098 * RX control handlers
2099 */
2100static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2101 struct rxdone_entry_desc *rxdesc)
2102{
2103 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2104 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2105 __le32 *rxd = (__le32 *)entry->skb->data;
2106 __le32 *rxwi;
2107 u32 rxd0;
2108 u32 rxwi0;
2109 u32 rxwi1;
2110 u32 rxwi2;
2111 u32 rxwi3;
2112
2113 /*
2114 * Copy descriptor to the skbdesc->desc buffer, making it safe from
2115 * moving of frame data in rt2x00usb.
2116 */
2117 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2118 rxd = (__le32 *)skbdesc->desc;
2119 rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2120
2121 /*
2122 * It is now safe to read the descriptor on all architectures.
2123 */
2124 rt2x00_desc_read(rxd, 0, &rxd0);
2125 rt2x00_desc_read(rxwi, 0, &rxwi0);
2126 rt2x00_desc_read(rxwi, 1, &rxwi1);
2127 rt2x00_desc_read(rxwi, 2, &rxwi2);
2128 rt2x00_desc_read(rxwi, 3, &rxwi3);
2129
2130 if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2131 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2132
2133 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2134 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2135 rxdesc->cipher_status =
2136 rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2137 }
2138
2139 if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2140 /*
2141 * Hardware has stripped IV/EIV data from 802.11 frame during
2142 * decryption. Unfortunately the descriptor doesn't contain
2143 * any fields with the EIV/IV data either, so they can't
2144 * be restored by rt2x00lib.
2145 */
2146 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2147
2148 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2149 rxdesc->flags |= RX_FLAG_DECRYPTED;
2150 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2151 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2152 }
2153
2154 if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2155 rxdesc->dev_flags |= RXDONE_MY_BSS;
2156
2157 if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD))
2158 rxdesc->dev_flags |= RXDONE_L2PAD;
2159
2160 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2161 rxdesc->flags |= RX_FLAG_SHORT_GI;
2162
2163 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2164 rxdesc->flags |= RX_FLAG_40MHZ;
2165
2166 /*
2167 * Detect RX rate, always use MCS as signal type.
2168 */
2169 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2170 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2171 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2172
2173 /*
2174 * Mask of 0x8 bit to remove the short preamble flag.
2175 */
2176 if (rxdesc->rate_mode == RATE_MODE_CCK)
2177 rxdesc->signal &= ~0x8;
2178
2179 rxdesc->rssi =
2180 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2181 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2182
2183 rxdesc->noise =
2184 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2185 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2186
2187 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2188
2189 /*
2190 * Remove RXWI descriptor from start of buffer.
2191 */
2192 skb_pull(entry->skb, skbdesc->desc_len);
2193 skb_trim(entry->skb, rxdesc->size);
2194}
2195
2196/*
2197 * Device probe functions.
2198 */
2199static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2200{
2201 u16 word;
2202 u8 *mac;
2203 u8 default_lna_gain;
2204
2205 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2206
2207 /*
2208 * Start validation of the data that has been read.
2209 */
2210 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2211 if (!is_valid_ether_addr(mac)) {
2212 DECLARE_MAC_BUF(macbuf);
2213
2214 random_ether_addr(mac);
2215 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2216 }
2217
2218 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2219 if (word == 0xffff) {
2220 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2221 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2222 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2223 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2224 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2225 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2226 /*
2227 * There is a max of 2 RX streams for RT2870 series
2228 */
2229 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2230 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2231 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2232 }
2233
2234 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2235 if (word == 0xffff) {
2236 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2237 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2238 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2239 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2240 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2241 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2242 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2243 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2244 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2245 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2246 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2247 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2248 }
2249
2250 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2251 if ((word & 0x00ff) == 0x00ff) {
2252 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2253 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2254 LED_MODE_TXRX_ACTIVITY);
2255 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2256 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2257 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2258 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2259 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2260 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2261 }
2262
2263 /*
2264 * During the LNA validation we are going to use
2265 * lna0 as correct value. Note that EEPROM_LNA
2266 * is never validated.
2267 */
2268 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2269 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2270
2271 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2272 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2273 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2274 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2275 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2276 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2277
2278 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2279 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2280 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2281 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2282 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2283 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2284 default_lna_gain);
2285 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2286
2287 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2288 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2289 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2290 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2291 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2292 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2293
2294 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2295 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2296 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2297 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2298 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2299 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2300 default_lna_gain);
2301 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2302
2303 return 0;
2304}
2305
2306static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2307{
2308 u32 reg;
2309 u16 value;
2310 u16 eeprom;
2311
2312 /*
2313 * Read EEPROM word for configuration.
2314 */
2315 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2316
2317 /*
2318 * Identify RF chipset.
2319 */
2320 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2321 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2322 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2323
2324 /*
2325 * The check for rt2860 is not a typo, some rt2870 hardware
2326 * identifies itself as rt2860 in the CSR register.
2327 */
2328 if ((rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2860) &&
2329 (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x2870) &&
2330 (rt2x00_get_field32(reg, MAC_CSR0_ASIC_VER) != 0x3070)) {
2331 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2332 return -ENODEV;
2333 }
2334
2335 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2336 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2337 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2338 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2339 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2340 !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2341 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2342 return -ENODEV;
2343 }
2344
2345 /*
2346 * Identify default antenna configuration.
2347 */
2348 rt2x00dev->default_ant.tx =
2349 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2350 rt2x00dev->default_ant.rx =
2351 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2352
2353 /*
2354 * Read frequency offset and RF programming sequence.
2355 */
2356 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2357 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2358
2359 /*
2360 * Read external LNA informations.
2361 */
2362 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2363
2364 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2365 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2366 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2367 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2368
2369 /*
2370 * Detect if this device has an hardware controlled radio.
2371 */
2372#ifdef CONFIG_RT2X00_LIB_RFKILL
2373 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2374 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2375#endif /* CONFIG_RT2X00_LIB_RFKILL */
2376
2377 /*
2378 * Store led settings, for correct led behaviour.
2379 */
2380#ifdef CONFIG_RT2X00_LIB_LEDS
2381 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2382 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2383 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2384
2385 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2386 &rt2x00dev->led_mcu_reg);
2387#endif /* CONFIG_RT2X00_LIB_LEDS */
2388
2389 return 0;
2390}
2391
2392/*
2393 * RF value list for rt2870
2394 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2395 */
2396static const struct rf_channel rf_vals[] = {
2397 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2398 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2399 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2400 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2401 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2402 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2403 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2404 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2405 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2406 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2407 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2408 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2409 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2410 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2411
2412 /* 802.11 UNI / HyperLan 2 */
2413 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2414 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2415 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2416 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2417 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2418 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2419 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2420 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2421 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2422 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2423 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2424 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2425
2426 /* 802.11 HyperLan 2 */
2427 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2428 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2429 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2430 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2431 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2432 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2433 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2434 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2435 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2436 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2437 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2438 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2439 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2440 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2441 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2442 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2443
2444 /* 802.11 UNII */
2445 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2446 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2447 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2448 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2449 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2450 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2451 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2452 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2453 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2454 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2455 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2456
2457 /* 802.11 Japan */
2458 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2459 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2460 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2461 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2462 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2463 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2464 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2465};
2466
2467/*
2468 * RF value list for rt3070
2469 * Supports: 2.4 GHz
2470 */
2471static const struct rf_channel rf_vals_3070[] = {
2472 {1, 241, 2, 2 },
2473 {2, 241, 2, 7 },
2474 {3, 242, 2, 2 },
2475 {4, 242, 2, 7 },
2476 {5, 243, 2, 2 },
2477 {6, 243, 2, 7 },
2478 {7, 244, 2, 2 },
2479 {8, 244, 2, 7 },
2480 {9, 245, 2, 2 },
2481 {10, 245, 2, 7 },
2482 {11, 246, 2, 2 },
2483 {12, 246, 2, 7 },
2484 {13, 247, 2, 2 },
2485 {14, 248, 2, 4 },
2486};
2487
2488static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2489{
2490 struct hw_mode_spec *spec = &rt2x00dev->spec;
2491 struct channel_info *info;
2492 char *tx_power1;
2493 char *tx_power2;
2494 unsigned int i;
2495 u16 eeprom;
2496
2497 /*
2498 * Initialize all hw fields.
2499 */
2500 rt2x00dev->hw->flags =
2501 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2502 IEEE80211_HW_SIGNAL_DBM |
2503 IEEE80211_HW_SUPPORTS_PS |
2504 IEEE80211_HW_PS_NULLFUNC_STACK;
2505 rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2506
2507 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2508 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2509 rt2x00_eeprom_addr(rt2x00dev,
2510 EEPROM_MAC_ADDR_0));
2511
2512 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2513
2514 /*
2515 * Initialize HT information.
2516 */
2517 spec->ht.ht_supported = true;
2518 spec->ht.cap =
2519 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2520 IEEE80211_HT_CAP_GRN_FLD |
2521 IEEE80211_HT_CAP_SGI_20 |
2522 IEEE80211_HT_CAP_SGI_40 |
2523 IEEE80211_HT_CAP_TX_STBC |
2524 IEEE80211_HT_CAP_RX_STBC |
2525 IEEE80211_HT_CAP_PSMP_SUPPORT;
2526 spec->ht.ampdu_factor = 3;
2527 spec->ht.ampdu_density = 4;
2528 spec->ht.mcs.tx_params =
2529 IEEE80211_HT_MCS_TX_DEFINED |
2530 IEEE80211_HT_MCS_TX_RX_DIFF |
2531 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2532 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2533
2534 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2535 case 3:
2536 spec->ht.mcs.rx_mask[2] = 0xff;
2537 case 2:
2538 spec->ht.mcs.rx_mask[1] = 0xff;
2539 case 1:
2540 spec->ht.mcs.rx_mask[0] = 0xff;
2541 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2542 break;
2543 }
2544
2545 /*
2546 * Initialize hw_mode information.
2547 */
2548 spec->supported_bands = SUPPORT_BAND_2GHZ;
2549 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2550
2551 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2552 rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2553 spec->num_channels = 14;
2554 spec->channels = rf_vals;
2555 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2556 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2557 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2558 spec->num_channels = ARRAY_SIZE(rf_vals);
2559 spec->channels = rf_vals;
2560 } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2561 rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2562 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2563 spec->channels = rf_vals_3070;
2564 }
2565
2566 /*
2567 * Create channel information array
2568 */
2569 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2570 if (!info)
2571 return -ENOMEM;
2572
2573 spec->channels_info = info;
2574
2575 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2576 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2577
2578 for (i = 0; i < 14; i++) {
2579 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2580 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2581 }
2582
2583 if (spec->num_channels > 14) {
2584 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2585 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2586
2587 for (i = 14; i < spec->num_channels; i++) {
2588 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2589 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2590 }
2591 }
2592
2593 return 0;
2594}
2595
2596static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2597{
2598 int retval;
2599
2600 /*
2601 * Allocate eeprom data.
2602 */
2603 retval = rt2800usb_validate_eeprom(rt2x00dev);
2604 if (retval)
2605 return retval;
2606
2607 retval = rt2800usb_init_eeprom(rt2x00dev);
2608 if (retval)
2609 return retval;
2610
2611 /*
2612 * Initialize hw specifications.
2613 */
2614 retval = rt2800usb_probe_hw_mode(rt2x00dev);
2615 if (retval)
2616 return retval;
2617
2618 /*
2619 * This device requires firmware.
2620 */
2621 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2622 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2623 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2624 if (!modparam_nohwcrypt)
2625 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2626
2627 /*
2628 * Set the rssi offset.
2629 */
2630 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2631
2632 return 0;
2633}
2634
2635/*
2636 * IEEE80211 stack callback functions.
2637 */
2638static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2639 u32 *iv32, u16 *iv16)
2640{
2641 struct rt2x00_dev *rt2x00dev = hw->priv;
2642 struct mac_iveiv_entry iveiv_entry;
2643 u32 offset;
2644
2645 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2646 rt2x00usb_register_multiread(rt2x00dev, offset,
2647 &iveiv_entry, sizeof(iveiv_entry));
2648
2649 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2650 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2651}
2652
2653static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2654{
2655 struct rt2x00_dev *rt2x00dev = hw->priv;
2656 u32 reg;
2657 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2658
2659 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2660 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2661 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2662
2663 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2664 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2665 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2666
2667 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2668 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2669 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2670
2671 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2672 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2673 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2674
2675 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2676 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2677 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2678
2679 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2680 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2681 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2682
2683 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2684 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2685 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2686
2687 return 0;
2688}
2689
2690static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2691 const struct ieee80211_tx_queue_params *params)
2692{
2693 struct rt2x00_dev *rt2x00dev = hw->priv;
2694 struct data_queue *queue;
2695 struct rt2x00_field32 field;
2696 int retval;
2697 u32 reg;
2698 u32 offset;
2699
2700 /*
2701 * First pass the configuration through rt2x00lib, that will
2702 * update the queue settings and validate the input. After that
2703 * we are free to update the registers based on the value
2704 * in the queue parameter.
2705 */
2706 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2707 if (retval)
2708 return retval;
2709
2710 /*
2711 * We only need to perform additional register initialization
2712 * for WMM queues/
2713 */
2714 if (queue_idx >= 4)
2715 return 0;
2716
2717 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2718
2719 /* Update WMM TXOP register */
2720 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2721 field.bit_offset = (queue_idx & 1) * 16;
2722 field.bit_mask = 0xffff << field.bit_offset;
2723
2724 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2725 rt2x00_set_field32(&reg, field, queue->txop);
2726 rt2x00usb_register_write(rt2x00dev, offset, reg);
2727
2728 /* Update WMM registers */
2729 field.bit_offset = queue_idx * 4;
2730 field.bit_mask = 0xf << field.bit_offset;
2731
2732 rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2733 rt2x00_set_field32(&reg, field, queue->aifs);
2734 rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2735
2736 rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2737 rt2x00_set_field32(&reg, field, queue->cw_min);
2738 rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2739
2740 rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2741 rt2x00_set_field32(&reg, field, queue->cw_max);
2742 rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2743
2744 /* Update EDCA registers */
2745 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2746
2747 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2748 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2749 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2750 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2751 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2752 rt2x00usb_register_write(rt2x00dev, offset, reg);
2753
2754 return 0;
2755}
2756
2757static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2758{
2759 struct rt2x00_dev *rt2x00dev = hw->priv;
2760 u64 tsf;
2761 u32 reg;
2762
2763 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2764 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2765 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2766 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2767
2768 return tsf;
2769}
2770
2771static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2772 .tx = rt2x00mac_tx,
2773 .start = rt2x00mac_start,
2774 .stop = rt2x00mac_stop,
2775 .add_interface = rt2x00mac_add_interface,
2776 .remove_interface = rt2x00mac_remove_interface,
2777 .config = rt2x00mac_config,
2778 .configure_filter = rt2x00mac_configure_filter,
2779 .set_key = rt2x00mac_set_key,
2780 .get_stats = rt2x00mac_get_stats,
2781 .get_tkip_seq = rt2800usb_get_tkip_seq,
2782 .set_rts_threshold = rt2800usb_set_rts_threshold,
2783 .bss_info_changed = rt2x00mac_bss_info_changed,
2784 .conf_tx = rt2800usb_conf_tx,
2785 .get_tx_stats = rt2x00mac_get_tx_stats,
2786 .get_tsf = rt2800usb_get_tsf,
2787};
2788
2789static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2790 .probe_hw = rt2800usb_probe_hw,
2791 .get_firmware_name = rt2800usb_get_firmware_name,
2792 .check_firmware = rt2800usb_check_firmware,
2793 .load_firmware = rt2800usb_load_firmware,
2794 .initialize = rt2x00usb_initialize,
2795 .uninitialize = rt2x00usb_uninitialize,
2796 .clear_entry = rt2x00usb_clear_entry,
2797 .set_device_state = rt2800usb_set_device_state,
2798 .rfkill_poll = rt2800usb_rfkill_poll,
2799 .link_stats = rt2800usb_link_stats,
2800 .reset_tuner = rt2800usb_reset_tuner,
2801 .link_tuner = rt2800usb_link_tuner,
2802 .write_tx_desc = rt2800usb_write_tx_desc,
2803 .write_tx_data = rt2x00usb_write_tx_data,
2804 .write_beacon = rt2800usb_write_beacon,
2805 .get_tx_data_len = rt2800usb_get_tx_data_len,
2806 .kick_tx_queue = rt2800usb_kick_tx_queue,
2807 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2808 .fill_rxdone = rt2800usb_fill_rxdone,
2809 .config_shared_key = rt2800usb_config_shared_key,
2810 .config_pairwise_key = rt2800usb_config_pairwise_key,
2811 .config_filter = rt2800usb_config_filter,
2812 .config_intf = rt2800usb_config_intf,
2813 .config_erp = rt2800usb_config_erp,
2814 .config_ant = rt2800usb_config_ant,
2815 .config = rt2800usb_config,
2816};
2817
2818static const struct data_queue_desc rt2800usb_queue_rx = {
2819 .entry_num = RX_ENTRIES,
2820 .data_size = AGGREGATION_SIZE,
2821 .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2822 .priv_size = sizeof(struct queue_entry_priv_usb),
2823};
2824
2825static const struct data_queue_desc rt2800usb_queue_tx = {
2826 .entry_num = TX_ENTRIES,
2827 .data_size = AGGREGATION_SIZE,
2828 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2829 .priv_size = sizeof(struct queue_entry_priv_usb),
2830};
2831
2832static const struct data_queue_desc rt2800usb_queue_bcn = {
2833 .entry_num = 8 * BEACON_ENTRIES,
2834 .data_size = MGMT_FRAME_SIZE,
2835 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2836 .priv_size = sizeof(struct queue_entry_priv_usb),
2837};
2838
2839static const struct rt2x00_ops rt2800usb_ops = {
2840 .name = KBUILD_MODNAME,
2841 .max_sta_intf = 1,
2842 .max_ap_intf = 8,
2843 .eeprom_size = EEPROM_SIZE,
2844 .rf_size = RF_SIZE,
2845 .tx_queues = NUM_TX_QUEUES,
2846 .rx = &rt2800usb_queue_rx,
2847 .tx = &rt2800usb_queue_tx,
2848 .bcn = &rt2800usb_queue_bcn,
2849 .lib = &rt2800usb_rt2x00_ops,
2850 .hw = &rt2800usb_mac80211_ops,
2851#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2852 .debugfs = &rt2800usb_rt2x00debug,
2853#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2854};
2855
2856/*
2857 * rt2800usb module information.
2858 */
2859static struct usb_device_id rt2800usb_device_table[] = {
2860 /* ??? */
2861 { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
2862 /* Abocom */
2863 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2864 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2865 { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2866 { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2867 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2868 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2869 /* AirTies */
2870 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2871 /* Amigo */
2872 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2873 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2874 /* Amit */
2875 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2876 /* ASUS */
2877 { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2878 { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2879 { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2880 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2881 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2882 /* AzureWave */
2883 { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2884 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2885 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2886 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2887 /* Belkin */
2888 { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2889 { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2890 { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2891 /* Buffalo */
2892 { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2893 { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2894 /* Conceptronic */
2895 { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2896 { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2897 { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2898 { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2899 { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2900 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2901 { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2902 { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2903 { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 /* Corega */
2906 { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2907 { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2910 { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 /* D-Link */
2912 { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2913 { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2915 { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2916 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2917 /* Edimax */
2918 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2919 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2920 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 /* EnGenius */
2922 { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2923 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2926 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2927 { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 /* Gemtek */
2929 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2930 /* Gigabyte */
2931 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2933 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2934 /* Hawking */
2935 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2936 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2939 /* LevelOne */
2940 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2941 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2942 /* Linksys */
2943 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2945 /* Logitec */
2946 { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2948 { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2949 /* Motorola */
2950 { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2951 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 /* Ovislink */
2953 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2954 /* Pegatron */
2955 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2957 /* Philips */
2958 { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2959 /* Planex */
2960 { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2961 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2962 { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 /* Qcom */
2964 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2965 /* Quanta */
2966 { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2967 /* Ralink */
2968 { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2969 { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2971 { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2972 { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2973 { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2974 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2975 { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
2976 /* Samsung */
2977 { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
2978 /* Siemens */
2979 { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
2980 /* Sitecom */
2981 { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
2982 { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
2983 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
2984 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
2985 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
2986 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
2987 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2988 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
2989 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
2990 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2991 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
2992 /* SMC */
2993 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
2994 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
2995 { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
2997 { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3001 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3002 /* Sparklan */
3003 { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3004 /* U-Media*/
3005 { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3006 /* ZCOM */
3007 { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3008 { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 /* Zinwell */
3010 { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 /* Zyxel */
3013 { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 { 0, }
3016};
3017
3018MODULE_AUTHOR(DRV_PROJECT);
3019MODULE_VERSION(DRV_VERSION);
3020MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3021MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3022MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3023MODULE_FIRMWARE(FIRMWARE_RT2870);
3024MODULE_LICENSE("GPL");
3025
3026static struct usb_driver rt2800usb_driver = {
3027 .name = KBUILD_MODNAME,
3028 .id_table = rt2800usb_device_table,
3029 .probe = rt2x00usb_probe,
3030 .disconnect = rt2x00usb_disconnect,
3031 .suspend = rt2x00usb_suspend,
3032 .resume = rt2x00usb_resume,
3033};
3034
3035static int __init rt2800usb_init(void)
3036{
3037 return usb_register(&rt2800usb_driver);
3038}
3039
3040static void __exit rt2800usb_exit(void)
3041{
3042 usb_deregister(&rt2800usb_driver);
3043}
3044
3045module_init(rt2800usb_init);
3046module_exit(rt2800usb_exit);
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
new file mode 100644
index 000000000000..8e4291d280b3
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -0,0 +1,1934 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800usb
23 Abstract: Data structures and registers for the rt2800usb module.
24 Supported chipsets: RT2800U.
25 */
26
27#ifndef RT2800USB_H
28#define RT2800USB_H
29
30/*
31 * RF chip defines.
32 *
33 * RF2820 2.4G 2T3R
34 * RF2850 2.4G/5G 2T3R
35 * RF2720 2.4G 1T2R
36 * RF2750 2.4G/5G 1T2R
37 * RF3020 2.4G 1T1R
38 * RF2020 2.4G B/G
39 */
40#define RF2820 0x0001
41#define RF2850 0x0002
42#define RF2720 0x0003
43#define RF2750 0x0004
44#define RF3020 0x0005
45#define RF2020 0x0006
46
47/*
48 * RT2870 version
49 */
50#define RT2860C_VERSION 0x28600100
51#define RT2860D_VERSION 0x28600101
52#define RT2880E_VERSION 0x28720200
53#define RT2883_VERSION 0x28830300
54#define RT3070_VERSION 0x30700200
55
56/*
57 * Signal information.
58 * Defaul offset is required for RSSI <-> dBm conversion.
59 */
60#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
61
62/*
63 * Register layout information.
64 */
65#define CSR_REG_BASE 0x1000
66#define CSR_REG_SIZE 0x0800
67#define EEPROM_BASE 0x0000
68#define EEPROM_SIZE 0x0110
69#define BBP_BASE 0x0000
70#define BBP_SIZE 0x0080
71#define RF_BASE 0x0004
72#define RF_SIZE 0x0010
73
74/*
75 * Number of TX queues.
76 */
77#define NUM_TX_QUEUES 4
78
79/*
80 * USB registers.
81 */
82
83/*
84 * HOST-MCU shared memory
85 */
86#define HOST_CMD_CSR 0x0404
87#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
88
89/*
90 * INT_SOURCE_CSR: Interrupt source register.
91 * Write one to clear corresponding bit.
92 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
93 */
94#define INT_SOURCE_CSR 0x0200
95#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
96#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
97#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
98#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
99#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
100#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
101#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
102#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
103#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
104#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
105#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
106#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
107#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
108#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
109#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
110#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
111#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
112#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
113
114/*
115 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
116 */
117#define INT_MASK_CSR 0x0204
118#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
119#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
120#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
121#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
122#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
123#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
124#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
125#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
126#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
127#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
128#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
129#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
130#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
131#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
132#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
133#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
134#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
135#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
136
137/*
138 * WPDMA_GLO_CFG
139 */
140#define WPDMA_GLO_CFG 0x0208
141#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
142#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
143#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
144#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
145#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
146#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
147#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
148#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
149#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
150
151/*
152 * WPDMA_RST_IDX
153 */
154#define WPDMA_RST_IDX 0x020c
155#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
156#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
157#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
158#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
159#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
160#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
161#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
162
163/*
164 * DELAY_INT_CFG
165 */
166#define DELAY_INT_CFG 0x0210
167#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
168#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
169#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
170#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
171#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
172#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
173
174/*
175 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
176 * AIFSN0: AC_BE
177 * AIFSN1: AC_BK
178 * AIFSN1: AC_VI
179 * AIFSN1: AC_VO
180 */
181#define WMM_AIFSN_CFG 0x0214
182#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
183#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
184#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
185#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
186
187/*
188 * WMM_CWMIN_CSR: CWmin for each EDCA AC
189 * CWMIN0: AC_BE
190 * CWMIN1: AC_BK
191 * CWMIN1: AC_VI
192 * CWMIN1: AC_VO
193 */
194#define WMM_CWMIN_CFG 0x0218
195#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
196#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
197#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
198#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
199
200/*
201 * WMM_CWMAX_CSR: CWmax for each EDCA AC
202 * CWMAX0: AC_BE
203 * CWMAX1: AC_BK
204 * CWMAX1: AC_VI
205 * CWMAX1: AC_VO
206 */
207#define WMM_CWMAX_CFG 0x021c
208#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
209#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
210#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
211#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
212
213/*
214 * AC_TXOP0: AC_BK/AC_BE TXOP register
215 * AC0TXOP: AC_BK in unit of 32us
216 * AC1TXOP: AC_BE in unit of 32us
217 */
218#define WMM_TXOP0_CFG 0x0220
219#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
220#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
221
222/*
223 * AC_TXOP1: AC_VO/AC_VI TXOP register
224 * AC2TXOP: AC_VI in unit of 32us
225 * AC3TXOP: AC_VO in unit of 32us
226 */
227#define WMM_TXOP1_CFG 0x0224
228#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
229#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
230
231/*
232 * GPIO_CTRL_CFG:
233 */
234#define GPIO_CTRL_CFG 0x0228
235#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
236#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
237#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
238#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
239#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
240#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
241#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
242#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
243#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
244
245/*
246 * MCU_CMD_CFG
247 */
248#define MCU_CMD_CFG 0x022c
249
250/*
251 * AC_BK register offsets
252 */
253#define TX_BASE_PTR0 0x0230
254#define TX_MAX_CNT0 0x0234
255#define TX_CTX_IDX0 0x0238
256#define TX_DTX_IDX0 0x023c
257
258/*
259 * AC_BE register offsets
260 */
261#define TX_BASE_PTR1 0x0240
262#define TX_MAX_CNT1 0x0244
263#define TX_CTX_IDX1 0x0248
264#define TX_DTX_IDX1 0x024c
265
266/*
267 * AC_VI register offsets
268 */
269#define TX_BASE_PTR2 0x0250
270#define TX_MAX_CNT2 0x0254
271#define TX_CTX_IDX2 0x0258
272#define TX_DTX_IDX2 0x025c
273
274/*
275 * AC_VO register offsets
276 */
277#define TX_BASE_PTR3 0x0260
278#define TX_MAX_CNT3 0x0264
279#define TX_CTX_IDX3 0x0268
280#define TX_DTX_IDX3 0x026c
281
282/*
283 * HCCA register offsets
284 */
285#define TX_BASE_PTR4 0x0270
286#define TX_MAX_CNT4 0x0274
287#define TX_CTX_IDX4 0x0278
288#define TX_DTX_IDX4 0x027c
289
290/*
291 * MGMT register offsets
292 */
293#define TX_BASE_PTR5 0x0280
294#define TX_MAX_CNT5 0x0284
295#define TX_CTX_IDX5 0x0288
296#define TX_DTX_IDX5 0x028c
297
298/*
299 * RX register offsets
300 */
301#define RX_BASE_PTR 0x0290
302#define RX_MAX_CNT 0x0294
303#define RX_CRX_IDX 0x0298
304#define RX_DRX_IDX 0x029c
305
306/*
307 * USB_DMA_CFG
308 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
309 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
310 * PHY_CLEAR: phy watch dog enable.
311 * TX_CLEAR: Clear USB DMA TX path.
312 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
313 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
314 * RX_BULK_EN: Enable USB DMA Rx.
315 * TX_BULK_EN: Enable USB DMA Tx.
316 * EP_OUT_VALID: OUT endpoint data valid.
317 * RX_BUSY: USB DMA RX FSM busy.
318 * TX_BUSY: USB DMA TX FSM busy.
319 */
320#define USB_DMA_CFG 0x02a0
321#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
322#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
323#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
324#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
325#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
326#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
327#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
328#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
329#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
330#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
331#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
332
333/*
334 * USB_CYC_CFG
335 */
336#define USB_CYC_CFG 0x02a4
337#define USB_CYC_CFG_CLOCK_CYCLE FIELD32(0x000000ff)
338
339/*
340 * PBF_SYS_CTRL
341 * HOST_RAM_WRITE: enable Host program ram write selection
342 */
343#define PBF_SYS_CTRL 0x0400
344#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
345#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
346
347/*
348 * PBF registers
349 * Most are for debug. Driver doesn't touch PBF register.
350 */
351#define PBF_CFG 0x0408
352#define PBF_MAX_PCNT 0x040c
353#define PBF_CTRL 0x0410
354#define PBF_INT_STA 0x0414
355#define PBF_INT_ENA 0x0418
356
357/*
358 * BCN_OFFSET0:
359 */
360#define BCN_OFFSET0 0x042c
361#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
362#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
363#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
364#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
365
366/*
367 * BCN_OFFSET1:
368 */
369#define BCN_OFFSET1 0x0430
370#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
371#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
372#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
373#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
374
375/*
376 * PBF registers
377 * Most are for debug. Driver doesn't touch PBF register.
378 */
379#define TXRXQ_PCNT 0x0438
380#define PBF_DBG 0x043c
381
382/*
383 * RF registers
384 */
385#define RF_CSR_CFG 0x0500
386#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
387#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
388#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
389#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
390
391/*
392 * MAC Control/Status Registers(CSR).
393 * Some values are set in TU, whereas 1 TU == 1024 us.
394 */
395
396/*
397 * MAC_CSR0: ASIC revision number.
398 * ASIC_REV: 0
399 * ASIC_VER: 2870
400 */
401#define MAC_CSR0 0x1000
402#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
403#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
404
405/*
406 * MAC_SYS_CTRL:
407 */
408#define MAC_SYS_CTRL 0x1004
409#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
410#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
411#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
412#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
413#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
414#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
415#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
416#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
417
418/*
419 * MAC_ADDR_DW0: STA MAC register 0
420 */
421#define MAC_ADDR_DW0 0x1008
422#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
423#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
424#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
425#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
426
427/*
428 * MAC_ADDR_DW1: STA MAC register 1
429 * UNICAST_TO_ME_MASK:
430 * Used to mask off bits from byte 5 of the MAC address
431 * to determine the UNICAST_TO_ME bit for RX frames.
432 * The full mask is complemented by BSS_ID_MASK:
433 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
434 */
435#define MAC_ADDR_DW1 0x100c
436#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
437#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
438#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
439
440/*
441 * MAC_BSSID_DW0: BSSID register 0
442 */
443#define MAC_BSSID_DW0 0x1010
444#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
445#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
446#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
447#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
448
449/*
450 * MAC_BSSID_DW1: BSSID register 1
451 * BSS_ID_MASK:
452 * 0: 1-BSSID mode (BSS index = 0)
453 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
454 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
455 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
456 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
457 * BSSID. This will make sure that those bits will be ignored
458 * when determining the MY_BSS of RX frames.
459 */
460#define MAC_BSSID_DW1 0x1014
461#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
462#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
463#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
464#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
465
466/*
467 * MAX_LEN_CFG: Maximum frame length register.
468 * MAX_MPDU: rt2860b max 16k bytes
469 * MAX_PSDU: Maximum PSDU length
470 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
471 */
472#define MAX_LEN_CFG 0x1018
473#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
474#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
475#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
476#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
477
478/*
479 * BBP_CSR_CFG: BBP serial control register
480 * VALUE: Register value to program into BBP
481 * REG_NUM: Selected BBP register
482 * READ_CONTROL: 0 write BBP, 1 read BBP
483 * BUSY: ASIC is busy executing BBP commands
484 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
485 * BBP_RW_MODE: 0 serial, 1 paralell
486 */
487#define BBP_CSR_CFG 0x101c
488#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
489#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
490#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
491#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
492#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
493#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
494
495/*
496 * RF_CSR_CFG0: RF control register
497 * REGID_AND_VALUE: Register value to program into RF
498 * BITWIDTH: Selected RF register
499 * STANDBYMODE: 0 high when standby, 1 low when standby
500 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
501 * BUSY: ASIC is busy executing RF commands
502 */
503#define RF_CSR_CFG0 0x1020
504#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
505#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
506#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
507#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
508#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
509#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
510
511/*
512 * RF_CSR_CFG1: RF control register
513 * REGID_AND_VALUE: Register value to program into RF
514 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
515 * 0: 3 system clock cycle (37.5usec)
516 * 1: 5 system clock cycle (62.5usec)
517 */
518#define RF_CSR_CFG1 0x1024
519#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
520#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
521
522/*
523 * RF_CSR_CFG2: RF control register
524 * VALUE: Register value to program into RF
525 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
526 * 0: 3 system clock cycle (37.5usec)
527 * 1: 5 system clock cycle (62.5usec)
528 */
529#define RF_CSR_CFG2 0x1028
530#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
531
532/*
533 * LED_CFG: LED control
534 * color LED's:
535 * 0: off
536 * 1: blinking upon TX2
537 * 2: periodic slow blinking
538 * 3: always on
539 * LED polarity:
540 * 0: active low
541 * 1: active high
542 */
543#define LED_CFG 0x102c
544#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
545#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
546#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
547#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
548#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
549#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
550#define LED_CFG_LED_POLAR FIELD32(0x40000000)
551
552/*
553 * XIFS_TIME_CFG: MAC timing
554 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
555 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
556 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
557 * when MAC doesn't reference BBP signal BBRXEND
558 * EIFS: unit 1us
559 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
560 *
561 */
562#define XIFS_TIME_CFG 0x1100
563#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
564#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
565#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
566#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
567#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
568
569/*
570 * BKOFF_SLOT_CFG:
571 */
572#define BKOFF_SLOT_CFG 0x1104
573#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
574#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
575
576/*
577 * NAV_TIME_CFG:
578 */
579#define NAV_TIME_CFG 0x1108
580#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
581#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
582#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
583#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
584
585/*
586 * CH_TIME_CFG: count as channel busy
587 */
588#define CH_TIME_CFG 0x110c
589
590/*
591 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
592 */
593#define PBF_LIFE_TIMER 0x1110
594
595/*
596 * BCN_TIME_CFG:
597 * BEACON_INTERVAL: in unit of 1/16 TU
598 * TSF_TICKING: Enable TSF auto counting
599 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
600 * BEACON_GEN: Enable beacon generator
601 */
602#define BCN_TIME_CFG 0x1114
603#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
604#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
605#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
606#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
607#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
608#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
609
610/*
611 * TBTT_SYNC_CFG:
612 */
613#define TBTT_SYNC_CFG 0x1118
614
615/*
616 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
617 */
618#define TSF_TIMER_DW0 0x111c
619#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
620
621/*
622 * TSF_TIMER_DW1: Local msb TSF timer, read-only
623 */
624#define TSF_TIMER_DW1 0x1120
625#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
626
627/*
628 * TBTT_TIMER: TImer remains till next TBTT, read-only
629 */
630#define TBTT_TIMER 0x1124
631
632/*
633 * INT_TIMER_CFG:
634 */
635#define INT_TIMER_CFG 0x1128
636
637/*
638 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
639 */
640#define INT_TIMER_EN 0x112c
641
642/*
643 * CH_IDLE_STA: channel idle time
644 */
645#define CH_IDLE_STA 0x1130
646
647/*
648 * CH_BUSY_STA: channel busy time
649 */
650#define CH_BUSY_STA 0x1134
651
652/*
653 * MAC_STATUS_CFG:
654 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
655 * if 1 or higher one of the 2 registers is busy.
656 */
657#define MAC_STATUS_CFG 0x1200
658#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
659
660/*
661 * PWR_PIN_CFG:
662 */
663#define PWR_PIN_CFG 0x1204
664
665/*
666 * AUTOWAKEUP_CFG: Manual power control / status register
667 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
668 * AUTOWAKE: 0:sleep, 1:awake
669 */
670#define AUTOWAKEUP_CFG 0x1208
671#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
672#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
673#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
674
675/*
676 * EDCA_AC0_CFG:
677 */
678#define EDCA_AC0_CFG 0x1300
679#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
680#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
681#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
682#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
683
684/*
685 * EDCA_AC1_CFG:
686 */
687#define EDCA_AC1_CFG 0x1304
688#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
689#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
690#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
691#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
692
693/*
694 * EDCA_AC2_CFG:
695 */
696#define EDCA_AC2_CFG 0x1308
697#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
698#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
699#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
700#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
701
702/*
703 * EDCA_AC3_CFG:
704 */
705#define EDCA_AC3_CFG 0x130c
706#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
707#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
708#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
709#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
710
711/*
712 * EDCA_TID_AC_MAP:
713 */
714#define EDCA_TID_AC_MAP 0x1310
715
716/*
717 * TX_PWR_CFG_0:
718 */
719#define TX_PWR_CFG_0 0x1314
720#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
721#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
722#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
723#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
724#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
725#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
726#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
727#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
728
729/*
730 * TX_PWR_CFG_1:
731 */
732#define TX_PWR_CFG_1 0x1318
733#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
734#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
735#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
736#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
737#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
738#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
739#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
740#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
741
742/*
743 * TX_PWR_CFG_2:
744 */
745#define TX_PWR_CFG_2 0x131c
746#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
747#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
748#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
749#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
750#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
751#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
752#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
753#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
754
755/*
756 * TX_PWR_CFG_3:
757 */
758#define TX_PWR_CFG_3 0x1320
759#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
760#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
761#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
762#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
763#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
764#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
765#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
766#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
767
768/*
769 * TX_PWR_CFG_4:
770 */
771#define TX_PWR_CFG_4 0x1324
772#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
773#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
774#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
775#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
776
777/*
778 * TX_PIN_CFG:
779 */
780#define TX_PIN_CFG 0x1328
781#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
782#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
783#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
784#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
785#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
786#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
787#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
788#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
789#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
790#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
791#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
792#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
793#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
794#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
795#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
796#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
797#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
798#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
799#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
800#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
801
802/*
803 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
804 */
805#define TX_BAND_CFG 0x132c
806#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
807#define TX_BAND_CFG_A FIELD32(0x00000002)
808#define TX_BAND_CFG_BG FIELD32(0x00000004)
809
810/*
811 * TX_SW_CFG0:
812 */
813#define TX_SW_CFG0 0x1330
814
815/*
816 * TX_SW_CFG1:
817 */
818#define TX_SW_CFG1 0x1334
819
820/*
821 * TX_SW_CFG2:
822 */
823#define TX_SW_CFG2 0x1338
824
825/*
826 * TXOP_THRES_CFG:
827 */
828#define TXOP_THRES_CFG 0x133c
829
830/*
831 * TXOP_CTRL_CFG:
832 */
833#define TXOP_CTRL_CFG 0x1340
834
835/*
836 * TX_RTS_CFG:
837 * RTS_THRES: unit:byte
838 * RTS_FBK_EN: enable rts rate fallback
839 */
840#define TX_RTS_CFG 0x1344
841#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
842#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
843#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
844
845/*
846 * TX_TIMEOUT_CFG:
847 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
848 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
849 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
850 * it is recommended that:
851 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
852 */
853#define TX_TIMEOUT_CFG 0x1348
854#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
855#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
856#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
857
858/*
859 * TX_RTY_CFG:
860 * SHORT_RTY_LIMIT: short retry limit
861 * LONG_RTY_LIMIT: long retry limit
862 * LONG_RTY_THRE: Long retry threshoold
863 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
864 * 0:expired by retry limit, 1: expired by mpdu life timer
865 * AGG_RTY_MODE: Aggregate MPDU retry mode
866 * 0:expired by retry limit, 1: expired by mpdu life timer
867 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
868 */
869#define TX_RTY_CFG 0x134c
870#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
871#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
872#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
873#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
874#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
875#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
876
877/*
878 * TX_LINK_CFG:
879 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
880 * MFB_ENABLE: TX apply remote MFB 1:enable
881 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
882 * 0: not apply remote remote unsolicit (MFS=7)
883 * TX_MRQ_EN: MCS request TX enable
884 * TX_RDG_EN: RDG TX enable
885 * TX_CF_ACK_EN: Piggyback CF-ACK enable
886 * REMOTE_MFB: remote MCS feedback
887 * REMOTE_MFS: remote MCS feedback sequence number
888 */
889#define TX_LINK_CFG 0x1350
890#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
891#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
892#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
893#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
894#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
895#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
896#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
897#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
898
899/*
900 * HT_FBK_CFG0:
901 */
902#define HT_FBK_CFG0 0x1354
903#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
904#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
905#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
906#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
907#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
908#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
909#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
910#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
911
912/*
913 * HT_FBK_CFG1:
914 */
915#define HT_FBK_CFG1 0x1358
916#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
917#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
918#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
919#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
920#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
921#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
922#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
923#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
924
925/*
926 * LG_FBK_CFG0:
927 */
928#define LG_FBK_CFG0 0x135c
929#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
930#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
931#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
932#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
933#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
934#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
935#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
936#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
937
938/*
939 * LG_FBK_CFG1:
940 */
941#define LG_FBK_CFG1 0x1360
942#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
943#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
944#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
945#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
946
947/*
948 * CCK_PROT_CFG: CCK Protection
949 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
950 * PROTECT_CTRL: Protection control frame type for CCK TX
951 * 0:none, 1:RTS/CTS, 2:CTS-to-self
952 * PROTECT_NAV: TXOP protection type for CCK TX
953 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
954 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
955 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
956 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
957 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
958 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
959 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
960 * RTS_TH_EN: RTS threshold enable on CCK TX
961 */
962#define CCK_PROT_CFG 0x1364
963#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
964#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
965#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
966#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
967#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
968#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
969#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
970#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
971#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
972#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
973
974/*
975 * OFDM_PROT_CFG: OFDM Protection
976 */
977#define OFDM_PROT_CFG 0x1368
978#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
979#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
980#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
981#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
982#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
983#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
984#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
985#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
986#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
987#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
988
989/*
990 * MM20_PROT_CFG: MM20 Protection
991 */
992#define MM20_PROT_CFG 0x136c
993#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
994#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
995#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
996#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
997#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
998#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
999#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1000#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1001#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1002#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1003
1004/*
1005 * MM40_PROT_CFG: MM40 Protection
1006 */
1007#define MM40_PROT_CFG 0x1370
1008#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1009#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1010#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1011#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1012#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1013#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1014#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1015#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1016#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1017#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1018
1019/*
1020 * GF20_PROT_CFG: GF20 Protection
1021 */
1022#define GF20_PROT_CFG 0x1374
1023#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1024#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1025#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1026#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1027#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1028#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1029#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1030#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1031#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1032#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1033
1034/*
1035 * GF40_PROT_CFG: GF40 Protection
1036 */
1037#define GF40_PROT_CFG 0x1378
1038#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1039#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1040#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1041#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1042#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1043#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1044#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1045#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1046#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1047#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1048
1049/*
1050 * EXP_CTS_TIME:
1051 */
1052#define EXP_CTS_TIME 0x137c
1053
1054/*
1055 * EXP_ACK_TIME:
1056 */
1057#define EXP_ACK_TIME 0x1380
1058
1059/*
1060 * RX_FILTER_CFG: RX configuration register.
1061 */
1062#define RX_FILTER_CFG 0x1400
1063#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1064#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1065#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1066#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1067#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1068#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1069#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1070#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1071#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1072#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1073#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1074#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1075#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1076#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1077#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1078#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1079#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1080
1081/*
1082 * AUTO_RSP_CFG:
1083 * AUTORESPONDER: 0: disable, 1: enable
1084 * BAC_ACK_POLICY: 0:long, 1:short preamble
1085 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1086 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1087 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1088 * DUAL_CTS_EN: Power bit value in control frame
1089 * ACK_CTS_PSM_BIT:Power bit value in control frame
1090 */
1091#define AUTO_RSP_CFG 0x1404
1092#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1093#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1094#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1095#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1096#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1097#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1098#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1099
1100/*
1101 * LEGACY_BASIC_RATE:
1102 */
1103#define LEGACY_BASIC_RATE 0x1408
1104
1105/*
1106 * HT_BASIC_RATE:
1107 */
1108#define HT_BASIC_RATE 0x140c
1109
1110/*
1111 * HT_CTRL_CFG:
1112 */
1113#define HT_CTRL_CFG 0x1410
1114
1115/*
1116 * SIFS_COST_CFG:
1117 */
1118#define SIFS_COST_CFG 0x1414
1119
1120/*
1121 * RX_PARSER_CFG:
1122 * Set NAV for all received frames
1123 */
1124#define RX_PARSER_CFG 0x1418
1125
1126/*
1127 * TX_SEC_CNT0:
1128 */
1129#define TX_SEC_CNT0 0x1500
1130
1131/*
1132 * RX_SEC_CNT0:
1133 */
1134#define RX_SEC_CNT0 0x1504
1135
1136/*
1137 * CCMP_FC_MUTE:
1138 */
1139#define CCMP_FC_MUTE 0x1508
1140
1141/*
1142 * TXOP_HLDR_ADDR0:
1143 */
1144#define TXOP_HLDR_ADDR0 0x1600
1145
1146/*
1147 * TXOP_HLDR_ADDR1:
1148 */
1149#define TXOP_HLDR_ADDR1 0x1604
1150
1151/*
1152 * TXOP_HLDR_ET:
1153 */
1154#define TXOP_HLDR_ET 0x1608
1155
1156/*
1157 * QOS_CFPOLL_RA_DW0:
1158 */
1159#define QOS_CFPOLL_RA_DW0 0x160c
1160
1161/*
1162 * QOS_CFPOLL_RA_DW1:
1163 */
1164#define QOS_CFPOLL_RA_DW1 0x1610
1165
1166/*
1167 * QOS_CFPOLL_QC:
1168 */
1169#define QOS_CFPOLL_QC 0x1614
1170
1171/*
1172 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1173 */
1174#define RX_STA_CNT0 0x1700
1175#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1176#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1177
1178/*
1179 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1180 */
1181#define RX_STA_CNT1 0x1704
1182#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1183#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1184
1185/*
1186 * RX_STA_CNT2:
1187 */
1188#define RX_STA_CNT2 0x1708
1189#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1190#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1191
1192/*
1193 * TX_STA_CNT0: TX Beacon count
1194 */
1195#define TX_STA_CNT0 0x170c
1196#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1197#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1198
1199/*
1200 * TX_STA_CNT1: TX tx count
1201 */
1202#define TX_STA_CNT1 0x1710
1203#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1204#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1205
1206/*
1207 * TX_STA_CNT2: TX tx count
1208 */
1209#define TX_STA_CNT2 0x1714
1210#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1211#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1212
1213/*
1214 * TX_STA_FIFO: TX Result for specific PID status fifo register
1215 */
1216#define TX_STA_FIFO 0x1718
1217#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1218#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1219#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1220#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1221#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1222#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1223#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1224
1225/*
1226 * TX_AGG_CNT: Debug counter
1227 */
1228#define TX_AGG_CNT 0x171c
1229#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1230#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1231
1232/*
1233 * TX_AGG_CNT0:
1234 */
1235#define TX_AGG_CNT0 0x1720
1236#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1237#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1238
1239/*
1240 * TX_AGG_CNT1:
1241 */
1242#define TX_AGG_CNT1 0x1724
1243#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1244#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1245
1246/*
1247 * TX_AGG_CNT2:
1248 */
1249#define TX_AGG_CNT2 0x1728
1250#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1251#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1252
1253/*
1254 * TX_AGG_CNT3:
1255 */
1256#define TX_AGG_CNT3 0x172c
1257#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1258#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1259
1260/*
1261 * TX_AGG_CNT4:
1262 */
1263#define TX_AGG_CNT4 0x1730
1264#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1265#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1266
1267/*
1268 * TX_AGG_CNT5:
1269 */
1270#define TX_AGG_CNT5 0x1734
1271#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1272#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1273
1274/*
1275 * TX_AGG_CNT6:
1276 */
1277#define TX_AGG_CNT6 0x1738
1278#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1279#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1280
1281/*
1282 * TX_AGG_CNT7:
1283 */
1284#define TX_AGG_CNT7 0x173c
1285#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1286#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1287
1288/*
1289 * MPDU_DENSITY_CNT:
1290 * TX_ZERO_DEL: TX zero length delimiter count
1291 * RX_ZERO_DEL: RX zero length delimiter count
1292 */
1293#define MPDU_DENSITY_CNT 0x1740
1294#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1295#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1296
1297/*
1298 * Security key table memory.
1299 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1300 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1301 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1302 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1303 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1304 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1305 */
1306#define MAC_WCID_BASE 0x1800
1307#define PAIRWISE_KEY_TABLE_BASE 0x4000
1308#define MAC_IVEIV_TABLE_BASE 0x6000
1309#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1310#define SHARED_KEY_TABLE_BASE 0x6c00
1311#define SHARED_KEY_MODE_BASE 0x7000
1312
1313#define MAC_WCID_ENTRY(__idx) \
1314 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1315#define PAIRWISE_KEY_ENTRY(__idx) \
1316 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1317#define MAC_IVEIV_ENTRY(__idx) \
1318 ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
1319#define MAC_WCID_ATTR_ENTRY(__idx) \
1320 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1321#define SHARED_KEY_ENTRY(__idx) \
1322 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1323#define SHARED_KEY_MODE_ENTRY(__idx) \
1324 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1325
1326struct mac_wcid_entry {
1327 u8 mac[6];
1328 u8 reserved[2];
1329} __attribute__ ((packed));
1330
1331struct hw_key_entry {
1332 u8 key[16];
1333 u8 tx_mic[8];
1334 u8 rx_mic[8];
1335} __attribute__ ((packed));
1336
1337struct mac_iveiv_entry {
1338 u8 iv[8];
1339} __attribute__ ((packed));
1340
1341/*
1342 * MAC_WCID_ATTRIBUTE:
1343 */
1344#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1345#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1346#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1347#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1348
1349/*
1350 * SHARED_KEY_MODE:
1351 */
1352#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1353#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1354#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1355#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1356#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1357#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1358#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1359#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1360
1361/*
1362 * HOST-MCU communication
1363 */
1364
1365/*
1366 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1367 */
1368#define H2M_MAILBOX_CSR 0x7010
1369#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1370#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1371#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1372#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1373
1374/*
1375 * H2M_MAILBOX_CID:
1376 */
1377#define H2M_MAILBOX_CID 0x7014
1378
1379/*
1380 * H2M_MAILBOX_STATUS:
1381 */
1382#define H2M_MAILBOX_STATUS 0x701c
1383
1384/*
1385 * H2M_INT_SRC:
1386 */
1387#define H2M_INT_SRC 0x7024
1388
1389/*
1390 * H2M_BBP_AGENT:
1391 */
1392#define H2M_BBP_AGENT 0x7028
1393
1394/*
1395 * MCU_LEDCS: LED control for MCU Mailbox.
1396 */
1397#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1398#define MCU_LEDCS_POLARITY FIELD8(0x01)
1399
1400/*
1401 * HW_CS_CTS_BASE:
1402 * Carrier-sense CTS frame base address.
1403 * It's where mac stores carrier-sense frame for carrier-sense function.
1404 */
1405#define HW_CS_CTS_BASE 0x7700
1406
1407/*
1408 * HW_DFS_CTS_BASE:
1409 * FS CTS frame base address. It's where mac stores CTS frame for DFS.
1410 */
1411#define HW_DFS_CTS_BASE 0x7780
1412
1413/*
1414 * TXRX control registers - base address 0x3000
1415 */
1416
1417/*
1418 * TXRX_CSR1:
1419 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1420 */
1421#define TXRX_CSR1 0x77d0
1422
1423/*
1424 * HW_DEBUG_SETTING_BASE:
1425 * since NULL frame won't be that long (256 byte)
1426 * We steal 16 tail bytes to save debugging settings
1427 */
1428#define HW_DEBUG_SETTING_BASE 0x77f0
1429#define HW_DEBUG_SETTING_BASE2 0x7770
1430
1431/*
1432 * HW_BEACON_BASE
1433 * In order to support maximum 8 MBSS and its maximum length
1434 * is 512 bytes for each beacon
1435 * Three section discontinue memory segments will be used.
1436 * 1. The original region for BCN 0~3
1437 * 2. Extract memory from FCE table for BCN 4~5
1438 * 3. Extract memory from Pair-wise key table for BCN 6~7
1439 * It occupied those memory of wcid 238~253 for BCN 6
1440 * and wcid 222~237 for BCN 7
1441 *
1442 * IMPORTANT NOTE: Not sure why legacy driver does this,
1443 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1444 */
1445#define HW_BEACON_BASE0 0x7800
1446#define HW_BEACON_BASE1 0x7a00
1447#define HW_BEACON_BASE2 0x7c00
1448#define HW_BEACON_BASE3 0x7e00
1449#define HW_BEACON_BASE4 0x7200
1450#define HW_BEACON_BASE5 0x7400
1451#define HW_BEACON_BASE6 0x5dc0
1452#define HW_BEACON_BASE7 0x5bc0
1453
1454#define HW_BEACON_OFFSET(__index) \
1455 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1456 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1457 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1458
1459/*
1460 * 8051 firmware image.
1461 */
1462#define FIRMWARE_RT2870 "rt2870.bin"
1463#define FIRMWARE_IMAGE_BASE 0x3000
1464
1465/*
1466 * BBP registers.
1467 * The wordsize of the BBP is 8 bits.
1468 */
1469
1470/*
1471 * BBP 1: TX Antenna
1472 */
1473#define BBP1_TX_POWER FIELD8(0x07)
1474#define BBP1_TX_ANTENNA FIELD8(0x18)
1475
1476/*
1477 * BBP 3: RX Antenna
1478 */
1479#define BBP3_RX_ANTENNA FIELD8(0x18)
1480#define BBP3_HT40_PLUS FIELD8(0x20)
1481
1482/*
1483 * BBP 4: Bandwidth
1484 */
1485#define BBP4_TX_BF FIELD8(0x01)
1486#define BBP4_BANDWIDTH FIELD8(0x18)
1487
1488/*
1489 * RFCSR registers
1490 * The wordsize of the RFCSR is 8 bits.
1491 */
1492
1493/*
1494 * RFCSR 6:
1495 */
1496#define RFCSR6_R FIELD8(0x03)
1497
1498/*
1499 * RFCSR 7:
1500 */
1501#define RFCSR7_RF_TUNING FIELD8(0x01)
1502
1503/*
1504 * RFCSR 12:
1505 */
1506#define RFCSR12_TX_POWER FIELD8(0x1f)
1507
1508/*
1509 * RFCSR 22:
1510 */
1511#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1512
1513/*
1514 * RFCSR 23:
1515 */
1516#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1517
1518/*
1519 * RFCSR 30:
1520 */
1521#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1522
1523/*
1524 * RF registers
1525 */
1526
1527/*
1528 * RF 2
1529 */
1530#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1531#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1532#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1533
1534/*
1535 * RF 3
1536 */
1537#define RF3_TXPOWER_G FIELD32(0x00003e00)
1538#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1539#define RF3_TXPOWER_A FIELD32(0x00003c00)
1540
1541/*
1542 * RF 4
1543 */
1544#define RF4_TXPOWER_G FIELD32(0x000007c0)
1545#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1546#define RF4_TXPOWER_A FIELD32(0x00000780)
1547#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1548#define RF4_HT40 FIELD32(0x00200000)
1549
1550/*
1551 * EEPROM content.
1552 * The wordsize of the EEPROM is 16 bits.
1553 */
1554
1555/*
1556 * EEPROM Version
1557 */
1558#define EEPROM_VERSION 0x0001
1559#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1560#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1561
1562/*
1563 * HW MAC address.
1564 */
1565#define EEPROM_MAC_ADDR_0 0x0002
1566#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1567#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1568#define EEPROM_MAC_ADDR_1 0x0003
1569#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1570#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1571#define EEPROM_MAC_ADDR_2 0x0004
1572#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1573#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1574
1575/*
1576 * EEPROM ANTENNA config
1577 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1578 * TXPATH: 1: 1T, 2: 2T
1579 */
1580#define EEPROM_ANTENNA 0x001a
1581#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1582#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1583#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1584
1585/*
1586 * EEPROM NIC config
1587 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1588 */
1589#define EEPROM_NIC 0x001b
1590#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1591#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1592#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1593#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1594#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1595#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1596#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1597#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1598#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1599#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1600
1601/*
1602 * EEPROM frequency
1603 */
1604#define EEPROM_FREQ 0x001d
1605#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1606#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1607#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1608
1609/*
1610 * EEPROM LED
1611 * POLARITY_RDY_G: Polarity RDY_G setting.
1612 * POLARITY_RDY_A: Polarity RDY_A setting.
1613 * POLARITY_ACT: Polarity ACT setting.
1614 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1615 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1616 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1617 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1618 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1619 * LED_MODE: Led mode.
1620 */
1621#define EEPROM_LED1 0x001e
1622#define EEPROM_LED2 0x001f
1623#define EEPROM_LED3 0x0020
1624#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1625#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1626#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1627#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1628#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1629#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1630#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1631#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1632#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1633
1634/*
1635 * EEPROM LNA
1636 */
1637#define EEPROM_LNA 0x0022
1638#define EEPROM_LNA_BG FIELD16(0x00ff)
1639#define EEPROM_LNA_A0 FIELD16(0xff00)
1640
1641/*
1642 * EEPROM RSSI BG offset
1643 */
1644#define EEPROM_RSSI_BG 0x0023
1645#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1646#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1647
1648/*
1649 * EEPROM RSSI BG2 offset
1650 */
1651#define EEPROM_RSSI_BG2 0x0024
1652#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1653#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1654
1655/*
1656 * EEPROM RSSI A offset
1657 */
1658#define EEPROM_RSSI_A 0x0025
1659#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1660#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1661
1662/*
1663 * EEPROM RSSI A2 offset
1664 */
1665#define EEPROM_RSSI_A2 0x0026
1666#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1667#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1668
1669/*
1670 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1671 * This is delta in 40MHZ.
1672 * VALUE: Tx Power dalta value (MAX=4)
1673 * TYPE: 1: Plus the delta value, 0: minus the delta value
1674 * TXPOWER: Enable:
1675 */
1676#define EEPROM_TXPOWER_DELTA 0x0028
1677#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1678#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1679#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1680
1681/*
1682 * EEPROM TXPOWER 802.11BG
1683 */
1684#define EEPROM_TXPOWER_BG1 0x0029
1685#define EEPROM_TXPOWER_BG2 0x0030
1686#define EEPROM_TXPOWER_BG_SIZE 7
1687#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1688#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1689
1690/*
1691 * EEPROM TXPOWER 802.11A
1692 */
1693#define EEPROM_TXPOWER_A1 0x003c
1694#define EEPROM_TXPOWER_A2 0x0053
1695#define EEPROM_TXPOWER_A_SIZE 6
1696#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1697#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1698
1699/*
1700 * EEPROM TXpower byrate: 20MHZ power
1701 */
1702#define EEPROM_TXPOWER_BYRATE 0x006f
1703
1704/*
1705 * EEPROM BBP.
1706 */
1707#define EEPROM_BBP_START 0x0078
1708#define EEPROM_BBP_SIZE 16
1709#define EEPROM_BBP_VALUE FIELD16(0x00ff)
1710#define EEPROM_BBP_REG_ID FIELD16(0xff00)
1711
1712/*
1713 * MCU mailbox commands.
1714 */
1715#define MCU_SLEEP 0x30
1716#define MCU_WAKEUP 0x31
1717#define MCU_RADIO_OFF 0x35
1718#define MCU_LED 0x50
1719#define MCU_LED_STRENGTH 0x51
1720#define MCU_LED_1 0x52
1721#define MCU_LED_2 0x53
1722#define MCU_LED_3 0x54
1723#define MCU_RADAR 0x60
1724#define MCU_BOOT_SIGNAL 0x72
1725#define MCU_BBP_SIGNAL 0x80
1726
1727/*
1728 * DMA descriptor defines.
1729 */
1730#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
1731#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
1732#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1733#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
1734#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1735
1736/*
1737 * TX descriptor format for TX, PRIO and Beacon Ring.
1738 */
1739
1740/*
1741 * Word0
1742 */
1743#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
1744
1745/*
1746 * Word1
1747 */
1748#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
1749#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
1750#define TXD_W1_BURST FIELD32(0x00008000)
1751#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
1752#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
1753#define TXD_W1_DMA_DONE FIELD32(0x80000000)
1754
1755/*
1756 * Word2
1757 */
1758#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
1759
1760/*
1761 * Word3
1762 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1763 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1764 * 0:MGMT, 1:HCCA 2:EDCA
1765 */
1766#define TXD_W3_WIV FIELD32(0x01000000)
1767#define TXD_W3_QSEL FIELD32(0x06000000)
1768#define TXD_W3_TCO FIELD32(0x20000000)
1769#define TXD_W3_UCO FIELD32(0x40000000)
1770#define TXD_W3_ICO FIELD32(0x80000000)
1771
1772/*
1773 * TX Info structure
1774 */
1775
1776/*
1777 * Word0
1778 * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
1779 * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
1780 * 0:MGMT, 1:HCCA 2:EDCA
1781 * USB_DMA_NEXT_VALID: Used ONLY in USB bulk Aggregation, NextValid
1782 * DMA_TX_BURST: used ONLY in USB bulk Aggregation.
1783 * Force USB DMA transmit frame from current selected endpoint
1784 */
1785#define TXINFO_W0_USB_DMA_TX_PKT_LEN FIELD32(0x0000ffff)
1786#define TXINFO_W0_WIV FIELD32(0x01000000)
1787#define TXINFO_W0_QSEL FIELD32(0x06000000)
1788#define TXINFO_W0_SW_USE_LAST_ROUND FIELD32(0x08000000)
1789#define TXINFO_W0_USB_DMA_NEXT_VALID FIELD32(0x40000000)
1790#define TXINFO_W0_USB_DMA_TX_BURST FIELD32(0x80000000)
1791
1792/*
1793 * TX WI structure
1794 */
1795
1796/*
1797 * Word0
1798 * FRAG: 1 To inform TKIP engine this is a fragment.
1799 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
1800 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
1801 * BW: Channel bandwidth 20MHz or 40 MHz
1802 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
1803 */
1804#define TXWI_W0_FRAG FIELD32(0x00000001)
1805#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
1806#define TXWI_W0_CF_ACK FIELD32(0x00000004)
1807#define TXWI_W0_TS FIELD32(0x00000008)
1808#define TXWI_W0_AMPDU FIELD32(0x00000010)
1809#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
1810#define TXWI_W0_TX_OP FIELD32(0x00000300)
1811#define TXWI_W0_MCS FIELD32(0x007f0000)
1812#define TXWI_W0_BW FIELD32(0x00800000)
1813#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
1814#define TXWI_W0_STBC FIELD32(0x06000000)
1815#define TXWI_W0_IFS FIELD32(0x08000000)
1816#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
1817
1818/*
1819 * Word1
1820 */
1821#define TXWI_W1_ACK FIELD32(0x00000001)
1822#define TXWI_W1_NSEQ FIELD32(0x00000002)
1823#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
1824#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
1825#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1826#define TXWI_W1_PACKETID FIELD32(0xf0000000)
1827
1828/*
1829 * Word2
1830 */
1831#define TXWI_W2_IV FIELD32(0xffffffff)
1832
1833/*
1834 * Word3
1835 */
1836#define TXWI_W3_EIV FIELD32(0xffffffff)
1837
1838/*
1839 * RX descriptor format for RX Ring.
1840 */
1841
1842/*
1843 * Word0
1844 * UNICAST_TO_ME: This RX frame is unicast to me.
1845 * MULTICAST: This is a multicast frame.
1846 * BROADCAST: This is a broadcast frame.
1847 * MY_BSS: this frame belongs to the same BSSID.
1848 * CRC_ERROR: CRC error.
1849 * CIPHER_ERROR: 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid.
1850 * AMSDU: rx with 802.3 header, not 802.11 header.
1851 */
1852
1853#define RXD_W0_BA FIELD32(0x00000001)
1854#define RXD_W0_DATA FIELD32(0x00000002)
1855#define RXD_W0_NULLDATA FIELD32(0x00000004)
1856#define RXD_W0_FRAG FIELD32(0x00000008)
1857#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000010)
1858#define RXD_W0_MULTICAST FIELD32(0x00000020)
1859#define RXD_W0_BROADCAST FIELD32(0x00000040)
1860#define RXD_W0_MY_BSS FIELD32(0x00000080)
1861#define RXD_W0_CRC_ERROR FIELD32(0x00000100)
1862#define RXD_W0_CIPHER_ERROR FIELD32(0x00000600)
1863#define RXD_W0_AMSDU FIELD32(0x00000800)
1864#define RXD_W0_HTC FIELD32(0x00001000)
1865#define RXD_W0_RSSI FIELD32(0x00002000)
1866#define RXD_W0_L2PAD FIELD32(0x00004000)
1867#define RXD_W0_AMPDU FIELD32(0x00008000)
1868#define RXD_W0_DECRYPTED FIELD32(0x00010000)
1869#define RXD_W0_PLCP_RSSI FIELD32(0x00020000)
1870#define RXD_W0_CIPHER_ALG FIELD32(0x00040000)
1871#define RXD_W0_LAST_AMSDU FIELD32(0x00080000)
1872#define RXD_W0_PLCP_SIGNAL FIELD32(0xfff00000)
1873
1874/*
1875 * RX WI structure
1876 */
1877
1878/*
1879 * Word0
1880 */
1881#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
1882#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
1883#define RXWI_W0_BSSID FIELD32(0x00001c00)
1884#define RXWI_W0_UDF FIELD32(0x0000e000)
1885#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
1886#define RXWI_W0_TID FIELD32(0xf0000000)
1887
1888/*
1889 * Word1
1890 */
1891#define RXWI_W1_FRAG FIELD32(0x0000000f)
1892#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
1893#define RXWI_W1_MCS FIELD32(0x007f0000)
1894#define RXWI_W1_BW FIELD32(0x00800000)
1895#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
1896#define RXWI_W1_STBC FIELD32(0x06000000)
1897#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
1898
1899/*
1900 * Word2
1901 */
1902#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
1903#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
1904#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
1905
1906/*
1907 * Word3
1908 */
1909#define RXWI_W3_SNR0 FIELD32(0x000000ff)
1910#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
1911
1912/*
1913 * Macro's for converting txpower from EEPROM to mac80211 value
1914 * and from mac80211 value to register value.
1915 */
1916#define MIN_G_TXPOWER 0
1917#define MIN_A_TXPOWER -7
1918#define MAX_G_TXPOWER 31
1919#define MAX_A_TXPOWER 15
1920#define DEFAULT_TXPOWER 5
1921
1922#define TXPOWER_G_FROM_DEV(__txpower) \
1923 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1924
1925#define TXPOWER_G_TO_DEV(__txpower) \
1926 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
1927
1928#define TXPOWER_A_FROM_DEV(__txpower) \
1929 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1930
1931#define TXPOWER_A_TO_DEV(__txpower) \
1932 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
1933
1934#endif /* RT2800USB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index ebe5f276679b..8d933ee30583 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -147,6 +147,7 @@ struct rt2x00_chip {
147#define RT2561 0x0302 147#define RT2561 0x0302
148#define RT2661 0x0401 148#define RT2661 0x0401
149#define RT2571 0x1300 149#define RT2571 0x1300
150#define RT2870 0x1600
150 151
151 u16 rf; 152 u16 rf;
152 u32 rev; 153 u32 rev;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-17 02:13:00 -0500