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authorIvo van Doorn <ivdoorn@gmail.com>2008-11-10 13:42:18 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-11-25 16:32:53 -0500
commit0f829b1d6f499447052f98098e41fd6a091eadd0 (patch)
tree3690f35175e75d94ee7a55320e5bb40620c600be /drivers/net/wireless/rt2x00/rt73usb.c
parentc9c3b1a5deac4297503145840fffcd122b253db5 (diff)
rt2x00: Move rt73usb register access wrappers into rt2x00usb
rt2500usb and rt73usb have different register word sizes, for that reason the register access wrappers were never moved into rt2x00usb. With rt2800usb on its way, we should favor the 32bit register access and move those wrappers into rt2x00usb. That saves duplicate code, since only rt2500usb will need the special 16bit wrappers. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt73usb.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c323
1 files changed, 122 insertions, 201 deletions
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index b4ca8488beff..ee59b4e35cdc 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -46,7 +46,7 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46/* 46/*
47 * Register access. 47 * Register access.
48 * All access to the CSR registers will go through the methods 48 * All access to the CSR registers will go through the methods
49 * rt73usb_register_read and rt73usb_register_write. 49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access, 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this. 51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits, 52 * These indirect registers work with busy bits,
@@ -57,89 +57,10 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 * and we will print an error. 57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex 58 * The _lock versions must be used if you already hold the csr_mutex
59 */ 59 */
60static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
61 const unsigned int offset, u32 *value)
62{
63 __le32 reg;
64 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
65 USB_VENDOR_REQUEST_IN, offset,
66 &reg, sizeof(reg), REGISTER_TIMEOUT);
67 *value = le32_to_cpu(reg);
68}
69
70static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset, u32 *value)
72{
73 __le32 reg;
74 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
75 USB_VENDOR_REQUEST_IN, offset,
76 &reg, sizeof(reg), REGISTER_TIMEOUT);
77 *value = le32_to_cpu(reg);
78}
79
80static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
81 const unsigned int offset,
82 void *value, const u32 length)
83{
84 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
85 USB_VENDOR_REQUEST_IN, offset,
86 value, length,
87 REGISTER_TIMEOUT32(length));
88}
89
90static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
91 const unsigned int offset, u32 value)
92{
93 __le32 reg = cpu_to_le32(value);
94 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
95 USB_VENDOR_REQUEST_OUT, offset,
96 &reg, sizeof(reg), REGISTER_TIMEOUT);
97}
98
99static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
100 const unsigned int offset, u32 value)
101{
102 __le32 reg = cpu_to_le32(value);
103 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
104 USB_VENDOR_REQUEST_OUT, offset,
105 &reg, sizeof(reg), REGISTER_TIMEOUT);
106}
107
108static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
109 const unsigned int offset,
110 void *value, const u32 length)
111{
112 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
113 USB_VENDOR_REQUEST_OUT, offset,
114 value, length,
115 REGISTER_TIMEOUT32(length));
116}
117
118static int rt73usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
119 const unsigned int offset,
120 struct rt2x00_field32 field,
121 u32 *reg)
122{
123 unsigned int i;
124
125 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
126 rt73usb_register_read_lock(rt2x00dev, offset, reg);
127 if (!rt2x00_get_field32(*reg, field))
128 return 1;
129 udelay(REGISTER_BUSY_DELAY);
130 }
131
132 ERROR(rt2x00dev, "Indirect register access failed: "
133 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
134 *reg = ~0;
135
136 return 0;
137}
138
139#define WAIT_FOR_BBP(__dev, __reg) \ 60#define WAIT_FOR_BBP(__dev, __reg) \
140 rt73usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
141#define WAIT_FOR_RF(__dev, __reg) \ 62#define WAIT_FOR_RF(__dev, __reg) \
142 rt73usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
143 64
144static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value) 66 const unsigned int word, const u8 value)
@@ -159,7 +80,7 @@ static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
159 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); 80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
160 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); 81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
161 82
162 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
163 } 84 }
164 85
165 mutex_unlock(&rt2x00dev->csr_mutex); 86 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -186,7 +107,7 @@ static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
186 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); 107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
187 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1); 108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
188 109
189 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
190 111
191 WAIT_FOR_BBP(rt2x00dev, &reg); 112 WAIT_FOR_BBP(rt2x00dev, &reg);
192 } 113 }
@@ -223,7 +144,7 @@ static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
223 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); 144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
224 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); 145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
225 146
226 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); 147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
227 rt2x00_rf_write(rt2x00dev, word, value); 148 rt2x00_rf_write(rt2x00dev, word, value);
228 } 149 }
229 150
@@ -234,8 +155,8 @@ static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
234static const struct rt2x00debug rt73usb_rt2x00debug = { 155static const struct rt2x00debug rt73usb_rt2x00debug = {
235 .owner = THIS_MODULE, 156 .owner = THIS_MODULE,
236 .csr = { 157 .csr = {
237 .read = rt73usb_register_read, 158 .read = rt2x00usb_register_read,
238 .write = rt73usb_register_write, 159 .write = rt2x00usb_register_write,
239 .flags = RT2X00DEBUGFS_OFFSET, 160 .flags = RT2X00DEBUGFS_OFFSET,
240 .word_base = CSR_REG_BASE, 161 .word_base = CSR_REG_BASE,
241 .word_size = sizeof(u32), 162 .word_size = sizeof(u32),
@@ -314,10 +235,10 @@ static int rt73usb_blink_set(struct led_classdev *led_cdev,
314 container_of(led_cdev, struct rt2x00_led, led_dev); 235 container_of(led_cdev, struct rt2x00_led, led_dev);
315 u32 reg; 236 u32 reg;
316 237
317 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg); 238 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
318 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on); 239 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
319 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off); 240 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
320 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg); 241 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
321 242
322 return 0; 243 return 0;
323} 244}
@@ -360,7 +281,7 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
360 */ 281 */
361 mask = (0xf << crypto->bssidx); 282 mask = (0xf << crypto->bssidx);
362 283
363 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg); 284 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
364 reg &= mask; 285 reg &= mask;
365 286
366 if (reg && reg == mask) 287 if (reg && reg == mask)
@@ -397,16 +318,16 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
397 field.bit_offset = (3 * key->hw_key_idx); 318 field.bit_offset = (3 * key->hw_key_idx);
398 field.bit_mask = 0x7 << field.bit_offset; 319 field.bit_mask = 0x7 << field.bit_offset;
399 320
400 rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg); 321 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
401 rt2x00_set_field32(&reg, field, crypto->cipher); 322 rt2x00_set_field32(&reg, field, crypto->cipher);
402 rt73usb_register_write(rt2x00dev, SEC_CSR1, reg); 323 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
403 } else { 324 } else {
404 field.bit_offset = (3 * (key->hw_key_idx - 8)); 325 field.bit_offset = (3 * (key->hw_key_idx - 8));
405 field.bit_mask = 0x7 << field.bit_offset; 326 field.bit_mask = 0x7 << field.bit_offset;
406 327
407 rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg); 328 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
408 rt2x00_set_field32(&reg, field, crypto->cipher); 329 rt2x00_set_field32(&reg, field, crypto->cipher);
409 rt73usb_register_write(rt2x00dev, SEC_CSR5, reg); 330 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
410 } 331 }
411 332
412 /* 333 /*
@@ -429,12 +350,12 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
429 */ 350 */
430 mask = 1 << key->hw_key_idx; 351 mask = 1 << key->hw_key_idx;
431 352
432 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg); 353 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
433 if (crypto->cmd == SET_KEY) 354 if (crypto->cmd == SET_KEY)
434 reg |= mask; 355 reg |= mask;
435 else if (crypto->cmd == DISABLE_KEY) 356 else if (crypto->cmd == DISABLE_KEY)
436 reg &= ~mask; 357 reg &= ~mask;
437 rt73usb_register_write(rt2x00dev, SEC_CSR0, reg); 358 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
438 359
439 return 0; 360 return 0;
440} 361}
@@ -459,10 +380,10 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
459 * When both registers are full, we drop the key, 380 * When both registers are full, we drop the key,
460 * otherwise we use the first invalid entry. 381 * otherwise we use the first invalid entry.
461 */ 382 */
462 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg); 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
463 if (reg && reg == ~0) { 384 if (reg && reg == ~0) {
464 key->hw_key_idx = 32; 385 key->hw_key_idx = 32;
465 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg); 386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
466 if (reg && reg == ~0) 387 if (reg && reg == ~0)
467 return -ENOSPC; 388 return -ENOSPC;
468 } 389 }
@@ -490,14 +411,14 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
490 /* 411 /*
491 * Send the address and cipher type to the hardware register. 412 * Send the address and cipher type to the hardware register.
492 * This data fits within the CSR cache size, so we can use 413 * This data fits within the CSR cache size, so we can use
493 * rt73usb_register_multiwrite() directly. 414 * rt2x00usb_register_multiwrite() directly.
494 */ 415 */
495 memset(&addr_entry, 0, sizeof(addr_entry)); 416 memset(&addr_entry, 0, sizeof(addr_entry));
496 memcpy(&addr_entry, crypto->address, ETH_ALEN); 417 memcpy(&addr_entry, crypto->address, ETH_ALEN);
497 addr_entry.cipher = crypto->cipher; 418 addr_entry.cipher = crypto->cipher;
498 419
499 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 420 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
500 rt73usb_register_multiwrite(rt2x00dev, reg, 421 rt2x00usb_register_multiwrite(rt2x00dev, reg,
501 &addr_entry, sizeof(addr_entry)); 422 &addr_entry, sizeof(addr_entry));
502 423
503 /* 424 /*
@@ -505,9 +426,9 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
505 * without this received frames will not be decrypted 426 * without this received frames will not be decrypted
506 * by the hardware. 427 * by the hardware.
507 */ 428 */
508 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg); 429 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
509 reg |= (1 << crypto->bssidx); 430 reg |= (1 << crypto->bssidx);
510 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg); 431 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
511 432
512 /* 433 /*
513 * The driver does not support the IV/EIV generation 434 * The driver does not support the IV/EIV generation
@@ -530,21 +451,21 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
530 if (key->hw_key_idx < 32) { 451 if (key->hw_key_idx < 32) {
531 mask = 1 << key->hw_key_idx; 452 mask = 1 << key->hw_key_idx;
532 453
533 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg); 454 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
534 if (crypto->cmd == SET_KEY) 455 if (crypto->cmd == SET_KEY)
535 reg |= mask; 456 reg |= mask;
536 else if (crypto->cmd == DISABLE_KEY) 457 else if (crypto->cmd == DISABLE_KEY)
537 reg &= ~mask; 458 reg &= ~mask;
538 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg); 459 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
539 } else { 460 } else {
540 mask = 1 << (key->hw_key_idx - 32); 461 mask = 1 << (key->hw_key_idx - 32);
541 462
542 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg); 463 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
543 if (crypto->cmd == SET_KEY) 464 if (crypto->cmd == SET_KEY)
544 reg |= mask; 465 reg |= mask;
545 else if (crypto->cmd == DISABLE_KEY) 466 else if (crypto->cmd == DISABLE_KEY)
546 reg &= ~mask; 467 reg &= ~mask;
547 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg); 468 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
548 } 469 }
549 470
550 return 0; 471 return 0;
@@ -561,7 +482,7 @@ static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
561 * and broadcast frames will always be accepted since 482 * and broadcast frames will always be accepted since
562 * there is no filter for it at this time. 483 * there is no filter for it at this time.
563 */ 484 */
564 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 485 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
565 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
566 !(filter_flags & FIF_FCSFAIL)); 487 !(filter_flags & FIF_FCSFAIL));
567 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
@@ -579,7 +500,7 @@ static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
579 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0); 500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
580 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
581 !(filter_flags & FIF_CONTROL)); 502 !(filter_flags & FIF_CONTROL));
582 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 503 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
583} 504}
584 505
585static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, 506static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
@@ -598,16 +519,16 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
598 * bits which (when set to 0) will invalidate the entire beacon. 519 * bits which (when set to 0) will invalidate the entire beacon.
599 */ 520 */
600 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); 521 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
601 rt73usb_register_write(rt2x00dev, beacon_base, 0); 522 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
602 523
603 /* 524 /*
604 * Enable synchronisation. 525 * Enable synchronisation.
605 */ 526 */
606 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 527 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
607 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 528 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
608 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 529 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
609 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 530 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
610 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 531 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
611 } 532 }
612 533
613 if (flags & CONFIG_UPDATE_MAC) { 534 if (flags & CONFIG_UPDATE_MAC) {
@@ -615,7 +536,7 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
615 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 536 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
616 conf->mac[1] = cpu_to_le32(reg); 537 conf->mac[1] = cpu_to_le32(reg);
617 538
618 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, 539 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
619 conf->mac, sizeof(conf->mac)); 540 conf->mac, sizeof(conf->mac));
620 } 541 }
621 542
@@ -624,7 +545,7 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
624 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3); 545 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
625 conf->bssid[1] = cpu_to_le32(reg); 546 conf->bssid[1] = cpu_to_le32(reg);
626 547
627 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, 548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
628 conf->bssid, sizeof(conf->bssid)); 549 conf->bssid, sizeof(conf->bssid));
629 } 550 }
630} 551}
@@ -634,26 +555,26 @@ static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
634{ 555{
635 u32 reg; 556 u32 reg;
636 557
637 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 558 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
638 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); 559 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
639 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 560 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
640 561
641 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 562 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
642 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 563 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
643 !!erp->short_preamble); 564 !!erp->short_preamble);
644 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 565 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
645 566
646 rt73usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 567 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
647 568
648 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); 569 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
649 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 570 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
650 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); 571 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
651 572
652 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg); 573 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
653 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); 574 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
654 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
655 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); 576 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
656 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg); 577 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
657} 578}
658 579
659static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 580static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
@@ -799,14 +720,14 @@ static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
799 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 720 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
800 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 721 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
801 722
802 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg); 723 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
803 724
804 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 725 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
805 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); 726 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
806 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 727 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
807 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); 728 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
808 729
809 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg); 730 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
810 731
811 if (rt2x00_rf(&rt2x00dev->chip, RF5226) || 732 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
812 rt2x00_rf(&rt2x00dev->chip, RF5225)) 733 rt2x00_rf(&rt2x00dev->chip, RF5225))
@@ -896,12 +817,12 @@ static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
896{ 817{
897 u32 reg; 818 u32 reg;
898 819
899 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 820 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
900 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, 821 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
901 libconf->conf->long_frame_max_tx_count); 822 libconf->conf->long_frame_max_tx_count);
902 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, 823 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
903 libconf->conf->short_frame_max_tx_count); 824 libconf->conf->short_frame_max_tx_count);
904 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 825 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
905} 826}
906 827
907static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev, 828static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
@@ -909,18 +830,18 @@ static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
909{ 830{
910 u32 reg; 831 u32 reg;
911 832
912 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 833 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
913 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 834 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
914 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 835 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
915 836
916 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 837 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
917 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 838 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
918 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 839 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
919 840
920 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 841 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
921 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 842 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
922 libconf->conf->beacon_int * 16); 843 libconf->conf->beacon_int * 16);
923 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
924} 845}
925 846
926static void rt73usb_config(struct rt2x00_dev *rt2x00dev, 847static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
@@ -953,13 +874,13 @@ static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
953 /* 874 /*
954 * Update FCS error count from register. 875 * Update FCS error count from register.
955 */ 876 */
956 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); 877 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
957 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 878 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
958 879
959 /* 880 /*
960 * Update False CCA count from register. 881 * Update False CCA count from register.
961 */ 882 */
962 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); 883 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
963 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 884 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
964} 885}
965 886
@@ -1119,7 +1040,7 @@ static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1119 * Wait for stable hardware. 1040 * Wait for stable hardware.
1120 */ 1041 */
1121 for (i = 0; i < 100; i++) { 1042 for (i = 0; i < 100; i++) {
1122 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1043 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1123 if (reg) 1044 if (reg)
1124 break; 1045 break;
1125 msleep(1); 1046 msleep(1);
@@ -1161,13 +1082,13 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1161{ 1082{
1162 u32 reg; 1083 u32 reg;
1163 1084
1164 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1085 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1165 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); 1086 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1166 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); 1087 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1167 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1088 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1168 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1089 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1169 1090
1170 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg); 1091 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1171 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1092 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1172 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); 1093 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1173 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1094 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
@@ -1176,12 +1097,12 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1176 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); 1097 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1177 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1098 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1178 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); 1099 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1179 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg); 1100 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1180 1101
1181 /* 1102 /*
1182 * CCK TXD BBP registers 1103 * CCK TXD BBP registers
1183 */ 1104 */
1184 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg); 1105 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1185 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); 1106 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1186 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); 1107 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1187 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); 1108 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
@@ -1190,77 +1111,77 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1190 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); 1111 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1191 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); 1112 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1192 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); 1113 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1193 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg); 1114 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1194 1115
1195 /* 1116 /*
1196 * OFDM TXD BBP registers 1117 * OFDM TXD BBP registers
1197 */ 1118 */
1198 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg); 1119 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1199 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); 1120 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1200 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); 1121 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1201 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); 1122 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1202 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); 1123 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1203 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); 1124 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1204 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); 1125 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1205 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg); 1126 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1206 1127
1207 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg); 1128 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1208 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); 1129 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1209 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); 1130 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1210 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); 1131 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1211 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); 1132 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1212 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg); 1133 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1213 1134
1214 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg); 1135 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1215 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); 1136 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1216 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); 1137 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1217 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); 1138 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1218 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); 1139 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1219 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg); 1140 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1220 1141
1221 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1142 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1222 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0); 1143 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1223 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1144 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1224 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0); 1145 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1225 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1146 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1226 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1147 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1227 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1148 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1228 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1149 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1229 1150
1230 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1231 1152
1232 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg); 1153 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1233 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); 1154 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1234 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg); 1155 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1235 1156
1236 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); 1157 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1237 1158
1238 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1159 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1239 return -EBUSY; 1160 return -EBUSY;
1240 1161
1241 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); 1162 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1242 1163
1243 /* 1164 /*
1244 * Invalidate all Shared Keys (SEC_CSR0), 1165 * Invalidate all Shared Keys (SEC_CSR0),
1245 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1166 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1246 */ 1167 */
1247 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1168 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1248 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1169 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1249 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1170 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1250 1171
1251 reg = 0x000023b0; 1172 reg = 0x000023b0;
1252 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 1173 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1253 rt2x00_rf(&rt2x00dev->chip, RF2527)) 1174 rt2x00_rf(&rt2x00dev->chip, RF2527))
1254 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1); 1175 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1255 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg); 1176 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1256 1177
1257 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); 1178 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1258 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1179 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1259 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); 1180 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1260 1181
1261 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); 1182 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1262 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); 1183 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1263 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); 1184 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1264 1185
1265 /* 1186 /*
1266 * Clear all beacons 1187 * Clear all beacons
@@ -1268,36 +1189,36 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1268 * the first byte since that byte contains the VALID and OWNER 1189 * the first byte since that byte contains the VALID and OWNER
1269 * bits which (when set to 0) will invalidate the entire beacon. 1190 * bits which (when set to 0) will invalidate the entire beacon.
1270 */ 1191 */
1271 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1192 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1272 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1193 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1273 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1194 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1274 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1195 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1275 1196
1276 /* 1197 /*
1277 * We must clear the error counters. 1198 * We must clear the error counters.
1278 * These registers are cleared on read, 1199 * These registers are cleared on read,
1279 * so we may pass a useless variable to store the value. 1200 * so we may pass a useless variable to store the value.
1280 */ 1201 */
1281 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); 1202 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1282 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); 1203 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1283 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg); 1204 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1284 1205
1285 /* 1206 /*
1286 * Reset MAC and BBP registers. 1207 * Reset MAC and BBP registers.
1287 */ 1208 */
1288 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1209 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1289 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); 1210 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1290 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); 1211 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1291 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1212 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1292 1213
1293 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1214 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1294 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); 1215 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1295 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); 1216 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1296 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1217 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1297 1218
1298 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1299 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); 1220 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1300 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1301 1222
1302 return 0; 1223 return 0;
1303} 1224}
@@ -1375,11 +1296,11 @@ static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1375{ 1296{
1376 u32 reg; 1297 u32 reg;
1377 1298
1378 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1299 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1379 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1300 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1380 (state == STATE_RADIO_RX_OFF) || 1301 (state == STATE_RADIO_RX_OFF) ||
1381 (state == STATE_RADIO_RX_OFF_LINK)); 1302 (state == STATE_RADIO_RX_OFF_LINK));
1382 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1303 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1383} 1304}
1384 1305
1385static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) 1306static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1396,12 +1317,12 @@ static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1396 1317
1397static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) 1318static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1398{ 1319{
1399 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1320 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1400 1321
1401 /* 1322 /*
1402 * Disable synchronisation. 1323 * Disable synchronisation.
1403 */ 1324 */
1404 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); 1325 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1405 1326
1406 rt2x00usb_disable_radio(rt2x00dev); 1327 rt2x00usb_disable_radio(rt2x00dev);
1407} 1328}
@@ -1414,10 +1335,10 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1414 1335
1415 put_to_sleep = (state != STATE_AWAKE); 1336 put_to_sleep = (state != STATE_AWAKE);
1416 1337
1417 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1338 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1418 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1339 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1419 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1340 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1420 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg); 1341 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1421 1342
1422 /* 1343 /*
1423 * Device is not guaranteed to be in the requested state yet. 1344 * Device is not guaranteed to be in the requested state yet.
@@ -1425,7 +1346,7 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1425 * device has entered the correct state. 1346 * device has entered the correct state.
1426 */ 1347 */
1427 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1348 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1428 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1349 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1429 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); 1350 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1430 if (state == !put_to_sleep) 1351 if (state == !put_to_sleep)
1431 return 0; 1352 return 0;
@@ -1565,11 +1486,11 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1565 * Disable beaconing while we are reloading the beacon data, 1486 * Disable beaconing while we are reloading the beacon data,
1566 * otherwise we might be sending out invalid data. 1487 * otherwise we might be sending out invalid data.
1567 */ 1488 */
1568 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1489 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1569 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1490 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1570 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1491 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1571 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1492 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1572 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1493 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1573 1494
1574 /* 1495 /*
1575 * Write entire beacon with descriptor to register. 1496 * Write entire beacon with descriptor to register.
@@ -1616,14 +1537,14 @@ static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1616 * For Wi-Fi faily generated beacons between participating stations. 1537 * For Wi-Fi faily generated beacons between participating stations.
1617 * Set TBTT phase adaptive adjustment step to 8us (default 16us) 1538 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1618 */ 1539 */
1619 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1540 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1620 1541
1621 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1542 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1622 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { 1543 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1623 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 1544 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1624 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 1545 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1625 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1546 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1626 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1547 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1627 } 1548 }
1628} 1549}
1629 1550
@@ -1862,7 +1783,7 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1862 * Identify RF chipset. 1783 * Identify RF chipset.
1863 */ 1784 */
1864 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1785 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1865 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1786 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1866 rt2x00_set_chip(rt2x00dev, RT2571, value, reg); 1787 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1867 1788
1868 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) { 1789 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
@@ -2216,33 +2137,33 @@ static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2216 field.bit_offset = queue_idx * 16; 2137 field.bit_offset = queue_idx * 16;
2217 field.bit_mask = 0xffff << field.bit_offset; 2138 field.bit_mask = 0xffff << field.bit_offset;
2218 2139
2219 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg); 2140 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2220 rt2x00_set_field32(&reg, field, queue->txop); 2141 rt2x00_set_field32(&reg, field, queue->txop);
2221 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg); 2142 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2222 } else if (queue_idx < 4) { 2143 } else if (queue_idx < 4) {
2223 field.bit_offset = (queue_idx - 2) * 16; 2144 field.bit_offset = (queue_idx - 2) * 16;
2224 field.bit_mask = 0xffff << field.bit_offset; 2145 field.bit_mask = 0xffff << field.bit_offset;
2225 2146
2226 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg); 2147 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2227 rt2x00_set_field32(&reg, field, queue->txop); 2148 rt2x00_set_field32(&reg, field, queue->txop);
2228 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg); 2149 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2229 } 2150 }
2230 2151
2231 /* Update WMM registers */ 2152 /* Update WMM registers */
2232 field.bit_offset = queue_idx * 4; 2153 field.bit_offset = queue_idx * 4;
2233 field.bit_mask = 0xf << field.bit_offset; 2154 field.bit_mask = 0xf << field.bit_offset;
2234 2155
2235 rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg); 2156 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2236 rt2x00_set_field32(&reg, field, queue->aifs); 2157 rt2x00_set_field32(&reg, field, queue->aifs);
2237 rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg); 2158 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2238 2159
2239 rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg); 2160 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2240 rt2x00_set_field32(&reg, field, queue->cw_min); 2161 rt2x00_set_field32(&reg, field, queue->cw_min);
2241 rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg); 2162 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2242 2163
2243 rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg); 2164 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2244 rt2x00_set_field32(&reg, field, queue->cw_max); 2165 rt2x00_set_field32(&reg, field, queue->cw_max);
2245 rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg); 2166 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2246 2167
2247 return 0; 2168 return 0;
2248} 2169}
@@ -2260,9 +2181,9 @@ static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2260 u64 tsf; 2181 u64 tsf;
2261 u32 reg; 2182 u32 reg;
2262 2183
2263 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg); 2184 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2264 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2185 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2265 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg); 2186 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2266 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2187 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2267 2188
2268 return tsf; 2189 return tsf;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:18:03 -0500