diff options
author | David S. Miller <davem@davemloft.net> | 2010-09-02 15:45:44 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-09-02 15:45:44 -0400 |
commit | 7162f6691e9d39d8d866574687cddb3f1ec65d72 (patch) | |
tree | c511679caf5c825ede4728870c513f92f4f1616b /drivers/net/wireless/rt2x00/rt61pci.c | |
parent | 250e061e1d3e26600236a3dd9172e7f5f5916c00 (diff) | |
parent | 78ab952717b62c0ba6ca7f7a27eaa0486685e45f (diff) |
Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt61pci.c | 57 |
1 files changed, 30 insertions, 27 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index 3f8d10b76fee..3a7759929190 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c | |||
@@ -1766,12 +1766,11 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1766 | /* | 1766 | /* |
1767 | * TX descriptor initialization | 1767 | * TX descriptor initialization |
1768 | */ | 1768 | */ |
1769 | static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | 1769 | static void rt61pci_write_tx_desc(struct queue_entry *entry, |
1770 | struct sk_buff *skb, | ||
1771 | struct txentry_desc *txdesc) | 1770 | struct txentry_desc *txdesc) |
1772 | { | 1771 | { |
1773 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); | 1772 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
1774 | struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; | 1773 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
1775 | __le32 *txd = entry_priv->desc; | 1774 | __le32 *txd = entry_priv->desc; |
1776 | u32 word; | 1775 | u32 word; |
1777 | 1776 | ||
@@ -1779,7 +1778,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1779 | * Start writing the descriptor words. | 1778 | * Start writing the descriptor words. |
1780 | */ | 1779 | */ |
1781 | rt2x00_desc_read(txd, 1, &word); | 1780 | rt2x00_desc_read(txd, 1, &word); |
1782 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); | 1781 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid); |
1783 | rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); | 1782 | rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); |
1784 | rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); | 1783 | rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); |
1785 | rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); | 1784 | rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); |
@@ -1802,15 +1801,15 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1802 | } | 1801 | } |
1803 | 1802 | ||
1804 | rt2x00_desc_read(txd, 5, &word); | 1803 | rt2x00_desc_read(txd, 5, &word); |
1805 | rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid); | 1804 | rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); |
1806 | rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, | 1805 | rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, |
1807 | skbdesc->entry->entry_idx); | 1806 | skbdesc->entry->entry_idx); |
1808 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, | 1807 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, |
1809 | TXPOWER_TO_DEV(rt2x00dev->tx_power)); | 1808 | TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); |
1810 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); | 1809 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1811 | rt2x00_desc_write(txd, 5, word); | 1810 | rt2x00_desc_write(txd, 5, word); |
1812 | 1811 | ||
1813 | if (txdesc->queue != QID_BEACON) { | 1812 | if (txdesc->qid != QID_BEACON) { |
1814 | rt2x00_desc_read(txd, 6, &word); | 1813 | rt2x00_desc_read(txd, 6, &word); |
1815 | rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, | 1814 | rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, |
1816 | skbdesc->skb_dma); | 1815 | skbdesc->skb_dma); |
@@ -1857,7 +1856,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1857 | */ | 1856 | */ |
1858 | skbdesc->desc = txd; | 1857 | skbdesc->desc = txd; |
1859 | skbdesc->desc_len = | 1858 | skbdesc->desc_len = |
1860 | (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE; | 1859 | (txdesc->qid == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE; |
1861 | } | 1860 | } |
1862 | 1861 | ||
1863 | /* | 1862 | /* |
@@ -1882,7 +1881,7 @@ static void rt61pci_write_beacon(struct queue_entry *entry, | |||
1882 | /* | 1881 | /* |
1883 | * Write the TX descriptor for the beacon. | 1882 | * Write the TX descriptor for the beacon. |
1884 | */ | 1883 | */ |
1885 | rt61pci_write_tx_desc(rt2x00dev, entry->skb, txdesc); | 1884 | rt61pci_write_tx_desc(entry, txdesc); |
1886 | 1885 | ||
1887 | /* | 1886 | /* |
1888 | * Dump beacon to userspace through debugfs. | 1887 | * Dump beacon to userspace through debugfs. |
@@ -1918,34 +1917,34 @@ static void rt61pci_write_beacon(struct queue_entry *entry, | |||
1918 | entry->skb = NULL; | 1917 | entry->skb = NULL; |
1919 | } | 1918 | } |
1920 | 1919 | ||
1921 | static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | 1920 | static void rt61pci_kick_tx_queue(struct data_queue *queue) |
1922 | const enum data_queue_qid queue) | ||
1923 | { | 1921 | { |
1922 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
1924 | u32 reg; | 1923 | u32 reg; |
1925 | 1924 | ||
1926 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); | 1925 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
1927 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE)); | 1926 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE)); |
1928 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK)); | 1927 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK)); |
1929 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI)); | 1928 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI)); |
1930 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO)); | 1929 | rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO)); |
1931 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); | 1930 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
1932 | } | 1931 | } |
1933 | 1932 | ||
1934 | static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, | 1933 | static void rt61pci_kill_tx_queue(struct data_queue *queue) |
1935 | const enum data_queue_qid qid) | ||
1936 | { | 1934 | { |
1935 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
1937 | u32 reg; | 1936 | u32 reg; |
1938 | 1937 | ||
1939 | if (qid == QID_BEACON) { | 1938 | if (queue->qid == QID_BEACON) { |
1940 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); | 1939 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); |
1941 | return; | 1940 | return; |
1942 | } | 1941 | } |
1943 | 1942 | ||
1944 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); | 1943 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); |
1945 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE)); | 1944 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE)); |
1946 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK)); | 1945 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK)); |
1947 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI)); | 1946 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI)); |
1948 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO)); | 1947 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO)); |
1949 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); | 1948 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
1950 | } | 1949 | } |
1951 | 1950 | ||
@@ -2657,13 +2656,17 @@ static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
2657 | spec->channels_info = info; | 2656 | spec->channels_info = info; |
2658 | 2657 | ||
2659 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); | 2658 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); |
2660 | for (i = 0; i < 14; i++) | 2659 | for (i = 0; i < 14; i++) { |
2661 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | 2660 | info[i].max_power = MAX_TXPOWER; |
2661 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | ||
2662 | } | ||
2662 | 2663 | ||
2663 | if (spec->num_channels > 14) { | 2664 | if (spec->num_channels > 14) { |
2664 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | 2665 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); |
2665 | for (i = 14; i < spec->num_channels; i++) | 2666 | for (i = 14; i < spec->num_channels; i++) { |
2666 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | 2667 | info[i].max_power = MAX_TXPOWER; |
2668 | info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]); | ||
2669 | } | ||
2667 | } | 2670 | } |
2668 | 2671 | ||
2669 | return 0; | 2672 | return 0; |