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authorIvo van Doorn <IvDoorn@gmail.com>2008-02-05 16:42:23 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-02-29 15:19:27 -0500
commit181d6902b6bad978d157e69479c95cc0ff213a76 (patch)
tree7a90b8a949a50bc8db6b7b5b2d76d5671fb9a89e /drivers/net/wireless/rt2x00/rt61pci.c
parent811aa9cad1bd927999888ab56ed9592519d2fef6 (diff)
rt2x00: Queue handling overhaul
This introduces a big queue handling overhaul, this also renames "ring" to "queues". Move queue handling into rt2x00queue.c and the matching header, use Kerneldoc to improve rt2x00 library documentation. Access to the queues is now protected under a spinlock, this to prevent race conditions which could corrupt the indexing system of the queue. Each queue entry allocates x bytes for driver/device specific data, this cleans up the queue structure significantly and improves code readability. rt2500usb no longer needs 2 entries in the beacon queue to correctly send out the guardian byte. This is now handled in the entry specific structure. rt61 and rt73 now use the correct descriptor size for beacon frames, since this data is written into the registers not the entire TXD descriptor was used but instead of a subset of it named TXINFO. Finally this also fixes numerous other bugs related to incorrect beacon handling or beacon related code. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c256
1 files changed, 136 insertions, 120 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 42cd1dc09164..547fa33e99dd 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -262,7 +262,7 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
262 u32 reg; 262 u32 reg;
263 263
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg); 264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);; 265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
266} 266}
267#else 267#else
268#define rt61pci_rfkill_poll NULL 268#define rt61pci_rfkill_poll NULL
@@ -990,49 +990,49 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
990} 990}
991 991
992static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 992static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
993 struct data_entry *entry) 993 struct queue_entry *entry)
994{ 994{
995 __le32 *rxd = entry->priv; 995 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
996 u32 word; 996 u32 word;
997 997
998 rt2x00_desc_read(rxd, 5, &word); 998 rt2x00_desc_read(priv_rx->desc, 5, &word);
999 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, 999 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
1000 entry->data_dma); 1000 rt2x00_desc_write(priv_rx->desc, 5, word);
1001 rt2x00_desc_write(rxd, 5, word);
1002 1001
1003 rt2x00_desc_read(rxd, 0, &word); 1002 rt2x00_desc_read(priv_rx->desc, 0, &word);
1004 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 1003 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1005 rt2x00_desc_write(rxd, 0, word); 1004 rt2x00_desc_write(priv_rx->desc, 0, word);
1006} 1005}
1007 1006
1008static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev, 1007static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1009 struct data_entry *entry) 1008 struct queue_entry *entry)
1010{ 1009{
1011 __le32 *txd = entry->priv; 1010 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1012 u32 word; 1011 u32 word;
1013 1012
1014 rt2x00_desc_read(txd, 1, &word); 1013 rt2x00_desc_read(priv_tx->desc, 1, &word);
1015 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); 1014 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1016 rt2x00_desc_write(txd, 1, word); 1015 rt2x00_desc_write(priv_tx->desc, 1, word);
1017 1016
1018 rt2x00_desc_read(txd, 5, &word); 1017 rt2x00_desc_read(priv_tx->desc, 5, &word);
1019 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->ring->queue_idx); 1018 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1020 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); 1019 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1021 rt2x00_desc_write(txd, 5, word); 1020 rt2x00_desc_write(priv_tx->desc, 5, word);
1022 1021
1023 rt2x00_desc_read(txd, 6, &word); 1022 rt2x00_desc_read(priv_tx->desc, 6, &word);
1024 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1023 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
1025 entry->data_dma); 1024 rt2x00_desc_write(priv_tx->desc, 6, word);
1026 rt2x00_desc_write(txd, 6, word);
1027 1025
1028 rt2x00_desc_read(txd, 0, &word); 1026 rt2x00_desc_read(priv_tx->desc, 0, &word);
1029 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 1027 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1030 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 1028 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1031 rt2x00_desc_write(txd, 0, word); 1029 rt2x00_desc_write(priv_tx->desc, 0, word);
1032} 1030}
1033 1031
1034static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev) 1032static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1035{ 1033{
1034 struct queue_entry_priv_pci_rx *priv_rx;
1035 struct queue_entry_priv_pci_tx *priv_tx;
1036 u32 reg; 1036 u32 reg;
1037 1037
1038 /* 1038 /*
@@ -1040,59 +1040,50 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1040 */ 1040 */
1041 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg); 1041 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1042 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE, 1042 rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1043 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit); 1043 rt2x00dev->tx[0].limit);
1044 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE, 1044 rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1045 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); 1045 rt2x00dev->tx[1].limit);
1046 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE, 1046 rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1047 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit); 1047 rt2x00dev->tx[2].limit);
1048 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE, 1048 rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1049 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit); 1049 rt2x00dev->tx[3].limit);
1050 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg); 1050 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1051 1051
1052 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg); 1052 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1053 rt2x00_set_field32(&reg, TX_RING_CSR1_MGMT_RING_SIZE,
1054 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1055 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE, 1053 rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1056 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size / 1054 rt2x00dev->tx[0].desc_size / 4);
1057 4);
1058 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); 1055 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1059 1056
1057 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1060 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1058 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1061 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, 1059 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
1062 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1063 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1060 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1064 1061
1062 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1065 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1063 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1066 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, 1064 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
1067 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1068 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1065 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1069 1066
1067 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1070 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1068 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1071 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, 1069 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
1072 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1073 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1070 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1074 1071
1072 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1075 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1073 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1076 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, 1074 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
1077 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1078 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1075 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1079 1076
1080 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, &reg);
1081 rt2x00_set_field32(&reg, MGMT_BASE_CSR_RING_REGISTER,
1082 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1083 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1084
1085 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1077 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1086 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, 1078 rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1087 rt2x00dev->rx->stats.limit);
1088 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE, 1079 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1089 rt2x00dev->rx->desc_size / 4); 1080 rt2x00dev->rx->desc_size / 4);
1090 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1081 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1091 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); 1082 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1092 1083
1084 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1093 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1085 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1094 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, 1086 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
1095 rt2x00dev->rx->data_dma);
1096 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1087 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1097 1088
1098 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1089 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
@@ -1108,7 +1099,7 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1108 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); 1099 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1109 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); 1100 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1110 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); 1101 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1111 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1); 1102 rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 0);
1112 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); 1103 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1113 1104
1114 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg); 1105 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
@@ -1375,7 +1366,7 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1375 /* 1366 /*
1376 * Initialize all registers. 1367 * Initialize all registers.
1377 */ 1368 */
1378 if (rt61pci_init_rings(rt2x00dev) || 1369 if (rt61pci_init_queues(rt2x00dev) ||
1379 rt61pci_init_registers(rt2x00dev) || 1370 rt61pci_init_registers(rt2x00dev) ||
1380 rt61pci_init_bbp(rt2x00dev)) { 1371 rt61pci_init_bbp(rt2x00dev)) {
1381 ERROR(rt2x00dev, "Register initialization failed.\n"); 1372 ERROR(rt2x00dev, "Register initialization failed.\n");
@@ -1508,10 +1499,10 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1508 */ 1499 */
1509static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1500static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1510 struct sk_buff *skb, 1501 struct sk_buff *skb,
1511 struct txdata_entry_desc *desc, 1502 struct txentry_desc *txdesc,
1512 struct ieee80211_tx_control *control) 1503 struct ieee80211_tx_control *control)
1513{ 1504{
1514 struct skb_desc *skbdesc = get_skb_desc(skb); 1505 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1515 __le32 *txd = skbdesc->desc; 1506 __le32 *txd = skbdesc->desc;
1516 u32 word; 1507 u32 word;
1517 1508
@@ -1519,19 +1510,19 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1519 * Start writing the descriptor words. 1510 * Start writing the descriptor words.
1520 */ 1511 */
1521 rt2x00_desc_read(txd, 1, &word); 1512 rt2x00_desc_read(txd, 1, &word);
1522 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue); 1513 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1523 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs); 1514 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1524 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min); 1515 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1525 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max); 1516 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1526 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER); 1517 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1527 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1); 1518 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1528 rt2x00_desc_write(txd, 1, word); 1519 rt2x00_desc_write(txd, 1, word);
1529 1520
1530 rt2x00_desc_read(txd, 2, &word); 1521 rt2x00_desc_read(txd, 2, &word);
1531 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal); 1522 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1532 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service); 1523 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1533 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low); 1524 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1534 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high); 1525 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1535 rt2x00_desc_write(txd, 2, word); 1526 rt2x00_desc_write(txd, 2, word);
1536 1527
1537 rt2x00_desc_read(txd, 5, &word); 1528 rt2x00_desc_read(txd, 5, &word);
@@ -1548,21 +1539,21 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1548 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1539 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1549 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1540 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1550 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1541 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1551 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags)); 1542 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1552 rt2x00_set_field32(&word, TXD_W0_ACK, 1543 rt2x00_set_field32(&word, TXD_W0_ACK,
1553 test_bit(ENTRY_TXD_ACK, &desc->flags)); 1544 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1554 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, 1545 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1555 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags)); 1546 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1556 rt2x00_set_field32(&word, TXD_W0_OFDM, 1547 rt2x00_set_field32(&word, TXD_W0_OFDM,
1557 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags)); 1548 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1558 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs); 1549 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1559 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1550 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1560 !!(control->flags & 1551 !!(control->flags &
1561 IEEE80211_TXCTL_LONG_RETRY_LIMIT)); 1552 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1562 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0); 1553 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1563 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); 1554 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1564 rt2x00_set_field32(&word, TXD_W0_BURST, 1555 rt2x00_set_field32(&word, TXD_W0_BURST,
1565 test_bit(ENTRY_TXD_BURST, &desc->flags)); 1556 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1566 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1557 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1567 rt2x00_desc_write(txd, 0, word); 1558 rt2x00_desc_write(txd, 0, word);
1568} 1559}
@@ -1648,28 +1639,28 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1648 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; 1639 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1649} 1640}
1650 1641
1651static void rt61pci_fill_rxdone(struct data_entry *entry, 1642static void rt61pci_fill_rxdone(struct queue_entry *entry,
1652 struct rxdata_entry_desc *desc) 1643 struct rxdone_entry_desc *rxdesc)
1653{ 1644{
1654 __le32 *rxd = entry->priv; 1645 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1655 u32 word0; 1646 u32 word0;
1656 u32 word1; 1647 u32 word1;
1657 1648
1658 rt2x00_desc_read(rxd, 0, &word0); 1649 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1659 rt2x00_desc_read(rxd, 1, &word1); 1650 rt2x00_desc_read(priv_rx->desc, 1, &word1);
1660 1651
1661 desc->flags = 0; 1652 rxdesc->flags = 0;
1662 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1653 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1663 desc->flags |= RX_FLAG_FAILED_FCS_CRC; 1654 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1664 1655
1665 /* 1656 /*
1666 * Obtain the status about this packet. 1657 * Obtain the status about this packet.
1667 */ 1658 */
1668 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); 1659 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1669 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1); 1660 rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1670 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM); 1661 rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1671 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1662 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1672 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS); 1663 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1673} 1664}
1674 1665
1675/* 1666/*
@@ -1677,17 +1668,16 @@ static void rt61pci_fill_rxdone(struct data_entry *entry,
1677 */ 1668 */
1678static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) 1669static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1679{ 1670{
1680 struct data_ring *ring; 1671 struct data_queue *queue;
1681 struct data_entry *entry; 1672 struct queue_entry *entry;
1682 struct data_entry *entry_done; 1673 struct queue_entry *entry_done;
1683 __le32 *txd; 1674 struct queue_entry_priv_pci_tx *priv_tx;
1675 struct txdone_entry_desc txdesc;
1684 u32 word; 1676 u32 word;
1685 u32 reg; 1677 u32 reg;
1686 u32 old_reg; 1678 u32 old_reg;
1687 int type; 1679 int type;
1688 int index; 1680 int index;
1689 int tx_status;
1690 int retry;
1691 1681
1692 /* 1682 /*
1693 * During each loop we will compare the freshly read 1683 * During each loop we will compare the freshly read
@@ -1710,11 +1700,11 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1710 1700
1711 /* 1701 /*
1712 * Skip this entry when it contains an invalid 1702 * Skip this entry when it contains an invalid
1713 * ring identication number. 1703 * queue identication number.
1714 */ 1704 */
1715 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 1705 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1716 ring = rt2x00lib_get_ring(rt2x00dev, type); 1706 queue = rt2x00queue_get_queue(rt2x00dev, type);
1717 if (unlikely(!ring)) 1707 if (unlikely(!queue))
1718 continue; 1708 continue;
1719 1709
1720 /* 1710 /*
@@ -1722,36 +1712,40 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1722 * index number. 1712 * index number.
1723 */ 1713 */
1724 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); 1714 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1725 if (unlikely(index >= ring->stats.limit)) 1715 if (unlikely(index >= queue->limit))
1726 continue; 1716 continue;
1727 1717
1728 entry = &ring->entry[index]; 1718 entry = &queue->entries[index];
1729 txd = entry->priv; 1719 priv_tx = entry->priv_data;
1730 rt2x00_desc_read(txd, 0, &word); 1720 rt2x00_desc_read(priv_tx->desc, 0, &word);
1731 1721
1732 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1722 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1733 !rt2x00_get_field32(word, TXD_W0_VALID)) 1723 !rt2x00_get_field32(word, TXD_W0_VALID))
1734 return; 1724 return;
1735 1725
1736 entry_done = rt2x00_get_data_entry_done(ring); 1726 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1737 while (entry != entry_done) { 1727 while (entry != entry_done) {
1738 /* Catch up. Just report any entries we missed as 1728 /* Catch up.
1739 * failed. */ 1729 * Just report any entries we missed as failed.
1730 */
1740 WARNING(rt2x00dev, 1731 WARNING(rt2x00dev,
1741 "TX status report missed for entry %p\n", 1732 "TX status report missed for entry %d\n",
1742 entry_done); 1733 entry_done->entry_idx);
1743 rt2x00pci_txdone(rt2x00dev, entry_done, TX_FAIL_OTHER, 1734
1744 0); 1735 txdesc.status = TX_FAIL_OTHER;
1745 entry_done = rt2x00_get_data_entry_done(ring); 1736 txdesc.retry = 0;
1737
1738 rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1739 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1746 } 1740 }
1747 1741
1748 /* 1742 /*
1749 * Obtain the status about this packet. 1743 * Obtain the status about this packet.
1750 */ 1744 */
1751 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT); 1745 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1752 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); 1746 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1753 1747
1754 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry); 1748 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1755 } 1749 }
1756} 1750}
1757 1751
@@ -2381,9 +2375,9 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2381 struct ieee80211_tx_control *control) 2375 struct ieee80211_tx_control *control)
2382{ 2376{
2383 struct rt2x00_dev *rt2x00dev = hw->priv; 2377 struct rt2x00_dev *rt2x00dev = hw->priv;
2384 struct skb_desc *desc; 2378 struct skb_frame_desc *skbdesc;
2385 struct data_ring *ring; 2379 struct data_queue *queue;
2386 struct data_entry *entry; 2380 struct queue_entry *entry;
2387 2381
2388 /* 2382 /*
2389 * Just in case the ieee80211 doesn't set this, 2383 * Just in case the ieee80211 doesn't set this,
@@ -2391,15 +2385,15 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2391 * initialization. 2385 * initialization.
2392 */ 2386 */
2393 control->queue = IEEE80211_TX_QUEUE_BEACON; 2387 control->queue = IEEE80211_TX_QUEUE_BEACON;
2394 ring = rt2x00lib_get_ring(rt2x00dev, control->queue); 2388 queue = rt2x00queue_get_queue(rt2x00dev, control->queue);
2395 entry = rt2x00_get_data_entry(ring); 2389 entry = rt2x00queue_get_entry(queue, Q_INDEX);
2396 2390
2397 /* 2391 /*
2398 * We need to append the descriptor in front of the 2392 * We need to append the descriptor in front of the
2399 * beacon frame. 2393 * beacon frame.
2400 */ 2394 */
2401 if (skb_headroom(skb) < TXD_DESC_SIZE) { 2395 if (skb_headroom(skb) < queue->desc_size) {
2402 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) { 2396 if (pskb_expand_head(skb, queue->desc_size, 0, GFP_ATOMIC)) {
2403 dev_kfree_skb(skb); 2397 dev_kfree_skb(skb);
2404 return -ENOMEM; 2398 return -ENOMEM;
2405 } 2399 }
@@ -2408,19 +2402,19 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2408 /* 2402 /*
2409 * Add the descriptor in front of the skb. 2403 * Add the descriptor in front of the skb.
2410 */ 2404 */
2411 skb_push(skb, ring->desc_size); 2405 skb_push(skb, queue->desc_size);
2412 memset(skb->data, 0, ring->desc_size); 2406 memset(skb->data, 0, queue->desc_size);
2413 2407
2414 /* 2408 /*
2415 * Fill in skb descriptor 2409 * Fill in skb descriptor
2416 */ 2410 */
2417 desc = get_skb_desc(skb); 2411 skbdesc = get_skb_frame_desc(skb);
2418 desc->desc_len = ring->desc_size; 2412 memset(skbdesc, 0, sizeof(*skbdesc));
2419 desc->data_len = skb->len - ring->desc_size; 2413 skbdesc->data = skb->data + queue->desc_size;
2420 desc->desc = skb->data; 2414 skbdesc->data_len = queue->data_size;
2421 desc->data = skb->data + ring->desc_size; 2415 skbdesc->desc = skb->data;
2422 desc->ring = ring; 2416 skbdesc->desc_len = queue->desc_size;
2423 desc->entry = entry; 2417 skbdesc->entry = entry;
2424 2418
2425 rt2x00lib_write_tx_desc(rt2x00dev, skb, control); 2419 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2426 2420
@@ -2479,12 +2473,34 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2479 .config = rt61pci_config, 2473 .config = rt61pci_config,
2480}; 2474};
2481 2475
2476static const struct data_queue_desc rt61pci_queue_rx = {
2477 .entry_num = RX_ENTRIES,
2478 .data_size = DATA_FRAME_SIZE,
2479 .desc_size = RXD_DESC_SIZE,
2480 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
2481};
2482
2483static const struct data_queue_desc rt61pci_queue_tx = {
2484 .entry_num = TX_ENTRIES,
2485 .data_size = DATA_FRAME_SIZE,
2486 .desc_size = TXD_DESC_SIZE,
2487 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2488};
2489
2490static const struct data_queue_desc rt61pci_queue_bcn = {
2491 .entry_num = BEACON_ENTRIES,
2492 .data_size = MGMT_FRAME_SIZE,
2493 .desc_size = TXINFO_SIZE,
2494 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
2495};
2496
2482static const struct rt2x00_ops rt61pci_ops = { 2497static const struct rt2x00_ops rt61pci_ops = {
2483 .name = KBUILD_MODNAME, 2498 .name = KBUILD_MODNAME,
2484 .rxd_size = RXD_DESC_SIZE,
2485 .txd_size = TXD_DESC_SIZE,
2486 .eeprom_size = EEPROM_SIZE, 2499 .eeprom_size = EEPROM_SIZE,
2487 .rf_size = RF_SIZE, 2500 .rf_size = RF_SIZE,
2501 .rx = &rt61pci_queue_rx,
2502 .tx = &rt61pci_queue_tx,
2503 .bcn = &rt61pci_queue_bcn,
2488 .lib = &rt61pci_rt2x00_ops, 2504 .lib = &rt61pci_rt2x00_ops,
2489 .hw = &rt61pci_mac80211_ops, 2505 .hw = &rt61pci_mac80211_ops,
2490#ifdef CONFIG_RT2X00_LIB_DEBUGFS 2506#ifdef CONFIG_RT2X00_LIB_DEBUGFS