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authorIvo van Doorn <ivdoorn@gmail.com>2008-02-17 11:33:24 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-02-29 15:37:22 -0500
commit30b3a23c2594e122e7086f97b5252a87eaf8a817 (patch)
tree6c97b928fce785471236543fe71bce3b6d0324cb /drivers/net/wireless/rt2x00/rt61pci.c
parente542239f639fa4e7b13a949d39d44ff1eccf7e3a (diff)
rt2x00: Fix Descriptor DMA initialization
As Adam Baker reported the DMA address for the descriptor base was incorrectly initialized in the PCI drivers. Instead of the DMA base for the descriptor, the DMA base for the data was passed resulting in a broken TX/RX state for PCI drivers. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 75f61f3c47b6..dcc694eb8b3b 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -975,7 +975,8 @@ static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
975 u32 word; 975 u32 word;
976 976
977 rt2x00_desc_read(priv_rx->desc, 5, &word); 977 rt2x00_desc_read(priv_rx->desc, 5, &word);
978 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma); 978 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
979 priv_rx->data_dma);
979 rt2x00_desc_write(priv_rx->desc, 5, word); 980 rt2x00_desc_write(priv_rx->desc, 5, word);
980 981
981 rt2x00_desc_read(priv_rx->desc, 0, &word); 982 rt2x00_desc_read(priv_rx->desc, 0, &word);
@@ -999,7 +1000,8 @@ static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
999 rt2x00_desc_write(priv_tx->desc, 5, word); 1000 rt2x00_desc_write(priv_tx->desc, 5, word);
1000 1001
1001 rt2x00_desc_read(priv_tx->desc, 6, &word); 1002 rt2x00_desc_read(priv_tx->desc, 6, &word);
1002 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma); 1003 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1004 priv_tx->data_dma);
1003 rt2x00_desc_write(priv_tx->desc, 6, word); 1005 rt2x00_desc_write(priv_tx->desc, 6, word);
1004 1006
1005 rt2x00_desc_read(priv_tx->desc, 0, &word); 1007 rt2x00_desc_read(priv_tx->desc, 0, &word);
@@ -1035,22 +1037,26 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1035 1037
1036 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 1038 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1037 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1039 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1038 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma); 1040 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1041 priv_tx->desc_dma);
1039 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1042 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1040 1043
1041 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 1044 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1042 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1045 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1043 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma); 1046 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1047 priv_tx->desc_dma);
1044 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1048 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1045 1049
1046 priv_tx = rt2x00dev->tx[2].entries[0].priv_data; 1050 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1047 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1051 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1048 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma); 1052 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1053 priv_tx->desc_dma);
1049 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1054 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1050 1055
1051 priv_tx = rt2x00dev->tx[3].entries[0].priv_data; 1056 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1052 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1057 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1053 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma); 1058 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1059 priv_tx->desc_dma);
1054 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1060 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1055 1061
1056 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1062 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
@@ -1062,7 +1068,8 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1062 1068
1063 priv_rx = rt2x00dev->rx->entries[0].priv_data; 1069 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1064 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1070 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1065 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, priv_rx->dma); 1071 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1072 priv_rx->desc_dma);
1066 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1073 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1067 1074
1068 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1075 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);