diff options
author | Ivo van Doorn <ivdoorn@gmail.com> | 2008-08-29 15:05:45 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-08-29 16:24:12 -0400 |
commit | 2af0a570b45ec315f364ea2c8a6d072cfcaa9d32 (patch) | |
tree | c3570f4c9bb0d24bef857977e5251b04309b95ad /drivers/net/wireless/rt2x00/rt61pci.c | |
parent | 2575c11d6ee7266f0f035e55c5056b36597cd336 (diff) |
rt2x00: Initialize txop during conf_tx() callback
The txop parameter is supported by rt61pci and rt73usb,
and thus should be written to the register instead
of using the fixed value set during initialization.
Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt61pci.c | 69 |
1 files changed, 58 insertions, 11 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index 9d27ce0e54fe..52537101c908 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c | |||
@@ -1478,16 +1478,6 @@ static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) | |||
1478 | 1478 | ||
1479 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); | 1479 | rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); |
1480 | 1480 | ||
1481 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®); | ||
1482 | rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0); | ||
1483 | rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0); | ||
1484 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg); | ||
1485 | |||
1486 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®); | ||
1487 | rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192); | ||
1488 | rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48); | ||
1489 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg); | ||
1490 | |||
1491 | /* | 1481 | /* |
1492 | * Clear all beacons | 1482 | * Clear all beacons |
1493 | * For the Beacon base registers we only need to clear | 1483 | * For the Beacon base registers we only need to clear |
@@ -2652,6 +2642,63 @@ static int rt61pci_set_retry_limit(struct ieee80211_hw *hw, | |||
2652 | return 0; | 2642 | return 0; |
2653 | } | 2643 | } |
2654 | 2644 | ||
2645 | static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, | ||
2646 | const struct ieee80211_tx_queue_params *params) | ||
2647 | { | ||
2648 | struct rt2x00_dev *rt2x00dev = hw->priv; | ||
2649 | struct data_queue *queue; | ||
2650 | struct rt2x00_field32 field; | ||
2651 | int retval; | ||
2652 | u32 reg; | ||
2653 | |||
2654 | /* | ||
2655 | * First pass the configuration through rt2x00lib, that will | ||
2656 | * update the queue settings and validate the input. After that | ||
2657 | * we are free to update the registers based on the value | ||
2658 | * in the queue parameter. | ||
2659 | */ | ||
2660 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | ||
2661 | if (retval) | ||
2662 | return retval; | ||
2663 | |||
2664 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | ||
2665 | |||
2666 | /* Update WMM TXOP register */ | ||
2667 | if (queue_idx < 2) { | ||
2668 | field.bit_offset = queue_idx * 16; | ||
2669 | field.bit_mask = 0xffff << field.bit_offset; | ||
2670 | |||
2671 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®); | ||
2672 | rt2x00_set_field32(®, field, queue->txop); | ||
2673 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg); | ||
2674 | } else if (queue_idx < 4) { | ||
2675 | field.bit_offset = (queue_idx - 2) * 16; | ||
2676 | field.bit_mask = 0xffff << field.bit_offset; | ||
2677 | |||
2678 | rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®); | ||
2679 | rt2x00_set_field32(®, field, queue->txop); | ||
2680 | rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg); | ||
2681 | } | ||
2682 | |||
2683 | /* Update WMM registers */ | ||
2684 | field.bit_offset = queue_idx * 4; | ||
2685 | field.bit_mask = 0xf << field.bit_offset; | ||
2686 | |||
2687 | rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, ®); | ||
2688 | rt2x00_set_field32(®, field, queue->aifs); | ||
2689 | rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg); | ||
2690 | |||
2691 | rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, ®); | ||
2692 | rt2x00_set_field32(®, field, queue->cw_min); | ||
2693 | rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg); | ||
2694 | |||
2695 | rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, ®); | ||
2696 | rt2x00_set_field32(®, field, queue->cw_max); | ||
2697 | rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg); | ||
2698 | |||
2699 | return 0; | ||
2700 | } | ||
2701 | |||
2655 | static u64 rt61pci_get_tsf(struct ieee80211_hw *hw) | 2702 | static u64 rt61pci_get_tsf(struct ieee80211_hw *hw) |
2656 | { | 2703 | { |
2657 | struct rt2x00_dev *rt2x00dev = hw->priv; | 2704 | struct rt2x00_dev *rt2x00dev = hw->priv; |
@@ -2679,7 +2726,7 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = { | |||
2679 | .get_stats = rt2x00mac_get_stats, | 2726 | .get_stats = rt2x00mac_get_stats, |
2680 | .set_retry_limit = rt61pci_set_retry_limit, | 2727 | .set_retry_limit = rt61pci_set_retry_limit, |
2681 | .bss_info_changed = rt2x00mac_bss_info_changed, | 2728 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2682 | .conf_tx = rt2x00mac_conf_tx, | 2729 | .conf_tx = rt61pci_conf_tx, |
2683 | .get_tx_stats = rt2x00mac_get_tx_stats, | 2730 | .get_tx_stats = rt2x00mac_get_tx_stats, |
2684 | .get_tsf = rt61pci_get_tsf, | 2731 | .get_tsf = rt61pci_get_tsf, |
2685 | }; | 2732 | }; |