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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-11-04 12:33:13 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-11-06 16:48:48 -0500
commit9ca21eb7cd2ba4f837bcde5e1c9ec0c784cfc03d (patch)
tree0457228627fecdd7cd81c7474fe8e41688e011ad /drivers/net/wireless/rt2x00/rt2800pci.c
parentabbb505dddef31707d06ff26539639ccdfa56f45 (diff)
rt2800pci: add rt2800_register_[read,write]() wrappers
Part of preparations for later code unification. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c479
1 files changed, 240 insertions, 239 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 5d3c48b9f5cc..802086dce707 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -57,7 +57,7 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57/* 57/*
58 * Register access. 58 * Register access.
59 * All access to the CSR registers will go through the methods 59 * All access to the CSR registers will go through the methods
60 * rt2x00pci_register_read and rt2x00pci_register_write. 60 * rt2800_register_read and rt2800_register_write.
61 * BBP and RF register require indirect register access, 61 * BBP and RF register require indirect register access,
62 * and use the CSR registers BBPCSR and RFCSR to achieve this. 62 * and use the CSR registers BBPCSR and RFCSR to achieve this.
63 * These indirect registers work with busy bits, 63 * These indirect registers work with busy bits,
@@ -66,6 +66,7 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
66 * between each attampt. When the busy bit is still set at that time, 66 * between each attampt. When the busy bit is still set at that time,
67 * the access attempt is considered to have failed, 67 * the access attempt is considered to have failed,
68 * and we will print an error. 68 * and we will print an error.
69 * The _lock versions must be used if you already hold the csr_mutex
69 */ 70 */
70#define WAIT_FOR_BBP(__dev, __reg) \ 71#define WAIT_FOR_BBP(__dev, __reg) \
71 rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg)) 72 rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
@@ -96,7 +97,7 @@ static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
96 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0); 97 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
97 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); 98 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
98 99
99 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg); 100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
100 } 101 }
101 102
102 mutex_unlock(&rt2x00dev->csr_mutex); 103 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -124,7 +125,7 @@ static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
124 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1); 125 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
125 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1); 126 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
126 127
127 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg); 128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
128 129
129 WAIT_FOR_BBP(rt2x00dev, &reg); 130 WAIT_FOR_BBP(rt2x00dev, &reg);
130 } 131 }
@@ -152,7 +153,7 @@ static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
152 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1); 153 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
153 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1); 154 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
154 155
155 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg); 156 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
156 } 157 }
157 158
158 mutex_unlock(&rt2x00dev->csr_mutex); 159 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -179,7 +180,7 @@ static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
179 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0); 180 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
180 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1); 181 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
181 182
182 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg); 183 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
183 184
184 WAIT_FOR_RFCSR(rt2x00dev, &reg); 185 WAIT_FOR_RFCSR(rt2x00dev, &reg);
185 } 186 }
@@ -207,7 +208,7 @@ static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
207 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0); 208 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
208 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1); 209 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
209 210
210 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg); 211 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
211 rt2x00_rf_write(rt2x00dev, word, value); 212 rt2x00_rf_write(rt2x00dev, word, value);
212 } 213 }
213 214
@@ -238,11 +239,11 @@ static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token); 239 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
239 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0); 240 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
240 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1); 241 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
241 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); 242 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
242 243
243 reg = 0; 244 reg = 0;
244 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command); 245 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
245 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg); 246 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
246 } 247 }
247 248
248 mutex_unlock(&rt2x00dev->csr_mutex); 249 mutex_unlock(&rt2x00dev->csr_mutex);
@@ -254,7 +255,7 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
254 u32 reg; 255 u32 reg;
255 256
256 for (i = 0; i < 200; i++) { 257 for (i = 0; i < 200; i++) {
257 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 258 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
258 259
259 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 260 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
260 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 261 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -268,8 +269,8 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
268 if (i == 200) 269 if (i == 200)
269 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 270 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
270 271
271 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 272 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
272 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 273 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
273} 274}
274 275
275#ifdef CONFIG_RT2800PCI_WISOC 276#ifdef CONFIG_RT2800PCI_WISOC
@@ -291,7 +292,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
291 struct rt2x00_dev *rt2x00dev = eeprom->data; 292 struct rt2x00_dev *rt2x00dev = eeprom->data;
292 u32 reg; 293 u32 reg;
293 294
294 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 295 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
295 296
296 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 297 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
297 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 298 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -313,7 +314,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
313 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 314 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
314 !!eeprom->reg_chip_select); 315 !!eeprom->reg_chip_select);
315 316
316 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 317 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
317} 318}
318 319
319static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 320static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -321,7 +322,7 @@ static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
321 struct eeprom_93cx6 eeprom; 322 struct eeprom_93cx6 eeprom;
322 u32 reg; 323 u32 reg;
323 324
324 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 325 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
325 326
326 eeprom.data = rt2x00dev; 327 eeprom.data = rt2x00dev;
327 eeprom.register_read = rt2800pci_eepromregister_read; 328 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -342,23 +343,23 @@ static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
342{ 343{
343 u32 reg; 344 u32 reg;
344 345
345 rt2x00pci_register_read(rt2x00dev, EFUSE_CTRL, &reg); 346 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
346 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 347 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
347 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 348 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
348 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 349 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
349 rt2x00pci_register_write(rt2x00dev, EFUSE_CTRL, reg); 350 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
350 351
351 /* Wait until the EEPROM has been loaded */ 352 /* Wait until the EEPROM has been loaded */
352 rt2x00pci_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 353 rt2x00pci_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
353 354
354 /* Apparently the data is read from end to start */ 355 /* Apparently the data is read from end to start */
355 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA3, 356 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
356 (u32 *)&rt2x00dev->eeprom[i]); 357 (u32 *)&rt2x00dev->eeprom[i]);
357 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA2, 358 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
358 (u32 *)&rt2x00dev->eeprom[i + 2]); 359 (u32 *)&rt2x00dev->eeprom[i + 2]);
359 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA1, 360 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
360 (u32 *)&rt2x00dev->eeprom[i + 4]); 361 (u32 *)&rt2x00dev->eeprom[i + 4]);
361 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA0, 362 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
362 (u32 *)&rt2x00dev->eeprom[i + 6]); 363 (u32 *)&rt2x00dev->eeprom[i + 6]);
363} 364}
364 365
@@ -383,8 +384,8 @@ static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
383static const struct rt2x00debug rt2800pci_rt2x00debug = { 384static const struct rt2x00debug rt2800pci_rt2x00debug = {
384 .owner = THIS_MODULE, 385 .owner = THIS_MODULE,
385 .csr = { 386 .csr = {
386 .read = rt2x00pci_register_read, 387 .read = rt2800_register_read,
387 .write = rt2x00pci_register_write, 388 .write = rt2800_register_write,
388 .flags = RT2X00DEBUGFS_OFFSET, 389 .flags = RT2X00DEBUGFS_OFFSET,
389 .word_base = CSR_REG_BASE, 390 .word_base = CSR_REG_BASE,
390 .word_size = sizeof(u32), 391 .word_size = sizeof(u32),
@@ -418,7 +419,7 @@ static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
418{ 419{
419 u32 reg; 420 u32 reg;
420 421
421 rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg); 422 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
422 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2); 423 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
423} 424}
424 425
@@ -467,7 +468,7 @@ static int rt2800pci_blink_set(struct led_classdev *led_cdev,
467 container_of(led_cdev, struct rt2x00_led, led_dev); 468 container_of(led_cdev, struct rt2x00_led, led_dev);
468 u32 reg; 469 u32 reg;
469 470
470 rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg); 471 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
471 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on); 472 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
472 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off); 473 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
473 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3); 474 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
@@ -475,7 +476,7 @@ static int rt2800pci_blink_set(struct led_classdev *led_cdev,
475 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12); 476 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
476 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3); 477 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
477 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1); 478 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
478 rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg); 479 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
479 480
480 return 0; 481 return 0;
481} 482}
@@ -506,7 +507,7 @@ static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
506 507
507 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); 508 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
508 509
509 rt2x00pci_register_read(rt2x00dev, offset, &reg); 510 rt2800_register_read(rt2x00dev, offset, &reg);
510 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 511 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
511 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); 512 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
512 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 513 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
@@ -514,7 +515,7 @@ static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
514 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, 515 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
515 (crypto->cmd == SET_KEY) * crypto->bssidx); 516 (crypto->cmd == SET_KEY) * crypto->bssidx);
516 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); 517 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
517 rt2x00pci_register_write(rt2x00dev, offset, reg); 518 rt2800_register_write(rt2x00dev, offset, reg);
518 519
519 offset = MAC_IVEIV_ENTRY(key->hw_key_idx); 520 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
520 521
@@ -572,10 +573,10 @@ static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
572 573
573 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); 574 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
574 575
575 rt2x00pci_register_read(rt2x00dev, offset, &reg); 576 rt2800_register_read(rt2x00dev, offset, &reg);
576 rt2x00_set_field32(&reg, field, 577 rt2x00_set_field32(&reg, field,
577 (crypto->cmd == SET_KEY) * crypto->cipher); 578 (crypto->cmd == SET_KEY) * crypto->cipher);
578 rt2x00pci_register_write(rt2x00dev, offset, reg); 579 rt2800_register_write(rt2x00dev, offset, reg);
579 580
580 /* 581 /*
581 * Update WCID information 582 * Update WCID information
@@ -635,7 +636,7 @@ static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
635 * and broadcast frames will always be accepted since 636 * and broadcast frames will always be accepted since
636 * there is no filter for it at this time. 637 * there is no filter for it at this time.
637 */ 638 */
638 rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg); 639 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
639 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR, 640 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
640 !(filter_flags & FIF_FCSFAIL)); 641 !(filter_flags & FIF_FCSFAIL));
641 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR, 642 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
@@ -664,7 +665,7 @@ static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
664 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0); 665 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
665 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL, 666 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
666 !(filter_flags & FIF_CONTROL)); 667 !(filter_flags & FIF_CONTROL));
667 rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg); 668 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
668} 669}
669 670
670static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev, 671static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
@@ -683,16 +684,16 @@ static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
683 * bits which (when set to 0) will invalidate the entire beacon. 684 * bits which (when set to 0) will invalidate the entire beacon.
684 */ 685 */
685 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); 686 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
686 rt2x00pci_register_write(rt2x00dev, beacon_base, 0); 687 rt2800_register_write(rt2x00dev, beacon_base, 0);
687 688
688 /* 689 /*
689 * Enable synchronisation. 690 * Enable synchronisation.
690 */ 691 */
691 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 692 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
692 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 693 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
693 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync); 694 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
694 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 695 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
695 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 696 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
696 } 697 }
697 698
698 if (flags & CONFIG_UPDATE_MAC) { 699 if (flags & CONFIG_UPDATE_MAC) {
@@ -720,43 +721,43 @@ static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
720{ 721{
721 u32 reg; 722 u32 reg;
722 723
723 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); 724 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
724 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20); 725 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
725 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 726 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
726 727
727 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 728 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
728 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 729 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
729 !!erp->short_preamble); 730 !!erp->short_preamble);
730 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 731 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
731 !!erp->short_preamble); 732 !!erp->short_preamble);
732 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 733 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
733 734
734 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 735 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
735 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 736 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
736 erp->cts_protection ? 2 : 0); 737 erp->cts_protection ? 2 : 0);
737 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 738 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
738 739
739 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 740 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
740 erp->basic_rates); 741 erp->basic_rates);
741 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 742 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
742 743
743 rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 744 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
744 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); 745 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
745 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); 746 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
746 rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 747 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
747 748
748 rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 749 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
749 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs); 750 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
750 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs); 751 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
751 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); 752 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
752 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); 753 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
753 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); 754 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
754 rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 755 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
755 756
756 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 757 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
757 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 758 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
758 erp->beacon_int * 16); 759 erp->beacon_int * 16);
759 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 760 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
760} 761}
761 762
762static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev, 763static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
@@ -965,11 +966,11 @@ static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
965 rt2800pci_bbp_write(rt2x00dev, 75, 0x50); 966 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
966 } 967 }
967 968
968 rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg); 969 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
969 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf)); 970 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
970 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14); 971 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
971 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14); 972 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
972 rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg); 973 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
973 974
974 tx_pin = 0; 975 tx_pin = 0;
975 976
@@ -992,7 +993,7 @@ static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
992 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); 993 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
993 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); 994 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
994 995
995 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 996 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
996 997
997 rt2800pci_bbp_read(rt2x00dev, 4, &bbp); 998 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
998 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 999 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
@@ -1028,7 +1029,7 @@ static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1028 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0); 1029 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1029 rt2800pci_bbp_write(rt2x00dev, 1, r1); 1030 rt2800pci_bbp_write(rt2x00dev, 1, r1);
1030 1031
1031 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg); 1032 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1032 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value); 1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value); 1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value); 1035 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
@@ -1037,9 +1038,9 @@ static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1037 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value); 1038 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1038 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value); 1039 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1039 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value); 1040 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1040 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg); 1041 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1041 1042
1042 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg); 1043 rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1043 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value); 1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value); 1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value); 1046 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
@@ -1048,9 +1049,9 @@ static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1048 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value); 1049 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1049 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value); 1050 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1050 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value); 1051 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1051 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg); 1052 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1052 1053
1053 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg); 1054 rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1054 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value); 1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value); 1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value); 1057 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
@@ -1059,9 +1060,9 @@ static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1059 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value); 1060 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1060 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value); 1061 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1061 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value); 1062 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1062 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg); 1063 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1063 1064
1064 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg); 1065 rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1065 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value); 1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value); 1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value); 1068 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
@@ -1070,14 +1071,14 @@ static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1070 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value); 1071 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1071 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value); 1072 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1072 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value); 1073 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1073 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg); 1074 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1074 1075
1075 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg); 1076 rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1076 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value); 1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value); 1078 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1078 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value); 1079 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1079 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value); 1080 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1080 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg); 1081 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1081} 1082}
1082 1083
1083static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, 1084static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
@@ -1085,7 +1086,7 @@ static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1085{ 1086{
1086 u32 reg; 1087 u32 reg;
1087 1088
1088 rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg); 1089 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1089 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 1090 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1090 libconf->conf->short_frame_max_tx_count); 1091 libconf->conf->short_frame_max_tx_count);
1091 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 1092 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
@@ -1094,7 +1095,7 @@ static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1094 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 1095 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1095 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0); 1096 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1096 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 1097 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1097 rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg); 1098 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1098} 1099}
1099 1100
1100static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev, 1101static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
@@ -1106,24 +1107,24 @@ static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1106 u32 reg; 1107 u32 reg;
1107 1108
1108 if (state == STATE_SLEEP) { 1109 if (state == STATE_SLEEP) {
1109 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); 1110 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1110 1111
1111 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 1112 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1112 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); 1113 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1113 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 1114 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1114 libconf->conf->listen_interval - 1); 1115 libconf->conf->listen_interval - 1);
1115 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1); 1116 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1116 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1117 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1117 1118
1118 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 1119 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1119 } else { 1120 } else {
1120 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 1121 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1121 1122
1122 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 1123 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1123 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 1124 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1124 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 1125 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1125 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0); 1126 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1126 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1127 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1127 } 1128 }
1128} 1129}
1129 1130
@@ -1156,7 +1157,7 @@ static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1156 /* 1157 /*
1157 * Update FCS error count from register. 1158 * Update FCS error count from register.
1158 */ 1159 */
1159 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg); 1160 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1160 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); 1161 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1161} 1162}
1162 1163
@@ -1259,7 +1260,7 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1259 * Wait for stable hardware. 1260 * Wait for stable hardware.
1260 */ 1261 */
1261 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1262 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1262 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 1263 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1263 if (reg && reg != ~0) 1264 if (reg && reg != ~0)
1264 break; 1265 break;
1265 msleep(1); 1266 msleep(1);
@@ -1270,27 +1271,27 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1270 return -EBUSY; 1271 return -EBUSY;
1271 } 1272 }
1272 1273
1273 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 1274 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1274 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 1275 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1275 1276
1276 /* 1277 /*
1277 * Disable DMA, will be reenabled later when enabling 1278 * Disable DMA, will be reenabled later when enabling
1278 * the radio. 1279 * the radio.
1279 */ 1280 */
1280 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 1281 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 1284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1284 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 1285 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1285 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 1286 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1286 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 1287 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1287 1288
1288 /* 1289 /*
1289 * enable Host program ram write selection 1290 * enable Host program ram write selection
1290 */ 1291 */
1291 reg = 0; 1292 reg = 0;
1292 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 1293 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1293 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 1294 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1294 1295
1295 /* 1296 /*
1296 * Write firmware to device. 1297 * Write firmware to device.
@@ -1298,14 +1299,14 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1298 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 1299 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1299 data, len); 1300 data, len);
1300 1301
1301 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 1302 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1302 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 1303 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1303 1304
1304 /* 1305 /*
1305 * Wait for device to stabilize. 1306 * Wait for device to stabilize.
1306 */ 1307 */
1307 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1308 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1308 rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 1309 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1309 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 1310 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1310 break; 1311 break;
1311 msleep(1); 1312 msleep(1);
@@ -1324,8 +1325,8 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1324 /* 1325 /*
1325 * Initialize BBP R/W access agent 1326 * Initialize BBP R/W access agent
1326 */ 1327 */
1327 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 1328 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1328 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 1329 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1329 1330
1330 return 0; 1331 return 0;
1331} 1332}
@@ -1375,7 +1376,7 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1375 struct queue_entry_priv_pci *entry_priv; 1376 struct queue_entry_priv_pci *entry_priv;
1376 u32 reg; 1377 u32 reg;
1377 1378
1378 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 1379 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 1380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1380 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 1381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 1382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -1383,54 +1384,54 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1383 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 1384 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1384 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 1385 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1385 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 1386 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1386 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 1387 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1387 1388
1388 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 1389 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1389 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 1390 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1390 1391
1391 /* 1392 /*
1392 * Initialize registers. 1393 * Initialize registers.
1393 */ 1394 */
1394 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 1395 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1395 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 1396 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1396 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); 1397 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1397 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0); 1398 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1398 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0); 1399 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1399 1400
1400 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 1401 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1401 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 1402 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1402 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); 1403 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1403 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0); 1404 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1404 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0); 1405 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1405 1406
1406 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 1407 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1407 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 1408 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1408 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); 1409 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1409 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0); 1410 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1410 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0); 1411 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1411 1412
1412 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 1413 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1413 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 1414 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1414 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); 1415 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1415 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0); 1416 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1416 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0); 1417 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1417 1418
1418 entry_priv = rt2x00dev->rx->entries[0].priv_data; 1419 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1419 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 1420 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1420 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); 1421 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1421 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); 1422 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1422 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0); 1423 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
1423 1424
1424 /* 1425 /*
1425 * Enable global DMA configuration 1426 * Enable global DMA configuration
1426 */ 1427 */
1427 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 1428 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 1429 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1429 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 1430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 1431 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1431 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 1432 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1432 1433
1433 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0); 1434 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1434 1435
1435 return 0; 1436 return 0;
1436} 1437}
@@ -1440,47 +1441,47 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1440 u32 reg; 1441 u32 reg;
1441 unsigned int i; 1442 unsigned int i;
1442 1443
1443 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1444 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1444 1445
1445 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1446 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1446 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1447 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1447 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1); 1448 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1448 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 1449 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1449 1450
1450 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 1451 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1451 1452
1452 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg); 1453 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1453 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */ 1454 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1454 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */ 1455 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1455 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */ 1456 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1456 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */ 1457 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1457 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg); 1458 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1458 1459
1459 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg); 1460 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1460 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */ 1461 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1461 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */ 1462 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1462 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */ 1463 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1463 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */ 1464 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1464 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg); 1465 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1465 1466
1466 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f); 1467 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1467 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003); 1468 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1468 1469
1469 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); 1470 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1470 1471
1471 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 1472 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1472 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0); 1473 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1473 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0); 1474 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1474 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0); 1475 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1475 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); 1476 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1476 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 1477 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1477 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 1478 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1478 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1479 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1479 1480
1480 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 1481 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1481 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1482 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1482 1483
1483 rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg); 1484 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1484 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 1485 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1485 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0); 1486 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1486 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 1487 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
@@ -1489,14 +1490,14 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1489 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1); 1490 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1490 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0); 1491 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1491 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0); 1492 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1492 rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg); 1493 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1493 1494
1494 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); 1495 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1495 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 1496 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1496 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 1497 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1497 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 1498 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1498 1499
1499 rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg); 1500 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1500 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 1501 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1501 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION && 1502 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1502 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION) 1503 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
@@ -1505,19 +1506,19 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1505 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1); 1506 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1506 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0); 1507 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1507 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0); 1508 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1508 rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1509 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1509 1510
1510 rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 1511 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1511 1512
1512 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 1513 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1513 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1); 1514 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1514 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0); 1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0); 1516 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1516 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 1517 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1517 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 1518 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1518 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1519 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1519 1520
1520 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 1521 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1521 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8); 1522 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1522 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 1523 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1523 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 1524 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
@@ -1527,9 +1528,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1527 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1528 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1528 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1529 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1529 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1530 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1530 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg); 1531 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1531 1532
1532 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 1533 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1533 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8); 1534 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1534 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 1535 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1535 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 1536 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
@@ -1539,9 +1540,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1539 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1540 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1540 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1541 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1541 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1542 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1542 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1543 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1543 1544
1544 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 1545 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1545 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 1546 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1546 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0); 1547 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1547 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1); 1548 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
@@ -1551,9 +1552,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1551 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1552 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1552 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1553 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1553 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1554 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1554 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1555 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1555 1556
1556 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 1557 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1557 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 1558 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1558 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0); 1559 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1559 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1); 1560 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
@@ -1563,9 +1564,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1563 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1564 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1564 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1565 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1565 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1566 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1566 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1567 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1567 1568
1568 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 1569 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1569 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 1570 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1570 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0); 1571 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1571 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1); 1572 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
@@ -1575,9 +1576,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1575 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1576 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1576 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1577 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1577 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1578 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1578 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1579 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1579 1580
1580 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 1581 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1581 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0); 1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1); 1584 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
@@ -1587,26 +1588,26 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1587 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1588 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1588 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1589 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1589 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1590 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1590 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1591 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1591 1592
1592 rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f); 1593 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1593 rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); 1594 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1594 1595
1595 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg); 1596 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1596 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); 1597 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1597 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, 1598 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1598 IEEE80211_MAX_RTS_THRESHOLD); 1599 IEEE80211_MAX_RTS_THRESHOLD);
1599 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0); 1600 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1600 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg); 1601 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1601 1602
1602 rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 1603 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1603 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1604 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1604 1605
1605 /* 1606 /*
1606 * ASIC will keep garbage value after boot, clear encryption keys. 1607 * ASIC will keep garbage value after boot, clear encryption keys.
1607 */ 1608 */
1608 for (i = 0; i < 4; i++) 1609 for (i = 0; i < 4; i++)
1609 rt2x00pci_register_write(rt2x00dev, 1610 rt2800_register_write(rt2x00dev,
1610 SHARED_KEY_MODE_ENTRY(i), 0); 1611 SHARED_KEY_MODE_ENTRY(i), 0);
1611 1612
1612 for (i = 0; i < 256; i++) { 1613 for (i = 0; i < 256; i++) {
@@ -1614,8 +1615,8 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1614 rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), 1615 rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1615 wcid, sizeof(wcid)); 1616 wcid, sizeof(wcid));
1616 1617
1617 rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); 1618 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1618 rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 1619 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1619 } 1620 }
1620 1621
1621 /* 1622 /*
@@ -1624,16 +1625,16 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1624 * the first byte since that byte contains the VALID and OWNER 1625 * the first byte since that byte contains the VALID and OWNER
1625 * bits which (when set to 0) will invalidate the entire beacon. 1626 * bits which (when set to 0) will invalidate the entire beacon.
1626 */ 1627 */
1627 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1628 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1628 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1629 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1629 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1630 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1630 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1631 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1631 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0); 1632 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1632 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0); 1633 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1633 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0); 1634 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1634 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0); 1635 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1635 1636
1636 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg); 1637 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1637 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0); 1638 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1638 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0); 1639 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1639 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1); 1640 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
@@ -1642,9 +1643,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1642 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4); 1643 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1643 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5); 1644 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1644 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6); 1645 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1645 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg); 1646 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1646 1647
1647 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg); 1648 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1648 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8); 1649 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1649 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8); 1650 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1650 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9); 1651 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
@@ -1653,9 +1654,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1653 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12); 1654 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1654 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13); 1655 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1655 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14); 1656 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1656 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg); 1657 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1657 1658
1658 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg); 1659 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1659 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8); 1660 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1660 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8); 1661 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1661 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9); 1662 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
@@ -1664,26 +1665,26 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1664 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12); 1665 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1665 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13); 1666 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1666 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14); 1667 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1667 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg); 1668 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1668 1669
1669 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg); 1670 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1670 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0); 1671 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1671 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0); 1672 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1672 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1); 1673 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1673 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2); 1674 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1674 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg); 1675 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1675 1676
1676 /* 1677 /*
1677 * We must clear the error counters. 1678 * We must clear the error counters.
1678 * These registers are cleared on read, 1679 * These registers are cleared on read,
1679 * so we may pass a useless variable to store the value. 1680 * so we may pass a useless variable to store the value.
1680 */ 1681 */
1681 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg); 1682 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1682 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg); 1683 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1683 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg); 1684 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1684 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg); 1685 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1685 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg); 1686 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1686 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg); 1687 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1687 1688
1688 return 0; 1689 return 0;
1689} 1690}
@@ -1694,7 +1695,7 @@ static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1694 u32 reg; 1695 u32 reg;
1695 1696
1696 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1697 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1697 rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg); 1698 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1698 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) 1699 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1699 return 0; 1700 return 0;
1700 1701
@@ -1714,8 +1715,8 @@ static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1714 * BBP was enabled after firmware was loaded, 1715 * BBP was enabled after firmware was loaded,
1715 * but we need to reactivate it now. 1716 * but we need to reactivate it now.
1716 */ 1717 */
1717 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 1718 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1718 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 1719 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1719 msleep(1); 1720 msleep(1);
1720 1721
1721 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1722 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
@@ -1928,11 +1929,11 @@ static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1928{ 1929{
1929 u32 reg; 1930 u32 reg;
1930 1931
1931 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1932 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1932 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1933 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1933 (state == STATE_RADIO_RX_ON) || 1934 (state == STATE_RADIO_RX_ON) ||
1934 (state == STATE_RADIO_RX_ON_LINK)); 1935 (state == STATE_RADIO_RX_ON_LINK));
1935 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 1936 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1936} 1937}
1937 1938
1938static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1939static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
@@ -1946,11 +1947,11 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1946 * should clear the register to assure a clean state. 1947 * should clear the register to assure a clean state.
1947 */ 1948 */
1948 if (state == STATE_RADIO_IRQ_ON) { 1949 if (state == STATE_RADIO_IRQ_ON) {
1949 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 1950 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1950 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1951 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1951 } 1952 }
1952 1953
1953 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 1954 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1954 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask); 1955 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1955 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask); 1956 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1956 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask); 1957 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
@@ -1969,7 +1970,7 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1969 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask); 1970 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1970 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask); 1971 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1971 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask); 1972 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1972 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 1973 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
1973} 1974}
1974 1975
1975static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 1976static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
@@ -1978,7 +1979,7 @@ static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1978 u32 reg; 1979 u32 reg;
1979 1980
1980 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1981 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1981 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 1982 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1982 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 1983 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1983 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 1984 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1984 return 0; 1985 return 0;
@@ -2014,22 +2015,22 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
2014 /* 2015 /*
2015 * Enable RX. 2016 * Enable RX.
2016 */ 2017 */
2017 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 2018 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2018 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 2019 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2019 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); 2020 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2020 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 2021 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2021 2022
2022 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 2023 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2023 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 2024 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2024 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 2025 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2025 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); 2026 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2026 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 2027 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2027 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 2028 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2028 2029
2029 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 2030 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2030 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 2031 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2031 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 2032 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2032 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 2033 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2033 2034
2034 /* 2035 /*
2035 * Initialize LED control 2036 * Initialize LED control
@@ -2053,21 +2054,21 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2053{ 2054{
2054 u32 reg; 2055 u32 reg;
2055 2056
2056 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 2057 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2057 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 2058 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2058 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 2059 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2059 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 2060 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2060 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 2061 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2061 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 2062 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2062 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 2063 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2063 2064
2064 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 2065 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2065 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0); 2066 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2066 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0); 2067 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2067 2068
2068 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280); 2069 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2069 2070
2070 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 2071 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2071 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 2072 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
2072 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 2073 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
2073 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 2074 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -2075,10 +2076,10 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2075 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 2076 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
2076 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 2077 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
2077 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 2078 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
2078 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 2079 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2079 2080
2080 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 2081 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
2081 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 2082 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
2082 2083
2083 /* Wait for DMA, ignore error */ 2084 /* Wait for DMA, ignore error */
2084 rt2800pci_wait_wpdma_ready(rt2x00dev); 2085 rt2800pci_wait_wpdma_ready(rt2x00dev);
@@ -2267,9 +2268,9 @@ static void rt2800pci_write_beacon(struct queue_entry *entry)
2267 * Disable beaconing while we are reloading the beacon data, 2268 * Disable beaconing while we are reloading the beacon data,
2268 * otherwise we might be sending out invalid data. 2269 * otherwise we might be sending out invalid data.
2269 */ 2270 */
2270 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 2271 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2271 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 2272 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2272 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2273 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2273 2274
2274 /* 2275 /*
2275 * Write entire beacon with descriptor to register. 2276 * Write entire beacon with descriptor to register.
@@ -2297,12 +2298,12 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2297 u32 reg; 2298 u32 reg;
2298 2299
2299 if (queue_idx == QID_BEACON) { 2300 if (queue_idx == QID_BEACON) {
2300 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 2301 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2301 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 2302 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2302 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 2303 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2303 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 2304 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2304 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 2305 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2305 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 2306 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2306 } 2307 }
2307 return; 2308 return;
2308 } 2309 }
@@ -2318,7 +2319,7 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2318 else 2319 else
2319 qidx = queue_idx; 2320 qidx = queue_idx;
2320 2321
2321 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx); 2322 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2322} 2323}
2323 2324
2324static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 2325static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -2327,16 +2328,16 @@ static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2327 u32 reg; 2328 u32 reg;
2328 2329
2329 if (qid == QID_BEACON) { 2330 if (qid == QID_BEACON) {
2330 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0); 2331 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2331 return; 2332 return;
2332 } 2333 }
2333 2334
2334 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 2335 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2335 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE)); 2336 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2336 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK)); 2337 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2337 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI)); 2338 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2338 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO)); 2339 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2339 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 2340 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2340} 2341}
2341 2342
2342/* 2343/*
@@ -2432,7 +2433,7 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2432 * Set RX IDX in register to inform hardware that we have handled 2433 * Set RX IDX in register to inform hardware that we have handled
2433 * this entry and it is available for reuse again. 2434 * this entry and it is available for reuse again.
2434 */ 2435 */
2435 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); 2436 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2436 2437
2437 /* 2438 /*
2438 * Remove TXWI descriptor from start of buffer. 2439 * Remove TXWI descriptor from start of buffer.
@@ -2469,7 +2470,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2469 old_reg = 0; 2470 old_reg = 0;
2470 2471
2471 while (1) { 2472 while (1) {
2472 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg); 2473 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2473 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID)) 2474 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2474 break; 2475 break;
2475 2476
@@ -2553,8 +2554,8 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2553 u32 reg; 2554 u32 reg;
2554 2555
2555 /* Read status and ACK all interrupts */ 2556 /* Read status and ACK all interrupts */
2556 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 2557 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2557 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 2558 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2558 2559
2559 if (!reg) 2560 if (!reg)
2560 return IRQ_NONE; 2561 return IRQ_NONE;
@@ -2711,7 +2712,7 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2711 * Identify RF chipset. 2712 * Identify RF chipset.
2712 */ 2713 */
2713 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 2714 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2714 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 2715 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2715 rt2x00_set_chip_rf(rt2x00dev, value, reg); 2716 rt2x00_set_chip_rf(rt2x00dev, value, reg);
2716 2717
2717 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) && 2718 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
@@ -3022,33 +3023,33 @@ static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3022 u32 reg; 3023 u32 reg;
3023 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); 3024 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3024 3025
3025 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg); 3026 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3026 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value); 3027 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3027 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg); 3028 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3028 3029
3029 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 3030 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3030 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled); 3031 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3031 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg); 3032 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3032 3033
3033 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 3034 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3034 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled); 3035 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3035 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 3036 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3036 3037
3037 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 3038 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3038 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled); 3039 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3039 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg); 3040 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3040 3041
3041 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 3042 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3042 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled); 3043 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3043 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg); 3044 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3044 3045
3045 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 3046 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3046 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled); 3047 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3047 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg); 3048 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3048 3049
3049 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 3050 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3050 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled); 3051 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3051 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg); 3052 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3052 3053
3053 return 0; 3054 return 0;
3054} 3055}
@@ -3087,35 +3088,35 @@ static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3087 field.bit_offset = (queue_idx & 1) * 16; 3088 field.bit_offset = (queue_idx & 1) * 16;
3088 field.bit_mask = 0xffff << field.bit_offset; 3089 field.bit_mask = 0xffff << field.bit_offset;
3089 3090
3090 rt2x00pci_register_read(rt2x00dev, offset, &reg); 3091 rt2800_register_read(rt2x00dev, offset, &reg);
3091 rt2x00_set_field32(&reg, field, queue->txop); 3092 rt2x00_set_field32(&reg, field, queue->txop);
3092 rt2x00pci_register_write(rt2x00dev, offset, reg); 3093 rt2800_register_write(rt2x00dev, offset, reg);
3093 3094
3094 /* Update WMM registers */ 3095 /* Update WMM registers */
3095 field.bit_offset = queue_idx * 4; 3096 field.bit_offset = queue_idx * 4;
3096 field.bit_mask = 0xf << field.bit_offset; 3097 field.bit_mask = 0xf << field.bit_offset;
3097 3098
3098 rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg); 3099 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3099 rt2x00_set_field32(&reg, field, queue->aifs); 3100 rt2x00_set_field32(&reg, field, queue->aifs);
3100 rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); 3101 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3101 3102
3102 rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg); 3103 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3103 rt2x00_set_field32(&reg, field, queue->cw_min); 3104 rt2x00_set_field32(&reg, field, queue->cw_min);
3104 rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); 3105 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3105 3106
3106 rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg); 3107 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3107 rt2x00_set_field32(&reg, field, queue->cw_max); 3108 rt2x00_set_field32(&reg, field, queue->cw_max);
3108 rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); 3109 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3109 3110
3110 /* Update EDCA registers */ 3111 /* Update EDCA registers */
3111 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); 3112 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3112 3113
3113 rt2x00pci_register_read(rt2x00dev, offset, &reg); 3114 rt2800_register_read(rt2x00dev, offset, &reg);
3114 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop); 3115 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3115 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs); 3116 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3116 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min); 3117 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3117 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max); 3118 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3118 rt2x00pci_register_write(rt2x00dev, offset, reg); 3119 rt2800_register_write(rt2x00dev, offset, reg);
3119 3120
3120 return 0; 3121 return 0;
3121} 3122}
@@ -3126,9 +3127,9 @@ static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3126 u64 tsf; 3127 u64 tsf;
3127 u32 reg; 3128 u32 reg;
3128 3129
3129 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg); 3130 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3130 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; 3131 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3131 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg); 3132 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3132 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); 3133 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3133 3134
3134 return tsf; 3135 return tsf;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 03:21:06 -0500