Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem

1 files changed, 613 insertions, 134 deletions

diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index c9bf074342ba..3da78bf0ca26 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -400,8 +400,15 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
         if (rt2800_wait_csr_ready(rt2x00dev))
                 return -EBUSY;
 
-        if (rt2x00_is_pci(rt2x00dev))
+       if (rt2x00_is_pci(rt2x00dev)) {
+               if (rt2x00_rt(rt2x00dev, RT5390)) {
+                       rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
+                       rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
+                       rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
+                       rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
+               }
                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
+       }
 
         /*
          * Disable DMA, will be reenabled later when enabling
@@ -773,13 +780,14 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
         unsigned int beacon_base;
         unsigned int padding_len;
-        u32 reg;
+        u32 orig_reg, reg;
 
         /*
          * Disable beaconing while we are reloading the beacon data,
          * otherwise we might be sending out invalid data.
          */
         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
+        orig_reg = reg;
         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 
@@ -810,7 +818,14 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
          * Write entire beacon with TXWI and padding to register.
          */
         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
-        skb_pad(entry->skb, padding_len);
+        if (padding_len && skb_pad(entry->skb, padding_len)) {
+                ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
+                /* skb freed by skb_pad() on failure */
+                entry->skb = NULL;
+                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
+                return;
+        }
+
         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
                                    entry->skb->len + padding_len);
@@ -1368,10 +1383,32 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
 }
 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 
+static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
+                                     enum antenna ant)
+{
+        u32 reg;
+        u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
+        u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
+
+        if (rt2x00_is_pci(rt2x00dev)) {
+                rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
+                rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
+                rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
+        } else if (rt2x00_is_usb(rt2x00dev))
+                rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
+                                   eesk_pin, 0);
+
+        rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
+        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
+        rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
+        rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+}
+
 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 {
         u8 r1;
         u8 r3;
+        u16 eeprom;
 
         rt2800_bbp_read(rt2x00dev, 1, &r1);
         rt2800_bbp_read(rt2x00dev, 3, &r3);
@@ -1379,7 +1416,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
         /*
          * Configure the TX antenna.
          */
-        switch ((int)ant->tx) {
+        switch (ant->tx_chain_num) {
         case 1:
                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
                 break;
@@ -1394,8 +1431,18 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
         /*
          * Configure the RX antenna.
          */
-        switch ((int)ant->rx) {
+        switch (ant->rx_chain_num) {
         case 1:
+                if (rt2x00_rt(rt2x00dev, RT3070) ||
+                    rt2x00_rt(rt2x00dev, RT3090) ||
+                    rt2x00_rt(rt2x00dev, RT3390)) {
+                        rt2x00_eeprom_read(rt2x00dev,
+                                           EEPROM_NIC_CONF1, &eeprom);
+                        if (rt2x00_get_field16(eeprom,
+                                                EEPROM_NIC_CONF1_ANT_DIVERSITY))
+                                rt2800_set_ant_diversity(rt2x00dev,
+                                                rt2x00dev->default_ant.rx);
+                }
                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
                 break;
         case 2:
@@ -1441,13 +1488,13 @@ static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
 {
         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 
-        if (rt2x00dev->default_ant.tx == 1)
+        if (rt2x00dev->default_ant.tx_chain_num == 1)
                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 
-        if (rt2x00dev->default_ant.rx == 1) {
+        if (rt2x00dev->default_ant.rx_chain_num == 1) {
                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
-        } else if (rt2x00dev->default_ant.rx == 2)
+        } else if (rt2x00dev->default_ant.rx_chain_num == 2)
                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 
         if (rf->channel > 14) {
@@ -1533,6 +1580,99 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
 }
 
+
+#define RT5390_POWER_BOUND     0x27
+#define RT5390_FREQ_OFFSET_BOUND       0x5f
+
+static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
+                                        struct ieee80211_conf *conf,
+                                        struct rf_channel *rf,
+                                        struct channel_info *info)
+{
+       u8 rfcsr;
+       u16 eeprom;
+
+       rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
+       rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
+       rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
+       rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
+       rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
+
+       rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
+       if (info->default_power1 > RT5390_POWER_BOUND)
+               rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
+       else
+               rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
+       rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
+
+       rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
+       rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
+       rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
+       rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
+       rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
+       rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
+
+       rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
+       if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
+               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, RT5390_FREQ_OFFSET_BOUND);
+       else
+               rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
+       rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
+
+       rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+       if (rf->channel <= 14) {
+               int idx = rf->channel-1;
+
+               if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
+                       if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
+                               /* r55/r59 value array of channel 1~14 */
+                               static const char r55_bt_rev[] = {0x83, 0x83,
+                                       0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
+                                       0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
+                               static const char r59_bt_rev[] = {0x0e, 0x0e,
+                                       0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
+                                       0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
+
+                               rt2800_rfcsr_write(rt2x00dev, 55, r55_bt_rev[idx]);
+                               rt2800_rfcsr_write(rt2x00dev, 59, r59_bt_rev[idx]);
+                       } else {
+                               static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
+                                       0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
+                                       0x88, 0x88, 0x86, 0x85, 0x84};
+
+                               rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
+                       }
+               } else {
+                       if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
+                               static const char r55_nonbt_rev[] = {0x23, 0x23,
+                                       0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
+                                       0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
+                               static const char r59_nonbt_rev[] = {0x07, 0x07,
+                                       0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
+                                       0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
+
+                               rt2800_rfcsr_write(rt2x00dev, 55, r55_nonbt_rev[idx]);
+                               rt2800_rfcsr_write(rt2x00dev, 59, r59_nonbt_rev[idx]);
+                       } else if (rt2x00_rt(rt2x00dev, RT5390)) {
+                               static const char r59_non_bt[] = {0x8f, 0x8f,
+                                       0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
+                                       0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
+
+                               rt2800_rfcsr_write(rt2x00dev, 59, r59_non_bt[idx]);
+                       }
+               }
+       }
+
+       rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
+       rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
+       rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
+       rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
+
+       rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
+       rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
+       rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
+}
+
 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
                                   struct ieee80211_conf *conf,
                                   struct rf_channel *rf,
@@ -1557,6 +1697,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
             rt2x00_rf(rt2x00dev, RF3052) ||
             rt2x00_rf(rt2x00dev, RF3320))
                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
+       else if (rt2x00_rf(rt2x00dev, RF5390))
+               rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
         else
                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
 
@@ -1569,12 +1711,14 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
         rt2800_bbp_write(rt2x00dev, 86, 0);
 
         if (rf->channel <= 14) {
-                if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
-                        rt2800_bbp_write(rt2x00dev, 82, 0x62);
-                        rt2800_bbp_write(rt2x00dev, 75, 0x46);
-                } else {
-                        rt2800_bbp_write(rt2x00dev, 82, 0x84);
-                        rt2800_bbp_write(rt2x00dev, 75, 0x50);
+               if (!rt2x00_rt(rt2x00dev, RT5390)) {
+                       if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
+                               rt2800_bbp_write(rt2x00dev, 82, 0x62);
+                               rt2800_bbp_write(rt2x00dev, 75, 0x46);
+                       } else {
+                               rt2800_bbp_write(rt2x00dev, 82, 0x84);
+                               rt2800_bbp_write(rt2x00dev, 75, 0x50);
+                       }
                 }
         } else {
                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
@@ -1594,13 +1738,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
         tx_pin = 0;
 
         /* Turn on unused PA or LNA when not using 1T or 1R */
-        if (rt2x00dev->default_ant.tx != 1) {
+        if (rt2x00dev->default_ant.tx_chain_num == 2) {
                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
         }
 
         /* Turn on unused PA or LNA when not using 1T or 1R */
-        if (rt2x00dev->default_ant.rx != 1) {
+        if (rt2x00dev->default_ant.rx_chain_num == 2) {
                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
         }
@@ -1644,30 +1788,116 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
 }
 
+static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
+                                      enum ieee80211_band band)
+{
+        u16 eeprom;
+        u8 comp_en;
+        u8 comp_type;
+        int comp_value;
+
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
+
+        if (eeprom == 0xffff)
+                return 0;
+
+        if (band == IEEE80211_BAND_2GHZ) {
+                comp_en = rt2x00_get_field16(eeprom,
+                                 EEPROM_TXPOWER_DELTA_ENABLE_2G);
+                if (comp_en) {
+                        comp_type = rt2x00_get_field16(eeprom,
+                                           EEPROM_TXPOWER_DELTA_TYPE_2G);
+                        comp_value = rt2x00_get_field16(eeprom,
+                                            EEPROM_TXPOWER_DELTA_VALUE_2G);
+                        if (!comp_type)
+                                comp_value = -comp_value;
+                }
+        } else {
+                comp_en = rt2x00_get_field16(eeprom,
+                                 EEPROM_TXPOWER_DELTA_ENABLE_5G);
+                if (comp_en) {
+                        comp_type = rt2x00_get_field16(eeprom,
+                                           EEPROM_TXPOWER_DELTA_TYPE_5G);
+                        comp_value = rt2x00_get_field16(eeprom,
+                                            EEPROM_TXPOWER_DELTA_VALUE_5G);
+                        if (!comp_type)
+                                comp_value = -comp_value;
+                }
+        }
+
+        return comp_value;
+}
+
+static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
+                                     int is_rate_b,
+                                     enum ieee80211_band band,
+                                     int power_level,
+                                     u8 txpower)
+{
+        u32 reg;
+        u16 eeprom;
+        u8 criterion;
+        u8 eirp_txpower;
+        u8 eirp_txpower_criterion;
+        u8 reg_limit;
+        int bw_comp = 0;
+
+        if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
+                return txpower;
+
+        if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
+                bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
+
+        if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
+                /*
+                 * Check if eirp txpower exceed txpower_limit.
+                 * We use OFDM 6M as criterion and its eirp txpower
+                 * is stored at EEPROM_EIRP_MAX_TX_POWER.
+                 * .11b data rate need add additional 4dbm
+                 * when calculating eirp txpower.
+                 */
+                rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
+                criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
+
+                rt2x00_eeprom_read(rt2x00dev,
+                                   EEPROM_EIRP_MAX_TX_POWER, &eeprom);
+
+                if (band == IEEE80211_BAND_2GHZ)
+                        eirp_txpower_criterion = rt2x00_get_field16(eeprom,
+                                                 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
+                else
+                        eirp_txpower_criterion = rt2x00_get_field16(eeprom,
+                                                 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
+
+                eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
+                                       (is_rate_b ? 4 : 0) + bw_comp;
+
+                reg_limit = (eirp_txpower > power_level) ?
+                                        (eirp_txpower - power_level) : 0;
+        } else
+                reg_limit = 0;
+
+        return txpower + bw_comp - reg_limit;
+}
+
 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
-                                  const int max_txpower)
+                                  struct ieee80211_conf *conf)
 {
         u8 txpower;
-        u8 max_value = (u8)max_txpower;
         u16 eeprom;
-        int i;
+        int i, is_rate_b;
         u32 reg;
         u8 r1;
         u32 offset;
+        enum ieee80211_band band = conf->channel->band;
+        int power_level = conf->power_level;
 
         /*
-         * set to normal tx power mode: +/- 0dBm
+         * set to normal bbp tx power control mode: +/- 0dBm
          */
         rt2800_bbp_read(rt2x00dev, 1, &r1);
-        rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
+        rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
         rt2800_bbp_write(rt2x00dev, 1, r1);
-
-        /*
-         * The eeprom contains the tx power values for each rate. These
-         * values map to 100% tx power. Each 16bit word contains four tx
-         * power values and the order is the same as used in the TX_PWR_CFG
-         * registers.
-         */
         offset = TX_PWR_CFG_0;
 
         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
@@ -1681,73 +1911,99 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
                                    &eeprom);
 
-                /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
+                is_rate_b = i ? 0 : 1;
+                /*
+                 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE0);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
 
-                /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
+                /*
+                 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE1);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
 
-                /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
+                /*
+                 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE2);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
 
-                /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
+                /*
+                 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE3);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
 
                 /* read the next four txpower values */
                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
                                    &eeprom);
 
-                /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
+                is_rate_b = 0;
+                /*
+                 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE0);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
 
-                /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
+                /*
+                 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE1);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
 
-                /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
+                /*
+                 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE2);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
 
-                /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
+                /*
+                 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
-                 * TX_PWR_CFG_4: unknown */
+                 * TX_PWR_CFG_4: unknown
+                 */
                 txpower = rt2x00_get_field16(eeprom,
                                              EEPROM_TXPOWER_BYRATE_RATE3);
-                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
-                                   min(txpower, max_value));
+                txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
+                                             power_level, txpower);
+                rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
 
                 rt2800_register_write(rt2x00dev, offset, reg);
 
@@ -1806,11 +2062,13 @@ void rt2800_config(struct rt2x00_dev *rt2x00dev,
         /* Always recalculate LNA gain before changing configuration */
         rt2800_config_lna_gain(rt2x00dev, libconf);
 
-        if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
+        if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
                 rt2800_config_channel(rt2x00dev, libconf->conf,
                                       &libconf->rf, &libconf->channel);
+                rt2800_config_txpower(rt2x00dev, libconf->conf);
+        }
         if (flags & IEEE80211_CONF_CHANGE_POWER)
-                rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
+                rt2800_config_txpower(rt2x00dev, libconf->conf);
         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
                 rt2800_config_retry_limit(rt2x00dev, libconf);
         if (flags & IEEE80211_CONF_CHANGE_PS)
@@ -1839,7 +2097,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
                 if (rt2x00_rt(rt2x00dev, RT3070) ||
                     rt2x00_rt(rt2x00dev, RT3071) ||
                     rt2x00_rt(rt2x00dev, RT3090) ||
-                    rt2x00_rt(rt2x00dev, RT3390))
+                   rt2x00_rt(rt2x00dev, RT3390) ||
+                   rt2x00_rt(rt2x00dev, RT5390))
                         return 0x1c + (2 * rt2x00dev->lna_gain);
                 else
                         return 0x2e + rt2x00dev->lna_gain;
@@ -1971,6 +2230,10 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
+       } else if (rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
+               rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
+               rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
         } else {
                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -2039,7 +2302,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
-        rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
+        rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2052,7 +2315,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
-        rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
+        rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2065,7 +2328,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
-        rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
+        rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2078,7 +2341,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
-        rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
+        rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2091,7 +2354,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
-        rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
+        rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2104,7 +2367,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
-        rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
+        rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2346,15 +2609,31 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                      rt2800_wait_bbp_ready(rt2x00dev)))
                 return -EACCES;
 
-        if (rt2800_is_305x_soc(rt2x00dev))
+       if (rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_bbp_read(rt2x00dev, 4, &value);
+               rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
+               rt2800_bbp_write(rt2x00dev, 4, value);
+       }
+
+       if (rt2800_is_305x_soc(rt2x00dev) ||
+           rt2x00_rt(rt2x00dev, RT5390))
                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
 
         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
         rt2800_bbp_write(rt2x00dev, 66, 0x38);
 
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 68, 0x0b);
+
         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
+       } else if (rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_bbp_write(rt2x00dev, 69, 0x12);
+               rt2800_bbp_write(rt2x00dev, 73, 0x13);
+               rt2800_bbp_write(rt2x00dev, 75, 0x46);
+               rt2800_bbp_write(rt2x00dev, 76, 0x28);
+               rt2800_bbp_write(rt2x00dev, 77, 0x59);
         } else {
                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -2365,7 +2644,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
         if (rt2x00_rt(rt2x00dev, RT3070) ||
             rt2x00_rt(rt2x00dev, RT3071) ||
             rt2x00_rt(rt2x00dev, RT3090) ||
-            rt2x00_rt(rt2x00dev, RT3390)) {
+           rt2x00_rt(rt2x00dev, RT3390) ||
+           rt2x00_rt(rt2x00dev, RT5390)) {
                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
@@ -2377,35 +2657,62 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
         }
 
         rt2800_bbp_write(rt2x00dev, 82, 0x62);
-        rt2800_bbp_write(rt2x00dev, 83, 0x6a);
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 83, 0x7a);
+       else
+               rt2800_bbp_write(rt2x00dev, 83, 0x6a);
 
         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
+       else if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 84, 0x9a);
         else
                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
 
-        rt2800_bbp_write(rt2x00dev, 86, 0x00);
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 86, 0x38);
+       else
+               rt2800_bbp_write(rt2x00dev, 86, 0x00);
+
         rt2800_bbp_write(rt2x00dev, 91, 0x04);
-        rt2800_bbp_write(rt2x00dev, 92, 0x00);
+
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 92, 0x02);
+       else
+               rt2800_bbp_write(rt2x00dev, 92, 0x00);
 
         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
+           rt2x00_rt(rt2x00dev, RT5390) ||
             rt2800_is_305x_soc(rt2x00dev))
                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
         else
                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
 
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 104, 0x92);
+
         if (rt2800_is_305x_soc(rt2x00dev))
                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
+       else if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 105, 0x3c);
         else
                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
-        rt2800_bbp_write(rt2x00dev, 106, 0x35);
+
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 106, 0x03);
+       else
+               rt2800_bbp_write(rt2x00dev, 106, 0x35);
+
+       if (rt2x00_rt(rt2x00dev, RT5390))
+               rt2800_bbp_write(rt2x00dev, 128, 0x12);
 
         if (rt2x00_rt(rt2x00dev, RT3071) ||
             rt2x00_rt(rt2x00dev, RT3090) ||
-            rt2x00_rt(rt2x00dev, RT3390)) {
+           rt2x00_rt(rt2x00dev, RT3390) ||
+           rt2x00_rt(rt2x00dev, RT5390)) {
                 rt2800_bbp_read(rt2x00dev, 138, &value);
 
                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
@@ -2417,6 +2724,41 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
                 rt2800_bbp_write(rt2x00dev, 138, value);
         }
 
+       if (rt2x00_rt(rt2x00dev, RT5390)) {
+               int ant, div_mode;
+
+               rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+               div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
+               ant = (div_mode == 3) ? 1 : 0;
+
+               /* check if this is a Bluetooth combo card */
+               rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+               if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
+                       u32 reg;
+
+                       rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
+                       rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
+                       if (ant == 0)
+                               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
+                       else if (ant == 1)
+                               rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
+                       rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
+               }
+
+               rt2800_bbp_read(rt2x00dev, 152, &value);
+               if (ant == 0)
+                       rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
+               else
+                       rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
+               rt2800_bbp_write(rt2x00dev, 152, value);
+
+               /* Init frequency calibration */
+               rt2800_bbp_write(rt2x00dev, 142, 1);
+               rt2800_bbp_write(rt2x00dev, 143, 57);
+       }
 
         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
@@ -2506,18 +2848,28 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
             !rt2x00_rt(rt2x00dev, RT3071) &&
             !rt2x00_rt(rt2x00dev, RT3090) &&
             !rt2x00_rt(rt2x00dev, RT3390) &&
+           !rt2x00_rt(rt2x00dev, RT5390) &&
             !rt2800_is_305x_soc(rt2x00dev))
                 return 0;
 
         /*
          * Init RF calibration.
          */
-        rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
-        rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
-        rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
-        msleep(1);
-        rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
-        rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
+       if (rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
+               rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
+               msleep(1);
+               rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
+               rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
+       } else {
+               rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
+               rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
+               msleep(1);
+               rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
+               rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
+       }
 
         if (rt2x00_rt(rt2x00dev, RT3070) ||
             rt2x00_rt(rt2x00dev, RT3071) ||
@@ -2608,6 +2960,87 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
                 return 0;
+       } else if (rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
+               rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
+               rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
+               if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
+                       rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
+               else
+                       rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
+               rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
+               rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
+               rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
+               rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
+               rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
+               rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
+
+               rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
+               rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
+               if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
+                       rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
+               else
+                       rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
+               rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
+               rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
+
+               rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
+               rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
+               rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
+               rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
+               rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
+
+               if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
+                       rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
+               else
+                       rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
+               rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
+               rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
+               rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
+               rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
+               rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
+               if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
+                       rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
+               else
+                       rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
+               rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
+               rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
+
+               rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
+               if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
+                       rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
+               else
+                       rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
+               rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
+               rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
+               rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
+               rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
+               rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
+               rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
+
+               rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
+               if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
+                       rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
+               else
+                       rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
+               rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
+               rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
         }
 
         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
@@ -2661,21 +3094,23 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
         }
 
-        /*
-         * Set back to initial state
-         */
-        rt2800_bbp_write(rt2x00dev, 24, 0);
+       if (!rt2x00_rt(rt2x00dev, RT5390)) {
+               /*
+                * Set back to initial state
+                */
+               rt2800_bbp_write(rt2x00dev, 24, 0);
 
-        rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
-        rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
-        rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
+               rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
+               rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
 
-        /*
-         * set BBP back to BW20
-         */
-        rt2800_bbp_read(rt2x00dev, 4, &bbp);
-        rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
-        rt2800_bbp_write(rt2x00dev, 4, bbp);
+               /*
+                * Set BBP back to BW20
+                */
+               rt2800_bbp_read(rt2x00dev, 4, &bbp);
+               rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
+               rt2800_bbp_write(rt2x00dev, 4, bbp);
+       }
 
         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
@@ -2687,21 +3122,23 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
 
-        rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
-        rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
-        if (rt2x00_rt(rt2x00dev, RT3070) ||
-            rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
-            rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
-            rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
-                if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
-                        rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
-        }
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
-        if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
-                rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
-                                  rt2x00_get_field16(eeprom,
-                                                   EEPROM_TXMIXER_GAIN_BG_VAL));
-        rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
+       if (!rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
+               if (rt2x00_rt(rt2x00dev, RT3070) ||
+                   rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
+                   rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
+                   rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
+                       if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
+                               rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
+               }
+               rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
+               if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
+                       rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
+                                       rt2x00_get_field16(eeprom,
+                                               EEPROM_TXMIXER_GAIN_BG_VAL));
+               rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
+       }
 
         if (rt2x00_rt(rt2x00dev, RT3090)) {
                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
@@ -2752,6 +3189,20 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
         }
 
+       if (rt2x00_rt(rt2x00dev, RT5390)) {
+               rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
+               rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
+
+               rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
+               rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
+
+               rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
+               rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
+       }
+
         return 0;
 }
 
@@ -3000,13 +3451,6 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
                                    default_lna_gain);
         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
-        if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
-                rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
-        if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
-                rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
-        rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
-
         return 0;
 }
 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
@@ -3023,10 +3467,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
 
         /*
-         * Identify RF chipset.
+        * Identify RF chipset by EEPROM value
+        * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
+        * RT53xx: defined in "EEPROM_CHIP_ID" field
          */
-        value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
+       if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
+               rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
+       else
+               value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
 
         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
@@ -3038,7 +3487,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
             !rt2x00_rt(rt2x00dev, RT3071) &&
             !rt2x00_rt(rt2x00dev, RT3090) &&
             !rt2x00_rt(rt2x00dev, RT3390) &&
-            !rt2x00_rt(rt2x00dev, RT3572)) {
+           !rt2x00_rt(rt2x00dev, RT3572) &&
+           !rt2x00_rt(rt2x00dev, RT5390)) {
                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
                 return -ENODEV;
         }
@@ -3052,7 +3502,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
             !rt2x00_rf(rt2x00dev, RF3021) &&
             !rt2x00_rf(rt2x00dev, RF3022) &&
             !rt2x00_rf(rt2x00dev, RF3052) &&
-            !rt2x00_rf(rt2x00dev, RF3320)) {
+           !rt2x00_rf(rt2x00dev, RF3320) &&
+           !rt2x00_rf(rt2x00dev, RF5390)) {
                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
                 return -ENODEV;
         }
@@ -3060,11 +3511,35 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
         /*
          * Identify default antenna configuration.
          */
-        rt2x00dev->default_ant.tx =
+        rt2x00dev->default_ant.tx_chain_num =
             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
-        rt2x00dev->default_ant.rx =
+        rt2x00dev->default_ant.rx_chain_num =
             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
 
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+
+        if (rt2x00_rt(rt2x00dev, RT3070) ||
+            rt2x00_rt(rt2x00dev, RT3090) ||
+            rt2x00_rt(rt2x00dev, RT3390)) {
+                value = rt2x00_get_field16(eeprom,
+                                EEPROM_NIC_CONF1_ANT_DIVERSITY);
+                switch (value) {
+                case 0:
+                case 1:
+                case 2:
+                        rt2x00dev->default_ant.tx = ANTENNA_A;
+                        rt2x00dev->default_ant.rx = ANTENNA_A;
+                        break;
+                case 3:
+                        rt2x00dev->default_ant.tx = ANTENNA_A;
+                        rt2x00dev->default_ant.rx = ANTENNA_B;
+                        break;
+                }
+        } else {
+                rt2x00dev->default_ant.tx = ANTENNA_A;
+                rt2x00dev->default_ant.rx = ANTENNA_A;
+        }
+
         /*
          * Read frequency offset and RF programming sequence.
          */
@@ -3098,6 +3573,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
 #endif /* CONFIG_RT2X00_LIB_LEDS */
 
+        /*
+         * Check if support EIRP tx power limit feature.
+         */
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
+
+        if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
+                                        EIRP_MAX_TX_POWER_LIMIT)
+                __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
+
         return 0;
 }
 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
@@ -3250,7 +3734,6 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
         char *default_power1;
         char *default_power2;
         unsigned int i;
-        unsigned short max_power;
         u16 eeprom;
 
         /*
@@ -3317,7 +3800,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
                    rt2x00_rf(rt2x00dev, RF2020) ||
                    rt2x00_rf(rt2x00dev, RF3021) ||
                    rt2x00_rf(rt2x00dev, RF3022) ||
-                   rt2x00_rf(rt2x00dev, RF3320)) {
+                  rt2x00_rf(rt2x00dev, RF3320) ||
+                  rt2x00_rf(rt2x00dev, RF5390)) {
                 spec->num_channels = 14;
                 spec->channels = rf_vals_3x;
         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
@@ -3375,26 +3859,21 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
 
         spec->channels_info = info;
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
-        max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
 
         for (i = 0; i < 14; i++) {
-                info[i].max_power = max_power;
-                info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
-                info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
+                info[i].default_power1 = default_power1[i];
+                info[i].default_power2 = default_power2[i];
         }
 
         if (spec->num_channels > 14) {
-                max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
 
                 for (i = 14; i < spec->num_channels; i++) {
-                        info[i].max_power = max_power;
-                        info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
-                        info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
+                        info[i].default_power1 = default_power1[i];
+                        info[i].default_power2 = default_power2[i];
                 }
         }