diff options
author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-11-04 12:35:54 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-11-06 16:48:55 -0500 |
commit | b54f78a8b7a108a4abc81d88d641769726be23c1 (patch) | |
tree | bd4e050eb359aa095ebfaff37d27d49faf450c19 /drivers/net/wireless/rt2x00/rt2800.h | |
parent | d42c8d86ca52185c053f3352c57b46857573307a (diff) |
rt2800: fix duplication in header files
Updated debugging scripts are located here:
http://www.kernel.org/pub/linux/kernel/people/bart/rt2800/scripts/
(they also work fine with older drivers)
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Acked-by: Ivo van Doorn <IvDoorn@gmail.com>
Acked-by: Gertjan van Wingerde <gwingerde@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800.h')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2800.h | 1819 |
1 files changed, 1819 insertions, 0 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h new file mode 100644 index 000000000000..c5a56bac3bb5 --- /dev/null +++ b/drivers/net/wireless/rt2x00/rt2800.h | |||
@@ -0,0 +1,1819 @@ | |||
1 | /* | ||
2 | Copyright (C) 2004 - 2009 rt2x00 SourceForge Project | ||
3 | <http://rt2x00.serialmonkey.com> | ||
4 | |||
5 | This program is free software; you can redistribute it and/or modify | ||
6 | it under the terms of the GNU General Public License as published by | ||
7 | the Free Software Foundation; either version 2 of the License, or | ||
8 | (at your option) any later version. | ||
9 | |||
10 | This program is distributed in the hope that it will be useful, | ||
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | GNU General Public License for more details. | ||
14 | |||
15 | You should have received a copy of the GNU General Public License | ||
16 | along with this program; if not, write to the | ||
17 | Free Software Foundation, Inc., | ||
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
19 | */ | ||
20 | |||
21 | /* | ||
22 | Module: rt2800 | ||
23 | Abstract: Data structures and registers for the rt2800 modules. | ||
24 | Supported chipsets: RT2800E, RT2800ED & RT2800U. | ||
25 | */ | ||
26 | |||
27 | #ifndef RT2800_H | ||
28 | #define RT2800_H | ||
29 | |||
30 | /* | ||
31 | * RF chip defines. | ||
32 | * | ||
33 | * RF2820 2.4G 2T3R | ||
34 | * RF2850 2.4G/5G 2T3R | ||
35 | * RF2720 2.4G 1T2R | ||
36 | * RF2750 2.4G/5G 1T2R | ||
37 | * RF3020 2.4G 1T1R | ||
38 | * RF2020 2.4G B/G | ||
39 | * RF3021 2.4G 1T2R | ||
40 | * RF3022 2.4G 2T2R | ||
41 | * RF3052 2.4G 2T2R | ||
42 | */ | ||
43 | #define RF2820 0x0001 | ||
44 | #define RF2850 0x0002 | ||
45 | #define RF2720 0x0003 | ||
46 | #define RF2750 0x0004 | ||
47 | #define RF3020 0x0005 | ||
48 | #define RF2020 0x0006 | ||
49 | #define RF3021 0x0007 | ||
50 | #define RF3022 0x0008 | ||
51 | #define RF3052 0x0009 | ||
52 | |||
53 | /* | ||
54 | * Chipset version. | ||
55 | */ | ||
56 | #define RT2860C_VERSION 0x28600100 | ||
57 | #define RT2860D_VERSION 0x28600101 | ||
58 | #define RT2880E_VERSION 0x28720200 | ||
59 | #define RT2883_VERSION 0x28830300 | ||
60 | #define RT3070_VERSION 0x30700200 | ||
61 | |||
62 | /* | ||
63 | * Signal information. | ||
64 | * Default offset is required for RSSI <-> dBm conversion. | ||
65 | */ | ||
66 | #define DEFAULT_RSSI_OFFSET 120 /* FIXME */ | ||
67 | |||
68 | /* | ||
69 | * Register layout information. | ||
70 | */ | ||
71 | #define CSR_REG_BASE 0x1000 | ||
72 | #define CSR_REG_SIZE 0x0800 | ||
73 | #define EEPROM_BASE 0x0000 | ||
74 | #define EEPROM_SIZE 0x0110 | ||
75 | #define BBP_BASE 0x0000 | ||
76 | #define BBP_SIZE 0x0080 | ||
77 | #define RF_BASE 0x0004 | ||
78 | #define RF_SIZE 0x0010 | ||
79 | |||
80 | /* | ||
81 | * Number of TX queues. | ||
82 | */ | ||
83 | #define NUM_TX_QUEUES 4 | ||
84 | |||
85 | /* | ||
86 | * USB registers. | ||
87 | */ | ||
88 | |||
89 | /* | ||
90 | * INT_SOURCE_CSR: Interrupt source register. | ||
91 | * Write one to clear corresponding bit. | ||
92 | * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c | ||
93 | */ | ||
94 | #define INT_SOURCE_CSR 0x0200 | ||
95 | #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) | ||
96 | #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002) | ||
97 | #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004) | ||
98 | #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008) | ||
99 | #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010) | ||
100 | #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020) | ||
101 | #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040) | ||
102 | #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | ||
103 | #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | ||
104 | #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200) | ||
105 | #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400) | ||
106 | #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800) | ||
107 | #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000) | ||
108 | #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | ||
109 | #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000) | ||
110 | #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000) | ||
111 | #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000) | ||
112 | #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000) | ||
113 | |||
114 | /* | ||
115 | * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. | ||
116 | */ | ||
117 | #define INT_MASK_CSR 0x0204 | ||
118 | #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001) | ||
119 | #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002) | ||
120 | #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004) | ||
121 | #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008) | ||
122 | #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010) | ||
123 | #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020) | ||
124 | #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040) | ||
125 | #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080) | ||
126 | #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100) | ||
127 | #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200) | ||
128 | #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400) | ||
129 | #define INT_MASK_CSR_TBTT FIELD32(0x00000800) | ||
130 | #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000) | ||
131 | #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000) | ||
132 | #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000) | ||
133 | #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000) | ||
134 | #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000) | ||
135 | #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000) | ||
136 | |||
137 | /* | ||
138 | * WPDMA_GLO_CFG | ||
139 | */ | ||
140 | #define WPDMA_GLO_CFG 0x0208 | ||
141 | #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001) | ||
142 | #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002) | ||
143 | #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004) | ||
144 | #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008) | ||
145 | #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030) | ||
146 | #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040) | ||
147 | #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080) | ||
148 | #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00) | ||
149 | #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000) | ||
150 | |||
151 | /* | ||
152 | * WPDMA_RST_IDX | ||
153 | */ | ||
154 | #define WPDMA_RST_IDX 0x020c | ||
155 | #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001) | ||
156 | #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002) | ||
157 | #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004) | ||
158 | #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008) | ||
159 | #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010) | ||
160 | #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020) | ||
161 | #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000) | ||
162 | |||
163 | /* | ||
164 | * DELAY_INT_CFG | ||
165 | */ | ||
166 | #define DELAY_INT_CFG 0x0210 | ||
167 | #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff) | ||
168 | #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00) | ||
169 | #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000) | ||
170 | #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000) | ||
171 | #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000) | ||
172 | #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000) | ||
173 | |||
174 | /* | ||
175 | * WMM_AIFSN_CFG: Aifsn for each EDCA AC | ||
176 | * AIFSN0: AC_BE | ||
177 | * AIFSN1: AC_BK | ||
178 | * AIFSN1: AC_VI | ||
179 | * AIFSN1: AC_VO | ||
180 | */ | ||
181 | #define WMM_AIFSN_CFG 0x0214 | ||
182 | #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f) | ||
183 | #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0) | ||
184 | #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00) | ||
185 | #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000) | ||
186 | |||
187 | /* | ||
188 | * WMM_CWMIN_CSR: CWmin for each EDCA AC | ||
189 | * CWMIN0: AC_BE | ||
190 | * CWMIN1: AC_BK | ||
191 | * CWMIN1: AC_VI | ||
192 | * CWMIN1: AC_VO | ||
193 | */ | ||
194 | #define WMM_CWMIN_CFG 0x0218 | ||
195 | #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f) | ||
196 | #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0) | ||
197 | #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00) | ||
198 | #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000) | ||
199 | |||
200 | /* | ||
201 | * WMM_CWMAX_CSR: CWmax for each EDCA AC | ||
202 | * CWMAX0: AC_BE | ||
203 | * CWMAX1: AC_BK | ||
204 | * CWMAX1: AC_VI | ||
205 | * CWMAX1: AC_VO | ||
206 | */ | ||
207 | #define WMM_CWMAX_CFG 0x021c | ||
208 | #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f) | ||
209 | #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0) | ||
210 | #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00) | ||
211 | #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000) | ||
212 | |||
213 | /* | ||
214 | * AC_TXOP0: AC_BK/AC_BE TXOP register | ||
215 | * AC0TXOP: AC_BK in unit of 32us | ||
216 | * AC1TXOP: AC_BE in unit of 32us | ||
217 | */ | ||
218 | #define WMM_TXOP0_CFG 0x0220 | ||
219 | #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff) | ||
220 | #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000) | ||
221 | |||
222 | /* | ||
223 | * AC_TXOP1: AC_VO/AC_VI TXOP register | ||
224 | * AC2TXOP: AC_VI in unit of 32us | ||
225 | * AC3TXOP: AC_VO in unit of 32us | ||
226 | */ | ||
227 | #define WMM_TXOP1_CFG 0x0224 | ||
228 | #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff) | ||
229 | #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000) | ||
230 | |||
231 | /* | ||
232 | * GPIO_CTRL_CFG: | ||
233 | */ | ||
234 | #define GPIO_CTRL_CFG 0x0228 | ||
235 | #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) | ||
236 | #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002) | ||
237 | #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004) | ||
238 | #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008) | ||
239 | #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010) | ||
240 | #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) | ||
241 | #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) | ||
242 | #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) | ||
243 | #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) | ||
244 | |||
245 | /* | ||
246 | * MCU_CMD_CFG | ||
247 | */ | ||
248 | #define MCU_CMD_CFG 0x022c | ||
249 | |||
250 | /* | ||
251 | * AC_BK register offsets | ||
252 | */ | ||
253 | #define TX_BASE_PTR0 0x0230 | ||
254 | #define TX_MAX_CNT0 0x0234 | ||
255 | #define TX_CTX_IDX0 0x0238 | ||
256 | #define TX_DTX_IDX0 0x023c | ||
257 | |||
258 | /* | ||
259 | * AC_BE register offsets | ||
260 | */ | ||
261 | #define TX_BASE_PTR1 0x0240 | ||
262 | #define TX_MAX_CNT1 0x0244 | ||
263 | #define TX_CTX_IDX1 0x0248 | ||
264 | #define TX_DTX_IDX1 0x024c | ||
265 | |||
266 | /* | ||
267 | * AC_VI register offsets | ||
268 | */ | ||
269 | #define TX_BASE_PTR2 0x0250 | ||
270 | #define TX_MAX_CNT2 0x0254 | ||
271 | #define TX_CTX_IDX2 0x0258 | ||
272 | #define TX_DTX_IDX2 0x025c | ||
273 | |||
274 | /* | ||
275 | * AC_VO register offsets | ||
276 | */ | ||
277 | #define TX_BASE_PTR3 0x0260 | ||
278 | #define TX_MAX_CNT3 0x0264 | ||
279 | #define TX_CTX_IDX3 0x0268 | ||
280 | #define TX_DTX_IDX3 0x026c | ||
281 | |||
282 | /* | ||
283 | * HCCA register offsets | ||
284 | */ | ||
285 | #define TX_BASE_PTR4 0x0270 | ||
286 | #define TX_MAX_CNT4 0x0274 | ||
287 | #define TX_CTX_IDX4 0x0278 | ||
288 | #define TX_DTX_IDX4 0x027c | ||
289 | |||
290 | /* | ||
291 | * MGMT register offsets | ||
292 | */ | ||
293 | #define TX_BASE_PTR5 0x0280 | ||
294 | #define TX_MAX_CNT5 0x0284 | ||
295 | #define TX_CTX_IDX5 0x0288 | ||
296 | #define TX_DTX_IDX5 0x028c | ||
297 | |||
298 | /* | ||
299 | * RX register offsets | ||
300 | */ | ||
301 | #define RX_BASE_PTR 0x0290 | ||
302 | #define RX_MAX_CNT 0x0294 | ||
303 | #define RX_CRX_IDX 0x0298 | ||
304 | #define RX_DRX_IDX 0x029c | ||
305 | |||
306 | /* | ||
307 | * PBF_SYS_CTRL | ||
308 | * HOST_RAM_WRITE: enable Host program ram write selection | ||
309 | */ | ||
310 | #define PBF_SYS_CTRL 0x0400 | ||
311 | #define PBF_SYS_CTRL_READY FIELD32(0x00000080) | ||
312 | #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000) | ||
313 | |||
314 | /* | ||
315 | * HOST-MCU shared memory | ||
316 | */ | ||
317 | #define HOST_CMD_CSR 0x0404 | ||
318 | #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff) | ||
319 | |||
320 | /* | ||
321 | * PBF registers | ||
322 | * Most are for debug. Driver doesn't touch PBF register. | ||
323 | */ | ||
324 | #define PBF_CFG 0x0408 | ||
325 | #define PBF_MAX_PCNT 0x040c | ||
326 | #define PBF_CTRL 0x0410 | ||
327 | #define PBF_INT_STA 0x0414 | ||
328 | #define PBF_INT_ENA 0x0418 | ||
329 | |||
330 | /* | ||
331 | * BCN_OFFSET0: | ||
332 | */ | ||
333 | #define BCN_OFFSET0 0x042c | ||
334 | #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff) | ||
335 | #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00) | ||
336 | #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000) | ||
337 | #define BCN_OFFSET0_BCN3 FIELD32(0xff000000) | ||
338 | |||
339 | /* | ||
340 | * BCN_OFFSET1: | ||
341 | */ | ||
342 | #define BCN_OFFSET1 0x0430 | ||
343 | #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff) | ||
344 | #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00) | ||
345 | #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000) | ||
346 | #define BCN_OFFSET1_BCN7 FIELD32(0xff000000) | ||
347 | |||
348 | /* | ||
349 | * PBF registers | ||
350 | * Most are for debug. Driver doesn't touch PBF register. | ||
351 | */ | ||
352 | #define TXRXQ_PCNT 0x0438 | ||
353 | #define PBF_DBG 0x043c | ||
354 | |||
355 | /* | ||
356 | * RF registers | ||
357 | */ | ||
358 | #define RF_CSR_CFG 0x0500 | ||
359 | #define RF_CSR_CFG_DATA FIELD32(0x000000ff) | ||
360 | #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) | ||
361 | #define RF_CSR_CFG_WRITE FIELD32(0x00010000) | ||
362 | #define RF_CSR_CFG_BUSY FIELD32(0x00020000) | ||
363 | |||
364 | /* | ||
365 | * MAC Control/Status Registers(CSR). | ||
366 | * Some values are set in TU, whereas 1 TU == 1024 us. | ||
367 | */ | ||
368 | |||
369 | /* | ||
370 | * MAC_CSR0: ASIC revision number. | ||
371 | * ASIC_REV: 0 | ||
372 | * ASIC_VER: 2860 or 2870 | ||
373 | */ | ||
374 | #define MAC_CSR0 0x1000 | ||
375 | #define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff) | ||
376 | #define MAC_CSR0_ASIC_VER FIELD32(0xffff0000) | ||
377 | |||
378 | /* | ||
379 | * MAC_SYS_CTRL: | ||
380 | */ | ||
381 | #define MAC_SYS_CTRL 0x1004 | ||
382 | #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001) | ||
383 | #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002) | ||
384 | #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004) | ||
385 | #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008) | ||
386 | #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010) | ||
387 | #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020) | ||
388 | #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040) | ||
389 | #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080) | ||
390 | |||
391 | /* | ||
392 | * MAC_ADDR_DW0: STA MAC register 0 | ||
393 | */ | ||
394 | #define MAC_ADDR_DW0 0x1008 | ||
395 | #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff) | ||
396 | #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00) | ||
397 | #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000) | ||
398 | #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000) | ||
399 | |||
400 | /* | ||
401 | * MAC_ADDR_DW1: STA MAC register 1 | ||
402 | * UNICAST_TO_ME_MASK: | ||
403 | * Used to mask off bits from byte 5 of the MAC address | ||
404 | * to determine the UNICAST_TO_ME bit for RX frames. | ||
405 | * The full mask is complemented by BSS_ID_MASK: | ||
406 | * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK | ||
407 | */ | ||
408 | #define MAC_ADDR_DW1 0x100c | ||
409 | #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff) | ||
410 | #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00) | ||
411 | #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000) | ||
412 | |||
413 | /* | ||
414 | * MAC_BSSID_DW0: BSSID register 0 | ||
415 | */ | ||
416 | #define MAC_BSSID_DW0 0x1010 | ||
417 | #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff) | ||
418 | #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00) | ||
419 | #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000) | ||
420 | #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000) | ||
421 | |||
422 | /* | ||
423 | * MAC_BSSID_DW1: BSSID register 1 | ||
424 | * BSS_ID_MASK: | ||
425 | * 0: 1-BSSID mode (BSS index = 0) | ||
426 | * 1: 2-BSSID mode (BSS index: Byte5, bit 0) | ||
427 | * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) | ||
428 | * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) | ||
429 | * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the | ||
430 | * BSSID. This will make sure that those bits will be ignored | ||
431 | * when determining the MY_BSS of RX frames. | ||
432 | */ | ||
433 | #define MAC_BSSID_DW1 0x1014 | ||
434 | #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff) | ||
435 | #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00) | ||
436 | #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000) | ||
437 | #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000) | ||
438 | |||
439 | /* | ||
440 | * MAX_LEN_CFG: Maximum frame length register. | ||
441 | * MAX_MPDU: rt2860b max 16k bytes | ||
442 | * MAX_PSDU: Maximum PSDU length | ||
443 | * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 | ||
444 | */ | ||
445 | #define MAX_LEN_CFG 0x1018 | ||
446 | #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff) | ||
447 | #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000) | ||
448 | #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000) | ||
449 | #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000) | ||
450 | |||
451 | /* | ||
452 | * BBP_CSR_CFG: BBP serial control register | ||
453 | * VALUE: Register value to program into BBP | ||
454 | * REG_NUM: Selected BBP register | ||
455 | * READ_CONTROL: 0 write BBP, 1 read BBP | ||
456 | * BUSY: ASIC is busy executing BBP commands | ||
457 | * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks | ||
458 | * BBP_RW_MODE: 0 serial, 1 paralell | ||
459 | */ | ||
460 | #define BBP_CSR_CFG 0x101c | ||
461 | #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff) | ||
462 | #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00) | ||
463 | #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000) | ||
464 | #define BBP_CSR_CFG_BUSY FIELD32(0x00020000) | ||
465 | #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000) | ||
466 | #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000) | ||
467 | |||
468 | /* | ||
469 | * RF_CSR_CFG0: RF control register | ||
470 | * REGID_AND_VALUE: Register value to program into RF | ||
471 | * BITWIDTH: Selected RF register | ||
472 | * STANDBYMODE: 0 high when standby, 1 low when standby | ||
473 | * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate | ||
474 | * BUSY: ASIC is busy executing RF commands | ||
475 | */ | ||
476 | #define RF_CSR_CFG0 0x1020 | ||
477 | #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff) | ||
478 | #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000) | ||
479 | #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff) | ||
480 | #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000) | ||
481 | #define RF_CSR_CFG0_SEL FIELD32(0x40000000) | ||
482 | #define RF_CSR_CFG0_BUSY FIELD32(0x80000000) | ||
483 | |||
484 | /* | ||
485 | * RF_CSR_CFG1: RF control register | ||
486 | * REGID_AND_VALUE: Register value to program into RF | ||
487 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | ||
488 | * 0: 3 system clock cycle (37.5usec) | ||
489 | * 1: 5 system clock cycle (62.5usec) | ||
490 | */ | ||
491 | #define RF_CSR_CFG1 0x1024 | ||
492 | #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff) | ||
493 | #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000) | ||
494 | |||
495 | /* | ||
496 | * RF_CSR_CFG2: RF control register | ||
497 | * VALUE: Register value to program into RF | ||
498 | * RFGAP: Gap between BB_CONTROL_RF and RF_LE | ||
499 | * 0: 3 system clock cycle (37.5usec) | ||
500 | * 1: 5 system clock cycle (62.5usec) | ||
501 | */ | ||
502 | #define RF_CSR_CFG2 0x1028 | ||
503 | #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff) | ||
504 | |||
505 | /* | ||
506 | * LED_CFG: LED control | ||
507 | * color LED's: | ||
508 | * 0: off | ||
509 | * 1: blinking upon TX2 | ||
510 | * 2: periodic slow blinking | ||
511 | * 3: always on | ||
512 | * LED polarity: | ||
513 | * 0: active low | ||
514 | * 1: active high | ||
515 | */ | ||
516 | #define LED_CFG 0x102c | ||
517 | #define LED_CFG_ON_PERIOD FIELD32(0x000000ff) | ||
518 | #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00) | ||
519 | #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000) | ||
520 | #define LED_CFG_R_LED_MODE FIELD32(0x03000000) | ||
521 | #define LED_CFG_G_LED_MODE FIELD32(0x0c000000) | ||
522 | #define LED_CFG_Y_LED_MODE FIELD32(0x30000000) | ||
523 | #define LED_CFG_LED_POLAR FIELD32(0x40000000) | ||
524 | |||
525 | /* | ||
526 | * XIFS_TIME_CFG: MAC timing | ||
527 | * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX | ||
528 | * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX | ||
529 | * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX | ||
530 | * when MAC doesn't reference BBP signal BBRXEND | ||
531 | * EIFS: unit 1us | ||
532 | * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer | ||
533 | * | ||
534 | */ | ||
535 | #define XIFS_TIME_CFG 0x1100 | ||
536 | #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff) | ||
537 | #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00) | ||
538 | #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000) | ||
539 | #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000) | ||
540 | #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000) | ||
541 | |||
542 | /* | ||
543 | * BKOFF_SLOT_CFG: | ||
544 | */ | ||
545 | #define BKOFF_SLOT_CFG 0x1104 | ||
546 | #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff) | ||
547 | #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00) | ||
548 | |||
549 | /* | ||
550 | * NAV_TIME_CFG: | ||
551 | */ | ||
552 | #define NAV_TIME_CFG 0x1108 | ||
553 | #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff) | ||
554 | #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00) | ||
555 | #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000) | ||
556 | #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000) | ||
557 | |||
558 | /* | ||
559 | * CH_TIME_CFG: count as channel busy | ||
560 | */ | ||
561 | #define CH_TIME_CFG 0x110c | ||
562 | |||
563 | /* | ||
564 | * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us | ||
565 | */ | ||
566 | #define PBF_LIFE_TIMER 0x1110 | ||
567 | |||
568 | /* | ||
569 | * BCN_TIME_CFG: | ||
570 | * BEACON_INTERVAL: in unit of 1/16 TU | ||
571 | * TSF_TICKING: Enable TSF auto counting | ||
572 | * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode | ||
573 | * BEACON_GEN: Enable beacon generator | ||
574 | */ | ||
575 | #define BCN_TIME_CFG 0x1114 | ||
576 | #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff) | ||
577 | #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000) | ||
578 | #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000) | ||
579 | #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000) | ||
580 | #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000) | ||
581 | #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000) | ||
582 | |||
583 | /* | ||
584 | * TBTT_SYNC_CFG: | ||
585 | */ | ||
586 | #define TBTT_SYNC_CFG 0x1118 | ||
587 | |||
588 | /* | ||
589 | * TSF_TIMER_DW0: Local lsb TSF timer, read-only | ||
590 | */ | ||
591 | #define TSF_TIMER_DW0 0x111c | ||
592 | #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff) | ||
593 | |||
594 | /* | ||
595 | * TSF_TIMER_DW1: Local msb TSF timer, read-only | ||
596 | */ | ||
597 | #define TSF_TIMER_DW1 0x1120 | ||
598 | #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff) | ||
599 | |||
600 | /* | ||
601 | * TBTT_TIMER: TImer remains till next TBTT, read-only | ||
602 | */ | ||
603 | #define TBTT_TIMER 0x1124 | ||
604 | |||
605 | /* | ||
606 | * INT_TIMER_CFG: | ||
607 | */ | ||
608 | #define INT_TIMER_CFG 0x1128 | ||
609 | |||
610 | /* | ||
611 | * INT_TIMER_EN: GP-timer and pre-tbtt Int enable | ||
612 | */ | ||
613 | #define INT_TIMER_EN 0x112c | ||
614 | |||
615 | /* | ||
616 | * CH_IDLE_STA: channel idle time | ||
617 | */ | ||
618 | #define CH_IDLE_STA 0x1130 | ||
619 | |||
620 | /* | ||
621 | * CH_BUSY_STA: channel busy time | ||
622 | */ | ||
623 | #define CH_BUSY_STA 0x1134 | ||
624 | |||
625 | /* | ||
626 | * MAC_STATUS_CFG: | ||
627 | * BBP_RF_BUSY: When set to 0, BBP and RF are stable. | ||
628 | * if 1 or higher one of the 2 registers is busy. | ||
629 | */ | ||
630 | #define MAC_STATUS_CFG 0x1200 | ||
631 | #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003) | ||
632 | |||
633 | /* | ||
634 | * PWR_PIN_CFG: | ||
635 | */ | ||
636 | #define PWR_PIN_CFG 0x1204 | ||
637 | |||
638 | /* | ||
639 | * AUTOWAKEUP_CFG: Manual power control / status register | ||
640 | * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set | ||
641 | * AUTOWAKE: 0:sleep, 1:awake | ||
642 | */ | ||
643 | #define AUTOWAKEUP_CFG 0x1208 | ||
644 | #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff) | ||
645 | #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00) | ||
646 | #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) | ||
647 | |||
648 | /* | ||
649 | * EDCA_AC0_CFG: | ||
650 | */ | ||
651 | #define EDCA_AC0_CFG 0x1300 | ||
652 | #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff) | ||
653 | #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00) | ||
654 | #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000) | ||
655 | #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000) | ||
656 | |||
657 | /* | ||
658 | * EDCA_AC1_CFG: | ||
659 | */ | ||
660 | #define EDCA_AC1_CFG 0x1304 | ||
661 | #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff) | ||
662 | #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00) | ||
663 | #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000) | ||
664 | #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000) | ||
665 | |||
666 | /* | ||
667 | * EDCA_AC2_CFG: | ||
668 | */ | ||
669 | #define EDCA_AC2_CFG 0x1308 | ||
670 | #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff) | ||
671 | #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00) | ||
672 | #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000) | ||
673 | #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000) | ||
674 | |||
675 | /* | ||
676 | * EDCA_AC3_CFG: | ||
677 | */ | ||
678 | #define EDCA_AC3_CFG 0x130c | ||
679 | #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff) | ||
680 | #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00) | ||
681 | #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000) | ||
682 | #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000) | ||
683 | |||
684 | /* | ||
685 | * EDCA_TID_AC_MAP: | ||
686 | */ | ||
687 | #define EDCA_TID_AC_MAP 0x1310 | ||
688 | |||
689 | /* | ||
690 | * TX_PWR_CFG_0: | ||
691 | */ | ||
692 | #define TX_PWR_CFG_0 0x1314 | ||
693 | #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f) | ||
694 | #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0) | ||
695 | #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00) | ||
696 | #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000) | ||
697 | #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000) | ||
698 | #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000) | ||
699 | #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000) | ||
700 | #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000) | ||
701 | |||
702 | /* | ||
703 | * TX_PWR_CFG_1: | ||
704 | */ | ||
705 | #define TX_PWR_CFG_1 0x1318 | ||
706 | #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f) | ||
707 | #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0) | ||
708 | #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00) | ||
709 | #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000) | ||
710 | #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000) | ||
711 | #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000) | ||
712 | #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000) | ||
713 | #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000) | ||
714 | |||
715 | /* | ||
716 | * TX_PWR_CFG_2: | ||
717 | */ | ||
718 | #define TX_PWR_CFG_2 0x131c | ||
719 | #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f) | ||
720 | #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0) | ||
721 | #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00) | ||
722 | #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000) | ||
723 | #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000) | ||
724 | #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000) | ||
725 | #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000) | ||
726 | #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000) | ||
727 | |||
728 | /* | ||
729 | * TX_PWR_CFG_3: | ||
730 | */ | ||
731 | #define TX_PWR_CFG_3 0x1320 | ||
732 | #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f) | ||
733 | #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0) | ||
734 | #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00) | ||
735 | #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000) | ||
736 | #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000) | ||
737 | #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000) | ||
738 | #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000) | ||
739 | #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000) | ||
740 | |||
741 | /* | ||
742 | * TX_PWR_CFG_4: | ||
743 | */ | ||
744 | #define TX_PWR_CFG_4 0x1324 | ||
745 | #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f) | ||
746 | #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0) | ||
747 | #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00) | ||
748 | #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000) | ||
749 | |||
750 | /* | ||
751 | * TX_PIN_CFG: | ||
752 | */ | ||
753 | #define TX_PIN_CFG 0x1328 | ||
754 | #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001) | ||
755 | #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002) | ||
756 | #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004) | ||
757 | #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008) | ||
758 | #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010) | ||
759 | #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020) | ||
760 | #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040) | ||
761 | #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080) | ||
762 | #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100) | ||
763 | #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200) | ||
764 | #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400) | ||
765 | #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800) | ||
766 | #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000) | ||
767 | #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000) | ||
768 | #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000) | ||
769 | #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000) | ||
770 | #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000) | ||
771 | #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) | ||
772 | #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) | ||
773 | #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) | ||
774 | |||
775 | /* | ||
776 | * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz | ||
777 | */ | ||
778 | #define TX_BAND_CFG 0x132c | ||
779 | #define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001) | ||
780 | #define TX_BAND_CFG_A FIELD32(0x00000002) | ||
781 | #define TX_BAND_CFG_BG FIELD32(0x00000004) | ||
782 | |||
783 | /* | ||
784 | * TX_SW_CFG0: | ||
785 | */ | ||
786 | #define TX_SW_CFG0 0x1330 | ||
787 | |||
788 | /* | ||
789 | * TX_SW_CFG1: | ||
790 | */ | ||
791 | #define TX_SW_CFG1 0x1334 | ||
792 | |||
793 | /* | ||
794 | * TX_SW_CFG2: | ||
795 | */ | ||
796 | #define TX_SW_CFG2 0x1338 | ||
797 | |||
798 | /* | ||
799 | * TXOP_THRES_CFG: | ||
800 | */ | ||
801 | #define TXOP_THRES_CFG 0x133c | ||
802 | |||
803 | /* | ||
804 | * TXOP_CTRL_CFG: | ||
805 | */ | ||
806 | #define TXOP_CTRL_CFG 0x1340 | ||
807 | |||
808 | /* | ||
809 | * TX_RTS_CFG: | ||
810 | * RTS_THRES: unit:byte | ||
811 | * RTS_FBK_EN: enable rts rate fallback | ||
812 | */ | ||
813 | #define TX_RTS_CFG 0x1344 | ||
814 | #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff) | ||
815 | #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00) | ||
816 | #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000) | ||
817 | |||
818 | /* | ||
819 | * TX_TIMEOUT_CFG: | ||
820 | * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us | ||
821 | * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure | ||
822 | * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. | ||
823 | * it is recommended that: | ||
824 | * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) | ||
825 | */ | ||
826 | #define TX_TIMEOUT_CFG 0x1348 | ||
827 | #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0) | ||
828 | #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00) | ||
829 | #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000) | ||
830 | |||
831 | /* | ||
832 | * TX_RTY_CFG: | ||
833 | * SHORT_RTY_LIMIT: short retry limit | ||
834 | * LONG_RTY_LIMIT: long retry limit | ||
835 | * LONG_RTY_THRE: Long retry threshoold | ||
836 | * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode | ||
837 | * 0:expired by retry limit, 1: expired by mpdu life timer | ||
838 | * AGG_RTY_MODE: Aggregate MPDU retry mode | ||
839 | * 0:expired by retry limit, 1: expired by mpdu life timer | ||
840 | * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable | ||
841 | */ | ||
842 | #define TX_RTY_CFG 0x134c | ||
843 | #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff) | ||
844 | #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00) | ||
845 | #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000) | ||
846 | #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000) | ||
847 | #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000) | ||
848 | #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000) | ||
849 | |||
850 | /* | ||
851 | * TX_LINK_CFG: | ||
852 | * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us | ||
853 | * MFB_ENABLE: TX apply remote MFB 1:enable | ||
854 | * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable | ||
855 | * 0: not apply remote remote unsolicit (MFS=7) | ||
856 | * TX_MRQ_EN: MCS request TX enable | ||
857 | * TX_RDG_EN: RDG TX enable | ||
858 | * TX_CF_ACK_EN: Piggyback CF-ACK enable | ||
859 | * REMOTE_MFB: remote MCS feedback | ||
860 | * REMOTE_MFS: remote MCS feedback sequence number | ||
861 | */ | ||
862 | #define TX_LINK_CFG 0x1350 | ||
863 | #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff) | ||
864 | #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100) | ||
865 | #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200) | ||
866 | #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400) | ||
867 | #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800) | ||
868 | #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000) | ||
869 | #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000) | ||
870 | #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000) | ||
871 | |||
872 | /* | ||
873 | * HT_FBK_CFG0: | ||
874 | */ | ||
875 | #define HT_FBK_CFG0 0x1354 | ||
876 | #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f) | ||
877 | #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0) | ||
878 | #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00) | ||
879 | #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000) | ||
880 | #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000) | ||
881 | #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000) | ||
882 | #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000) | ||
883 | #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000) | ||
884 | |||
885 | /* | ||
886 | * HT_FBK_CFG1: | ||
887 | */ | ||
888 | #define HT_FBK_CFG1 0x1358 | ||
889 | #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f) | ||
890 | #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0) | ||
891 | #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00) | ||
892 | #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000) | ||
893 | #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000) | ||
894 | #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000) | ||
895 | #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000) | ||
896 | #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000) | ||
897 | |||
898 | /* | ||
899 | * LG_FBK_CFG0: | ||
900 | */ | ||
901 | #define LG_FBK_CFG0 0x135c | ||
902 | #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f) | ||
903 | #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0) | ||
904 | #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00) | ||
905 | #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000) | ||
906 | #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000) | ||
907 | #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000) | ||
908 | #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000) | ||
909 | #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000) | ||
910 | |||
911 | /* | ||
912 | * LG_FBK_CFG1: | ||
913 | */ | ||
914 | #define LG_FBK_CFG1 0x1360 | ||
915 | #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f) | ||
916 | #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0) | ||
917 | #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00) | ||
918 | #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000) | ||
919 | |||
920 | /* | ||
921 | * CCK_PROT_CFG: CCK Protection | ||
922 | * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) | ||
923 | * PROTECT_CTRL: Protection control frame type for CCK TX | ||
924 | * 0:none, 1:RTS/CTS, 2:CTS-to-self | ||
925 | * PROTECT_NAV: TXOP protection type for CCK TX | ||
926 | * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect | ||
927 | * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow | ||
928 | * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow | ||
929 | * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow | ||
930 | * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow | ||
931 | * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow | ||
932 | * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow | ||
933 | * RTS_TH_EN: RTS threshold enable on CCK TX | ||
934 | */ | ||
935 | #define CCK_PROT_CFG 0x1364 | ||
936 | #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | ||
937 | #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | ||
938 | #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | ||
939 | #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | ||
940 | #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | ||
941 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | ||
942 | #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | ||
943 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | ||
944 | #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | ||
945 | #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | ||
946 | |||
947 | /* | ||
948 | * OFDM_PROT_CFG: OFDM Protection | ||
949 | */ | ||
950 | #define OFDM_PROT_CFG 0x1368 | ||
951 | #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | ||
952 | #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | ||
953 | #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | ||
954 | #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | ||
955 | #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | ||
956 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | ||
957 | #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | ||
958 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | ||
959 | #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | ||
960 | #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | ||
961 | |||
962 | /* | ||
963 | * MM20_PROT_CFG: MM20 Protection | ||
964 | */ | ||
965 | #define MM20_PROT_CFG 0x136c | ||
966 | #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | ||
967 | #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | ||
968 | #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | ||
969 | #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | ||
970 | #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | ||
971 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | ||
972 | #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | ||
973 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | ||
974 | #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | ||
975 | #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | ||
976 | |||
977 | /* | ||
978 | * MM40_PROT_CFG: MM40 Protection | ||
979 | */ | ||
980 | #define MM40_PROT_CFG 0x1370 | ||
981 | #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | ||
982 | #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | ||
983 | #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | ||
984 | #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | ||
985 | #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | ||
986 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | ||
987 | #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | ||
988 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | ||
989 | #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | ||
990 | #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | ||
991 | |||
992 | /* | ||
993 | * GF20_PROT_CFG: GF20 Protection | ||
994 | */ | ||
995 | #define GF20_PROT_CFG 0x1374 | ||
996 | #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | ||
997 | #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | ||
998 | #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | ||
999 | #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | ||
1000 | #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | ||
1001 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | ||
1002 | #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | ||
1003 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | ||
1004 | #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | ||
1005 | #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | ||
1006 | |||
1007 | /* | ||
1008 | * GF40_PROT_CFG: GF40 Protection | ||
1009 | */ | ||
1010 | #define GF40_PROT_CFG 0x1378 | ||
1011 | #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) | ||
1012 | #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) | ||
1013 | #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) | ||
1014 | #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) | ||
1015 | #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) | ||
1016 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) | ||
1017 | #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000) | ||
1018 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000) | ||
1019 | #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000) | ||
1020 | #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000) | ||
1021 | |||
1022 | /* | ||
1023 | * EXP_CTS_TIME: | ||
1024 | */ | ||
1025 | #define EXP_CTS_TIME 0x137c | ||
1026 | |||
1027 | /* | ||
1028 | * EXP_ACK_TIME: | ||
1029 | */ | ||
1030 | #define EXP_ACK_TIME 0x1380 | ||
1031 | |||
1032 | /* | ||
1033 | * RX_FILTER_CFG: RX configuration register. | ||
1034 | */ | ||
1035 | #define RX_FILTER_CFG 0x1400 | ||
1036 | #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001) | ||
1037 | #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002) | ||
1038 | #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004) | ||
1039 | #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008) | ||
1040 | #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010) | ||
1041 | #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020) | ||
1042 | #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040) | ||
1043 | #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080) | ||
1044 | #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100) | ||
1045 | #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200) | ||
1046 | #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400) | ||
1047 | #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800) | ||
1048 | #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000) | ||
1049 | #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000) | ||
1050 | #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000) | ||
1051 | #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000) | ||
1052 | #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000) | ||
1053 | |||
1054 | /* | ||
1055 | * AUTO_RSP_CFG: | ||
1056 | * AUTORESPONDER: 0: disable, 1: enable | ||
1057 | * BAC_ACK_POLICY: 0:long, 1:short preamble | ||
1058 | * CTS_40_MMODE: Response CTS 40MHz duplicate mode | ||
1059 | * CTS_40_MREF: Response CTS 40MHz duplicate mode | ||
1060 | * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble | ||
1061 | * DUAL_CTS_EN: Power bit value in control frame | ||
1062 | * ACK_CTS_PSM_BIT:Power bit value in control frame | ||
1063 | */ | ||
1064 | #define AUTO_RSP_CFG 0x1404 | ||
1065 | #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001) | ||
1066 | #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002) | ||
1067 | #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004) | ||
1068 | #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008) | ||
1069 | #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010) | ||
1070 | #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040) | ||
1071 | #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080) | ||
1072 | |||
1073 | /* | ||
1074 | * LEGACY_BASIC_RATE: | ||
1075 | */ | ||
1076 | #define LEGACY_BASIC_RATE 0x1408 | ||
1077 | |||
1078 | /* | ||
1079 | * HT_BASIC_RATE: | ||
1080 | */ | ||
1081 | #define HT_BASIC_RATE 0x140c | ||
1082 | |||
1083 | /* | ||
1084 | * HT_CTRL_CFG: | ||
1085 | */ | ||
1086 | #define HT_CTRL_CFG 0x1410 | ||
1087 | |||
1088 | /* | ||
1089 | * SIFS_COST_CFG: | ||
1090 | */ | ||
1091 | #define SIFS_COST_CFG 0x1414 | ||
1092 | |||
1093 | /* | ||
1094 | * RX_PARSER_CFG: | ||
1095 | * Set NAV for all received frames | ||
1096 | */ | ||
1097 | #define RX_PARSER_CFG 0x1418 | ||
1098 | |||
1099 | /* | ||
1100 | * TX_SEC_CNT0: | ||
1101 | */ | ||
1102 | #define TX_SEC_CNT0 0x1500 | ||
1103 | |||
1104 | /* | ||
1105 | * RX_SEC_CNT0: | ||
1106 | */ | ||
1107 | #define RX_SEC_CNT0 0x1504 | ||
1108 | |||
1109 | /* | ||
1110 | * CCMP_FC_MUTE: | ||
1111 | */ | ||
1112 | #define CCMP_FC_MUTE 0x1508 | ||
1113 | |||
1114 | /* | ||
1115 | * TXOP_HLDR_ADDR0: | ||
1116 | */ | ||
1117 | #define TXOP_HLDR_ADDR0 0x1600 | ||
1118 | |||
1119 | /* | ||
1120 | * TXOP_HLDR_ADDR1: | ||
1121 | */ | ||
1122 | #define TXOP_HLDR_ADDR1 0x1604 | ||
1123 | |||
1124 | /* | ||
1125 | * TXOP_HLDR_ET: | ||
1126 | */ | ||
1127 | #define TXOP_HLDR_ET 0x1608 | ||
1128 | |||
1129 | /* | ||
1130 | * QOS_CFPOLL_RA_DW0: | ||
1131 | */ | ||
1132 | #define QOS_CFPOLL_RA_DW0 0x160c | ||
1133 | |||
1134 | /* | ||
1135 | * QOS_CFPOLL_RA_DW1: | ||
1136 | */ | ||
1137 | #define QOS_CFPOLL_RA_DW1 0x1610 | ||
1138 | |||
1139 | /* | ||
1140 | * QOS_CFPOLL_QC: | ||
1141 | */ | ||
1142 | #define QOS_CFPOLL_QC 0x1614 | ||
1143 | |||
1144 | /* | ||
1145 | * RX_STA_CNT0: RX PLCP error count & RX CRC error count | ||
1146 | */ | ||
1147 | #define RX_STA_CNT0 0x1700 | ||
1148 | #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff) | ||
1149 | #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000) | ||
1150 | |||
1151 | /* | ||
1152 | * RX_STA_CNT1: RX False CCA count & RX LONG frame count | ||
1153 | */ | ||
1154 | #define RX_STA_CNT1 0x1704 | ||
1155 | #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff) | ||
1156 | #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000) | ||
1157 | |||
1158 | /* | ||
1159 | * RX_STA_CNT2: | ||
1160 | */ | ||
1161 | #define RX_STA_CNT2 0x1708 | ||
1162 | #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff) | ||
1163 | #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000) | ||
1164 | |||
1165 | /* | ||
1166 | * TX_STA_CNT0: TX Beacon count | ||
1167 | */ | ||
1168 | #define TX_STA_CNT0 0x170c | ||
1169 | #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff) | ||
1170 | #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000) | ||
1171 | |||
1172 | /* | ||
1173 | * TX_STA_CNT1: TX tx count | ||
1174 | */ | ||
1175 | #define TX_STA_CNT1 0x1710 | ||
1176 | #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff) | ||
1177 | #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000) | ||
1178 | |||
1179 | /* | ||
1180 | * TX_STA_CNT2: TX tx count | ||
1181 | */ | ||
1182 | #define TX_STA_CNT2 0x1714 | ||
1183 | #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff) | ||
1184 | #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000) | ||
1185 | |||
1186 | /* | ||
1187 | * TX_STA_FIFO: TX Result for specific PID status fifo register | ||
1188 | */ | ||
1189 | #define TX_STA_FIFO 0x1718 | ||
1190 | #define TX_STA_FIFO_VALID FIELD32(0x00000001) | ||
1191 | #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e) | ||
1192 | #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020) | ||
1193 | #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040) | ||
1194 | #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080) | ||
1195 | #define TX_STA_FIFO_WCID FIELD32(0x0000ff00) | ||
1196 | #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000) | ||
1197 | #define TX_STA_FIFO_MCS FIELD32(0x007f0000) | ||
1198 | #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000) | ||
1199 | |||
1200 | /* | ||
1201 | * TX_AGG_CNT: Debug counter | ||
1202 | */ | ||
1203 | #define TX_AGG_CNT 0x171c | ||
1204 | #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff) | ||
1205 | #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000) | ||
1206 | |||
1207 | /* | ||
1208 | * TX_AGG_CNT0: | ||
1209 | */ | ||
1210 | #define TX_AGG_CNT0 0x1720 | ||
1211 | #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff) | ||
1212 | #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000) | ||
1213 | |||
1214 | /* | ||
1215 | * TX_AGG_CNT1: | ||
1216 | */ | ||
1217 | #define TX_AGG_CNT1 0x1724 | ||
1218 | #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff) | ||
1219 | #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000) | ||
1220 | |||
1221 | /* | ||
1222 | * TX_AGG_CNT2: | ||
1223 | */ | ||
1224 | #define TX_AGG_CNT2 0x1728 | ||
1225 | #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff) | ||
1226 | #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000) | ||
1227 | |||
1228 | /* | ||
1229 | * TX_AGG_CNT3: | ||
1230 | */ | ||
1231 | #define TX_AGG_CNT3 0x172c | ||
1232 | #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff) | ||
1233 | #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000) | ||
1234 | |||
1235 | /* | ||
1236 | * TX_AGG_CNT4: | ||
1237 | */ | ||
1238 | #define TX_AGG_CNT4 0x1730 | ||
1239 | #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff) | ||
1240 | #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000) | ||
1241 | |||
1242 | /* | ||
1243 | * TX_AGG_CNT5: | ||
1244 | */ | ||
1245 | #define TX_AGG_CNT5 0x1734 | ||
1246 | #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff) | ||
1247 | #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000) | ||
1248 | |||
1249 | /* | ||
1250 | * TX_AGG_CNT6: | ||
1251 | */ | ||
1252 | #define TX_AGG_CNT6 0x1738 | ||
1253 | #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff) | ||
1254 | #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000) | ||
1255 | |||
1256 | /* | ||
1257 | * TX_AGG_CNT7: | ||
1258 | */ | ||
1259 | #define TX_AGG_CNT7 0x173c | ||
1260 | #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff) | ||
1261 | #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000) | ||
1262 | |||
1263 | /* | ||
1264 | * MPDU_DENSITY_CNT: | ||
1265 | * TX_ZERO_DEL: TX zero length delimiter count | ||
1266 | * RX_ZERO_DEL: RX zero length delimiter count | ||
1267 | */ | ||
1268 | #define MPDU_DENSITY_CNT 0x1740 | ||
1269 | #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff) | ||
1270 | #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000) | ||
1271 | |||
1272 | /* | ||
1273 | * Security key table memory. | ||
1274 | * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry | ||
1275 | * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry | ||
1276 | * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry | ||
1277 | * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry | ||
1278 | * SHARED_KEY_TABLE_BASE: 32 bytes * 32-entry | ||
1279 | * SHARED_KEY_MODE_BASE: 4 bits * 32-entry | ||
1280 | */ | ||
1281 | #define MAC_WCID_BASE 0x1800 | ||
1282 | #define PAIRWISE_KEY_TABLE_BASE 0x4000 | ||
1283 | #define MAC_IVEIV_TABLE_BASE 0x6000 | ||
1284 | #define MAC_WCID_ATTRIBUTE_BASE 0x6800 | ||
1285 | #define SHARED_KEY_TABLE_BASE 0x6c00 | ||
1286 | #define SHARED_KEY_MODE_BASE 0x7000 | ||
1287 | |||
1288 | #define MAC_WCID_ENTRY(__idx) \ | ||
1289 | ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) ) | ||
1290 | #define PAIRWISE_KEY_ENTRY(__idx) \ | ||
1291 | ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) | ||
1292 | #define MAC_IVEIV_ENTRY(__idx) \ | ||
1293 | ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) ) | ||
1294 | #define MAC_WCID_ATTR_ENTRY(__idx) \ | ||
1295 | ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) ) | ||
1296 | #define SHARED_KEY_ENTRY(__idx) \ | ||
1297 | ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) ) | ||
1298 | #define SHARED_KEY_MODE_ENTRY(__idx) \ | ||
1299 | ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) ) | ||
1300 | |||
1301 | struct mac_wcid_entry { | ||
1302 | u8 mac[6]; | ||
1303 | u8 reserved[2]; | ||
1304 | } __attribute__ ((packed)); | ||
1305 | |||
1306 | struct hw_key_entry { | ||
1307 | u8 key[16]; | ||
1308 | u8 tx_mic[8]; | ||
1309 | u8 rx_mic[8]; | ||
1310 | } __attribute__ ((packed)); | ||
1311 | |||
1312 | struct mac_iveiv_entry { | ||
1313 | u8 iv[8]; | ||
1314 | } __attribute__ ((packed)); | ||
1315 | |||
1316 | /* | ||
1317 | * MAC_WCID_ATTRIBUTE: | ||
1318 | */ | ||
1319 | #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001) | ||
1320 | #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e) | ||
1321 | #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070) | ||
1322 | #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380) | ||
1323 | |||
1324 | /* | ||
1325 | * SHARED_KEY_MODE: | ||
1326 | */ | ||
1327 | #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007) | ||
1328 | #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070) | ||
1329 | #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700) | ||
1330 | #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000) | ||
1331 | #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000) | ||
1332 | #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000) | ||
1333 | #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000) | ||
1334 | #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000) | ||
1335 | |||
1336 | /* | ||
1337 | * HOST-MCU communication | ||
1338 | */ | ||
1339 | |||
1340 | /* | ||
1341 | * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. | ||
1342 | */ | ||
1343 | #define H2M_MAILBOX_CSR 0x7010 | ||
1344 | #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff) | ||
1345 | #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00) | ||
1346 | #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000) | ||
1347 | #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000) | ||
1348 | |||
1349 | /* | ||
1350 | * H2M_MAILBOX_CID: | ||
1351 | */ | ||
1352 | #define H2M_MAILBOX_CID 0x7014 | ||
1353 | #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff) | ||
1354 | #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00) | ||
1355 | #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000) | ||
1356 | #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000) | ||
1357 | |||
1358 | /* | ||
1359 | * H2M_MAILBOX_STATUS: | ||
1360 | */ | ||
1361 | #define H2M_MAILBOX_STATUS 0x701c | ||
1362 | |||
1363 | /* | ||
1364 | * H2M_INT_SRC: | ||
1365 | */ | ||
1366 | #define H2M_INT_SRC 0x7024 | ||
1367 | |||
1368 | /* | ||
1369 | * H2M_BBP_AGENT: | ||
1370 | */ | ||
1371 | #define H2M_BBP_AGENT 0x7028 | ||
1372 | |||
1373 | /* | ||
1374 | * MCU_LEDCS: LED control for MCU Mailbox. | ||
1375 | */ | ||
1376 | #define MCU_LEDCS_LED_MODE FIELD8(0x1f) | ||
1377 | #define MCU_LEDCS_POLARITY FIELD8(0x01) | ||
1378 | |||
1379 | /* | ||
1380 | * HW_CS_CTS_BASE: | ||
1381 | * Carrier-sense CTS frame base address. | ||
1382 | * It's where mac stores carrier-sense frame for carrier-sense function. | ||
1383 | */ | ||
1384 | #define HW_CS_CTS_BASE 0x7700 | ||
1385 | |||
1386 | /* | ||
1387 | * HW_DFS_CTS_BASE: | ||
1388 | * FS CTS frame base address. It's where mac stores CTS frame for DFS. | ||
1389 | */ | ||
1390 | #define HW_DFS_CTS_BASE 0x7780 | ||
1391 | |||
1392 | /* | ||
1393 | * TXRX control registers - base address 0x3000 | ||
1394 | */ | ||
1395 | |||
1396 | /* | ||
1397 | * TXRX_CSR1: | ||
1398 | * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. | ||
1399 | */ | ||
1400 | #define TXRX_CSR1 0x77d0 | ||
1401 | |||
1402 | /* | ||
1403 | * HW_DEBUG_SETTING_BASE: | ||
1404 | * since NULL frame won't be that long (256 byte) | ||
1405 | * We steal 16 tail bytes to save debugging settings | ||
1406 | */ | ||
1407 | #define HW_DEBUG_SETTING_BASE 0x77f0 | ||
1408 | #define HW_DEBUG_SETTING_BASE2 0x7770 | ||
1409 | |||
1410 | /* | ||
1411 | * HW_BEACON_BASE | ||
1412 | * In order to support maximum 8 MBSS and its maximum length | ||
1413 | * is 512 bytes for each beacon | ||
1414 | * Three section discontinue memory segments will be used. | ||
1415 | * 1. The original region for BCN 0~3 | ||
1416 | * 2. Extract memory from FCE table for BCN 4~5 | ||
1417 | * 3. Extract memory from Pair-wise key table for BCN 6~7 | ||
1418 | * It occupied those memory of wcid 238~253 for BCN 6 | ||
1419 | * and wcid 222~237 for BCN 7 | ||
1420 | * | ||
1421 | * IMPORTANT NOTE: Not sure why legacy driver does this, | ||
1422 | * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. | ||
1423 | */ | ||
1424 | #define HW_BEACON_BASE0 0x7800 | ||
1425 | #define HW_BEACON_BASE1 0x7a00 | ||
1426 | #define HW_BEACON_BASE2 0x7c00 | ||
1427 | #define HW_BEACON_BASE3 0x7e00 | ||
1428 | #define HW_BEACON_BASE4 0x7200 | ||
1429 | #define HW_BEACON_BASE5 0x7400 | ||
1430 | #define HW_BEACON_BASE6 0x5dc0 | ||
1431 | #define HW_BEACON_BASE7 0x5bc0 | ||
1432 | |||
1433 | #define HW_BEACON_OFFSET(__index) \ | ||
1434 | ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \ | ||
1435 | (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \ | ||
1436 | (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) ) | ||
1437 | |||
1438 | /* | ||
1439 | * BBP registers. | ||
1440 | * The wordsize of the BBP is 8 bits. | ||
1441 | */ | ||
1442 | |||
1443 | /* | ||
1444 | * BBP 1: TX Antenna | ||
1445 | */ | ||
1446 | #define BBP1_TX_POWER FIELD8(0x07) | ||
1447 | #define BBP1_TX_ANTENNA FIELD8(0x18) | ||
1448 | |||
1449 | /* | ||
1450 | * BBP 3: RX Antenna | ||
1451 | */ | ||
1452 | #define BBP3_RX_ANTENNA FIELD8(0x18) | ||
1453 | #define BBP3_HT40_PLUS FIELD8(0x20) | ||
1454 | |||
1455 | /* | ||
1456 | * BBP 4: Bandwidth | ||
1457 | */ | ||
1458 | #define BBP4_TX_BF FIELD8(0x01) | ||
1459 | #define BBP4_BANDWIDTH FIELD8(0x18) | ||
1460 | |||
1461 | /* | ||
1462 | * RFCSR registers | ||
1463 | * The wordsize of the RFCSR is 8 bits. | ||
1464 | */ | ||
1465 | |||
1466 | /* | ||
1467 | * RFCSR 6: | ||
1468 | */ | ||
1469 | #define RFCSR6_R FIELD8(0x03) | ||
1470 | |||
1471 | /* | ||
1472 | * RFCSR 7: | ||
1473 | */ | ||
1474 | #define RFCSR7_RF_TUNING FIELD8(0x01) | ||
1475 | |||
1476 | /* | ||
1477 | * RFCSR 12: | ||
1478 | */ | ||
1479 | #define RFCSR12_TX_POWER FIELD8(0x1f) | ||
1480 | |||
1481 | /* | ||
1482 | * RFCSR 22: | ||
1483 | */ | ||
1484 | #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) | ||
1485 | |||
1486 | /* | ||
1487 | * RFCSR 23: | ||
1488 | */ | ||
1489 | #define RFCSR23_FREQ_OFFSET FIELD8(0x7f) | ||
1490 | |||
1491 | /* | ||
1492 | * RFCSR 30: | ||
1493 | */ | ||
1494 | #define RFCSR30_RF_CALIBRATION FIELD8(0x80) | ||
1495 | |||
1496 | /* | ||
1497 | * RF registers | ||
1498 | */ | ||
1499 | |||
1500 | /* | ||
1501 | * RF 2 | ||
1502 | */ | ||
1503 | #define RF2_ANTENNA_RX2 FIELD32(0x00000040) | ||
1504 | #define RF2_ANTENNA_TX1 FIELD32(0x00004000) | ||
1505 | #define RF2_ANTENNA_RX1 FIELD32(0x00020000) | ||
1506 | |||
1507 | /* | ||
1508 | * RF 3 | ||
1509 | */ | ||
1510 | #define RF3_TXPOWER_G FIELD32(0x00003e00) | ||
1511 | #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200) | ||
1512 | #define RF3_TXPOWER_A FIELD32(0x00003c00) | ||
1513 | |||
1514 | /* | ||
1515 | * RF 4 | ||
1516 | */ | ||
1517 | #define RF4_TXPOWER_G FIELD32(0x000007c0) | ||
1518 | #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040) | ||
1519 | #define RF4_TXPOWER_A FIELD32(0x00000780) | ||
1520 | #define RF4_FREQ_OFFSET FIELD32(0x001f8000) | ||
1521 | #define RF4_HT40 FIELD32(0x00200000) | ||
1522 | |||
1523 | /* | ||
1524 | * EEPROM content. | ||
1525 | * The wordsize of the EEPROM is 16 bits. | ||
1526 | */ | ||
1527 | |||
1528 | /* | ||
1529 | * EEPROM Version | ||
1530 | */ | ||
1531 | #define EEPROM_VERSION 0x0001 | ||
1532 | #define EEPROM_VERSION_FAE FIELD16(0x00ff) | ||
1533 | #define EEPROM_VERSION_VERSION FIELD16(0xff00) | ||
1534 | |||
1535 | /* | ||
1536 | * HW MAC address. | ||
1537 | */ | ||
1538 | #define EEPROM_MAC_ADDR_0 0x0002 | ||
1539 | #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) | ||
1540 | #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) | ||
1541 | #define EEPROM_MAC_ADDR_1 0x0003 | ||
1542 | #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) | ||
1543 | #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) | ||
1544 | #define EEPROM_MAC_ADDR_2 0x0004 | ||
1545 | #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) | ||
1546 | #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) | ||
1547 | |||
1548 | /* | ||
1549 | * EEPROM ANTENNA config | ||
1550 | * RXPATH: 1: 1R, 2: 2R, 3: 3R | ||
1551 | * TXPATH: 1: 1T, 2: 2T | ||
1552 | */ | ||
1553 | #define EEPROM_ANTENNA 0x001a | ||
1554 | #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f) | ||
1555 | #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0) | ||
1556 | #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00) | ||
1557 | |||
1558 | /* | ||
1559 | * EEPROM NIC config | ||
1560 | * CARDBUS_ACCEL: 0 - enable, 1 - disable | ||
1561 | */ | ||
1562 | #define EEPROM_NIC 0x001b | ||
1563 | #define EEPROM_NIC_HW_RADIO FIELD16(0x0001) | ||
1564 | #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002) | ||
1565 | #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004) | ||
1566 | #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008) | ||
1567 | #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010) | ||
1568 | #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020) | ||
1569 | #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040) | ||
1570 | #define EEPROM_NIC_WPS_PBC FIELD16(0x0080) | ||
1571 | #define EEPROM_NIC_BW40M_BG FIELD16(0x0100) | ||
1572 | #define EEPROM_NIC_BW40M_A FIELD16(0x0200) | ||
1573 | |||
1574 | /* | ||
1575 | * EEPROM frequency | ||
1576 | */ | ||
1577 | #define EEPROM_FREQ 0x001d | ||
1578 | #define EEPROM_FREQ_OFFSET FIELD16(0x00ff) | ||
1579 | #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00) | ||
1580 | #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000) | ||
1581 | |||
1582 | /* | ||
1583 | * EEPROM LED | ||
1584 | * POLARITY_RDY_G: Polarity RDY_G setting. | ||
1585 | * POLARITY_RDY_A: Polarity RDY_A setting. | ||
1586 | * POLARITY_ACT: Polarity ACT setting. | ||
1587 | * POLARITY_GPIO_0: Polarity GPIO0 setting. | ||
1588 | * POLARITY_GPIO_1: Polarity GPIO1 setting. | ||
1589 | * POLARITY_GPIO_2: Polarity GPIO2 setting. | ||
1590 | * POLARITY_GPIO_3: Polarity GPIO3 setting. | ||
1591 | * POLARITY_GPIO_4: Polarity GPIO4 setting. | ||
1592 | * LED_MODE: Led mode. | ||
1593 | */ | ||
1594 | #define EEPROM_LED1 0x001e | ||
1595 | #define EEPROM_LED2 0x001f | ||
1596 | #define EEPROM_LED3 0x0020 | ||
1597 | #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001) | ||
1598 | #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002) | ||
1599 | #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004) | ||
1600 | #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008) | ||
1601 | #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010) | ||
1602 | #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020) | ||
1603 | #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040) | ||
1604 | #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080) | ||
1605 | #define EEPROM_LED_LED_MODE FIELD16(0x1f00) | ||
1606 | |||
1607 | /* | ||
1608 | * EEPROM LNA | ||
1609 | */ | ||
1610 | #define EEPROM_LNA 0x0022 | ||
1611 | #define EEPROM_LNA_BG FIELD16(0x00ff) | ||
1612 | #define EEPROM_LNA_A0 FIELD16(0xff00) | ||
1613 | |||
1614 | /* | ||
1615 | * EEPROM RSSI BG offset | ||
1616 | */ | ||
1617 | #define EEPROM_RSSI_BG 0x0023 | ||
1618 | #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff) | ||
1619 | #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00) | ||
1620 | |||
1621 | /* | ||
1622 | * EEPROM RSSI BG2 offset | ||
1623 | */ | ||
1624 | #define EEPROM_RSSI_BG2 0x0024 | ||
1625 | #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff) | ||
1626 | #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) | ||
1627 | |||
1628 | /* | ||
1629 | * EEPROM RSSI A offset | ||
1630 | */ | ||
1631 | #define EEPROM_RSSI_A 0x0025 | ||
1632 | #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff) | ||
1633 | #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00) | ||
1634 | |||
1635 | /* | ||
1636 | * EEPROM RSSI A2 offset | ||
1637 | */ | ||
1638 | #define EEPROM_RSSI_A2 0x0026 | ||
1639 | #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff) | ||
1640 | #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) | ||
1641 | |||
1642 | /* | ||
1643 | * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. | ||
1644 | * This is delta in 40MHZ. | ||
1645 | * VALUE: Tx Power dalta value (MAX=4) | ||
1646 | * TYPE: 1: Plus the delta value, 0: minus the delta value | ||
1647 | * TXPOWER: Enable: | ||
1648 | */ | ||
1649 | #define EEPROM_TXPOWER_DELTA 0x0028 | ||
1650 | #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) | ||
1651 | #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) | ||
1652 | #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) | ||
1653 | |||
1654 | /* | ||
1655 | * EEPROM TXPOWER 802.11BG | ||
1656 | */ | ||
1657 | #define EEPROM_TXPOWER_BG1 0x0029 | ||
1658 | #define EEPROM_TXPOWER_BG2 0x0030 | ||
1659 | #define EEPROM_TXPOWER_BG_SIZE 7 | ||
1660 | #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff) | ||
1661 | #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00) | ||
1662 | |||
1663 | /* | ||
1664 | * EEPROM TXPOWER 802.11A | ||
1665 | */ | ||
1666 | #define EEPROM_TXPOWER_A1 0x003c | ||
1667 | #define EEPROM_TXPOWER_A2 0x0053 | ||
1668 | #define EEPROM_TXPOWER_A_SIZE 6 | ||
1669 | #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff) | ||
1670 | #define EEPROM_TXPOWER_A_2 FIELD16(0xff00) | ||
1671 | |||
1672 | /* | ||
1673 | * EEPROM TXpower byrate: 20MHZ power | ||
1674 | */ | ||
1675 | #define EEPROM_TXPOWER_BYRATE 0x006f | ||
1676 | |||
1677 | /* | ||
1678 | * EEPROM BBP. | ||
1679 | */ | ||
1680 | #define EEPROM_BBP_START 0x0078 | ||
1681 | #define EEPROM_BBP_SIZE 16 | ||
1682 | #define EEPROM_BBP_VALUE FIELD16(0x00ff) | ||
1683 | #define EEPROM_BBP_REG_ID FIELD16(0xff00) | ||
1684 | |||
1685 | /* | ||
1686 | * MCU mailbox commands. | ||
1687 | */ | ||
1688 | #define MCU_SLEEP 0x30 | ||
1689 | #define MCU_WAKEUP 0x31 | ||
1690 | #define MCU_RADIO_OFF 0x35 | ||
1691 | #define MCU_CURRENT 0x36 | ||
1692 | #define MCU_LED 0x50 | ||
1693 | #define MCU_LED_STRENGTH 0x51 | ||
1694 | #define MCU_LED_1 0x52 | ||
1695 | #define MCU_LED_2 0x53 | ||
1696 | #define MCU_LED_3 0x54 | ||
1697 | #define MCU_RADAR 0x60 | ||
1698 | #define MCU_BOOT_SIGNAL 0x72 | ||
1699 | #define MCU_BBP_SIGNAL 0x80 | ||
1700 | #define MCU_POWER_SAVE 0x83 | ||
1701 | |||
1702 | /* | ||
1703 | * MCU mailbox tokens | ||
1704 | */ | ||
1705 | #define TOKEN_WAKUP 3 | ||
1706 | |||
1707 | /* | ||
1708 | * DMA descriptor defines. | ||
1709 | */ | ||
1710 | #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) ) | ||
1711 | #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) ) | ||
1712 | |||
1713 | /* | ||
1714 | * TX WI structure | ||
1715 | */ | ||
1716 | |||
1717 | /* | ||
1718 | * Word0 | ||
1719 | * FRAG: 1 To inform TKIP engine this is a fragment. | ||
1720 | * MIMO_PS: The remote peer is in dynamic MIMO-PS mode | ||
1721 | * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs | ||
1722 | * BW: Channel bandwidth 20MHz or 40 MHz | ||
1723 | * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED | ||
1724 | */ | ||
1725 | #define TXWI_W0_FRAG FIELD32(0x00000001) | ||
1726 | #define TXWI_W0_MIMO_PS FIELD32(0x00000002) | ||
1727 | #define TXWI_W0_CF_ACK FIELD32(0x00000004) | ||
1728 | #define TXWI_W0_TS FIELD32(0x00000008) | ||
1729 | #define TXWI_W0_AMPDU FIELD32(0x00000010) | ||
1730 | #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0) | ||
1731 | #define TXWI_W0_TX_OP FIELD32(0x00000300) | ||
1732 | #define TXWI_W0_MCS FIELD32(0x007f0000) | ||
1733 | #define TXWI_W0_BW FIELD32(0x00800000) | ||
1734 | #define TXWI_W0_SHORT_GI FIELD32(0x01000000) | ||
1735 | #define TXWI_W0_STBC FIELD32(0x06000000) | ||
1736 | #define TXWI_W0_IFS FIELD32(0x08000000) | ||
1737 | #define TXWI_W0_PHYMODE FIELD32(0xc0000000) | ||
1738 | |||
1739 | /* | ||
1740 | * Word1 | ||
1741 | */ | ||
1742 | #define TXWI_W1_ACK FIELD32(0x00000001) | ||
1743 | #define TXWI_W1_NSEQ FIELD32(0x00000002) | ||
1744 | #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc) | ||
1745 | #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00) | ||
1746 | #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | ||
1747 | #define TXWI_W1_PACKETID FIELD32(0xf0000000) | ||
1748 | |||
1749 | /* | ||
1750 | * Word2 | ||
1751 | */ | ||
1752 | #define TXWI_W2_IV FIELD32(0xffffffff) | ||
1753 | |||
1754 | /* | ||
1755 | * Word3 | ||
1756 | */ | ||
1757 | #define TXWI_W3_EIV FIELD32(0xffffffff) | ||
1758 | |||
1759 | /* | ||
1760 | * RX WI structure | ||
1761 | */ | ||
1762 | |||
1763 | /* | ||
1764 | * Word0 | ||
1765 | */ | ||
1766 | #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff) | ||
1767 | #define RXWI_W0_KEY_INDEX FIELD32(0x00000300) | ||
1768 | #define RXWI_W0_BSSID FIELD32(0x00001c00) | ||
1769 | #define RXWI_W0_UDF FIELD32(0x0000e000) | ||
1770 | #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000) | ||
1771 | #define RXWI_W0_TID FIELD32(0xf0000000) | ||
1772 | |||
1773 | /* | ||
1774 | * Word1 | ||
1775 | */ | ||
1776 | #define RXWI_W1_FRAG FIELD32(0x0000000f) | ||
1777 | #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0) | ||
1778 | #define RXWI_W1_MCS FIELD32(0x007f0000) | ||
1779 | #define RXWI_W1_BW FIELD32(0x00800000) | ||
1780 | #define RXWI_W1_SHORT_GI FIELD32(0x01000000) | ||
1781 | #define RXWI_W1_STBC FIELD32(0x06000000) | ||
1782 | #define RXWI_W1_PHYMODE FIELD32(0xc0000000) | ||
1783 | |||
1784 | /* | ||
1785 | * Word2 | ||
1786 | */ | ||
1787 | #define RXWI_W2_RSSI0 FIELD32(0x000000ff) | ||
1788 | #define RXWI_W2_RSSI1 FIELD32(0x0000ff00) | ||
1789 | #define RXWI_W2_RSSI2 FIELD32(0x00ff0000) | ||
1790 | |||
1791 | /* | ||
1792 | * Word3 | ||
1793 | */ | ||
1794 | #define RXWI_W3_SNR0 FIELD32(0x000000ff) | ||
1795 | #define RXWI_W3_SNR1 FIELD32(0x0000ff00) | ||
1796 | |||
1797 | /* | ||
1798 | * Macros for converting txpower from EEPROM to mac80211 value | ||
1799 | * and from mac80211 value to register value. | ||
1800 | */ | ||
1801 | #define MIN_G_TXPOWER 0 | ||
1802 | #define MIN_A_TXPOWER -7 | ||
1803 | #define MAX_G_TXPOWER 31 | ||
1804 | #define MAX_A_TXPOWER 15 | ||
1805 | #define DEFAULT_TXPOWER 5 | ||
1806 | |||
1807 | #define TXPOWER_G_FROM_DEV(__txpower) \ | ||
1808 | ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | ||
1809 | |||
1810 | #define TXPOWER_G_TO_DEV(__txpower) \ | ||
1811 | clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER) | ||
1812 | |||
1813 | #define TXPOWER_A_FROM_DEV(__txpower) \ | ||
1814 | ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) | ||
1815 | |||
1816 | #define TXPOWER_A_TO_DEV(__txpower) \ | ||
1817 | clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) | ||
1818 | |||
1819 | #endif /* RT2800_H */ | ||