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authorJohn W. Linville <linville@tuxdriver.com>2010-07-13 15:57:29 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-07-13 15:57:29 -0400
commite300d955debdadf599c36e47eb0bc16f5976215c (patch)
tree8fafcc789dc06e90665e6eee6388af228bbd2fd7 /drivers/net/wireless/rt2x00/rt2800.h
parent242647bcf8464860f173f3d4d4ab3490d3558518 (diff)
parent815868e7b5c207ba42d5b317ccc51f8112732268 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
Conflicts: drivers/net/wireless/wl12xx/wl1271_cmd.h
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800.h')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h30
1 files changed, 27 insertions, 3 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 552f9f4c73d6..ed4ebcdde7c9 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -74,7 +74,7 @@
74 * Signal information. 74 * Signal information.
75 * Default offset is required for RSSI <-> dBm conversion. 75 * Default offset is required for RSSI <-> dBm conversion.
76 */ 76 */
77#define DEFAULT_RSSI_OFFSET 120 /* FIXME */ 77#define DEFAULT_RSSI_OFFSET 120
78 78
79/* 79/*
80 * Register layout information. 80 * Register layout information.
@@ -719,14 +719,20 @@
719#define TBTT_TIMER 0x1124 719#define TBTT_TIMER 0x1124
720 720
721/* 721/*
722 * INT_TIMER_CFG: 722 * INT_TIMER_CFG: timer configuration
723 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
724 * GP_TIMER: period of general purpose timer in units of 1/16 TU
723 */ 725 */
724#define INT_TIMER_CFG 0x1128 726#define INT_TIMER_CFG 0x1128
727#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
728#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
725 729
726/* 730/*
727 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable 731 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
728 */ 732 */
729#define INT_TIMER_EN 0x112c 733#define INT_TIMER_EN 0x112c
734#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
735#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
730 736
731/* 737/*
732 * CH_IDLE_STA: channel idle time 738 * CH_IDLE_STA: channel idle time
@@ -803,6 +809,18 @@
803#define EDCA_TID_AC_MAP 0x1310 809#define EDCA_TID_AC_MAP 0x1310
804 810
805/* 811/*
812 * TX_PWR_CFG:
813 */
814#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
815#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
816#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
817#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
818#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
819#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
820#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
821#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
822
823/*
806 * TX_PWR_CFG_0: 824 * TX_PWR_CFG_0:
807 */ 825 */
808#define TX_PWR_CFG_0 0x1314 826#define TX_PWR_CFG_0 0x1314
@@ -1853,9 +1871,15 @@ struct mac_iveiv_entry {
1853#define EEPROM_TXPOWER_A_2 FIELD16(0xff00) 1871#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1854 1872
1855/* 1873/*
1856 * EEPROM TXpower byrate: 20MHZ power 1874 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
1857 */ 1875 */
1858#define EEPROM_TXPOWER_BYRATE 0x006f 1876#define EEPROM_TXPOWER_BYRATE 0x006f
1877#define EEPROM_TXPOWER_BYRATE_SIZE 9
1878
1879#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
1880#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
1881#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
1882#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
1859 1883
1860/* 1884/*
1861 * EEPROM BBP. 1885 * EEPROM BBP.