diff options
author | David S. Miller <davem@davemloft.net> | 2008-06-10 04:54:31 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-06-10 04:54:31 -0400 |
commit | 788c0a53164c05c5ccdb1472474372b72ba74644 (patch) | |
tree | 5f274102e3dc4bcca6cb3a695aa2c8228ad5fc4f /drivers/net/wireless/rt2x00/rt2500pci.c | |
parent | e64bda89b8fe81cce9b4a20885d2c204c2d52532 (diff) | |
parent | 78cf07472f0ede8394bacc4bc02354505080cfe1 (diff) |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/linville/wireless-next-2.6
Conflicts:
drivers/net/ps3_gelic_wireless.c
drivers/net/wireless/libertas/main.c
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2500pci.c | 120 |
1 files changed, 68 insertions, 52 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c index c06f1b5e5887..673350953b89 100644 --- a/drivers/net/wireless/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/rt2x00/rt2500pci.c | |||
@@ -715,38 +715,33 @@ dynamic_cca_tune: | |||
715 | static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, | 715 | static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, |
716 | struct queue_entry *entry) | 716 | struct queue_entry *entry) |
717 | { | 717 | { |
718 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; | 718 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
719 | u32 word; | 719 | u32 word; |
720 | 720 | ||
721 | rt2x00_desc_read(priv_rx->desc, 1, &word); | 721 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
722 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); | 722 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma); |
723 | rt2x00_desc_write(priv_rx->desc, 1, word); | 723 | rt2x00_desc_write(entry_priv->desc, 1, word); |
724 | 724 | ||
725 | rt2x00_desc_read(priv_rx->desc, 0, &word); | 725 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
726 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | 726 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
727 | rt2x00_desc_write(priv_rx->desc, 0, word); | 727 | rt2x00_desc_write(entry_priv->desc, 0, word); |
728 | } | 728 | } |
729 | 729 | ||
730 | static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, | 730 | static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, |
731 | struct queue_entry *entry) | 731 | struct queue_entry *entry) |
732 | { | 732 | { |
733 | struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; | 733 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
734 | u32 word; | 734 | u32 word; |
735 | 735 | ||
736 | rt2x00_desc_read(priv_tx->desc, 1, &word); | 736 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
737 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma); | ||
738 | rt2x00_desc_write(priv_tx->desc, 1, word); | ||
739 | |||
740 | rt2x00_desc_read(priv_tx->desc, 0, &word); | ||
741 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | 737 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
742 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | 738 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
743 | rt2x00_desc_write(priv_tx->desc, 0, word); | 739 | rt2x00_desc_write(entry_priv->desc, 0, word); |
744 | } | 740 | } |
745 | 741 | ||
746 | static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) | 742 | static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) |
747 | { | 743 | { |
748 | struct queue_entry_priv_pci_rx *priv_rx; | 744 | struct queue_entry_priv_pci *entry_priv; |
749 | struct queue_entry_priv_pci_tx *priv_tx; | ||
750 | u32 reg; | 745 | u32 reg; |
751 | 746 | ||
752 | /* | 747 | /* |
@@ -759,28 +754,28 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
759 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); | 754 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
760 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); | 755 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
761 | 756 | ||
762 | priv_tx = rt2x00dev->tx[1].entries[0].priv_data; | 757 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
763 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); | 758 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
764 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, | 759 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
765 | priv_tx->desc_dma); | 760 | entry_priv->desc_dma); |
766 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); | 761 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
767 | 762 | ||
768 | priv_tx = rt2x00dev->tx[0].entries[0].priv_data; | 763 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
769 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); | 764 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
770 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, | 765 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
771 | priv_tx->desc_dma); | 766 | entry_priv->desc_dma); |
772 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); | 767 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
773 | 768 | ||
774 | priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; | 769 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; |
775 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); | 770 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
776 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, | 771 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
777 | priv_tx->desc_dma); | 772 | entry_priv->desc_dma); |
778 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); | 773 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
779 | 774 | ||
780 | priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; | 775 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; |
781 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); | 776 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
782 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, | 777 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
783 | priv_tx->desc_dma); | 778 | entry_priv->desc_dma); |
784 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); | 779 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
785 | 780 | ||
786 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); | 781 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); |
@@ -788,9 +783,10 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
788 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); | 783 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
789 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); | 784 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
790 | 785 | ||
791 | priv_rx = rt2x00dev->rx->entries[0].priv_data; | 786 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
792 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); | 787 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
793 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); | 788 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
789 | entry_priv->desc_dma); | ||
794 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); | 790 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
795 | 791 | ||
796 | return 0; | 792 | return 0; |
@@ -1155,16 +1151,20 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1155 | */ | 1151 | */ |
1156 | static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | 1152 | static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, |
1157 | struct sk_buff *skb, | 1153 | struct sk_buff *skb, |
1158 | struct txentry_desc *txdesc, | 1154 | struct txentry_desc *txdesc) |
1159 | struct ieee80211_tx_control *control) | ||
1160 | { | 1155 | { |
1161 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); | 1156 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
1157 | struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; | ||
1162 | __le32 *txd = skbdesc->desc; | 1158 | __le32 *txd = skbdesc->desc; |
1163 | u32 word; | 1159 | u32 word; |
1164 | 1160 | ||
1165 | /* | 1161 | /* |
1166 | * Start writing the descriptor words. | 1162 | * Start writing the descriptor words. |
1167 | */ | 1163 | */ |
1164 | rt2x00_desc_read(entry_priv->desc, 1, &word); | ||
1165 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma); | ||
1166 | rt2x00_desc_write(entry_priv->desc, 1, word); | ||
1167 | |||
1168 | rt2x00_desc_read(txd, 2, &word); | 1168 | rt2x00_desc_read(txd, 2, &word); |
1169 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); | 1169 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); |
1170 | rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); | 1170 | rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); |
@@ -1198,9 +1198,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1198 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); | 1198 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); |
1199 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | 1199 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
1200 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | 1200 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1201 | !!(control->flags & | 1201 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
1202 | IEEE80211_TXCTL_LONG_RETRY_LIMIT)); | ||
1203 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len); | ||
1204 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); | 1202 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); |
1205 | rt2x00_desc_write(txd, 0, word); | 1203 | rt2x00_desc_write(txd, 0, word); |
1206 | } | 1204 | } |
@@ -1237,14 +1235,13 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | |||
1237 | static void rt2500pci_fill_rxdone(struct queue_entry *entry, | 1235 | static void rt2500pci_fill_rxdone(struct queue_entry *entry, |
1238 | struct rxdone_entry_desc *rxdesc) | 1236 | struct rxdone_entry_desc *rxdesc) |
1239 | { | 1237 | { |
1240 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; | 1238 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
1241 | u32 word0; | 1239 | u32 word0; |
1242 | u32 word2; | 1240 | u32 word2; |
1243 | 1241 | ||
1244 | rt2x00_desc_read(priv_rx->desc, 0, &word0); | 1242 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
1245 | rt2x00_desc_read(priv_rx->desc, 2, &word2); | 1243 | rt2x00_desc_read(entry_priv->desc, 2, &word2); |
1246 | 1244 | ||
1247 | rxdesc->flags = 0; | ||
1248 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) | 1245 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
1249 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; | 1246 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
1250 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) | 1247 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
@@ -1261,7 +1258,6 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry, | |||
1261 | entry->queue->rt2x00dev->rssi_offset; | 1258 | entry->queue->rt2x00dev->rssi_offset; |
1262 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); | 1259 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
1263 | 1260 | ||
1264 | rxdesc->dev_flags = 0; | ||
1265 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) | 1261 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1266 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | 1262 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
1267 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) | 1263 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
@@ -1275,15 +1271,15 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, | |||
1275 | const enum data_queue_qid queue_idx) | 1271 | const enum data_queue_qid queue_idx) |
1276 | { | 1272 | { |
1277 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | 1273 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
1278 | struct queue_entry_priv_pci_tx *priv_tx; | 1274 | struct queue_entry_priv_pci *entry_priv; |
1279 | struct queue_entry *entry; | 1275 | struct queue_entry *entry; |
1280 | struct txdone_entry_desc txdesc; | 1276 | struct txdone_entry_desc txdesc; |
1281 | u32 word; | 1277 | u32 word; |
1282 | 1278 | ||
1283 | while (!rt2x00queue_empty(queue)) { | 1279 | while (!rt2x00queue_empty(queue)) { |
1284 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | 1280 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
1285 | priv_tx = entry->priv_data; | 1281 | entry_priv = entry->priv_data; |
1286 | rt2x00_desc_read(priv_tx->desc, 0, &word); | 1282 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
1287 | 1283 | ||
1288 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | 1284 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
1289 | !rt2x00_get_field32(word, TXD_W0_VALID)) | 1285 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
@@ -1292,7 +1288,18 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, | |||
1292 | /* | 1288 | /* |
1293 | * Obtain the status about this packet. | 1289 | * Obtain the status about this packet. |
1294 | */ | 1290 | */ |
1295 | txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); | 1291 | txdesc.flags = 0; |
1292 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { | ||
1293 | case 0: /* Success */ | ||
1294 | case 1: /* Success with retry */ | ||
1295 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | ||
1296 | break; | ||
1297 | case 2: /* Failure, excessive retries */ | ||
1298 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | ||
1299 | /* Don't break, this is a failed frame! */ | ||
1300 | default: /* Failure */ | ||
1301 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | ||
1302 | } | ||
1296 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); | 1303 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
1297 | 1304 | ||
1298 | rt2x00pci_txdone(rt2x00dev, entry, &txdesc); | 1305 | rt2x00pci_txdone(rt2x00dev, entry, &txdesc); |
@@ -1684,7 +1691,6 @@ static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
1684 | IEEE80211_HW_SIGNAL_DBM; | 1691 | IEEE80211_HW_SIGNAL_DBM; |
1685 | 1692 | ||
1686 | rt2x00dev->hw->extra_tx_headroom = 0; | 1693 | rt2x00dev->hw->extra_tx_headroom = 0; |
1687 | rt2x00dev->hw->queues = 2; | ||
1688 | 1694 | ||
1689 | SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); | 1695 | SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); |
1690 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | 1696 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
@@ -1793,19 +1799,28 @@ static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw) | |||
1793 | return tsf; | 1799 | return tsf; |
1794 | } | 1800 | } |
1795 | 1801 | ||
1796 | static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, | 1802 | static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb) |
1797 | struct ieee80211_tx_control *control) | ||
1798 | { | 1803 | { |
1799 | struct rt2x00_dev *rt2x00dev = hw->priv; | 1804 | struct rt2x00_dev *rt2x00dev = hw->priv; |
1800 | struct rt2x00_intf *intf = vif_to_intf(control->vif); | 1805 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1801 | struct queue_entry_priv_pci_tx *priv_tx; | 1806 | struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); |
1807 | struct queue_entry_priv_pci *entry_priv; | ||
1802 | struct skb_frame_desc *skbdesc; | 1808 | struct skb_frame_desc *skbdesc; |
1809 | struct txentry_desc txdesc; | ||
1803 | u32 reg; | 1810 | u32 reg; |
1804 | 1811 | ||
1805 | if (unlikely(!intf->beacon)) | 1812 | if (unlikely(!intf->beacon)) |
1806 | return -ENOBUFS; | 1813 | return -ENOBUFS; |
1807 | 1814 | ||
1808 | priv_tx = intf->beacon->priv_data; | 1815 | entry_priv = intf->beacon->priv_data; |
1816 | |||
1817 | /* | ||
1818 | * Copy all TX descriptor information into txdesc, | ||
1819 | * after that we are free to use the skb->cb array | ||
1820 | * for our information. | ||
1821 | */ | ||
1822 | intf->beacon->skb = skb; | ||
1823 | rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc); | ||
1809 | 1824 | ||
1810 | /* | 1825 | /* |
1811 | * Fill in skb descriptor | 1826 | * Fill in skb descriptor |
@@ -1815,7 +1830,7 @@ static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, | |||
1815 | skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; | 1830 | skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; |
1816 | skbdesc->data = skb->data; | 1831 | skbdesc->data = skb->data; |
1817 | skbdesc->data_len = skb->len; | 1832 | skbdesc->data_len = skb->len; |
1818 | skbdesc->desc = priv_tx->desc; | 1833 | skbdesc->desc = entry_priv->desc; |
1819 | skbdesc->desc_len = intf->beacon->queue->desc_size; | 1834 | skbdesc->desc_len = intf->beacon->queue->desc_size; |
1820 | skbdesc->entry = intf->beacon; | 1835 | skbdesc->entry = intf->beacon; |
1821 | 1836 | ||
@@ -1834,8 +1849,8 @@ static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, | |||
1834 | * Write entire beacon with descriptor to register, | 1849 | * Write entire beacon with descriptor to register, |
1835 | * and kick the beacon generator. | 1850 | * and kick the beacon generator. |
1836 | */ | 1851 | */ |
1837 | rt2x00lib_write_tx_desc(rt2x00dev, skb, control); | 1852 | memcpy(entry_priv->data, skb->data, skb->len); |
1838 | memcpy(priv_tx->data, skb->data, skb->len); | 1853 | rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc); |
1839 | rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON); | 1854 | rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON); |
1840 | 1855 | ||
1841 | return 0; | 1856 | return 0; |
@@ -1895,28 +1910,28 @@ static const struct data_queue_desc rt2500pci_queue_rx = { | |||
1895 | .entry_num = RX_ENTRIES, | 1910 | .entry_num = RX_ENTRIES, |
1896 | .data_size = DATA_FRAME_SIZE, | 1911 | .data_size = DATA_FRAME_SIZE, |
1897 | .desc_size = RXD_DESC_SIZE, | 1912 | .desc_size = RXD_DESC_SIZE, |
1898 | .priv_size = sizeof(struct queue_entry_priv_pci_rx), | 1913 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1899 | }; | 1914 | }; |
1900 | 1915 | ||
1901 | static const struct data_queue_desc rt2500pci_queue_tx = { | 1916 | static const struct data_queue_desc rt2500pci_queue_tx = { |
1902 | .entry_num = TX_ENTRIES, | 1917 | .entry_num = TX_ENTRIES, |
1903 | .data_size = DATA_FRAME_SIZE, | 1918 | .data_size = DATA_FRAME_SIZE, |
1904 | .desc_size = TXD_DESC_SIZE, | 1919 | .desc_size = TXD_DESC_SIZE, |
1905 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | 1920 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1906 | }; | 1921 | }; |
1907 | 1922 | ||
1908 | static const struct data_queue_desc rt2500pci_queue_bcn = { | 1923 | static const struct data_queue_desc rt2500pci_queue_bcn = { |
1909 | .entry_num = BEACON_ENTRIES, | 1924 | .entry_num = BEACON_ENTRIES, |
1910 | .data_size = MGMT_FRAME_SIZE, | 1925 | .data_size = MGMT_FRAME_SIZE, |
1911 | .desc_size = TXD_DESC_SIZE, | 1926 | .desc_size = TXD_DESC_SIZE, |
1912 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | 1927 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1913 | }; | 1928 | }; |
1914 | 1929 | ||
1915 | static const struct data_queue_desc rt2500pci_queue_atim = { | 1930 | static const struct data_queue_desc rt2500pci_queue_atim = { |
1916 | .entry_num = ATIM_ENTRIES, | 1931 | .entry_num = ATIM_ENTRIES, |
1917 | .data_size = DATA_FRAME_SIZE, | 1932 | .data_size = DATA_FRAME_SIZE, |
1918 | .desc_size = TXD_DESC_SIZE, | 1933 | .desc_size = TXD_DESC_SIZE, |
1919 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | 1934 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1920 | }; | 1935 | }; |
1921 | 1936 | ||
1922 | static const struct rt2x00_ops rt2500pci_ops = { | 1937 | static const struct rt2x00_ops rt2500pci_ops = { |
@@ -1925,6 +1940,7 @@ static const struct rt2x00_ops rt2500pci_ops = { | |||
1925 | .max_ap_intf = 1, | 1940 | .max_ap_intf = 1, |
1926 | .eeprom_size = EEPROM_SIZE, | 1941 | .eeprom_size = EEPROM_SIZE, |
1927 | .rf_size = RF_SIZE, | 1942 | .rf_size = RF_SIZE, |
1943 | .tx_queues = NUM_TX_QUEUES, | ||
1928 | .rx = &rt2500pci_queue_rx, | 1944 | .rx = &rt2500pci_queue_rx, |
1929 | .tx = &rt2500pci_queue_tx, | 1945 | .tx = &rt2500pci_queue_tx, |
1930 | .bcn = &rt2500pci_queue_bcn, | 1946 | .bcn = &rt2500pci_queue_bcn, |