aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/rt2x00/rt2500pci.c
diff options
context:
space:
mode:
authorIvo van Doorn <ivdoorn@gmail.com>2008-05-10 07:46:03 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-05-21 21:47:35 -0400
commitb8be63ffa5dc44324e7f507997870fa3e4b17619 (patch)
treead9ef1c3e4e09111ad93b003baaec325bd5e40e0 /drivers/net/wireless/rt2x00/rt2500pci.c
parentdec13b6bda600c7e7da993e634562873112af50b (diff)
rt2x00: Merge RX and TX entry private data
With the pending removal of the tx_control structure we can merge the RX and TX entry private data structure in advance. This will temporarily increase the required memory for the queue, but that overhead will only be limited. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c72
1 files changed, 36 insertions, 36 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 805781306dd1..06e87cdff455 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -715,34 +715,33 @@ dynamic_cca_tune:
715static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 715static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
716 struct queue_entry *entry) 716 struct queue_entry *entry)
717{ 717{
718 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 718 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
719 u32 word; 719 u32 word;
720 720
721 rt2x00_desc_read(priv_rx->desc, 1, &word); 721 rt2x00_desc_read(entry_priv->desc, 1, &word);
722 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); 722 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
723 rt2x00_desc_write(priv_rx->desc, 1, word); 723 rt2x00_desc_write(entry_priv->desc, 1, word);
724 724
725 rt2x00_desc_read(priv_rx->desc, 0, &word); 725 rt2x00_desc_read(entry_priv->desc, 0, &word);
726 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 726 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
727 rt2x00_desc_write(priv_rx->desc, 0, word); 727 rt2x00_desc_write(entry_priv->desc, 0, word);
728} 728}
729 729
730static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, 730static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
731 struct queue_entry *entry) 731 struct queue_entry *entry)
732{ 732{
733 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 733 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
734 u32 word; 734 u32 word;
735 735
736 rt2x00_desc_read(priv_tx->desc, 0, &word); 736 rt2x00_desc_read(entry_priv->desc, 0, &word);
737 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 737 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
738 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 738 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
739 rt2x00_desc_write(priv_tx->desc, 0, word); 739 rt2x00_desc_write(entry_priv->desc, 0, word);
740} 740}
741 741
742static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) 742static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
743{ 743{
744 struct queue_entry_priv_pci_rx *priv_rx; 744 struct queue_entry_priv_pci *entry_priv;
745 struct queue_entry_priv_pci_tx *priv_tx;
746 u32 reg; 745 u32 reg;
747 746
748 /* 747 /*
@@ -755,28 +754,28 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
755 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 754 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
756 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 755 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
757 756
758 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 757 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
759 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 758 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
760 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 759 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
761 priv_tx->desc_dma); 760 entry_priv->desc_dma);
762 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 761 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
763 762
764 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 763 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
765 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 764 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
766 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 765 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
767 priv_tx->desc_dma); 766 entry_priv->desc_dma);
768 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 767 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
769 768
770 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 769 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
771 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 770 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
772 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 771 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
773 priv_tx->desc_dma); 772 entry_priv->desc_dma);
774 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 773 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
775 774
776 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 775 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
777 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 776 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
778 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 777 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
779 priv_tx->desc_dma); 778 entry_priv->desc_dma);
780 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 779 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
781 780
782 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 781 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -784,9 +783,10 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
784 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 783 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
785 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 784 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
786 785
787 priv_rx = rt2x00dev->rx->entries[0].priv_data; 786 entry_priv = rt2x00dev->rx->entries[0].priv_data;
788 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 787 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
789 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); 788 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
789 entry_priv->desc_dma);
790 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 790 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
791 791
792 return 0; 792 return 0;
@@ -1154,7 +1154,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1154 struct txentry_desc *txdesc) 1154 struct txentry_desc *txdesc)
1155{ 1155{
1156 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1156 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1157 struct queue_entry_priv_pci_tx *entry_priv = skbdesc->entry->priv_data; 1157 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1158 __le32 *txd = skbdesc->desc; 1158 __le32 *txd = skbdesc->desc;
1159 u32 word; 1159 u32 word;
1160 1160
@@ -1235,12 +1235,12 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1235static void rt2500pci_fill_rxdone(struct queue_entry *entry, 1235static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1236 struct rxdone_entry_desc *rxdesc) 1236 struct rxdone_entry_desc *rxdesc)
1237{ 1237{
1238 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1238 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1239 u32 word0; 1239 u32 word0;
1240 u32 word2; 1240 u32 word2;
1241 1241
1242 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1242 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1243 rt2x00_desc_read(priv_rx->desc, 2, &word2); 1243 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1244 1244
1245 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1245 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1246 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1246 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
@@ -1271,15 +1271,15 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1271 const enum data_queue_qid queue_idx) 1271 const enum data_queue_qid queue_idx)
1272{ 1272{
1273 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1273 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1274 struct queue_entry_priv_pci_tx *priv_tx; 1274 struct queue_entry_priv_pci *entry_priv;
1275 struct queue_entry *entry; 1275 struct queue_entry *entry;
1276 struct txdone_entry_desc txdesc; 1276 struct txdone_entry_desc txdesc;
1277 u32 word; 1277 u32 word;
1278 1278
1279 while (!rt2x00queue_empty(queue)) { 1279 while (!rt2x00queue_empty(queue)) {
1280 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1280 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1281 priv_tx = entry->priv_data; 1281 entry_priv = entry->priv_data;
1282 rt2x00_desc_read(priv_tx->desc, 0, &word); 1282 rt2x00_desc_read(entry_priv->desc, 0, &word);
1283 1283
1284 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1284 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1285 !rt2x00_get_field32(word, TXD_W0_VALID)) 1285 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1804,7 +1804,7 @@ static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1804{ 1804{
1805 struct rt2x00_dev *rt2x00dev = hw->priv; 1805 struct rt2x00_dev *rt2x00dev = hw->priv;
1806 struct rt2x00_intf *intf = vif_to_intf(control->vif); 1806 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1807 struct queue_entry_priv_pci_tx *priv_tx; 1807 struct queue_entry_priv_pci *entry_priv;
1808 struct skb_frame_desc *skbdesc; 1808 struct skb_frame_desc *skbdesc;
1809 struct txentry_desc txdesc; 1809 struct txentry_desc txdesc;
1810 u32 reg; 1810 u32 reg;
@@ -1812,7 +1812,7 @@ static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1812 if (unlikely(!intf->beacon)) 1812 if (unlikely(!intf->beacon))
1813 return -ENOBUFS; 1813 return -ENOBUFS;
1814 1814
1815 priv_tx = intf->beacon->priv_data; 1815 entry_priv = intf->beacon->priv_data;
1816 1816
1817 /* 1817 /*
1818 * Copy all TX descriptor information into txdesc, 1818 * Copy all TX descriptor information into txdesc,
@@ -1830,7 +1830,7 @@ static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1830 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; 1830 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1831 skbdesc->data = skb->data; 1831 skbdesc->data = skb->data;
1832 skbdesc->data_len = skb->len; 1832 skbdesc->data_len = skb->len;
1833 skbdesc->desc = priv_tx->desc; 1833 skbdesc->desc = entry_priv->desc;
1834 skbdesc->desc_len = intf->beacon->queue->desc_size; 1834 skbdesc->desc_len = intf->beacon->queue->desc_size;
1835 skbdesc->entry = intf->beacon; 1835 skbdesc->entry = intf->beacon;
1836 1836
@@ -1849,7 +1849,7 @@ static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1849 * Write entire beacon with descriptor to register, 1849 * Write entire beacon with descriptor to register,
1850 * and kick the beacon generator. 1850 * and kick the beacon generator.
1851 */ 1851 */
1852 memcpy(priv_tx->data, skb->data, skb->len); 1852 memcpy(entry_priv->data, skb->data, skb->len);
1853 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc); 1853 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1854 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON); 1854 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1855 1855
@@ -1910,28 +1910,28 @@ static const struct data_queue_desc rt2500pci_queue_rx = {
1910 .entry_num = RX_ENTRIES, 1910 .entry_num = RX_ENTRIES,
1911 .data_size = DATA_FRAME_SIZE, 1911 .data_size = DATA_FRAME_SIZE,
1912 .desc_size = RXD_DESC_SIZE, 1912 .desc_size = RXD_DESC_SIZE,
1913 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 1913 .priv_size = sizeof(struct queue_entry_priv_pci),
1914}; 1914};
1915 1915
1916static const struct data_queue_desc rt2500pci_queue_tx = { 1916static const struct data_queue_desc rt2500pci_queue_tx = {
1917 .entry_num = TX_ENTRIES, 1917 .entry_num = TX_ENTRIES,
1918 .data_size = DATA_FRAME_SIZE, 1918 .data_size = DATA_FRAME_SIZE,
1919 .desc_size = TXD_DESC_SIZE, 1919 .desc_size = TXD_DESC_SIZE,
1920 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1920 .priv_size = sizeof(struct queue_entry_priv_pci),
1921}; 1921};
1922 1922
1923static const struct data_queue_desc rt2500pci_queue_bcn = { 1923static const struct data_queue_desc rt2500pci_queue_bcn = {
1924 .entry_num = BEACON_ENTRIES, 1924 .entry_num = BEACON_ENTRIES,
1925 .data_size = MGMT_FRAME_SIZE, 1925 .data_size = MGMT_FRAME_SIZE,
1926 .desc_size = TXD_DESC_SIZE, 1926 .desc_size = TXD_DESC_SIZE,
1927 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1927 .priv_size = sizeof(struct queue_entry_priv_pci),
1928}; 1928};
1929 1929
1930static const struct data_queue_desc rt2500pci_queue_atim = { 1930static const struct data_queue_desc rt2500pci_queue_atim = {
1931 .entry_num = ATIM_ENTRIES, 1931 .entry_num = ATIM_ENTRIES,
1932 .data_size = DATA_FRAME_SIZE, 1932 .data_size = DATA_FRAME_SIZE,
1933 .desc_size = TXD_DESC_SIZE, 1933 .desc_size = TXD_DESC_SIZE,
1934 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1934 .priv_size = sizeof(struct queue_entry_priv_pci),
1935}; 1935};
1936 1936
1937static const struct rt2x00_ops rt2500pci_ops = { 1937static const struct rt2x00_ops rt2500pci_ops = {