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authorJohn W. Linville <linville@tuxdriver.com>2010-09-21 15:49:14 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-09-21 15:49:14 -0400
commitb618f6f885579a6237e5bf4582fa6167972ddef4 (patch)
treeb11508178570b98ce9cb2d76ecebd046a6f0e77c /drivers/net/wireless/rt2x00/rt2500pci.c
parent462fb2af9788a82a534f8184abfde31574e1cfa0 (diff)
parent6e5c2b4e8addfaab8ef54dedaf7b607e1585c35b (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
Conflicts: arch/arm/mach-omap2/board-omap3pandora.c drivers/net/wireless/ath/ath5k/base.c
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c115
1 files changed, 65 insertions, 50 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index ab0507110e42..2214c3231727 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -327,7 +327,8 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327} 327}
328 328
329static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev, 329static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
330 struct rt2x00lib_erp *erp) 330 struct rt2x00lib_erp *erp,
331 u32 changed)
331{ 332{
332 int preamble_mask; 333 int preamble_mask;
333 u32 reg; 334 u32 reg;
@@ -335,59 +336,73 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
335 /* 336 /*
336 * When short preamble is enabled, we should set bit 0x08 337 * When short preamble is enabled, we should set bit 0x08
337 */ 338 */
338 preamble_mask = erp->short_preamble << 3; 339 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
339 340 preamble_mask = erp->short_preamble << 3;
340 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg); 341
341 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162); 342 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
342 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2); 343 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x162);
343 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); 344 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0xa2);
344 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1); 345 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
345 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg); 346 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
346 347 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
347 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 348
348 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); 349 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
349 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); 350 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
350 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10)); 351 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
351 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); 352 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352 353 GET_DURATION(ACK_SIZE, 10));
353 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg); 354 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
354 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); 355
355 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); 356 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
356 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20)); 357 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
357 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); 358 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
358 359 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg); 360 GET_DURATION(ACK_SIZE, 20));
360 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); 361 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
361 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); 362
362 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55)); 363 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
363 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); 364 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
364 365 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
365 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg); 366 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); 367 GET_DURATION(ACK_SIZE, 55));
367 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 368 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110)); 369
369 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 370 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
370 371 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 372 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
373 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
374 GET_DURATION(ACK_SIZE, 110));
375 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
376 }
372 377
373 rt2x00pci_register_read(rt2x00dev, CSR11, &reg); 378 if (changed & BSS_CHANGED_BASIC_RATES)
374 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time); 379 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
375 rt2x00pci_register_write(rt2x00dev, CSR11, reg); 380
381 if (changed & BSS_CHANGED_ERP_SLOT) {
382 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
383 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
384 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376 385
377 rt2x00pci_register_read(rt2x00dev, CSR12, &reg); 386 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
378 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, erp->beacon_int * 16); 387 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
379 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, erp->beacon_int * 16); 388 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
380 rt2x00pci_register_write(rt2x00dev, CSR12, reg); 389 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
381 390
382 rt2x00pci_register_read(rt2x00dev, CSR18, &reg); 391 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
383 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs); 392 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
384 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs); 393 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
385 rt2x00pci_register_write(rt2x00dev, CSR18, reg); 394 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
395 }
396
397 if (changed & BSS_CHANGED_BEACON_INT) {
398 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
399 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
400 erp->beacon_int * 16);
401 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
402 erp->beacon_int * 16);
403 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
404 }
386 405
387 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
388 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
389 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
390 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
391} 406}
392 407
393static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev, 408static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,