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authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>2011-08-26 02:11:14 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-08-29 15:30:29 -0400
commit83ed90155f98bd949735c2cc22d832b557a6d7d1 (patch)
tree795ecd1ebd93357a80895825310c19315a633e49 /drivers/net/wireless/iwlwifi
parenta72b8b088c3465b28192c1a14ba97be8223a8cec (diff)
iwlagn: all function iwl-io.c receive iwl_bus
Which means that iwl-io.c doesn't need to include iwl-dev.h any more. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-1000.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-2000.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-6000.c8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-tt.c14
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-ucode.c20
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c59
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-bus.h3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c27
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debugfs.c6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-dev.h3
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-devtrace.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c58
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-helpers.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.c192
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h61
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.c6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-pci.c4
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rx.c8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sv-open.c6
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c72
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c34
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans.c113
24 files changed, 363 insertions, 351 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index 7d60cd2f49c6..3368b8dea199 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -85,13 +85,13 @@ static void iwl1000_set_ct_threshold(struct iwl_priv *priv)
85static void iwl1000_nic_config(struct iwl_priv *priv) 85static void iwl1000_nic_config(struct iwl_priv *priv)
86{ 86{
87 /* set CSR_HW_CONFIG_REG for uCode use */ 87 /* set CSR_HW_CONFIG_REG for uCode use */
88 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 88 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
89 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 89 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
90 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 90 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
91 91
92 /* Setting digital SVR for 1000 card to 1.32V */ 92 /* Setting digital SVR for 1000 card to 1.32V */
93 /* locking is acquired in iwl_set_bits_mask_prph() function */ 93 /* locking is acquired in iwl_set_bits_mask_prph() function */
94 iwl_set_bits_mask_prph(priv, APMG_DIGITAL_SVR_REG, 94 iwl_set_bits_mask_prph(bus(priv), APMG_DIGITAL_SVR_REG,
95 APMG_SVR_DIGITAL_VOLTAGE_1_32, 95 APMG_SVR_DIGITAL_VOLTAGE_1_32,
96 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK); 96 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
97} 97}
diff --git a/drivers/net/wireless/iwlwifi/iwl-2000.c b/drivers/net/wireless/iwlwifi/iwl-2000.c
index 8d71eec36699..047c22b64285 100644
--- a/drivers/net/wireless/iwlwifi/iwl-2000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-2000.c
@@ -89,7 +89,7 @@ static void iwl2000_nic_config(struct iwl_priv *priv)
89 iwl_rf_config(priv); 89 iwl_rf_config(priv);
90 90
91 if (priv->cfg->iq_invert) 91 if (priv->cfg->iq_invert)
92 iwl_set_bit(priv, CSR_GP_DRIVER_REG, 92 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG,
93 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER); 93 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
94} 94}
95 95
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index 55fdbf57df98..d2ef4be44c61 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -75,7 +75,7 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
75 * (PCIe power is lost before PERST# is asserted), 75 * (PCIe power is lost before PERST# is asserted),
76 * causing ME FW to lose ownership and not being able to obtain it back. 76 * causing ME FW to lose ownership and not being able to obtain it back.
77 */ 77 */
78 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 78 iwl_set_bits_mask_prph(bus(priv), APMG_PS_CTRL_REG,
79 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 79 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
80 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 80 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
81 81
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index 63089bc28d9c..955a99cef949 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -83,7 +83,7 @@ static void iwl6050_additional_nic_config(struct iwl_priv *priv)
83{ 83{
84 /* Indicate calibration version to uCode. */ 84 /* Indicate calibration version to uCode. */
85 if (iwlagn_eeprom_calib_version(priv) >= 6) 85 if (iwlagn_eeprom_calib_version(priv) >= 6)
86 iwl_set_bit(priv, CSR_GP_DRIVER_REG, 86 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG,
87 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); 87 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
88} 88}
89 89
@@ -91,9 +91,9 @@ static void iwl6150_additional_nic_config(struct iwl_priv *priv)
91{ 91{
92 /* Indicate calibration version to uCode. */ 92 /* Indicate calibration version to uCode. */
93 if (iwlagn_eeprom_calib_version(priv) >= 6) 93 if (iwlagn_eeprom_calib_version(priv) >= 6)
94 iwl_set_bit(priv, CSR_GP_DRIVER_REG, 94 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG,
95 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6); 95 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
96 iwl_set_bit(priv, CSR_GP_DRIVER_REG, 96 iwl_set_bit(bus(priv), CSR_GP_DRIVER_REG,
97 CSR_GP_DRIVER_REG_BIT_6050_1x2); 97 CSR_GP_DRIVER_REG_BIT_6050_1x2);
98} 98}
99 99
@@ -105,7 +105,7 @@ static void iwl6000_nic_config(struct iwl_priv *priv)
105 /* no locking required for register write */ 105 /* no locking required for register write */
106 if (priv->cfg->pa_type == IWL_PA_INTERNAL) { 106 if (priv->cfg->pa_type == IWL_PA_INTERNAL) {
107 /* 2x2 IPA phy type */ 107 /* 2x2 IPA phy type */
108 iwl_write32(priv, CSR_GP_DRIVER_REG, 108 iwl_write32(bus(priv), CSR_GP_DRIVER_REG,
109 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA); 109 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
110 } 110 }
111 /* do additional nic configuration if needed */ 111 /* do additional nic configuration if needed */
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tt.c b/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
index 1a39aafb3b05..495f93664741 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
@@ -181,19 +181,19 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
181 181
182 if (tt->state == IWL_TI_CT_KILL) { 182 if (tt->state == IWL_TI_CT_KILL) {
183 if (priv->thermal_throttle.ct_kill_toggle) { 183 if (priv->thermal_throttle.ct_kill_toggle) {
184 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 184 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR,
185 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 185 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
186 priv->thermal_throttle.ct_kill_toggle = false; 186 priv->thermal_throttle.ct_kill_toggle = false;
187 } else { 187 } else {
188 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 188 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_SET,
189 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 189 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
190 priv->thermal_throttle.ct_kill_toggle = true; 190 priv->thermal_throttle.ct_kill_toggle = true;
191 } 191 }
192 iwl_read32(priv, CSR_UCODE_DRV_GP1); 192 iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
193 spin_lock_irqsave(&priv->reg_lock, flags); 193 spin_lock_irqsave(&bus(priv)->reg_lock, flags);
194 if (!iwl_grab_nic_access(priv)) 194 if (!iwl_grab_nic_access(bus(priv)))
195 iwl_release_nic_access(priv); 195 iwl_release_nic_access(bus(priv));
196 spin_unlock_irqrestore(&priv->reg_lock, flags); 196 spin_unlock_irqrestore(&bus(priv)->reg_lock, flags);
197 197
198 /* Reschedule the ct_kill timer to occur in 198 /* Reschedule the ct_kill timer to occur in
199 * CT_KILL_EXIT_DURATION seconds to ensure we get a 199 * CT_KILL_EXIT_DURATION seconds to ensure we get a
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
index 033f595a6d55..02b00d177323 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
@@ -85,29 +85,29 @@ static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
85 85
86 priv->ucode_write_complete = 0; 86 priv->ucode_write_complete = 0;
87 87
88 iwl_write_direct32(priv, 88 iwl_write_direct32(bus(priv),
89 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 89 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
90 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 90 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
91 91
92 iwl_write_direct32(priv, 92 iwl_write_direct32(bus(priv),
93 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); 93 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
94 94
95 iwl_write_direct32(priv, 95 iwl_write_direct32(bus(priv),
96 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 96 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
97 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 97 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
98 98
99 iwl_write_direct32(priv, 99 iwl_write_direct32(bus(priv),
100 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 100 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
101 (iwl_get_dma_hi_addr(phy_addr) 101 (iwl_get_dma_hi_addr(phy_addr)
102 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 102 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
103 103
104 iwl_write_direct32(priv, 104 iwl_write_direct32(bus(priv),
105 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 105 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
106 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 106 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
107 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 107 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
108 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 108 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
109 109
110 iwl_write_direct32(priv, 110 iwl_write_direct32(bus(priv),
111 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 111 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
112 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 112 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
113 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 113 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
@@ -384,9 +384,9 @@ static int iwl_verify_inst_sparse(struct iwl_priv *priv,
384 /* read data comes through single port, auto-incr addr */ 384 /* read data comes through single port, auto-incr addr */
385 /* NOTE: Use the debugless read so we don't flood kernel log 385 /* NOTE: Use the debugless read so we don't flood kernel log
386 * if IWL_DL_IO is set */ 386 * if IWL_DL_IO is set */
387 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, 387 iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
388 i + IWLAGN_RTC_INST_LOWER_BOUND); 388 i + IWLAGN_RTC_INST_LOWER_BOUND);
389 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 389 val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
390 if (val != le32_to_cpu(*image)) 390 if (val != le32_to_cpu(*image))
391 return -EIO; 391 return -EIO;
392 } 392 }
@@ -405,14 +405,14 @@ static void iwl_print_mismatch_inst(struct iwl_priv *priv,
405 405
406 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len); 406 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
407 407
408 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, 408 iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
409 IWLAGN_RTC_INST_LOWER_BOUND); 409 IWLAGN_RTC_INST_LOWER_BOUND);
410 410
411 for (offs = 0; 411 for (offs = 0;
412 offs < len && errors < 20; 412 offs < len && errors < 20;
413 offs += sizeof(u32), image++) { 413 offs += sizeof(u32), image++) {
414 /* read data comes through single port, auto-incr addr */ 414 /* read data comes through single port, auto-incr addr */
415 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 415 val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
416 if (val != le32_to_cpu(*image)) { 416 if (val != le32_to_cpu(*image)) {
417 IWL_ERR(priv, "uCode INST section at " 417 IWL_ERR(priv, "uCode INST section at "
418 "offset 0x%x, is 0x%x, s/b 0x%x\n", 418 "offset 0x%x, is 0x%x, s/b 0x%x\n",
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 5d2696257541..37d2043fb7e9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -329,14 +329,14 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
329 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); 329 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
330 330
331 /* Make sure device is powered up for SRAM reads */ 331 /* Make sure device is powered up for SRAM reads */
332 spin_lock_irqsave(&priv->reg_lock, reg_flags); 332 spin_lock_irqsave(&bus(priv)->reg_lock, reg_flags);
333 if (iwl_grab_nic_access(priv)) { 333 if (iwl_grab_nic_access(bus(priv))) {
334 spin_unlock_irqrestore(&priv->reg_lock, reg_flags); 334 spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags);
335 return; 335 return;
336 } 336 }
337 337
338 /* Set starting address; reads will auto-increment */ 338 /* Set starting address; reads will auto-increment */
339 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); 339 iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, ptr);
340 rmb(); 340 rmb();
341 341
342 /* 342 /*
@@ -344,20 +344,20 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
344 * place event id # at far right for easier visual parsing. 344 * place event id # at far right for easier visual parsing.
345 */ 345 */
346 for (i = 0; i < num_events; i++) { 346 for (i = 0; i < num_events; i++) {
347 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 347 ev = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
348 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 348 time = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
349 if (mode == 0) { 349 if (mode == 0) {
350 trace_iwlwifi_dev_ucode_cont_event(priv, 350 trace_iwlwifi_dev_ucode_cont_event(priv,
351 0, time, ev); 351 0, time, ev);
352 } else { 352 } else {
353 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 353 data = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
354 trace_iwlwifi_dev_ucode_cont_event(priv, 354 trace_iwlwifi_dev_ucode_cont_event(priv,
355 time, data, ev); 355 time, data, ev);
356 } 356 }
357 } 357 }
358 /* Allow device to power down */ 358 /* Allow device to power down */
359 iwl_release_nic_access(priv); 359 iwl_release_nic_access(bus(priv));
360 spin_unlock_irqrestore(&priv->reg_lock, reg_flags); 360 spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags);
361} 361}
362 362
363static void iwl_continuous_event_trace(struct iwl_priv *priv) 363static void iwl_continuous_event_trace(struct iwl_priv *priv)
@@ -370,10 +370,12 @@ static void iwl_continuous_event_trace(struct iwl_priv *priv)
370 370
371 base = priv->device_pointers.error_event_table; 371 base = priv->device_pointers.error_event_table;
372 if (iwlagn_hw_valid_rtc_data_addr(base)) { 372 if (iwlagn_hw_valid_rtc_data_addr(base)) {
373 capacity = iwl_read_targ_mem(priv, base); 373 capacity = iwl_read_targ_mem(bus(priv), base);
374 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); 374 num_wraps = iwl_read_targ_mem(bus(priv),
375 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); 375 base + (2 * sizeof(u32)));
376 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); 376 mode = iwl_read_targ_mem(bus(priv), base + (1 * sizeof(u32)));
377 next_entry = iwl_read_targ_mem(bus(priv),
378 base + (3 * sizeof(u32)));
377 } else 379 } else
378 return; 380 return;
379 381
@@ -1316,7 +1318,7 @@ static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1316 int ret = 0; 1318 int ret = 0;
1317 1319
1318 spin_lock_irqsave(&priv->shrd->lock, flags); 1320 spin_lock_irqsave(&priv->shrd->lock, flags);
1319 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 1321 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR,
1320 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 1322 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1321 spin_unlock_irqrestore(&priv->shrd->lock, flags); 1323 spin_unlock_irqrestore(&priv->shrd->lock, flags);
1322 priv->thermal_throttle.ct_kill_toggle = false; 1324 priv->thermal_throttle.ct_kill_toggle = false;
@@ -1934,7 +1936,7 @@ static void iwlagn_mac_stop(struct ieee80211_hw *hw)
1934 1936
1935 /* User space software may expect getting rfkill changes 1937 /* User space software may expect getting rfkill changes
1936 * even if interface is down */ 1938 * even if interface is down */
1937 iwl_write32(priv, CSR_INT, 0xFFFFFFFF); 1939 iwl_write32(bus(priv), CSR_INT, 0xFFFFFFFF);
1938 iwl_enable_rfkill_int(priv); 1940 iwl_enable_rfkill_int(priv);
1939 1941
1940 IWL_DEBUG_MAC80211(priv, "leave\n"); 1942 IWL_DEBUG_MAC80211(priv, "leave\n");
@@ -2329,7 +2331,7 @@ static int iwlagn_mac_suspend(struct ieee80211_hw *hw,
2329 device_set_wakeup_enable(priv->bus->dev, true); 2331 device_set_wakeup_enable(priv->bus->dev, true);
2330 2332
2331 /* Now let the ucode operate on its own */ 2333 /* Now let the ucode operate on its own */
2332 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 2334 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_SET,
2333 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); 2335 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
2334 2336
2335 goto out; 2337 goto out;
@@ -2355,19 +2357,19 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
2355 2357
2356 mutex_lock(&priv->shrd->mutex); 2358 mutex_lock(&priv->shrd->mutex);
2357 2359
2358 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 2360 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR,
2359 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE); 2361 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
2360 2362
2361 base = priv->device_pointers.error_event_table; 2363 base = priv->device_pointers.error_event_table;
2362 if (iwlagn_hw_valid_rtc_data_addr(base)) { 2364 if (iwlagn_hw_valid_rtc_data_addr(base)) {
2363 spin_lock_irqsave(&priv->reg_lock, flags); 2365 spin_lock_irqsave(&bus(priv)->reg_lock, flags);
2364 ret = iwl_grab_nic_access_silent(priv); 2366 ret = iwl_grab_nic_access_silent(bus(priv));
2365 if (ret == 0) { 2367 if (ret == 0) {
2366 iwl_write32(priv, HBUS_TARG_MEM_RADDR, base); 2368 iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, base);
2367 status = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 2369 status = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
2368 iwl_release_nic_access(priv); 2370 iwl_release_nic_access(bus(priv));
2369 } 2371 }
2370 spin_unlock_irqrestore(&priv->reg_lock, flags); 2372 spin_unlock_irqrestore(&bus(priv)->reg_lock, flags);
2371 2373
2372#ifdef CONFIG_IWLWIFI_DEBUGFS 2374#ifdef CONFIG_IWLWIFI_DEBUGFS
2373 if (ret == 0) { 2375 if (ret == 0) {
@@ -2378,7 +2380,7 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
2378 2380
2379 if (priv->wowlan_sram) 2381 if (priv->wowlan_sram)
2380 _iwl_read_targ_mem_words( 2382 _iwl_read_targ_mem_words(
2381 priv, 0x800000, priv->wowlan_sram, 2383 bus(priv), 0x800000, priv->wowlan_sram,
2382 priv->ucode_wowlan.data.len / 4); 2384 priv->ucode_wowlan.data.len / 4);
2383 } 2385 }
2384#endif 2386#endif
@@ -3186,7 +3188,7 @@ struct ieee80211_ops iwlagn_hw_ops = {
3186 3188
3187static u32 iwl_hw_detect(struct iwl_priv *priv) 3189static u32 iwl_hw_detect(struct iwl_priv *priv)
3188{ 3190{
3189 return iwl_read32(priv, CSR_HW_REV); 3191 return iwl_read32(bus(priv), CSR_HW_REV);
3190} 3192}
3191 3193
3192/* Size of one Rx buffer in host DRAM */ 3194/* Size of one Rx buffer in host DRAM */
@@ -3286,7 +3288,7 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,
3286 /* these spin locks will be used in apm_ops.init and EEPROM access 3288 /* these spin locks will be used in apm_ops.init and EEPROM access
3287 * we should init now 3289 * we should init now
3288 */ 3290 */
3289 spin_lock_init(&priv->reg_lock); 3291 spin_lock_init(&bus(priv)->reg_lock);
3290 spin_lock_init(&priv->shrd->lock); 3292 spin_lock_init(&priv->shrd->lock);
3291 3293
3292 /* 3294 /*
@@ -3294,7 +3296,7 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,
3294 * strange state ... like being left stranded by a primary kernel 3296 * strange state ... like being left stranded by a primary kernel
3295 * and this is now the kdump kernel trying to start up 3297 * and this is now the kdump kernel trying to start up
3296 */ 3298 */
3297 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 3299 iwl_write32(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3298 3300
3299 /*********************** 3301 /***********************
3300 * 3. Read REV register 3302 * 3. Read REV register
@@ -3375,7 +3377,8 @@ int iwl_probe(struct iwl_bus *bus, const struct iwl_trans_ops *trans_ops,
3375 iwl_enable_rfkill_int(priv); 3377 iwl_enable_rfkill_int(priv);
3376 3378
3377 /* If platform's RF_KILL switch is NOT set to KILL */ 3379 /* If platform's RF_KILL switch is NOT set to KILL */
3378 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 3380 if (iwl_read32(bus(priv),
3381 CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3379 clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status); 3382 clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
3380 else 3383 else
3381 set_bit(STATUS_RF_KILL_HW, &priv->shrd->status); 3384 set_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
diff --git a/drivers/net/wireless/iwlwifi/iwl-bus.h b/drivers/net/wireless/iwlwifi/iwl-bus.h
index e1cb65c45395..83aed46673e1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-bus.h
+++ b/drivers/net/wireless/iwlwifi/iwl-bus.h
@@ -66,6 +66,7 @@
66/*This file includes the declaration that are exported from the bus layer */ 66/*This file includes the declaration that are exported from the bus layer */
67 67
68#include <linux/types.h> 68#include <linux/types.h>
69#include <linux/spinlock.h>
69 70
70struct iwl_shared; 71struct iwl_shared;
71struct iwl_bus; 72struct iwl_bus;
@@ -96,6 +97,7 @@ struct iwl_bus_ops {
96 * @ops - pointer to iwl_bus_ops 97 * @ops - pointer to iwl_bus_ops
97 * @shrd - pointer to iwl_shared which holds shared data from the upper layer 98 * @shrd - pointer to iwl_shared which holds shared data from the upper layer
98 * @irq - the irq number for the device 99 * @irq - the irq number for the device
100 * @reg_lock - protect hw register access
99 */ 101 */
100struct iwl_bus { 102struct iwl_bus {
101 /* Common data to all buses */ 103 /* Common data to all buses */
@@ -104,6 +106,7 @@ struct iwl_bus {
104 struct iwl_shared *shrd; 106 struct iwl_shared *shrd;
105 107
106 unsigned int irq; 108 unsigned int irq;
109 spinlock_t reg_lock;
107 110
108 /* pointer to bus specific struct */ 111 /* pointer to bus specific struct */
109 /*Ensure that this pointer will always be aligned to sizeof pointer */ 112 /*Ensure that this pointer will always be aligned to sizeof pointer */
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 048c8e2578f5..411edc8f3f9d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -907,9 +907,10 @@ static int iwl_apm_stop_master(struct iwl_priv *priv)
907 int ret = 0; 907 int ret = 0;
908 908
909 /* stop device's busmaster DMA activity */ 909 /* stop device's busmaster DMA activity */
910 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 910 iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
911 911
912 ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, 912 ret = iwl_poll_bit(bus(priv), CSR_RESET,
913 CSR_RESET_REG_FLAG_MASTER_DISABLED,
913 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 914 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
914 if (ret) 915 if (ret)
915 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n"); 916 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
@@ -929,7 +930,7 @@ void iwl_apm_stop(struct iwl_priv *priv)
929 iwl_apm_stop_master(priv); 930 iwl_apm_stop_master(priv);
930 931
931 /* Reset the entire device */ 932 /* Reset the entire device */
932 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 933 iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
933 934
934 udelay(10); 935 udelay(10);
935 936
@@ -937,7 +938,7 @@ void iwl_apm_stop(struct iwl_priv *priv)
937 * Clear "initialization complete" bit to move adapter from 938 * Clear "initialization complete" bit to move adapter from
938 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 939 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
939 */ 940 */
940 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 941 iwl_clear_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
941} 942}
942 943
943 944
@@ -957,45 +958,45 @@ int iwl_apm_init(struct iwl_priv *priv)
957 */ 958 */
958 959
959 /* Disable L0S exit timer (platform NMI Work/Around) */ 960 /* Disable L0S exit timer (platform NMI Work/Around) */
960 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 961 iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS,
961 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 962 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
962 963
963 /* 964 /*
964 * Disable L0s without affecting L1; 965 * Disable L0s without affecting L1;
965 * don't wait for ICH L0s (ICH bug W/A) 966 * don't wait for ICH L0s (ICH bug W/A)
966 */ 967 */
967 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, 968 iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS,
968 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 969 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
969 970
970 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 971 /* Set FH wait threshold to maximum (HW error during stress W/A) */
971 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 972 iwl_set_bit(bus(priv), CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
972 973
973 /* 974 /*
974 * Enable HAP INTA (interrupt from management bus) to 975 * Enable HAP INTA (interrupt from management bus) to
975 * wake device's PCI Express link L1a -> L0s 976 * wake device's PCI Express link L1a -> L0s
976 */ 977 */
977 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 978 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
978 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 979 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
979 980
980 bus_apm_config(priv->bus); 981 bus_apm_config(priv->bus);
981 982
982 /* Configure analog phase-lock-loop before activating to D0A */ 983 /* Configure analog phase-lock-loop before activating to D0A */
983 if (priv->cfg->base_params->pll_cfg_val) 984 if (priv->cfg->base_params->pll_cfg_val)
984 iwl_set_bit(priv, CSR_ANA_PLL_CFG, 985 iwl_set_bit(bus(priv), CSR_ANA_PLL_CFG,
985 priv->cfg->base_params->pll_cfg_val); 986 priv->cfg->base_params->pll_cfg_val);
986 987
987 /* 988 /*
988 * Set "initialization complete" bit to move adapter from 989 * Set "initialization complete" bit to move adapter from
989 * D0U* --> D0A* (powered-up active) state. 990 * D0U* --> D0A* (powered-up active) state.
990 */ 991 */
991 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 992 iwl_set_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
992 993
993 /* 994 /*
994 * Wait for clock stabilization; once stabilized, access to 995 * Wait for clock stabilization; once stabilized, access to
995 * device-internal resources is supported, e.g. iwl_write_prph() 996 * device-internal resources is supported, e.g. iwl_write_prph()
996 * and accesses to uCode SRAM. 997 * and accesses to uCode SRAM.
997 */ 998 */
998 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 999 ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL,
999 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1000 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1000 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1001 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1001 if (ret < 0) { 1002 if (ret < 0) {
@@ -1010,11 +1011,11 @@ int iwl_apm_init(struct iwl_priv *priv)
1010 * do not disable clocks. This preserves any hardware bits already 1011 * do not disable clocks. This preserves any hardware bits already
1011 * set by default in "CLK_CTRL_REG" after reset. 1012 * set by default in "CLK_CTRL_REG" after reset.
1012 */ 1013 */
1013 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 1014 iwl_write_prph(bus(priv), APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
1014 udelay(20); 1015 udelay(20);
1015 1016
1016 /* Disable L1-Active */ 1017 /* Disable L1-Active */
1017 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 1018 iwl_set_bits_prph(bus(priv), APMG_PCIDEV_STT_REG,
1018 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1019 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1019 1020
1020 set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status); 1021 set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status);
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index a12b8d47ccbc..a01beb31d994 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -254,7 +254,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
254 sram = priv->dbgfs_sram_offset & ~0x3; 254 sram = priv->dbgfs_sram_offset & ~0x3;
255 255
256 /* read the first u32 from sram */ 256 /* read the first u32 from sram */
257 val = iwl_read_targ_mem(priv, sram); 257 val = iwl_read_targ_mem(bus(priv), sram);
258 258
259 for (; len; len--) { 259 for (; len; len--) {
260 /* put the address at the start of every line */ 260 /* put the address at the start of every line */
@@ -273,7 +273,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
273 if (++offset == 4) { 273 if (++offset == 4) {
274 sram += 4; 274 sram += 4;
275 offset = 0; 275 offset = 0;
276 val = iwl_read_targ_mem(priv, sram); 276 val = iwl_read_targ_mem(bus(priv), sram);
277 } 277 }
278 278
279 /* put in extra spaces and split lines for human readability */ 279 /* put in extra spaces and split lines for human readability */
@@ -1954,7 +1954,7 @@ static ssize_t iwl_dbgfs_power_save_status_read(struct file *file,
1954 const size_t bufsz = sizeof(buf); 1954 const size_t bufsz = sizeof(buf);
1955 u32 pwrsave_status; 1955 u32 pwrsave_status;
1956 1956
1957 pwrsave_status = iwl_read32(priv, CSR_GP_CNTRL) & 1957 pwrsave_status = iwl_read32(bus(priv), CSR_GP_CNTRL) &
1958 CSR_GP_REG_POWER_SAVE_STATUS_MSK; 1958 CSR_GP_REG_POWER_SAVE_STATUS_MSK;
1959 1959
1960 pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: "); 1960 pos += scnprintf(buf + pos, bufsz - pos, "Power Save Status: ");
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index 12cca9deabdc..711f2afceedd 100644
--- a/drivers/net/wireless/iwlwifi/iwl-dev.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -1169,9 +1169,6 @@ struct iwl_priv {
1169 u8 scan_tx_ant[IEEE80211_NUM_BANDS]; 1169 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1170 u8 mgmt_tx_ant; 1170 u8 mgmt_tx_ant;
1171 1171
1172 /* spinlock */
1173 spinlock_t reg_lock; /* protect hw register access */
1174
1175 /*TODO: remove these pointers - use bus(priv) instead */ 1172 /*TODO: remove these pointers - use bus(priv) instead */
1176 struct iwl_bus *bus; /* bus specific data */ 1173 struct iwl_bus *bus; /* bus specific data */
1177 1174
diff --git a/drivers/net/wireless/iwlwifi/iwl-devtrace.h b/drivers/net/wireless/iwlwifi/iwl-devtrace.h
index 2c84ba95afca..8a51c5ccda1e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-devtrace.h
+++ b/drivers/net/wireless/iwlwifi/iwl-devtrace.h
@@ -29,6 +29,8 @@
29 29
30#include <linux/tracepoint.h> 30#include <linux/tracepoint.h>
31 31
32struct iwl_priv;
33
32#if !defined(CONFIG_IWLWIFI_DEVICE_TRACING) || defined(__CHECKER__) 34#if !defined(CONFIG_IWLWIFI_DEVICE_TRACING) || defined(__CHECKER__)
33#undef TRACE_EVENT 35#undef TRACE_EVENT
34#define TRACE_EVENT(name, proto, ...) \ 36#define TRACE_EVENT(name, proto, ...) \
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index c790f7f2ffaa..80ee65be9cd1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -155,11 +155,11 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
155 155
156 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { 156 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
157 /* Request semaphore */ 157 /* Request semaphore */
158 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 158 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
159 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 159 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
160 160
161 /* See if we got it */ 161 /* See if we got it */
162 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, 162 ret = iwl_poll_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
163 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 163 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
164 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, 164 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
165 EEPROM_SEM_TIMEOUT); 165 EEPROM_SEM_TIMEOUT);
@@ -176,14 +176,14 @@ static int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
176 176
177static void iwl_eeprom_release_semaphore(struct iwl_priv *priv) 177static void iwl_eeprom_release_semaphore(struct iwl_priv *priv)
178{ 178{
179 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG, 179 iwl_clear_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
180 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); 180 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
181 181
182} 182}
183 183
184static int iwl_eeprom_verify_signature(struct iwl_priv *priv) 184static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
185{ 185{
186 u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 186 u32 gp = iwl_read32(bus(priv), CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
187 int ret = 0; 187 int ret = 0;
188 188
189 IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp); 189 IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
@@ -216,13 +216,13 @@ static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
216 216
217static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode) 217static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
218{ 218{
219 iwl_read32(priv, CSR_OTP_GP_REG); 219 iwl_read32(bus(priv), CSR_OTP_GP_REG);
220 220
221 if (mode == IWL_OTP_ACCESS_ABSOLUTE) 221 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
222 iwl_clear_bit(priv, CSR_OTP_GP_REG, 222 iwl_clear_bit(bus(priv), CSR_OTP_GP_REG,
223 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 223 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
224 else 224 else
225 iwl_set_bit(priv, CSR_OTP_GP_REG, 225 iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
226 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 226 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
227} 227}
228 228
@@ -243,7 +243,7 @@ static int iwl_get_nvm_type(struct iwl_priv *priv, u32 hw_rev)
243 nvm_type = NVM_DEVICE_TYPE_EEPROM; 243 nvm_type = NVM_DEVICE_TYPE_EEPROM;
244 break; 244 break;
245 default: 245 default:
246 otpgp = iwl_read32(priv, CSR_OTP_GP_REG); 246 otpgp = iwl_read32(bus(priv), CSR_OTP_GP_REG);
247 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 247 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
248 nvm_type = NVM_DEVICE_TYPE_OTP; 248 nvm_type = NVM_DEVICE_TYPE_OTP;
249 else 249 else
@@ -258,22 +258,22 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
258 int ret; 258 int ret;
259 259
260 /* Enable 40MHz radio clock */ 260 /* Enable 40MHz radio clock */
261 iwl_write32(priv, CSR_GP_CNTRL, 261 iwl_write32(bus(priv), CSR_GP_CNTRL,
262 iwl_read32(priv, CSR_GP_CNTRL) | 262 iwl_read32(bus(priv), CSR_GP_CNTRL) |
263 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 263 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
264 264
265 /* wait for clock to be ready */ 265 /* wait for clock to be ready */
266 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 266 ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL,
267 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 267 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
268 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 268 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
269 25000); 269 25000);
270 if (ret < 0) 270 if (ret < 0)
271 IWL_ERR(priv, "Time out access OTP\n"); 271 IWL_ERR(priv, "Time out access OTP\n");
272 else { 272 else {
273 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, 273 iwl_set_bits_prph(bus(priv), APMG_PS_CTRL_REG,
274 APMG_PS_CTRL_VAL_RESET_REQ); 274 APMG_PS_CTRL_VAL_RESET_REQ);
275 udelay(5); 275 udelay(5);
276 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 276 iwl_clear_bits_prph(bus(priv), APMG_PS_CTRL_REG,
277 APMG_PS_CTRL_VAL_RESET_REQ); 277 APMG_PS_CTRL_VAL_RESET_REQ);
278 278
279 /* 279 /*
@@ -281,7 +281,7 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
281 * this is only applicable for HW with OTP shadow RAM 281 * this is only applicable for HW with OTP shadow RAM
282 */ 282 */
283 if (priv->cfg->base_params->shadow_ram_support) 283 if (priv->cfg->base_params->shadow_ram_support)
284 iwl_set_bit(priv, CSR_DBG_LINK_PWR_MGMT_REG, 284 iwl_set_bit(bus(priv), CSR_DBG_LINK_PWR_MGMT_REG,
285 CSR_RESET_LINK_PWR_MGMT_DISABLED); 285 CSR_RESET_LINK_PWR_MGMT_DISABLED);
286 } 286 }
287 return ret; 287 return ret;
@@ -293,9 +293,9 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
293 u32 r; 293 u32 r;
294 u32 otpgp; 294 u32 otpgp;
295 295
296 iwl_write32(priv, CSR_EEPROM_REG, 296 iwl_write32(bus(priv), CSR_EEPROM_REG,
297 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 297 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
298 ret = iwl_poll_bit(priv, CSR_EEPROM_REG, 298 ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG,
299 CSR_EEPROM_REG_READ_VALID_MSK, 299 CSR_EEPROM_REG_READ_VALID_MSK,
300 CSR_EEPROM_REG_READ_VALID_MSK, 300 CSR_EEPROM_REG_READ_VALID_MSK,
301 IWL_EEPROM_ACCESS_TIMEOUT); 301 IWL_EEPROM_ACCESS_TIMEOUT);
@@ -303,13 +303,13 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
303 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr); 303 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
304 return ret; 304 return ret;
305 } 305 }
306 r = iwl_read32(priv, CSR_EEPROM_REG); 306 r = iwl_read32(bus(priv), CSR_EEPROM_REG);
307 /* check for ECC errors: */ 307 /* check for ECC errors: */
308 otpgp = iwl_read32(priv, CSR_OTP_GP_REG); 308 otpgp = iwl_read32(bus(priv), CSR_OTP_GP_REG);
309 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 309 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
310 /* stop in this case */ 310 /* stop in this case */
311 /* set the uncorrectable OTP ECC bit for acknowledgement */ 311 /* set the uncorrectable OTP ECC bit for acknowledgement */
312 iwl_set_bit(priv, CSR_OTP_GP_REG, 312 iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
313 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 313 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
314 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n"); 314 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
315 return -EINVAL; 315 return -EINVAL;
@@ -317,7 +317,7 @@ static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, __le16 *eeprom_dat
317 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 317 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
318 /* continue in this case */ 318 /* continue in this case */
319 /* set the correctable OTP ECC bit for acknowledgement */ 319 /* set the correctable OTP ECC bit for acknowledgement */
320 iwl_set_bit(priv, CSR_OTP_GP_REG, 320 iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
321 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 321 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
322 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n"); 322 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
323 } 323 }
@@ -424,7 +424,7 @@ u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
424int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev) 424int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
425{ 425{
426 __le16 *e; 426 __le16 *e;
427 u32 gp = iwl_read32(priv, CSR_EEPROM_GP); 427 u32 gp = iwl_read32(bus(priv), CSR_EEPROM_GP);
428 int sz; 428 int sz;
429 int ret; 429 int ret;
430 u16 addr; 430 u16 addr;
@@ -469,11 +469,11 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
469 ret = -ENOENT; 469 ret = -ENOENT;
470 goto done; 470 goto done;
471 } 471 }
472 iwl_write32(priv, CSR_EEPROM_GP, 472 iwl_write32(bus(priv), CSR_EEPROM_GP,
473 iwl_read32(priv, CSR_EEPROM_GP) & 473 iwl_read32(bus(priv), CSR_EEPROM_GP) &
474 ~CSR_EEPROM_GP_IF_OWNER_MSK); 474 ~CSR_EEPROM_GP_IF_OWNER_MSK);
475 475
476 iwl_set_bit(priv, CSR_OTP_GP_REG, 476 iwl_set_bit(bus(priv), CSR_OTP_GP_REG,
477 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 477 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
478 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 478 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
479 /* traversing the linked list if no shadow ram supported */ 479 /* traversing the linked list if no shadow ram supported */
@@ -498,10 +498,10 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
498 for (addr = 0; addr < sz; addr += sizeof(u16)) { 498 for (addr = 0; addr < sz; addr += sizeof(u16)) {
499 u32 r; 499 u32 r;
500 500
501 iwl_write32(priv, CSR_EEPROM_REG, 501 iwl_write32(bus(priv), CSR_EEPROM_REG,
502 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 502 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
503 503
504 ret = iwl_poll_bit(priv, CSR_EEPROM_REG, 504 ret = iwl_poll_bit(bus(priv), CSR_EEPROM_REG,
505 CSR_EEPROM_REG_READ_VALID_MSK, 505 CSR_EEPROM_REG_READ_VALID_MSK,
506 CSR_EEPROM_REG_READ_VALID_MSK, 506 CSR_EEPROM_REG_READ_VALID_MSK,
507 IWL_EEPROM_ACCESS_TIMEOUT); 507 IWL_EEPROM_ACCESS_TIMEOUT);
@@ -509,7 +509,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
509 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr); 509 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
510 goto done; 510 goto done;
511 } 511 }
512 r = iwl_read32(priv, CSR_EEPROM_REG); 512 r = iwl_read32(bus(priv), CSR_EEPROM_REG);
513 e[addr / 2] = cpu_to_le16(r >> 16); 513 e[addr / 2] = cpu_to_le16(r >> 16);
514 } 514 }
515 } 515 }
@@ -838,7 +838,7 @@ void iwl_rf_config(struct iwl_priv *priv)
838 838
839 /* write radio config values to register */ 839 /* write radio config values to register */
840 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) { 840 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
841 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 841 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
842 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | 842 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
843 EEPROM_RF_CFG_STEP_MSK(radio_cfg) | 843 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
844 EEPROM_RF_CFG_DASH_MSK(radio_cfg)); 844 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
@@ -850,7 +850,7 @@ void iwl_rf_config(struct iwl_priv *priv)
850 WARN_ON(1); 850 WARN_ON(1);
851 851
852 /* set CSR_HW_CONFIG_REG for uCode use */ 852 /* set CSR_HW_CONFIG_REG for uCode use */
853 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 853 iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
854 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 854 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
855 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 855 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
856} 856}
diff --git a/drivers/net/wireless/iwlwifi/iwl-helpers.h b/drivers/net/wireless/iwlwifi/iwl-helpers.h
index f744fdc39a4d..8ca624d2a8b0 100644
--- a/drivers/net/wireless/iwlwifi/iwl-helpers.h
+++ b/drivers/net/wireless/iwlwifi/iwl-helpers.h
@@ -141,7 +141,7 @@ static inline void iwl_wake_any_queue(struct iwl_priv *priv,
141static inline void iwl_enable_rfkill_int(struct iwl_priv *priv) 141static inline void iwl_enable_rfkill_int(struct iwl_priv *priv)
142{ 142{
143 IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n"); 143 IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n");
144 iwl_write32(priv, CSR_INT_MASK, CSR_INT_BIT_RF_KILL); 144 iwl_write32(bus(priv), CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
145} 145}
146 146
147/** 147/**
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.c b/drivers/net/wireless/iwlwifi/iwl-io.c
index aa4a90674452..3ffa8e62b856 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.c
+++ b/drivers/net/wireless/iwlwifi/iwl-io.c
@@ -25,46 +25,50 @@
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 * 26 *
27 *****************************************************************************/ 27 *****************************************************************************/
28#include <linux/delay.h>
29#include <linux/device.h>
28 30
29#include "iwl-io.h" 31#include "iwl-io.h"
32#include"iwl-csr.h"
33#include "iwl-debug.h"
30 34
31#define IWL_POLL_INTERVAL 10 /* microseconds */ 35#define IWL_POLL_INTERVAL 10 /* microseconds */
32 36
33static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) 37static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask)
34{ 38{
35 iwl_write32(priv, reg, iwl_read32(priv, reg) | mask); 39 iwl_write32(bus, reg, iwl_read32(bus, reg) | mask);
36} 40}
37 41
38static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) 42static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask)
39{ 43{
40 iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask); 44 iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask);
41} 45}
42 46
43void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) 47void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask)
44{ 48{
45 unsigned long flags; 49 unsigned long flags;
46 50
47 spin_lock_irqsave(&priv->reg_lock, flags); 51 spin_lock_irqsave(&bus->reg_lock, flags);
48 __iwl_set_bit(priv, reg, mask); 52 __iwl_set_bit(bus, reg, mask);
49 spin_unlock_irqrestore(&priv->reg_lock, flags); 53 spin_unlock_irqrestore(&bus->reg_lock, flags);
50} 54}
51 55
52void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) 56void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask)
53{ 57{
54 unsigned long flags; 58 unsigned long flags;
55 59
56 spin_lock_irqsave(&priv->reg_lock, flags); 60 spin_lock_irqsave(&bus->reg_lock, flags);
57 __iwl_clear_bit(priv, reg, mask); 61 __iwl_clear_bit(bus, reg, mask);
58 spin_unlock_irqrestore(&priv->reg_lock, flags); 62 spin_unlock_irqrestore(&bus->reg_lock, flags);
59} 63}
60 64
61int iwl_poll_bit(struct iwl_priv *priv, u32 addr, 65int iwl_poll_bit(struct iwl_bus *bus, u32 addr,
62 u32 bits, u32 mask, int timeout) 66 u32 bits, u32 mask, int timeout)
63{ 67{
64 int t = 0; 68 int t = 0;
65 69
66 do { 70 do {
67 if ((iwl_read32(priv, addr) & mask) == (bits & mask)) 71 if ((iwl_read32(bus, addr) & mask) == (bits & mask))
68 return t; 72 return t;
69 udelay(IWL_POLL_INTERVAL); 73 udelay(IWL_POLL_INTERVAL);
70 t += IWL_POLL_INTERVAL; 74 t += IWL_POLL_INTERVAL;
@@ -73,14 +77,14 @@ int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
73 return -ETIMEDOUT; 77 return -ETIMEDOUT;
74} 78}
75 79
76int iwl_grab_nic_access_silent(struct iwl_priv *priv) 80int iwl_grab_nic_access_silent(struct iwl_bus *bus)
77{ 81{
78 int ret; 82 int ret;
79 83
80 lockdep_assert_held(&priv->reg_lock); 84 lockdep_assert_held(&bus->reg_lock);
81 85
82 /* this bit wakes up the NIC */ 86 /* this bit wakes up the NIC */
83 __iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 87 __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
84 88
85 /* 89 /*
86 * These bits say the device is running, and should keep running for 90 * These bits say the device is running, and should keep running for
@@ -101,70 +105,70 @@ int iwl_grab_nic_access_silent(struct iwl_priv *priv)
101 * 5000 series and later (including 1000 series) have non-volatile SRAM, 105 * 5000 series and later (including 1000 series) have non-volatile SRAM,
102 * and do not save/restore SRAM when power cycling. 106 * and do not save/restore SRAM when power cycling.
103 */ 107 */
104 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 108 ret = iwl_poll_bit(bus, CSR_GP_CNTRL,
105 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 109 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
106 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 110 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
107 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 111 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
108 if (ret < 0) { 112 if (ret < 0) {
109 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 113 iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
110 return -EIO; 114 return -EIO;
111 } 115 }
112 116
113 return 0; 117 return 0;
114} 118}
115 119
116int iwl_grab_nic_access(struct iwl_priv *priv) 120int iwl_grab_nic_access(struct iwl_bus *bus)
117{ 121{
118 int ret = iwl_grab_nic_access_silent(priv); 122 int ret = iwl_grab_nic_access_silent(bus);
119 if (ret) { 123 if (ret) {
120 u32 val = iwl_read32(priv, CSR_GP_CNTRL); 124 u32 val = iwl_read32(bus, CSR_GP_CNTRL);
121 IWL_ERR(priv, 125 IWL_ERR(bus,
122 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); 126 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
123 } 127 }
124 128
125 return ret; 129 return ret;
126} 130}
127 131
128void iwl_release_nic_access(struct iwl_priv *priv) 132void iwl_release_nic_access(struct iwl_bus *bus)
129{ 133{
130 lockdep_assert_held(&priv->reg_lock); 134 lockdep_assert_held(&bus->reg_lock);
131 __iwl_clear_bit(priv, CSR_GP_CNTRL, 135 __iwl_clear_bit(bus, CSR_GP_CNTRL,
132 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 136 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
133} 137}
134 138
135u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg) 139u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg)
136{ 140{
137 u32 value; 141 u32 value;
138 unsigned long flags; 142 unsigned long flags;
139 143
140 spin_lock_irqsave(&priv->reg_lock, flags); 144 spin_lock_irqsave(&bus->reg_lock, flags);
141 iwl_grab_nic_access(priv); 145 iwl_grab_nic_access(bus);
142 value = iwl_read32(priv, reg); 146 value = iwl_read32(bus(bus), reg);
143 iwl_release_nic_access(priv); 147 iwl_release_nic_access(bus);
144 spin_unlock_irqrestore(&priv->reg_lock, flags); 148 spin_unlock_irqrestore(&bus->reg_lock, flags);
145 149
146 return value; 150 return value;
147} 151}
148 152
149void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value) 153void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value)
150{ 154{
151 unsigned long flags; 155 unsigned long flags;
152 156
153 spin_lock_irqsave(&priv->reg_lock, flags); 157 spin_lock_irqsave(&bus->reg_lock, flags);
154 if (!iwl_grab_nic_access(priv)) { 158 if (!iwl_grab_nic_access(bus)) {
155 iwl_write32(priv, reg, value); 159 iwl_write32(bus, reg, value);
156 iwl_release_nic_access(priv); 160 iwl_release_nic_access(bus);
157 } 161 }
158 spin_unlock_irqrestore(&priv->reg_lock, flags); 162 spin_unlock_irqrestore(&bus->reg_lock, flags);
159} 163}
160 164
161int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask, 165int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask,
162 int timeout) 166 int timeout)
163{ 167{
164 int t = 0; 168 int t = 0;
165 169
166 do { 170 do {
167 if ((iwl_read_direct32(priv, addr) & mask) == mask) 171 if ((iwl_read_direct32(bus, addr) & mask) == mask)
168 return t; 172 return t;
169 udelay(IWL_POLL_INTERVAL); 173 udelay(IWL_POLL_INTERVAL);
170 t += IWL_POLL_INTERVAL; 174 t += IWL_POLL_INTERVAL;
@@ -173,122 +177,122 @@ int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
173 return -ETIMEDOUT; 177 return -ETIMEDOUT;
174} 178}
175 179
176static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg) 180static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg)
177{ 181{
178 iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 182 iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
179 rmb(); 183 rmb();
180 return iwl_read32(priv, HBUS_TARG_PRPH_RDAT); 184 return iwl_read32(bus, HBUS_TARG_PRPH_RDAT);
181} 185}
182 186
183static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val) 187static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val)
184{ 188{
185 iwl_write32(priv, HBUS_TARG_PRPH_WADDR, 189 iwl_write32(bus, HBUS_TARG_PRPH_WADDR,
186 ((addr & 0x0000FFFF) | (3 << 24))); 190 ((addr & 0x0000FFFF) | (3 << 24)));
187 wmb(); 191 wmb();
188 iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val); 192 iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val);
189} 193}
190 194
191u32 iwl_read_prph(struct iwl_priv *priv, u32 reg) 195u32 iwl_read_prph(struct iwl_bus *bus, u32 reg)
192{ 196{
193 unsigned long flags; 197 unsigned long flags;
194 u32 val; 198 u32 val;
195 199
196 spin_lock_irqsave(&priv->reg_lock, flags); 200 spin_lock_irqsave(&bus->reg_lock, flags);
197 iwl_grab_nic_access(priv); 201 iwl_grab_nic_access(bus);
198 val = __iwl_read_prph(priv, reg); 202 val = __iwl_read_prph(bus, reg);
199 iwl_release_nic_access(priv); 203 iwl_release_nic_access(bus);
200 spin_unlock_irqrestore(&priv->reg_lock, flags); 204 spin_unlock_irqrestore(&bus->reg_lock, flags);
201 return val; 205 return val;
202} 206}
203 207
204void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val) 208void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val)
205{ 209{
206 unsigned long flags; 210 unsigned long flags;
207 211
208 spin_lock_irqsave(&priv->reg_lock, flags); 212 spin_lock_irqsave(&bus->reg_lock, flags);
209 if (!iwl_grab_nic_access(priv)) { 213 if (!iwl_grab_nic_access(bus)) {
210 __iwl_write_prph(priv, addr, val); 214 __iwl_write_prph(bus, addr, val);
211 iwl_release_nic_access(priv); 215 iwl_release_nic_access(bus);
212 } 216 }
213 spin_unlock_irqrestore(&priv->reg_lock, flags); 217 spin_unlock_irqrestore(&bus->reg_lock, flags);
214} 218}
215 219
216void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask) 220void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask)
217{ 221{
218 unsigned long flags; 222 unsigned long flags;
219 223
220 spin_lock_irqsave(&priv->reg_lock, flags); 224 spin_lock_irqsave(&bus->reg_lock, flags);
221 iwl_grab_nic_access(priv); 225 iwl_grab_nic_access(bus);
222 __iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask); 226 __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask);
223 iwl_release_nic_access(priv); 227 iwl_release_nic_access(bus);
224 spin_unlock_irqrestore(&priv->reg_lock, flags); 228 spin_unlock_irqrestore(&bus->reg_lock, flags);
225} 229}
226 230
227void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg, 231void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg,
228 u32 bits, u32 mask) 232 u32 bits, u32 mask)
229{ 233{
230 unsigned long flags; 234 unsigned long flags;
231 235
232 spin_lock_irqsave(&priv->reg_lock, flags); 236 spin_lock_irqsave(&bus->reg_lock, flags);
233 iwl_grab_nic_access(priv); 237 iwl_grab_nic_access(bus);
234 __iwl_write_prph(priv, reg, 238 __iwl_write_prph(bus, reg,
235 (__iwl_read_prph(priv, reg) & mask) | bits); 239 (__iwl_read_prph(bus, reg) & mask) | bits);
236 iwl_release_nic_access(priv); 240 iwl_release_nic_access(bus);
237 spin_unlock_irqrestore(&priv->reg_lock, flags); 241 spin_unlock_irqrestore(&bus->reg_lock, flags);
238} 242}
239 243
240void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask) 244void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask)
241{ 245{
242 unsigned long flags; 246 unsigned long flags;
243 u32 val; 247 u32 val;
244 248
245 spin_lock_irqsave(&priv->reg_lock, flags); 249 spin_lock_irqsave(&bus->reg_lock, flags);
246 iwl_grab_nic_access(priv); 250 iwl_grab_nic_access(bus);
247 val = __iwl_read_prph(priv, reg); 251 val = __iwl_read_prph(bus, reg);
248 __iwl_write_prph(priv, reg, (val & ~mask)); 252 __iwl_write_prph(bus, reg, (val & ~mask));
249 iwl_release_nic_access(priv); 253 iwl_release_nic_access(bus);
250 spin_unlock_irqrestore(&priv->reg_lock, flags); 254 spin_unlock_irqrestore(&bus->reg_lock, flags);
251} 255}
252 256
253void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr, 257void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr,
254 void *buf, int words) 258 void *buf, int words)
255{ 259{
256 unsigned long flags; 260 unsigned long flags;
257 int offs; 261 int offs;
258 u32 *vals = buf; 262 u32 *vals = buf;
259 263
260 spin_lock_irqsave(&priv->reg_lock, flags); 264 spin_lock_irqsave(&bus->reg_lock, flags);
261 iwl_grab_nic_access(priv); 265 iwl_grab_nic_access(bus);
262 266
263 iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr); 267 iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr);
264 rmb(); 268 rmb();
265 269
266 for (offs = 0; offs < words; offs++) 270 for (offs = 0; offs < words; offs++)
267 vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 271 vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
268 272
269 iwl_release_nic_access(priv); 273 iwl_release_nic_access(bus);
270 spin_unlock_irqrestore(&priv->reg_lock, flags); 274 spin_unlock_irqrestore(&bus->reg_lock, flags);
271} 275}
272 276
273u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr) 277u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr)
274{ 278{
275 u32 value; 279 u32 value;
276 280
277 _iwl_read_targ_mem_words(priv, addr, &value, 1); 281 _iwl_read_targ_mem_words(bus, addr, &value, 1);
278 282
279 return value; 283 return value;
280} 284}
281 285
282void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) 286void iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val)
283{ 287{
284 unsigned long flags; 288 unsigned long flags;
285 289
286 spin_lock_irqsave(&priv->reg_lock, flags); 290 spin_lock_irqsave(&bus->reg_lock, flags);
287 if (!iwl_grab_nic_access(priv)) { 291 if (!iwl_grab_nic_access(bus)) {
288 iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr); 292 iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr);
289 wmb(); 293 wmb();
290 iwl_write32(priv, HBUS_TARG_MEM_WDAT, val); 294 iwl_write32(bus, HBUS_TARG_MEM_WDAT, val);
291 iwl_release_nic_access(priv); 295 iwl_release_nic_access(bus);
292 } 296 }
293 spin_unlock_irqrestore(&priv->reg_lock, flags); 297 spin_unlock_irqrestore(&bus->reg_lock, flags);
294} 298}
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index 19a093101122..ced2cbeb6eae 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -29,65 +29,62 @@
29#ifndef __iwl_io_h__ 29#ifndef __iwl_io_h__
30#define __iwl_io_h__ 30#define __iwl_io_h__
31 31
32#include <linux/io.h>
33
34#include "iwl-dev.h"
35#include "iwl-debug.h"
36#include "iwl-devtrace.h" 32#include "iwl-devtrace.h"
33#include "iwl-shared.h"
37#include "iwl-bus.h" 34#include "iwl-bus.h"
38 35
39static inline void iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val) 36static inline void iwl_write8(struct iwl_bus *bus, u32 ofs, u8 val)
40{ 37{
41 trace_iwlwifi_dev_iowrite8(priv, ofs, val); 38 trace_iwlwifi_dev_iowrite8(priv(bus), ofs, val);
42 bus_write8(priv->bus, ofs, val); 39 bus_write8(bus, ofs, val);
43} 40}
44 41
45static inline void iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val) 42static inline void iwl_write32(struct iwl_bus *bus, u32 ofs, u32 val)
46{ 43{
47 trace_iwlwifi_dev_iowrite32(priv, ofs, val); 44 trace_iwlwifi_dev_iowrite32(priv(bus), ofs, val);
48 bus_write32(priv->bus, ofs, val); 45 bus_write32(bus, ofs, val);
49} 46}
50 47
51static inline u32 iwl_read32(struct iwl_priv *priv, u32 ofs) 48static inline u32 iwl_read32(struct iwl_bus *bus, u32 ofs)
52{ 49{
53 u32 val = bus_read32(priv->bus, ofs); 50 u32 val = bus_read32(bus, ofs);
54 trace_iwlwifi_dev_ioread32(priv, ofs, val); 51 trace_iwlwifi_dev_ioread32(priv(bus), ofs, val);
55 return val; 52 return val;
56} 53}
57 54
58void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask); 55void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask);
59void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask); 56void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask);
60 57
61int iwl_poll_bit(struct iwl_priv *priv, u32 addr, 58int iwl_poll_bit(struct iwl_bus *bus, u32 addr,
62 u32 bits, u32 mask, int timeout); 59 u32 bits, u32 mask, int timeout);
63int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask, 60int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask,
64 int timeout); 61 int timeout);
65 62
66int iwl_grab_nic_access_silent(struct iwl_priv *priv); 63int iwl_grab_nic_access_silent(struct iwl_bus *bus);
67int iwl_grab_nic_access(struct iwl_priv *priv); 64int iwl_grab_nic_access(struct iwl_bus *bus);
68void iwl_release_nic_access(struct iwl_priv *priv); 65void iwl_release_nic_access(struct iwl_bus *bus);
69 66
70u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg); 67u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg);
71void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value); 68void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value);
72 69
73 70
74u32 iwl_read_prph(struct iwl_priv *priv, u32 reg); 71u32 iwl_read_prph(struct iwl_bus *bus, u32 reg);
75void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val); 72void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val);
76void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask); 73void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask);
77void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg, 74void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg,
78 u32 bits, u32 mask); 75 u32 bits, u32 mask);
79void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask); 76void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask);
80 77
81void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr, 78void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr,
82 void *buf, int words); 79 void *buf, int words);
83 80
84#define iwl_read_targ_mem_words(priv, addr, buf, bufsize) \ 81#define iwl_read_targ_mem_words(bus, addr, buf, bufsize) \
85 do { \ 82 do { \
86 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 83 BUILD_BUG_ON((bufsize) % sizeof(u32)); \
87 _iwl_read_targ_mem_words(priv, addr, buf, \ 84 _iwl_read_targ_mem_words(bus, addr, buf, \
88 (bufsize) / sizeof(u32));\ 85 (bufsize) / sizeof(u32));\
89 } while (0) 86 } while (0)
90 87
91u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr); 88u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr);
92void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val); 89void iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val);
93#endif 90#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index 4bc7389b1a6f..7dffed186f0a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -71,7 +71,7 @@ static const struct ieee80211_tpt_blink iwl_blink[] = {
71/* Set led register off */ 71/* Set led register off */
72void iwlagn_led_enable(struct iwl_priv *priv) 72void iwlagn_led_enable(struct iwl_priv *priv)
73{ 73{
74 iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_ON); 74 iwl_write32(bus(priv), CSR_LED_REG, CSR_LED_REG_TRUN_ON);
75} 75}
76 76
77/* 77/*
@@ -108,9 +108,9 @@ static int iwl_send_led_cmd(struct iwl_priv *priv, struct iwl_led_cmd *led_cmd)
108 }; 108 };
109 u32 reg; 109 u32 reg;
110 110
111 reg = iwl_read32(priv, CSR_LED_REG); 111 reg = iwl_read32(bus(priv), CSR_LED_REG);
112 if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) 112 if (reg != (reg & CSR_LED_BSM_CTRL_MSK))
113 iwl_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); 113 iwl_write32(bus(priv), CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK);
114 114
115 return iwl_trans_send_cmd(trans(priv), &cmd); 115 return iwl_trans_send_cmd(trans(priv), &cmd);
116} 116}
diff --git a/drivers/net/wireless/iwlwifi/iwl-pci.c b/drivers/net/wireless/iwlwifi/iwl-pci.c
index 191c16adeeb3..17f3fb241b6f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-pci.c
+++ b/drivers/net/wireless/iwlwifi/iwl-pci.c
@@ -124,12 +124,12 @@ static void iwl_pci_apm_config(struct iwl_bus *bus)
124 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == 124 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
125 PCI_CFG_LINK_CTRL_VAL_L1_EN) { 125 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
126 /* L1-ASPM enabled; disable(!) L0S */ 126 /* L1-ASPM enabled; disable(!) L0S */
127 iwl_set_bit(priv(bus), CSR_GIO_REG, 127 iwl_set_bit(bus, CSR_GIO_REG,
128 CSR_GIO_REG_VAL_L0S_ENABLED); 128 CSR_GIO_REG_VAL_L0S_ENABLED);
129 dev_printk(KERN_INFO, bus->dev, "L1 Enabled; Disabling L0S\n"); 129 dev_printk(KERN_INFO, bus->dev, "L1 Enabled; Disabling L0S\n");
130 } else { 130 } else {
131 /* L1-ASPM disabled; enable(!) L0S */ 131 /* L1-ASPM disabled; enable(!) L0S */
132 iwl_clear_bit(priv(bus), CSR_GIO_REG, 132 iwl_clear_bit(bus, CSR_GIO_REG,
133 CSR_GIO_REG_VAL_L0S_ENABLED); 133 CSR_GIO_REG_VAL_L0S_ENABLED);
134 dev_printk(KERN_INFO, bus->dev, "L1 Disabled; Enabling L0S\n"); 134 dev_printk(KERN_INFO, bus->dev, "L1 Disabled; Enabling L0S\n");
135 } 135 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
index d7c7c93b2daf..2c6659c82f92 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -531,16 +531,16 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv,
531 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | 531 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
532 CT_CARD_DISABLED)) { 532 CT_CARD_DISABLED)) {
533 533
534 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 534 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_SET,
535 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 535 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
536 536
537 iwl_write_direct32(priv, HBUS_TARG_MBX_C, 537 iwl_write_direct32(bus(priv), HBUS_TARG_MBX_C,
538 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 538 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
539 539
540 if (!(flags & RXON_CARD_DISABLED)) { 540 if (!(flags & RXON_CARD_DISABLED)) {
541 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 541 iwl_write32(bus(priv), CSR_UCODE_DRV_GP1_CLR,
542 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 542 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
543 iwl_write_direct32(priv, HBUS_TARG_MBX_C, 543 iwl_write_direct32(bus(priv), HBUS_TARG_MBX_C,
544 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 544 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
545 } 545 }
546 if (flags & CT_CARD_DISABLED) 546 if (flags & CT_CARD_DISABLED)
diff --git a/drivers/net/wireless/iwlwifi/iwl-sv-open.c b/drivers/net/wireless/iwlwifi/iwl-sv-open.c
index 15c9be8d455f..b53d77b131d5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sv-open.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sv-open.c
@@ -276,7 +276,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
276 276
277 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) { 277 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
278 case IWL_TM_CMD_APP2DEV_REG_READ32: 278 case IWL_TM_CMD_APP2DEV_REG_READ32:
279 val32 = iwl_read32(priv, ofs); 279 val32 = iwl_read32(bus(priv), ofs);
280 IWL_INFO(priv, "32bit value to read 0x%x\n", val32); 280 IWL_INFO(priv, "32bit value to read 0x%x\n", val32);
281 281
282 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20); 282 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 20);
@@ -298,7 +298,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
298 } else { 298 } else {
299 val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]); 299 val32 = nla_get_u32(tb[IWL_TM_ATTR_REG_VALUE32]);
300 IWL_INFO(priv, "32bit value to write 0x%x\n", val32); 300 IWL_INFO(priv, "32bit value to write 0x%x\n", val32);
301 iwl_write32(priv, ofs, val32); 301 iwl_write32(bus(priv), ofs, val32);
302 } 302 }
303 break; 303 break;
304 case IWL_TM_CMD_APP2DEV_REG_WRITE8: 304 case IWL_TM_CMD_APP2DEV_REG_WRITE8:
@@ -308,7 +308,7 @@ static int iwl_testmode_reg(struct ieee80211_hw *hw, struct nlattr **tb)
308 } else { 308 } else {
309 val8 = nla_get_u8(tb[IWL_TM_ATTR_REG_VALUE8]); 309 val8 = nla_get_u8(tb[IWL_TM_ATTR_REG_VALUE8]);
310 IWL_INFO(priv, "8bit value to write 0x%x\n", val8); 310 IWL_INFO(priv, "8bit value to write 0x%x\n", val8);
311 iwl_write8(priv, ofs, val8); 311 iwl_write8(bus(priv), ofs, val8);
312 } 312 }
313 break; 313 break;
314 default: 314 default:
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h b/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h
index b77b0f79fcb0..bd6e64026a06 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h
@@ -200,12 +200,12 @@ static inline void iwl_disable_interrupts(struct iwl_trans *trans)
200 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status); 200 clear_bit(STATUS_INT_ENABLED, &trans->shrd->status);
201 201
202 /* disable interrupts from uCode/NIC to host */ 202 /* disable interrupts from uCode/NIC to host */
203 iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000); 203 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
204 204
205 /* acknowledge/clear/reset any interrupts still pending 205 /* acknowledge/clear/reset any interrupts still pending
206 * from uCode or flow handler (Rx/Tx DMA) */ 206 * from uCode or flow handler (Rx/Tx DMA) */
207 iwl_write32(priv(trans), CSR_INT, 0xffffffff); 207 iwl_write32(bus(trans), CSR_INT, 0xffffffff);
208 iwl_write32(priv(trans), CSR_FH_INT_STATUS, 0xffffffff); 208 iwl_write32(bus(trans), CSR_FH_INT_STATUS, 0xffffffff);
209 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 209 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
210} 210}
211 211
@@ -216,7 +216,7 @@ static inline void iwl_enable_interrupts(struct iwl_trans *trans)
216 216
217 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 217 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
218 set_bit(STATUS_INT_ENABLED, &trans->shrd->status); 218 set_bit(STATUS_INT_ENABLED, &trans->shrd->status);
219 iwl_write32(priv(trans), CSR_INT_MASK, trans_pcie->inta_mask); 219 iwl_write32(bus(trans), CSR_INT_MASK, trans_pcie->inta_mask);
220} 220}
221 221
222#endif /* __iwl_trans_int_pcie_h__ */ 222#endif /* __iwl_trans_int_pcie_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c
index 7f8ac2ed49ab..5cff771af92f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c
@@ -143,30 +143,30 @@ void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
143 /* shadow register enabled */ 143 /* shadow register enabled */
144 /* Device expects a multiple of 8 */ 144 /* Device expects a multiple of 8 */
145 q->write_actual = (q->write & ~0x7); 145 q->write_actual = (q->write & ~0x7);
146 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual); 146 iwl_write32(bus(priv), FH_RSCSR_CHNL0_WPTR, q->write_actual);
147 } else { 147 } else {
148 /* If power-saving is in use, make sure device is awake */ 148 /* If power-saving is in use, make sure device is awake */
149 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) { 149 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
150 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); 150 reg = iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
151 151
152 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 152 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
153 IWL_DEBUG_INFO(trans, 153 IWL_DEBUG_INFO(trans,
154 "Rx queue requesting wakeup," 154 "Rx queue requesting wakeup,"
155 " GP1 = 0x%x\n", reg); 155 " GP1 = 0x%x\n", reg);
156 iwl_set_bit(priv, CSR_GP_CNTRL, 156 iwl_set_bit(bus(priv), CSR_GP_CNTRL,
157 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 157 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
158 goto exit_unlock; 158 goto exit_unlock;
159 } 159 }
160 160
161 q->write_actual = (q->write & ~0x7); 161 q->write_actual = (q->write & ~0x7);
162 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, 162 iwl_write_direct32(bus(priv), FH_RSCSR_CHNL0_WPTR,
163 q->write_actual); 163 q->write_actual);
164 164
165 /* Else device is assumed to be awake */ 165 /* Else device is assumed to be awake */
166 } else { 166 } else {
167 /* Device expects a multiple of 8 */ 167 /* Device expects a multiple of 8 */
168 q->write_actual = (q->write & ~0x7); 168 q->write_actual = (q->write & ~0x7);
169 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR, 169 iwl_write_direct32(bus(priv), FH_RSCSR_CHNL0_WPTR,
170 q->write_actual); 170 q->write_actual);
171 } 171 }
172 } 172 }
@@ -591,7 +591,7 @@ static void iwl_dump_nic_error_log(struct iwl_trans *trans)
591 return; 591 return;
592 } 592 }
593 593
594 iwl_read_targ_mem_words(priv, base, &table, sizeof(table)); 594 iwl_read_targ_mem_words(bus(priv), base, &table, sizeof(table));
595 595
596 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { 596 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
597 IWL_ERR(trans, "Start IWL Error Log Dump:\n"); 597 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
@@ -637,9 +637,9 @@ static void iwl_irq_handle_error(struct iwl_trans *trans)
637 struct iwl_priv *priv = priv(trans); 637 struct iwl_priv *priv = priv(trans);
638 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */ 638 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
639 if (priv->cfg->internal_wimax_coex && 639 if (priv->cfg->internal_wimax_coex &&
640 (!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) & 640 (!(iwl_read_prph(bus(trans), APMG_CLK_CTRL_REG) &
641 APMS_CLK_VAL_MRB_FUNC_MODE) || 641 APMS_CLK_VAL_MRB_FUNC_MODE) ||
642 (iwl_read_prph(priv, APMG_PS_CTRL_REG) & 642 (iwl_read_prph(bus(trans), APMG_PS_CTRL_REG) &
643 APMG_PS_CTRL_VAL_RESET_REQ))) { 643 APMG_PS_CTRL_VAL_RESET_REQ))) {
644 /* 644 /*
645 * Keep the restart process from trying to send host 645 * Keep the restart process from trying to send host
@@ -706,18 +706,18 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
706 ptr = base + EVENT_START_OFFSET + (start_idx * event_size); 706 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
707 707
708 /* Make sure device is powered up for SRAM reads */ 708 /* Make sure device is powered up for SRAM reads */
709 spin_lock_irqsave(&priv->reg_lock, reg_flags); 709 spin_lock_irqsave(&bus(priv)->reg_lock, reg_flags);
710 iwl_grab_nic_access(priv); 710 iwl_grab_nic_access(bus(priv));
711 711
712 /* Set starting address; reads will auto-increment */ 712 /* Set starting address; reads will auto-increment */
713 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); 713 iwl_write32(bus(priv), HBUS_TARG_MEM_RADDR, ptr);
714 rmb(); 714 rmb();
715 715
716 /* "time" is actually "data" for mode 0 (no timestamp). 716 /* "time" is actually "data" for mode 0 (no timestamp).
717 * place event id # at far right for easier visual parsing. */ 717 * place event id # at far right for easier visual parsing. */
718 for (i = 0; i < num_events; i++) { 718 for (i = 0; i < num_events; i++) {
719 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 719 ev = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
720 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 720 time = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
721 if (mode == 0) { 721 if (mode == 0) {
722 /* data, ev */ 722 /* data, ev */
723 if (bufsz) { 723 if (bufsz) {
@@ -731,7 +731,7 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
731 time, ev); 731 time, ev);
732 } 732 }
733 } else { 733 } else {
734 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 734 data = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
735 if (bufsz) { 735 if (bufsz) {
736 pos += scnprintf(*buf + pos, bufsz - pos, 736 pos += scnprintf(*buf + pos, bufsz - pos,
737 "EVT_LOGT:%010u:0x%08x:%04u\n", 737 "EVT_LOGT:%010u:0x%08x:%04u\n",
@@ -746,8 +746,8 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
746 } 746 }
747 747
748 /* Allow device to power down */ 748 /* Allow device to power down */
749 iwl_release_nic_access(priv); 749 iwl_release_nic_access(bus(priv));
750 spin_unlock_irqrestore(&priv->reg_lock, reg_flags); 750 spin_unlock_irqrestore(&bus(priv)->reg_lock, reg_flags);
751 return pos; 751 return pos;
752} 752}
753 753
@@ -824,10 +824,10 @@ int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
824 } 824 }
825 825
826 /* event log header */ 826 /* event log header */
827 capacity = iwl_read_targ_mem(priv, base); 827 capacity = iwl_read_targ_mem(bus(priv), base);
828 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); 828 mode = iwl_read_targ_mem(bus(priv), base + (1 * sizeof(u32)));
829 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); 829 num_wraps = iwl_read_targ_mem(bus(priv), base + (2 * sizeof(u32)));
830 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); 830 next_entry = iwl_read_targ_mem(bus(priv), base + (3 * sizeof(u32)));
831 831
832 if (capacity > logsize) { 832 if (capacity > logsize) {
833 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d " 833 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
@@ -927,7 +927,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
927 * hardware bugs here by ACKing all the possible interrupts so that 927 * hardware bugs here by ACKing all the possible interrupts so that
928 * interrupt coalescing can still be achieved. 928 * interrupt coalescing can still be achieved.
929 */ 929 */
930 iwl_write32(priv(trans), CSR_INT, 930 iwl_write32(bus(trans), CSR_INT,
931 trans_pcie->inta | ~trans_pcie->inta_mask); 931 trans_pcie->inta | ~trans_pcie->inta_mask);
932 932
933 inta = trans_pcie->inta; 933 inta = trans_pcie->inta;
@@ -935,7 +935,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
935#ifdef CONFIG_IWLWIFI_DEBUG 935#ifdef CONFIG_IWLWIFI_DEBUG
936 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) { 936 if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
937 /* just for debug */ 937 /* just for debug */
938 inta_mask = iwl_read32(priv(trans), CSR_INT_MASK); 938 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK);
939 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ", 939 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
940 inta, inta_mask); 940 inta, inta_mask);
941 } 941 }
@@ -983,7 +983,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
983 /* HW RF KILL switch toggled */ 983 /* HW RF KILL switch toggled */
984 if (inta & CSR_INT_BIT_RF_KILL) { 984 if (inta & CSR_INT_BIT_RF_KILL) {
985 int hw_rf_kill = 0; 985 int hw_rf_kill = 0;
986 if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) & 986 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
987 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 987 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
988 hw_rf_kill = 1; 988 hw_rf_kill = 1;
989 989
@@ -1048,12 +1048,12 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1048 IWL_DEBUG_ISR(trans, "Rx interrupt\n"); 1048 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1049 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 1049 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1050 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1050 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1051 iwl_write32(priv(trans), CSR_FH_INT_STATUS, 1051 iwl_write32(bus(trans), CSR_FH_INT_STATUS,
1052 CSR_FH_INT_RX_MASK); 1052 CSR_FH_INT_RX_MASK);
1053 } 1053 }
1054 if (inta & CSR_INT_BIT_RX_PERIODIC) { 1054 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1055 handled |= CSR_INT_BIT_RX_PERIODIC; 1055 handled |= CSR_INT_BIT_RX_PERIODIC;
1056 iwl_write32(priv(trans), 1056 iwl_write32(bus(trans),
1057 CSR_INT, CSR_INT_BIT_RX_PERIODIC); 1057 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1058 } 1058 }
1059 /* Sending RX interrupt require many steps to be done in the 1059 /* Sending RX interrupt require many steps to be done in the
@@ -1068,7 +1068,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1068 */ 1068 */
1069 1069
1070 /* Disable periodic interrupt; we use it as just a one-shot. */ 1070 /* Disable periodic interrupt; we use it as just a one-shot. */
1071 iwl_write8(priv(trans), CSR_INT_PERIODIC_REG, 1071 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1072 CSR_INT_PERIODIC_DIS); 1072 CSR_INT_PERIODIC_DIS);
1073 iwl_rx_handle(trans); 1073 iwl_rx_handle(trans);
1074 1074
@@ -1080,7 +1080,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1080 * to extend the periodic interrupt; one-shot is enough. 1080 * to extend the periodic interrupt; one-shot is enough.
1081 */ 1081 */
1082 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) 1082 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1083 iwl_write8(priv(trans), CSR_INT_PERIODIC_REG, 1083 iwl_write8(bus(trans), CSR_INT_PERIODIC_REG,
1084 CSR_INT_PERIODIC_ENA); 1084 CSR_INT_PERIODIC_ENA);
1085 1085
1086 isr_stats->rx++; 1086 isr_stats->rx++;
@@ -1088,7 +1088,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
1088 1088
1089 /* This "Tx" DMA channel is used only for loading uCode */ 1089 /* This "Tx" DMA channel is used only for loading uCode */
1090 if (inta & CSR_INT_BIT_FH_TX) { 1090 if (inta & CSR_INT_BIT_FH_TX) {
1091 iwl_write32(priv(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); 1091 iwl_write32(bus(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1092 IWL_DEBUG_ISR(trans, "uCode load interrupt\n"); 1092 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1093 isr_stats->tx++; 1093 isr_stats->tx++;
1094 handled |= CSR_INT_BIT_FH_TX; 1094 handled |= CSR_INT_BIT_FH_TX;
@@ -1216,10 +1216,10 @@ int iwl_reset_ict(struct iwl_trans *trans)
1216 val, 1216 val,
1217 (unsigned long long)trans_pcie->aligned_ict_tbl_dma); 1217 (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
1218 1218
1219 iwl_write32(priv(trans), CSR_DRAM_INT_TBL_REG, val); 1219 iwl_write32(bus(trans), CSR_DRAM_INT_TBL_REG, val);
1220 trans_pcie->use_ict = true; 1220 trans_pcie->use_ict = true;
1221 trans_pcie->ict_index = 0; 1221 trans_pcie->ict_index = 0;
1222 iwl_write32(priv(trans), CSR_INT, trans_pcie->inta_mask); 1222 iwl_write32(bus(trans), CSR_INT, trans_pcie->inta_mask);
1223 iwl_enable_interrupts(trans); 1223 iwl_enable_interrupts(trans);
1224 spin_unlock_irqrestore(&trans->shrd->lock, flags); 1224 spin_unlock_irqrestore(&trans->shrd->lock, flags);
1225 1225
@@ -1259,11 +1259,11 @@ static irqreturn_t iwl_isr(int irq, void *data)
1259 * back-to-back ISRs and sporadic interrupts from our NIC. 1259 * back-to-back ISRs and sporadic interrupts from our NIC.
1260 * If we have something to service, the tasklet will re-enable ints. 1260 * If we have something to service, the tasklet will re-enable ints.
1261 * If we *don't* have something, we'll re-enable before leaving here. */ 1261 * If we *don't* have something, we'll re-enable before leaving here. */
1262 inta_mask = iwl_read32(priv(trans), CSR_INT_MASK); /* just for debug */ 1262 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */
1263 iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000); 1263 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1264 1264
1265 /* Discover which interrupts are active/pending */ 1265 /* Discover which interrupts are active/pending */
1266 inta = iwl_read32(priv(trans), CSR_INT); 1266 inta = iwl_read32(bus(trans), CSR_INT);
1267 1267
1268 /* Ignore interrupt if there's nothing in NIC to service. 1268 /* Ignore interrupt if there's nothing in NIC to service.
1269 * This may be due to IRQ shared with another device, 1269 * This may be due to IRQ shared with another device,
@@ -1282,7 +1282,7 @@ static irqreturn_t iwl_isr(int irq, void *data)
1282 1282
1283#ifdef CONFIG_IWLWIFI_DEBUG 1283#ifdef CONFIG_IWLWIFI_DEBUG
1284 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) { 1284 if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
1285 inta_fh = iwl_read32(priv(trans), CSR_FH_INT_STATUS); 1285 inta_fh = iwl_read32(bus(trans), CSR_FH_INT_STATUS);
1286 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, " 1286 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1287 "fh 0x%08x\n", inta, inta_mask, inta_fh); 1287 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1288 } 1288 }
@@ -1345,8 +1345,8 @@ irqreturn_t iwl_isr_ict(int irq, void *data)
1345 * If we have something to service, the tasklet will re-enable ints. 1345 * If we have something to service, the tasklet will re-enable ints.
1346 * If we *don't* have something, we'll re-enable before leaving here. 1346 * If we *don't* have something, we'll re-enable before leaving here.
1347 */ 1347 */
1348 inta_mask = iwl_read32(priv(trans), CSR_INT_MASK); /* just for debug */ 1348 inta_mask = iwl_read32(bus(trans), CSR_INT_MASK); /* just for debug */
1349 iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000); 1349 iwl_write32(bus(trans), CSR_INT_MASK, 0x00000000);
1350 1350
1351 1351
1352 /* Ignore interrupt if there's nothing in NIC to service. 1352 /* Ignore interrupt if there's nothing in NIC to service.
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
index 835e3edb9cce..3105409bd3cc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
@@ -96,7 +96,7 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
96 96
97 if (priv->cfg->base_params->shadow_reg_enable) { 97 if (priv->cfg->base_params->shadow_reg_enable) {
98 /* shadow register enabled */ 98 /* shadow register enabled */
99 iwl_write32(priv, HBUS_TARG_WRPTR, 99 iwl_write32(bus(priv), HBUS_TARG_WRPTR,
100 txq->q.write_ptr | (txq_id << 8)); 100 txq->q.write_ptr | (txq_id << 8));
101 } else { 101 } else {
102 /* if we're trying to save power */ 102 /* if we're trying to save power */
@@ -104,18 +104,18 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
104 /* wake up nic if it's powered down ... 104 /* wake up nic if it's powered down ...
105 * uCode will wake up, and interrupt us again, so next 105 * uCode will wake up, and interrupt us again, so next
106 * time we'll skip this part. */ 106 * time we'll skip this part. */
107 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1); 107 reg = iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
108 108
109 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 109 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
110 IWL_DEBUG_INFO(priv, 110 IWL_DEBUG_INFO(priv,
111 "Tx queue %d requesting wakeup," 111 "Tx queue %d requesting wakeup,"
112 " GP1 = 0x%x\n", txq_id, reg); 112 " GP1 = 0x%x\n", txq_id, reg);
113 iwl_set_bit(priv, CSR_GP_CNTRL, 113 iwl_set_bit(bus(priv), CSR_GP_CNTRL,
114 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 114 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
115 return; 115 return;
116 } 116 }
117 117
118 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 118 iwl_write_direct32(bus(priv), HBUS_TARG_WRPTR,
119 txq->q.write_ptr | (txq_id << 8)); 119 txq->q.write_ptr | (txq_id << 8));
120 120
121 /* 121 /*
@@ -124,7 +124,7 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
124 * trying to tx (during RFKILL, we're not trying to tx). 124 * trying to tx (during RFKILL, we're not trying to tx).
125 */ 125 */
126 } else 126 } else
127 iwl_write32(priv, HBUS_TARG_WRPTR, 127 iwl_write32(bus(priv), HBUS_TARG_WRPTR,
128 txq->q.write_ptr | (txq_id << 8)); 128 txq->q.write_ptr | (txq_id << 8));
129 } 129 }
130 txq->need_update = 0; 130 txq->need_update = 0;
@@ -374,14 +374,14 @@ static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
374 tbl_dw_addr = trans_pcie->scd_base_addr + 374 tbl_dw_addr = trans_pcie->scd_base_addr +
375 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 375 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
376 376
377 tbl_dw = iwl_read_targ_mem(priv(trans), tbl_dw_addr); 377 tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
378 378
379 if (txq_id & 0x1) 379 if (txq_id & 0x1)
380 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 380 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
381 else 381 else
382 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 382 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
383 383
384 iwl_write_targ_mem(priv(trans), tbl_dw_addr, tbl_dw); 384 iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
385 385
386 return 0; 386 return 0;
387} 387}
@@ -390,7 +390,7 @@ static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
390{ 390{
391 /* Simply stop the queue, but don't change any configuration; 391 /* Simply stop the queue, but don't change any configuration;
392 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 392 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
393 iwl_write_prph(priv(trans), 393 iwl_write_prph(bus(trans),
394 SCD_QUEUE_STATUS_BITS(txq_id), 394 SCD_QUEUE_STATUS_BITS(txq_id),
395 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| 395 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
396 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 396 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
@@ -399,9 +399,9 @@ static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
399void iwl_trans_set_wr_ptrs(struct iwl_trans *trans, 399void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
400 int txq_id, u32 index) 400 int txq_id, u32 index)
401{ 401{
402 iwl_write_direct32(priv(trans), HBUS_TARG_WRPTR, 402 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
403 (index & 0xff) | (txq_id << 8)); 403 (index & 0xff) | (txq_id << 8));
404 iwl_write_prph(priv(trans), SCD_QUEUE_RDPTR(txq_id), index); 404 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
405} 405}
406 406
407void iwl_trans_tx_queue_set_status(struct iwl_priv *priv, 407void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
@@ -411,7 +411,7 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
411 int txq_id = txq->q.id; 411 int txq_id = txq->q.id;
412 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; 412 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
413 413
414 iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id), 414 iwl_write_prph(bus(priv), SCD_QUEUE_STATUS_BITS(txq_id),
415 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 415 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
416 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | 416 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
417 (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 417 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
@@ -459,10 +459,10 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
459 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id); 459 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
460 460
461 /* Set this queue as a chain-building queue */ 461 /* Set this queue as a chain-building queue */
462 iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id)); 462 iwl_set_bits_prph(bus(priv), SCD_QUEUECHAIN_SEL, (1<<txq_id));
463 463
464 /* enable aggregations for the queue */ 464 /* enable aggregations for the queue */
465 iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id)); 465 iwl_set_bits_prph(bus(priv), SCD_AGGR_SEL, (1<<txq_id));
466 466
467 /* Place first TFD at index corresponding to start sequence number. 467 /* Place first TFD at index corresponding to start sequence number.
468 * Assumes that ssn_idx is valid (!= 0xFFF) */ 468 * Assumes that ssn_idx is valid (!= 0xFFF) */
@@ -471,7 +471,7 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
471 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx); 471 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
472 472
473 /* Set up Tx window size and frame limit for this queue */ 473 /* Set up Tx window size and frame limit for this queue */
474 iwl_write_targ_mem(priv, trans_pcie->scd_base_addr + 474 iwl_write_targ_mem(bus(priv), trans_pcie->scd_base_addr +
475 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + 475 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
476 sizeof(u32), 476 sizeof(u32),
477 ((frame_limit << 477 ((frame_limit <<
@@ -481,7 +481,7 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
481 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 481 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
482 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 482 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
483 483
484 iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); 484 iwl_set_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
485 485
486 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 486 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
487 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 487 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
@@ -509,14 +509,14 @@ int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
509 509
510 iwlagn_tx_queue_stop_scheduler(trans, txq_id); 510 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
511 511
512 iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id)); 512 iwl_clear_bits_prph(bus(priv), SCD_AGGR_SEL, (1 << txq_id));
513 513
514 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 514 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
515 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 515 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
516 /* supposes that ssn_idx is valid (!= 0xFFF) */ 516 /* supposes that ssn_idx is valid (!= 0xFFF) */
517 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx); 517 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
518 518
519 iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); 519 iwl_clear_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
520 iwl_txq_ctx_deactivate(priv, txq_id); 520 iwl_txq_ctx_deactivate(priv, txq_id);
521 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 521 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
522 522
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.c b/drivers/net/wireless/iwlwifi/iwl-trans.c
index 95c9e8794839..b95e71389b7c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-trans.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans.c
@@ -144,6 +144,7 @@ static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
144 u32 rb_size; 144 u32 rb_size;
145 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 145 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
146 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */ 146 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
147 struct iwl_trans *trans = trans(priv);
147 148
148 rb_timeout = RX_RB_TIMEOUT; 149 rb_timeout = RX_RB_TIMEOUT;
149 150
@@ -153,17 +154,17 @@ static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
153 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 154 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
154 155
155 /* Stop Rx DMA */ 156 /* Stop Rx DMA */
156 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 157 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
157 158
158 /* Reset driver's Rx queue write index */ 159 /* Reset driver's Rx queue write index */
159 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 160 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
160 161
161 /* Tell device where to find RBD circular buffer in DRAM */ 162 /* Tell device where to find RBD circular buffer in DRAM */
162 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 163 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_RBDCB_BASE_REG,
163 (u32)(rxq->bd_dma >> 8)); 164 (u32)(rxq->bd_dma >> 8));
164 165
165 /* Tell device where in DRAM to update its Rx status */ 166 /* Tell device where in DRAM to update its Rx status */
166 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, 167 iwl_write_direct32(bus(trans), FH_RSCSR_CHNL0_STTS_WPTR_REG,
167 rxq->rb_stts_dma >> 4); 168 rxq->rb_stts_dma >> 4);
168 169
169 /* Enable Rx DMA 170 /* Enable Rx DMA
@@ -174,7 +175,7 @@ static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
174 * RB timeout 0x10 175 * RB timeout 0x10
175 * 256 RBDs 176 * 256 RBDs
176 */ 177 */
177 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 178 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG,
178 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 179 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
179 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 180 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
180 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 181 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
@@ -184,7 +185,7 @@ static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
184 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 185 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
185 186
186 /* Set interrupt coalescing timer to default (2048 usecs) */ 187 /* Set interrupt coalescing timer to default (2048 usecs) */
187 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 188 iwl_write8(bus(trans), CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
188} 189}
189 190
190static int iwl_rx_init(struct iwl_trans *trans) 191static int iwl_rx_init(struct iwl_trans *trans)
@@ -268,8 +269,8 @@ static int iwl_trans_rx_stop(struct iwl_trans *trans)
268{ 269{
269 270
270 /* stop Rx DMA */ 271 /* stop Rx DMA */
271 iwl_write_direct32(priv(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 272 iwl_write_direct32(bus(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
272 return iwl_poll_direct_bit(priv(trans), FH_MEM_RSSR_RX_STATUS_REG, 273 return iwl_poll_direct_bit(bus(trans), FH_MEM_RSSR_RX_STATUS_REG,
273 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 274 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
274} 275}
275 276
@@ -397,7 +398,7 @@ static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
397 * Tell nic where to find circular buffer of Tx Frame Descriptors for 398 * Tell nic where to find circular buffer of Tx Frame Descriptors for
398 * given Tx queue, and enable the DMA channel used for that queue. 399 * given Tx queue, and enable the DMA channel used for that queue.
399 * Circular buffer (TFD queue in DRAM) physical base address */ 400 * Circular buffer (TFD queue in DRAM) physical base address */
400 iwl_write_direct32(priv(trans), FH_MEM_CBBC_QUEUE(txq_id), 401 iwl_write_direct32(bus(trans), FH_MEM_CBBC_QUEUE(txq_id),
401 txq->q.dma_addr >> 8); 402 txq->q.dma_addr >> 8);
402 403
403 return 0; 404 return 0;
@@ -579,10 +580,11 @@ static int iwl_tx_init(struct iwl_trans *trans)
579 spin_lock_irqsave(&trans->shrd->lock, flags); 580 spin_lock_irqsave(&trans->shrd->lock, flags);
580 581
581 /* Turn off all Tx DMA fifos */ 582 /* Turn off all Tx DMA fifos */
582 iwl_write_prph(priv, SCD_TXFACT, 0); 583 iwl_write_prph(bus(trans), SCD_TXFACT, 0);
583 584
584 /* Tell NIC where to find the "keep warm" buffer */ 585 /* Tell NIC where to find the "keep warm" buffer */
585 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, trans_pcie->kw.dma >> 4); 586 iwl_write_direct32(bus(trans), FH_KW_MEM_ADDR_REG,
587 trans_pcie->kw.dma >> 4);
586 588
587 spin_unlock_irqrestore(&trans->shrd->lock, flags); 589 spin_unlock_irqrestore(&trans->shrd->lock, flags);
588 590
@@ -608,17 +610,18 @@ error:
608 610
609static void iwl_set_pwr_vmain(struct iwl_priv *priv) 611static void iwl_set_pwr_vmain(struct iwl_priv *priv)
610{ 612{
613 struct iwl_trans *trans = trans(priv);
611/* 614/*
612 * (for documentation purposes) 615 * (for documentation purposes)
613 * to set power to V_AUX, do: 616 * to set power to V_AUX, do:
614 617
615 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) 618 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
616 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 619 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
617 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 620 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
618 ~APMG_PS_CTRL_MSK_PWR_SRC); 621 ~APMG_PS_CTRL_MSK_PWR_SRC);
619 */ 622 */
620 623
621 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 624 iwl_set_bits_mask_prph(bus(trans), APMG_PS_CTRL_REG,
622 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 625 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
623 ~APMG_PS_CTRL_MSK_PWR_SRC); 626 ~APMG_PS_CTRL_MSK_PWR_SRC);
624} 627}
@@ -633,7 +636,8 @@ static int iwl_nic_init(struct iwl_trans *trans)
633 iwl_apm_init(priv); 636 iwl_apm_init(priv);
634 637
635 /* Set interrupt coalescing calibration timer to default (512 usecs) */ 638 /* Set interrupt coalescing calibration timer to default (512 usecs) */
636 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); 639 iwl_write8(bus(trans), CSR_INT_COALESCING,
640 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
637 641
638 spin_unlock_irqrestore(&trans->shrd->lock, flags); 642 spin_unlock_irqrestore(&trans->shrd->lock, flags);
639 643
@@ -650,7 +654,7 @@ static int iwl_nic_init(struct iwl_trans *trans)
650 654
651 if (priv->cfg->base_params->shadow_reg_enable) { 655 if (priv->cfg->base_params->shadow_reg_enable) {
652 /* enable shadow regs in HW */ 656 /* enable shadow regs in HW */
653 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL, 657 iwl_set_bit(bus(trans), CSR_MAC_SHADOW_REG_CTRL,
654 0x800FFFFF); 658 0x800FFFFF);
655 } 659 }
656 660
@@ -666,11 +670,11 @@ static int iwl_set_hw_ready(struct iwl_trans *trans)
666{ 670{
667 int ret; 671 int ret;
668 672
669 iwl_set_bit(priv(trans), CSR_HW_IF_CONFIG_REG, 673 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
670 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 674 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
671 675
672 /* See if we got it */ 676 /* See if we got it */
673 ret = iwl_poll_bit(priv(trans), CSR_HW_IF_CONFIG_REG, 677 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
674 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 678 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
675 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 679 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
676 HW_READY_TIMEOUT); 680 HW_READY_TIMEOUT);
@@ -691,10 +695,10 @@ static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
691 return 0; 695 return 0;
692 696
693 /* If HW is not ready, prepare the conditions to check again */ 697 /* If HW is not ready, prepare the conditions to check again */
694 iwl_set_bit(priv(trans), CSR_HW_IF_CONFIG_REG, 698 iwl_set_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
695 CSR_HW_IF_CONFIG_REG_PREPARE); 699 CSR_HW_IF_CONFIG_REG_PREPARE);
696 700
697 ret = iwl_poll_bit(priv(trans), CSR_HW_IF_CONFIG_REG, 701 ret = iwl_poll_bit(bus(trans), CSR_HW_IF_CONFIG_REG,
698 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 702 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
699 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); 703 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
700 704
@@ -722,7 +726,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
722 } 726 }
723 727
724 /* If platform's RF_KILL switch is NOT set to KILL */ 728 /* If platform's RF_KILL switch is NOT set to KILL */
725 if (iwl_read32(priv, CSR_GP_CNTRL) & 729 if (iwl_read32(bus(trans), CSR_GP_CNTRL) &
726 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 730 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
727 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status); 731 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
728 else 732 else
@@ -734,7 +738,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
734 return -ERFKILL; 738 return -ERFKILL;
735 } 739 }
736 740
737 iwl_write32(priv, CSR_INT, 0xFFFFFFFF); 741 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
738 742
739 ret = iwl_nic_init(trans); 743 ret = iwl_nic_init(trans);
740 if (ret) { 744 if (ret) {
@@ -743,17 +747,17 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
743 } 747 }
744 748
745 /* make sure rfkill handshake bits are cleared */ 749 /* make sure rfkill handshake bits are cleared */
746 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 750 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
747 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 751 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR,
748 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 752 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
749 753
750 /* clear (again), then enable host interrupts */ 754 /* clear (again), then enable host interrupts */
751 iwl_write32(priv, CSR_INT, 0xFFFFFFFF); 755 iwl_write32(bus(trans), CSR_INT, 0xFFFFFFFF);
752 iwl_enable_interrupts(trans); 756 iwl_enable_interrupts(trans);
753 757
754 /* really make sure rfkill handshake bits are cleared */ 758 /* really make sure rfkill handshake bits are cleared */
755 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 759 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
756 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 760 iwl_write32(bus(trans), CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
757 761
758 return 0; 762 return 0;
759} 763}
@@ -764,7 +768,7 @@ static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
764 */ 768 */
765static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask) 769static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
766{ 770{
767 iwl_write_prph(priv(trans), SCD_TXFACT, mask); 771 iwl_write_prph(bus(trans), SCD_TXFACT, mask);
768} 772}
769 773
770#define IWL_AC_UNSET -1 774#define IWL_AC_UNSET -1
@@ -814,46 +818,47 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
814 818
815 spin_lock_irqsave(&trans->shrd->lock, flags); 819 spin_lock_irqsave(&trans->shrd->lock, flags);
816 820
817 trans_pcie->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR); 821 trans_pcie->scd_base_addr =
822 iwl_read_prph(bus(trans), SCD_SRAM_BASE_ADDR);
818 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND; 823 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
819 /* reset conext data memory */ 824 /* reset conext data memory */
820 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; 825 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
821 a += 4) 826 a += 4)
822 iwl_write_targ_mem(priv, a, 0); 827 iwl_write_targ_mem(bus(trans), a, 0);
823 /* reset tx status memory */ 828 /* reset tx status memory */
824 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; 829 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
825 a += 4) 830 a += 4)
826 iwl_write_targ_mem(priv, a, 0); 831 iwl_write_targ_mem(bus(trans), a, 0);
827 for (; a < trans_pcie->scd_base_addr + 832 for (; a < trans_pcie->scd_base_addr +
828 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num); 833 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
829 a += 4) 834 a += 4)
830 iwl_write_targ_mem(priv, a, 0); 835 iwl_write_targ_mem(bus(trans), a, 0);
831 836
832 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR, 837 iwl_write_prph(bus(trans), SCD_DRAM_BASE_ADDR,
833 trans_pcie->scd_bc_tbls.dma >> 10); 838 trans_pcie->scd_bc_tbls.dma >> 10);
834 839
835 /* Enable DMA channel */ 840 /* Enable DMA channel */
836 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++) 841 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
837 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 842 iwl_write_direct32(bus(trans), FH_TCSR_CHNL_TX_CONFIG_REG(chan),
838 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 843 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
839 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 844 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
840 845
841 /* Update FH chicken bits */ 846 /* Update FH chicken bits */
842 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); 847 reg_val = iwl_read_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG);
843 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, 848 iwl_write_direct32(bus(trans), FH_TX_CHICKEN_BITS_REG,
844 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 849 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
845 850
846 iwl_write_prph(priv, SCD_QUEUECHAIN_SEL, 851 iwl_write_prph(bus(trans), SCD_QUEUECHAIN_SEL,
847 SCD_QUEUECHAIN_SEL_ALL(priv)); 852 SCD_QUEUECHAIN_SEL_ALL(priv));
848 iwl_write_prph(priv, SCD_AGGR_SEL, 0); 853 iwl_write_prph(bus(trans), SCD_AGGR_SEL, 0);
849 854
850 /* initiate the queues */ 855 /* initiate the queues */
851 for (i = 0; i < hw_params(priv).max_txq_num; i++) { 856 for (i = 0; i < hw_params(priv).max_txq_num; i++) {
852 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0); 857 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(i), 0);
853 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 858 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR, 0 | (i << 8));
854 iwl_write_targ_mem(priv, trans_pcie->scd_base_addr + 859 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
855 SCD_CONTEXT_QUEUE_OFFSET(i), 0); 860 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
856 iwl_write_targ_mem(priv, trans_pcie->scd_base_addr + 861 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
857 SCD_CONTEXT_QUEUE_OFFSET(i) + 862 SCD_CONTEXT_QUEUE_OFFSET(i) +
858 sizeof(u32), 863 sizeof(u32),
859 ((SCD_WIN_SIZE << 864 ((SCD_WIN_SIZE <<
@@ -864,7 +869,7 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
864 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 869 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
865 } 870 }
866 871
867 iwl_write_prph(priv, SCD_INTERRUPT_MASK, 872 iwl_write_prph(bus(trans), SCD_INTERRUPT_MASK,
868 IWL_MASK(0, hw_params(trans).max_txq_num)); 873 IWL_MASK(0, hw_params(trans).max_txq_num));
869 874
870 /* Activate all Tx DMA/FIFO channels */ 875 /* Activate all Tx DMA/FIFO channels */
@@ -910,7 +915,7 @@ static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
910 spin_unlock_irqrestore(&trans->shrd->lock, flags); 915 spin_unlock_irqrestore(&trans->shrd->lock, flags);
911 916
912 /* Enable L1-Active */ 917 /* Enable L1-Active */
913 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG, 918 iwl_clear_bits_prph(bus(trans), APMG_PCIDEV_STT_REG,
914 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 919 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
915} 920}
916 921
@@ -930,14 +935,14 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
930 935
931 /* Stop each Tx DMA channel, and wait for it to be idle */ 936 /* Stop each Tx DMA channel, and wait for it to be idle */
932 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 937 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
933 iwl_write_direct32(priv(trans), 938 iwl_write_direct32(bus(trans),
934 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 939 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
935 if (iwl_poll_direct_bit(priv(trans), FH_TSSR_TX_STATUS_REG, 940 if (iwl_poll_direct_bit(bus(trans), FH_TSSR_TX_STATUS_REG,
936 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 941 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
937 1000)) 942 1000))
938 IWL_ERR(trans, "Failing on timeout while stopping" 943 IWL_ERR(trans, "Failing on timeout while stopping"
939 " DMA channel %d [0x%08x]", ch, 944 " DMA channel %d [0x%08x]", ch,
940 iwl_read_direct32(priv(trans), 945 iwl_read_direct32(bus(trans),
941 FH_TSSR_TX_STATUS_REG)); 946 FH_TSSR_TX_STATUS_REG));
942 } 947 }
943 spin_unlock_irqrestore(&trans->shrd->lock, flags); 948 spin_unlock_irqrestore(&trans->shrd->lock, flags);
@@ -957,7 +962,7 @@ static int iwl_trans_tx_stop(struct iwl_trans *trans)
957static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 962static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
958{ 963{
959 /* stop and reset the on-board processor */ 964 /* stop and reset the on-board processor */
960 iwl_write32(priv(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 965 iwl_write32(bus(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
961 966
962 /* tell the device to stop sending interrupts */ 967 /* tell the device to stop sending interrupts */
963 iwl_trans_disable_sync_irq(trans); 968 iwl_trans_disable_sync_irq(trans);
@@ -977,13 +982,13 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
977 iwl_trans_rx_stop(trans); 982 iwl_trans_rx_stop(trans);
978 983
979 /* Power-down device's busmaster DMA clocks */ 984 /* Power-down device's busmaster DMA clocks */
980 iwl_write_prph(priv(trans), APMG_CLK_DIS_REG, 985 iwl_write_prph(bus(trans), APMG_CLK_DIS_REG,
981 APMG_CLK_VAL_DMA_CLK_RQT); 986 APMG_CLK_VAL_DMA_CLK_RQT);
982 udelay(5); 987 udelay(5);
983 } 988 }
984 989
985 /* Make sure (redundant) we've released our request to stay awake */ 990 /* Make sure (redundant) we've released our request to stay awake */
986 iwl_clear_bit(priv(trans), CSR_GP_CNTRL, 991 iwl_clear_bit(bus(trans), CSR_GP_CNTRL,
987 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 992 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
988 993
989 /* Stop the device, and put it in low power state */ 994 /* Stop the device, and put it in low power state */
@@ -1148,7 +1153,7 @@ static int iwl_trans_pcie_tx(struct iwl_priv *priv, struct sk_buff *skb,
1148static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans) 1153static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
1149{ 1154{
1150 /* Remove all resets to allow NIC to operate */ 1155 /* Remove all resets to allow NIC to operate */
1151 iwl_write32(priv(trans), CSR_RESET, 0); 1156 iwl_write32(bus(trans), CSR_RESET, 0);
1152} 1157}
1153 1158
1154static int iwl_trans_pcie_request_irq(struct iwl_trans *trans) 1159static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
@@ -1253,7 +1258,7 @@ static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1253 1258
1254 iwl_enable_interrupts(trans); 1259 iwl_enable_interrupts(trans);
1255 1260
1256 if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) & 1261 if (!(iwl_read32(bus(trans), CSR_GP_CNTRL) &
1257 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 1262 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1258 hw_rfkill = true; 1263 hw_rfkill = true;
1259 1264
@@ -1712,7 +1717,7 @@ void iwl_dump_csr(struct iwl_trans *trans)
1712 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 1717 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1713 IWL_ERR(trans, " %25s: 0X%08x\n", 1718 IWL_ERR(trans, " %25s: 0X%08x\n",
1714 get_csr_string(csr_tbl[i]), 1719 get_csr_string(csr_tbl[i]),
1715 iwl_read32(priv(trans), csr_tbl[i])); 1720 iwl_read32(bus(trans), csr_tbl[i]));
1716 } 1721 }
1717} 1722}
1718 1723
@@ -1784,7 +1789,7 @@ int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1784 pos += scnprintf(*buf + pos, bufsz - pos, 1789 pos += scnprintf(*buf + pos, bufsz - pos,
1785 " %34s: 0X%08x\n", 1790 " %34s: 0X%08x\n",
1786 get_fh_string(fh_tbl[i]), 1791 get_fh_string(fh_tbl[i]),
1787 iwl_read_direct32(priv(trans), fh_tbl[i])); 1792 iwl_read_direct32(bus(trans), fh_tbl[i]));
1788 } 1793 }
1789 return pos; 1794 return pos;
1790 } 1795 }
@@ -1793,7 +1798,7 @@ int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1793 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1798 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1794 IWL_ERR(trans, " %34s: 0X%08x\n", 1799 IWL_ERR(trans, " %34s: 0X%08x\n",
1795 get_fh_string(fh_tbl[i]), 1800 get_fh_string(fh_tbl[i]),
1796 iwl_read_direct32(priv(trans), fh_tbl[i])); 1801 iwl_read_direct32(bus(trans), fh_tbl[i]));
1797 } 1802 }
1798 return 0; 1803 return 0;
1799} 1804}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 08:29:32 -0400