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authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>2014-09-23 16:02:41 -0400
committerEmmanuel Grumbach <emmanuel.grumbach@intel.com>2014-10-23 14:21:47 -0400
commit9180ac50716a097a407c6d7e7e4589754a922260 (patch)
tree175305c65dceb1e32571d9aaf33d60303b985682 /drivers/net/wireless/iwlwifi/pcie/trans.c
parent35a9ad8af0bb0fa3525e6d0d20e32551d226f38e (diff)
iwlwifi: configure the LTR
The LTR is the handshake between the device and the root complex about the latency allowed when the bus exits power save. This configuration was missing and this led to high latency in the link power up. The end user could experience high latency in the network because of this. Cc: <stable@vger.kernel.org> [3.10+] Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/pcie/trans.c')
-rw-r--r--drivers/net/wireless/iwlwifi/pcie/trans.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 1393bac0025c..c706dba67cdd 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -174,6 +174,7 @@ static void iwl_pcie_apm_config(struct iwl_trans *trans)
174{ 174{
175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
176 u16 lctl; 176 u16 lctl;
177 u16 cap;
177 178
178 /* 179 /*
179 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 180 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
@@ -184,16 +185,17 @@ static void iwl_pcie_apm_config(struct iwl_trans *trans)
184 * power savings, even without L1. 185 * power savings, even without L1.
185 */ 186 */
186 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 187 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
187 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { 188 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
188 /* L1-ASPM enabled; disable(!) L0S */
189 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 189 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
190 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); 190 else
191 } else {
192 /* L1-ASPM disabled; enable(!) L0S */
193 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 191 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
194 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
195 }
196 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 192 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
193
194 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
195 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
196 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
197 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
198 trans->ltr_enabled ? "En" : "Dis");
197} 199}
198 200
199/* 201/*