iwlwifi: enable communication with WoWLAN firmware

On resuming, the opmode may have to be able to talk
to the WoWLAN/D3 firmware in order to query it about
its status and wakeup reasons. To do that, the opmode
has to call the new d3_resume() transport API which
will set up the device for command communcation.

Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>

1 files changed, 74 insertions, 17 deletions

diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 4028c03eff5f..59340ff13a64 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -75,21 +75,16 @@
 #include "iwl-agn-hw.h"
 #include "internal.h"
 
-static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
+static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 {
-/*
- * (for documentation purposes)
- * to set power to V_AUX, do:
-
-                if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
-                        iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
-                                               APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
-                                               ~APMG_PS_CTRL_MSK_PWR_SRC);
- */
-
-        iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
-                               APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
-                               ~APMG_PS_CTRL_MSK_PWR_SRC);
+        if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
+                iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
+                                       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
+                                       ~APMG_PS_CTRL_MSK_PWR_SRC);
+        else
+                iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
+                                       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
+                                       ~APMG_PS_CTRL_MSK_PWR_SRC);
 }
 
 /* PCI registers */
@@ -259,7 +254,7 @@ static int iwl_pcie_nic_init(struct iwl_trans *trans)
 
         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 
-        iwl_pcie_set_pwr_vmain(trans);
+        iwl_pcie_set_pwr(trans, false);
 
         iwl_op_mode_nic_config(trans->op_mode);
 
@@ -545,15 +540,76 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 }
 
-static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
+static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans)
 {
         /* let the ucode operate on its own */
         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 
         iwl_disable_interrupts(trans);
+        iwl_pcie_disable_ict(trans);
+
         iwl_clear_bit(trans, CSR_GP_CNTRL,
                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+        iwl_clear_bit(trans, CSR_GP_CNTRL,
+                      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+
+        /*
+         * reset TX queues -- some of their registers reset during S3
+         * so if we don't reset everything here the D3 image would try
+         * to execute some invalid memory upon resume
+         */
+        iwl_trans_pcie_tx_reset(trans);
+
+        iwl_pcie_set_pwr(trans, true);
+}
+
+static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
+                                    enum iwl_d3_status *status)
+{
+        u32 val;
+        int ret;
+
+        iwl_pcie_set_pwr(trans, false);
+
+        val = iwl_read32(trans, CSR_RESET);
+        if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
+                *status = IWL_D3_STATUS_RESET;
+                return 0;
+        }
+
+        /*
+         * Also enables interrupts - none will happen as the device doesn't
+         * know we're waking it up, only when the opmode actually tells it
+         * after this call.
+         */
+        iwl_pcie_reset_ict(trans);
+
+        iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+        iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+
+        ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
+                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
+                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
+                           25000);
+        if (ret) {
+                IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
+                return ret;
+        }
+
+        iwl_trans_pcie_tx_reset(trans);
+
+        ret = iwl_pcie_rx_init(trans);
+        if (ret) {
+                IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
+                return ret;
+        }
+
+        iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
+                    CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
+
+        *status = IWL_D3_STATUS_ALIVE;
+        return 0;
 }
 
 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
@@ -1279,7 +1335,8 @@ static const struct iwl_trans_ops trans_ops_pcie = {
         .start_fw = iwl_trans_pcie_start_fw,
         .stop_device = iwl_trans_pcie_stop_device,
 
-        .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
+        .d3_suspend = iwl_trans_pcie_d3_suspend,
+        .d3_resume = iwl_trans_pcie_d3_resume,
 
         .send_cmd = iwl_trans_pcie_send_hcmd,