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authorBen Cahill <ben.m.cahill@intel.com>2007-11-28 22:10:07 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:05:31 -0500
commite3851447664113bccf9b23af0308e266872a735c (patch)
treee6e5b41c7981c99224f980bf86c04f029bc33032 /drivers/net/wireless/iwlwifi/iwl-prph.h
parent5d5456fe50cb07347dd350fc045dc98677dbc58f (diff)
iwlwifi: document 4965 Tx scheduler
Document 4965 Tx scheduler Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-prph.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-prph.h14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index 137947dd269f..4ba121634877 100644
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -63,7 +63,10 @@
63#ifndef __iwl_prph_h__ 63#ifndef __iwl_prph_h__
64#define __iwl_prph_h__ 64#define __iwl_prph_h__
65 65
66 66/*
67 * Registers in this file are internal, not PCI bus memory mapped.
68 * Driver accesses these via HBUS_TARG_PRPH_* registers.
69 */
67#define PRPH_BASE (0x00000) 70#define PRPH_BASE (0x00000)
68#define PRPH_END (0xFFFFF) 71#define PRPH_END (0xFFFFF)
69 72
@@ -225,8 +228,8 @@
225#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800) 228#define BSM_SRAM_LOWER_BOUND (PRPH_BASE + 0x3800)
226#define BSM_SRAM_SIZE (1024) /* bytes */ 229#define BSM_SRAM_SIZE (1024) /* bytes */
227 230
228/* ALM SCD */ 231
229/* SCD (Scheduler) */ 232/* 3945 Tx scheduler registers */
230#define ALM_SCD_BASE (PRPH_BASE + 0x2E00) 233#define ALM_SCD_BASE (PRPH_BASE + 0x2E00)
231#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000) 234#define ALM_SCD_MODE_REG (ALM_SCD_BASE + 0x000)
232#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004) 235#define ALM_SCD_ARASTAT_REG (ALM_SCD_BASE + 0x004)
@@ -236,7 +239,10 @@
236#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C) 239#define ALM_SCD_SBYP_MODE_1_REG (ALM_SCD_BASE + 0x02C)
237#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030) 240#define ALM_SCD_SBYP_MODE_2_REG (ALM_SCD_BASE + 0x030)
238 241
239/* 4965 SCD memory mapped registers */ 242/*
243 * 4965 Tx Scheduler registers.
244 * Details are documented in iwl-4965-hw.h
245 */
240#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00) 246#define KDR_SCD_BASE (PRPH_BASE + 0xa02c00)
241 247
242#define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0) 248#define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0)