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authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>2011-08-26 02:11:14 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-08-29 15:30:29 -0400
commit83ed90155f98bd949735c2cc22d832b557a6d7d1 (patch)
tree795ecd1ebd93357a80895825310c19315a633e49 /drivers/net/wireless/iwlwifi/iwl-io.c
parenta72b8b088c3465b28192c1a14ba97be8223a8cec (diff)
iwlagn: all function iwl-io.c receive iwl_bus
Which means that iwl-io.c doesn't need to include iwl-dev.h any more. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-io.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.c192
1 files changed, 98 insertions, 94 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.c b/drivers/net/wireless/iwlwifi/iwl-io.c
index aa4a90674452..3ffa8e62b856 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.c
+++ b/drivers/net/wireless/iwlwifi/iwl-io.c
@@ -25,46 +25,50 @@
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 * 26 *
27 *****************************************************************************/ 27 *****************************************************************************/
28#include <linux/delay.h>
29#include <linux/device.h>
28 30
29#include "iwl-io.h" 31#include "iwl-io.h"
32#include"iwl-csr.h"
33#include "iwl-debug.h"
30 34
31#define IWL_POLL_INTERVAL 10 /* microseconds */ 35#define IWL_POLL_INTERVAL 10 /* microseconds */
32 36
33static inline void __iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) 37static inline void __iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask)
34{ 38{
35 iwl_write32(priv, reg, iwl_read32(priv, reg) | mask); 39 iwl_write32(bus, reg, iwl_read32(bus, reg) | mask);
36} 40}
37 41
38static inline void __iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) 42static inline void __iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask)
39{ 43{
40 iwl_write32(priv, reg, iwl_read32(priv, reg) & ~mask); 44 iwl_write32(bus, reg, iwl_read32(bus, reg) & ~mask);
41} 45}
42 46
43void iwl_set_bit(struct iwl_priv *priv, u32 reg, u32 mask) 47void iwl_set_bit(struct iwl_bus *bus, u32 reg, u32 mask)
44{ 48{
45 unsigned long flags; 49 unsigned long flags;
46 50
47 spin_lock_irqsave(&priv->reg_lock, flags); 51 spin_lock_irqsave(&bus->reg_lock, flags);
48 __iwl_set_bit(priv, reg, mask); 52 __iwl_set_bit(bus, reg, mask);
49 spin_unlock_irqrestore(&priv->reg_lock, flags); 53 spin_unlock_irqrestore(&bus->reg_lock, flags);
50} 54}
51 55
52void iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) 56void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask)
53{ 57{
54 unsigned long flags; 58 unsigned long flags;
55 59
56 spin_lock_irqsave(&priv->reg_lock, flags); 60 spin_lock_irqsave(&bus->reg_lock, flags);
57 __iwl_clear_bit(priv, reg, mask); 61 __iwl_clear_bit(bus, reg, mask);
58 spin_unlock_irqrestore(&priv->reg_lock, flags); 62 spin_unlock_irqrestore(&bus->reg_lock, flags);
59} 63}
60 64
61int iwl_poll_bit(struct iwl_priv *priv, u32 addr, 65int iwl_poll_bit(struct iwl_bus *bus, u32 addr,
62 u32 bits, u32 mask, int timeout) 66 u32 bits, u32 mask, int timeout)
63{ 67{
64 int t = 0; 68 int t = 0;
65 69
66 do { 70 do {
67 if ((iwl_read32(priv, addr) & mask) == (bits & mask)) 71 if ((iwl_read32(bus, addr) & mask) == (bits & mask))
68 return t; 72 return t;
69 udelay(IWL_POLL_INTERVAL); 73 udelay(IWL_POLL_INTERVAL);
70 t += IWL_POLL_INTERVAL; 74 t += IWL_POLL_INTERVAL;
@@ -73,14 +77,14 @@ int iwl_poll_bit(struct iwl_priv *priv, u32 addr,
73 return -ETIMEDOUT; 77 return -ETIMEDOUT;
74} 78}
75 79
76int iwl_grab_nic_access_silent(struct iwl_priv *priv) 80int iwl_grab_nic_access_silent(struct iwl_bus *bus)
77{ 81{
78 int ret; 82 int ret;
79 83
80 lockdep_assert_held(&priv->reg_lock); 84 lockdep_assert_held(&bus->reg_lock);
81 85
82 /* this bit wakes up the NIC */ 86 /* this bit wakes up the NIC */
83 __iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 87 __iwl_set_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
84 88
85 /* 89 /*
86 * These bits say the device is running, and should keep running for 90 * These bits say the device is running, and should keep running for
@@ -101,70 +105,70 @@ int iwl_grab_nic_access_silent(struct iwl_priv *priv)
101 * 5000 series and later (including 1000 series) have non-volatile SRAM, 105 * 5000 series and later (including 1000 series) have non-volatile SRAM,
102 * and do not save/restore SRAM when power cycling. 106 * and do not save/restore SRAM when power cycling.
103 */ 107 */
104 ret = iwl_poll_bit(priv, CSR_GP_CNTRL, 108 ret = iwl_poll_bit(bus, CSR_GP_CNTRL,
105 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 109 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
106 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 110 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
107 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 111 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
108 if (ret < 0) { 112 if (ret < 0) {
109 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 113 iwl_write32(bus, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
110 return -EIO; 114 return -EIO;
111 } 115 }
112 116
113 return 0; 117 return 0;
114} 118}
115 119
116int iwl_grab_nic_access(struct iwl_priv *priv) 120int iwl_grab_nic_access(struct iwl_bus *bus)
117{ 121{
118 int ret = iwl_grab_nic_access_silent(priv); 122 int ret = iwl_grab_nic_access_silent(bus);
119 if (ret) { 123 if (ret) {
120 u32 val = iwl_read32(priv, CSR_GP_CNTRL); 124 u32 val = iwl_read32(bus, CSR_GP_CNTRL);
121 IWL_ERR(priv, 125 IWL_ERR(bus,
122 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); 126 "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
123 } 127 }
124 128
125 return ret; 129 return ret;
126} 130}
127 131
128void iwl_release_nic_access(struct iwl_priv *priv) 132void iwl_release_nic_access(struct iwl_bus *bus)
129{ 133{
130 lockdep_assert_held(&priv->reg_lock); 134 lockdep_assert_held(&bus->reg_lock);
131 __iwl_clear_bit(priv, CSR_GP_CNTRL, 135 __iwl_clear_bit(bus, CSR_GP_CNTRL,
132 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 136 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
133} 137}
134 138
135u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg) 139u32 iwl_read_direct32(struct iwl_bus *bus, u32 reg)
136{ 140{
137 u32 value; 141 u32 value;
138 unsigned long flags; 142 unsigned long flags;
139 143
140 spin_lock_irqsave(&priv->reg_lock, flags); 144 spin_lock_irqsave(&bus->reg_lock, flags);
141 iwl_grab_nic_access(priv); 145 iwl_grab_nic_access(bus);
142 value = iwl_read32(priv, reg); 146 value = iwl_read32(bus(bus), reg);
143 iwl_release_nic_access(priv); 147 iwl_release_nic_access(bus);
144 spin_unlock_irqrestore(&priv->reg_lock, flags); 148 spin_unlock_irqrestore(&bus->reg_lock, flags);
145 149
146 return value; 150 return value;
147} 151}
148 152
149void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value) 153void iwl_write_direct32(struct iwl_bus *bus, u32 reg, u32 value)
150{ 154{
151 unsigned long flags; 155 unsigned long flags;
152 156
153 spin_lock_irqsave(&priv->reg_lock, flags); 157 spin_lock_irqsave(&bus->reg_lock, flags);
154 if (!iwl_grab_nic_access(priv)) { 158 if (!iwl_grab_nic_access(bus)) {
155 iwl_write32(priv, reg, value); 159 iwl_write32(bus, reg, value);
156 iwl_release_nic_access(priv); 160 iwl_release_nic_access(bus);
157 } 161 }
158 spin_unlock_irqrestore(&priv->reg_lock, flags); 162 spin_unlock_irqrestore(&bus->reg_lock, flags);
159} 163}
160 164
161int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask, 165int iwl_poll_direct_bit(struct iwl_bus *bus, u32 addr, u32 mask,
162 int timeout) 166 int timeout)
163{ 167{
164 int t = 0; 168 int t = 0;
165 169
166 do { 170 do {
167 if ((iwl_read_direct32(priv, addr) & mask) == mask) 171 if ((iwl_read_direct32(bus, addr) & mask) == mask)
168 return t; 172 return t;
169 udelay(IWL_POLL_INTERVAL); 173 udelay(IWL_POLL_INTERVAL);
170 t += IWL_POLL_INTERVAL; 174 t += IWL_POLL_INTERVAL;
@@ -173,122 +177,122 @@ int iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, u32 mask,
173 return -ETIMEDOUT; 177 return -ETIMEDOUT;
174} 178}
175 179
176static inline u32 __iwl_read_prph(struct iwl_priv *priv, u32 reg) 180static inline u32 __iwl_read_prph(struct iwl_bus *bus, u32 reg)
177{ 181{
178 iwl_write32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 182 iwl_write32(bus, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
179 rmb(); 183 rmb();
180 return iwl_read32(priv, HBUS_TARG_PRPH_RDAT); 184 return iwl_read32(bus, HBUS_TARG_PRPH_RDAT);
181} 185}
182 186
183static inline void __iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val) 187static inline void __iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val)
184{ 188{
185 iwl_write32(priv, HBUS_TARG_PRPH_WADDR, 189 iwl_write32(bus, HBUS_TARG_PRPH_WADDR,
186 ((addr & 0x0000FFFF) | (3 << 24))); 190 ((addr & 0x0000FFFF) | (3 << 24)));
187 wmb(); 191 wmb();
188 iwl_write32(priv, HBUS_TARG_PRPH_WDAT, val); 192 iwl_write32(bus, HBUS_TARG_PRPH_WDAT, val);
189} 193}
190 194
191u32 iwl_read_prph(struct iwl_priv *priv, u32 reg) 195u32 iwl_read_prph(struct iwl_bus *bus, u32 reg)
192{ 196{
193 unsigned long flags; 197 unsigned long flags;
194 u32 val; 198 u32 val;
195 199
196 spin_lock_irqsave(&priv->reg_lock, flags); 200 spin_lock_irqsave(&bus->reg_lock, flags);
197 iwl_grab_nic_access(priv); 201 iwl_grab_nic_access(bus);
198 val = __iwl_read_prph(priv, reg); 202 val = __iwl_read_prph(bus, reg);
199 iwl_release_nic_access(priv); 203 iwl_release_nic_access(bus);
200 spin_unlock_irqrestore(&priv->reg_lock, flags); 204 spin_unlock_irqrestore(&bus->reg_lock, flags);
201 return val; 205 return val;
202} 206}
203 207
204void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val) 208void iwl_write_prph(struct iwl_bus *bus, u32 addr, u32 val)
205{ 209{
206 unsigned long flags; 210 unsigned long flags;
207 211
208 spin_lock_irqsave(&priv->reg_lock, flags); 212 spin_lock_irqsave(&bus->reg_lock, flags);
209 if (!iwl_grab_nic_access(priv)) { 213 if (!iwl_grab_nic_access(bus)) {
210 __iwl_write_prph(priv, addr, val); 214 __iwl_write_prph(bus, addr, val);
211 iwl_release_nic_access(priv); 215 iwl_release_nic_access(bus);
212 } 216 }
213 spin_unlock_irqrestore(&priv->reg_lock, flags); 217 spin_unlock_irqrestore(&bus->reg_lock, flags);
214} 218}
215 219
216void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask) 220void iwl_set_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask)
217{ 221{
218 unsigned long flags; 222 unsigned long flags;
219 223
220 spin_lock_irqsave(&priv->reg_lock, flags); 224 spin_lock_irqsave(&bus->reg_lock, flags);
221 iwl_grab_nic_access(priv); 225 iwl_grab_nic_access(bus);
222 __iwl_write_prph(priv, reg, __iwl_read_prph(priv, reg) | mask); 226 __iwl_write_prph(bus, reg, __iwl_read_prph(bus, reg) | mask);
223 iwl_release_nic_access(priv); 227 iwl_release_nic_access(bus);
224 spin_unlock_irqrestore(&priv->reg_lock, flags); 228 spin_unlock_irqrestore(&bus->reg_lock, flags);
225} 229}
226 230
227void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg, 231void iwl_set_bits_mask_prph(struct iwl_bus *bus, u32 reg,
228 u32 bits, u32 mask) 232 u32 bits, u32 mask)
229{ 233{
230 unsigned long flags; 234 unsigned long flags;
231 235
232 spin_lock_irqsave(&priv->reg_lock, flags); 236 spin_lock_irqsave(&bus->reg_lock, flags);
233 iwl_grab_nic_access(priv); 237 iwl_grab_nic_access(bus);
234 __iwl_write_prph(priv, reg, 238 __iwl_write_prph(bus, reg,
235 (__iwl_read_prph(priv, reg) & mask) | bits); 239 (__iwl_read_prph(bus, reg) & mask) | bits);
236 iwl_release_nic_access(priv); 240 iwl_release_nic_access(bus);
237 spin_unlock_irqrestore(&priv->reg_lock, flags); 241 spin_unlock_irqrestore(&bus->reg_lock, flags);
238} 242}
239 243
240void iwl_clear_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask) 244void iwl_clear_bits_prph(struct iwl_bus *bus, u32 reg, u32 mask)
241{ 245{
242 unsigned long flags; 246 unsigned long flags;
243 u32 val; 247 u32 val;
244 248
245 spin_lock_irqsave(&priv->reg_lock, flags); 249 spin_lock_irqsave(&bus->reg_lock, flags);
246 iwl_grab_nic_access(priv); 250 iwl_grab_nic_access(bus);
247 val = __iwl_read_prph(priv, reg); 251 val = __iwl_read_prph(bus, reg);
248 __iwl_write_prph(priv, reg, (val & ~mask)); 252 __iwl_write_prph(bus, reg, (val & ~mask));
249 iwl_release_nic_access(priv); 253 iwl_release_nic_access(bus);
250 spin_unlock_irqrestore(&priv->reg_lock, flags); 254 spin_unlock_irqrestore(&bus->reg_lock, flags);
251} 255}
252 256
253void _iwl_read_targ_mem_words(struct iwl_priv *priv, u32 addr, 257void _iwl_read_targ_mem_words(struct iwl_bus *bus, u32 addr,
254 void *buf, int words) 258 void *buf, int words)
255{ 259{
256 unsigned long flags; 260 unsigned long flags;
257 int offs; 261 int offs;
258 u32 *vals = buf; 262 u32 *vals = buf;
259 263
260 spin_lock_irqsave(&priv->reg_lock, flags); 264 spin_lock_irqsave(&bus->reg_lock, flags);
261 iwl_grab_nic_access(priv); 265 iwl_grab_nic_access(bus);
262 266
263 iwl_write32(priv, HBUS_TARG_MEM_RADDR, addr); 267 iwl_write32(bus, HBUS_TARG_MEM_RADDR, addr);
264 rmb(); 268 rmb();
265 269
266 for (offs = 0; offs < words; offs++) 270 for (offs = 0; offs < words; offs++)
267 vals[offs] = iwl_read32(priv, HBUS_TARG_MEM_RDAT); 271 vals[offs] = iwl_read32(bus, HBUS_TARG_MEM_RDAT);
268 272
269 iwl_release_nic_access(priv); 273 iwl_release_nic_access(bus);
270 spin_unlock_irqrestore(&priv->reg_lock, flags); 274 spin_unlock_irqrestore(&bus->reg_lock, flags);
271} 275}
272 276
273u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr) 277u32 iwl_read_targ_mem(struct iwl_bus *bus, u32 addr)
274{ 278{
275 u32 value; 279 u32 value;
276 280
277 _iwl_read_targ_mem_words(priv, addr, &value, 1); 281 _iwl_read_targ_mem_words(bus, addr, &value, 1);
278 282
279 return value; 283 return value;
280} 284}
281 285
282void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) 286void iwl_write_targ_mem(struct iwl_bus *bus, u32 addr, u32 val)
283{ 287{
284 unsigned long flags; 288 unsigned long flags;
285 289
286 spin_lock_irqsave(&priv->reg_lock, flags); 290 spin_lock_irqsave(&bus->reg_lock, flags);
287 if (!iwl_grab_nic_access(priv)) { 291 if (!iwl_grab_nic_access(bus)) {
288 iwl_write32(priv, HBUS_TARG_MEM_WADDR, addr); 292 iwl_write32(bus, HBUS_TARG_MEM_WADDR, addr);
289 wmb(); 293 wmb();
290 iwl_write32(priv, HBUS_TARG_MEM_WDAT, val); 294 iwl_write32(bus, HBUS_TARG_MEM_WDAT, val);
291 iwl_release_nic_access(priv); 295 iwl_release_nic_access(bus);
292 } 296 }
293 spin_unlock_irqrestore(&priv->reg_lock, flags); 297 spin_unlock_irqrestore(&bus->reg_lock, flags);
294} 298}