diff options
author | Mohamed Abbas <mabbas@linux.intel.com> | 2008-03-25 19:33:36 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-03-27 16:03:16 -0400 |
commit | ab53d8af6772b22d4d68b1bcd74f7a5dba693983 (patch) | |
tree | 599c6682d75e15b30af9bf994595e7d5eed5c3ac /drivers/net/wireless/iwlwifi/iwl-csr.h | |
parent | e0e0a67e44ce13e34f553b6ab6377560fa9813f1 (diff) |
iwlwifi: Add led support
This patch add LEDS support to 3965 and 4965 drivers. It is based on
led trigger and class. For our drivers we needed to avoid two things.
1- We receive led trigger on/off on each Rx\Tx frame. In our driver
we can not call led command like that. In this driver once driver
receive a start of traffic it call the led command to start blinking
then we count all bytes of Tx and Rx frame, after two second we count the
blink rate of last two second then id blink rate changed we call the led
commands
2- Since we can call led command very often, we make sure we call the
led command after we receive the statistics notification so
we don't need to wake up the ucode id it is in sleep state.
This patch was tested with 4965 and 3945.
Signed-off-by: Mohamed Abbas <mabbas@linux.intel.com>
Signed-off-by: Ian Schram<ischram@telenet.be>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index f0a2c8d180f0..12725796ea5f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -93,6 +93,7 @@ | |||
93 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | 93 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) |
94 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) | 94 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) |
95 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) | 95 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
96 | #define CSR_LED_REG (CSR_BASE+0x094) | ||
96 | 97 | ||
97 | /* Analog phase-lock-loop configuration (3945 only) | 98 | /* Analog phase-lock-loop configuration (3945 only) |
98 | * Set bit 24. */ | 99 | * Set bit 24. */ |
@@ -214,6 +215,11 @@ | |||
214 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) | 215 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
215 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | 216 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |
216 | 217 | ||
218 | /* LED */ | ||
219 | #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) | ||
220 | #define CSR_LED_REG_TRUN_ON (0x78) | ||
221 | #define CSR_LED_REG_TRUN_OFF (0x38) | ||
222 | |||
217 | /*=== HBUS (Host-side Bus) ===*/ | 223 | /*=== HBUS (Host-side Bus) ===*/ |
218 | #define HBUS_BASE (0x400) | 224 | #define HBUS_BASE (0x400) |
219 | /* | 225 | /* |