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authorWey-Yi Guy <wey-yi.w.guy@intel.com>2009-05-22 14:01:49 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-05-22 14:06:05 -0400
commita2b0f02e4795bfde5f11720a10af8923cb98b654 (patch)
tree1d2cad3ff20f43ba51aace00a8c2c627fe013581 /drivers/net/wireless/iwlwifi/iwl-commands.h
parenta9c146b369cd8facbbbec7d8b31440f6eaa43e03 (diff)
iwlwifi: support "pure 40MHz" in RXON command
Fix the bug when using 11n "pure 40MHz" mode cause uCode crashing by adding support for "pure 40MHz" in RX_ON command flag. the "mode" field (bits 25:26) has value of 0-3 0 = 20 MHz only 1 = 40MHz only 2 = Mixed 3 = Reserved Control Channel ID (bit 22) is valid only in Mixed mode. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-commands.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-commands.h14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h
index 7b84d5246b36..e581dc323f0a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-commands.h
@@ -614,8 +614,18 @@ enum {
614 614
615#define RXON_FLG_CHANNEL_MODE_POS (25) 615#define RXON_FLG_CHANNEL_MODE_POS (25)
616#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25) 616#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
617#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK cpu_to_le32(0x1 << 25) 617
618#define RXON_FLG_CHANNEL_MODE_MIXED_MSK cpu_to_le32(0x2 << 25) 618/* channel mode */
619enum {
620 CHANNEL_MODE_LEGACY = 0,
621 CHANNEL_MODE_PURE_40 = 1,
622 CHANNEL_MODE_MIXED = 2,
623 CHANNEL_MODE_RESERVED = 3,
624};
625#define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
626#define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
627#define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
628
619/* CTS to self (if spec allows) flag */ 629/* CTS to self (if spec allows) flag */
620#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30) 630#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
621 631