diff options
author | Mohamed Abbas <mohamed.abbas@intel.com> | 2009-05-22 14:01:47 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-05-22 14:06:04 -0400 |
commit | a8b50a0a966d7ac313f624c6ab4996231a5fe25a (patch) | |
tree | 8c000ee1d429f1e639fde9613cb48b268aee1ff6 /drivers/net/wireless/iwlwifi/iwl-agn.c | |
parent | 0848e297c2107dbc12a91a1709c879c73bd188d8 (diff) |
iwlcore: register locks
Add new lock to be used when accessing some registers. Also move
the register lock and iwl_grab_nic_access inside the function for register access. This
will prevent from forgetting to hold locks and nic access in the right way and make code
easier to maintain.
We over use the priv->lock spin lock and I guess we need to add new
one for Tx queue after that we might need to change most of these lock to
BH and just keep priv->lock as irq type.
Signed-off-by: Mohamed Abbas <mohamed.abbas@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn.c')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-agn.c | 56 |
1 files changed, 13 insertions, 43 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index fd3673448d7a..4e41038a92c1 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -503,24 +503,12 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |||
503 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | 503 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, |
504 | struct iwl_tx_queue *txq) | 504 | struct iwl_tx_queue *txq) |
505 | { | 505 | { |
506 | int ret; | ||
507 | unsigned long flags; | ||
508 | int txq_id = txq->q.id; | 506 | int txq_id = txq->q.id; |
509 | 507 | ||
510 | spin_lock_irqsave(&priv->lock, flags); | ||
511 | ret = iwl_grab_nic_access(priv); | ||
512 | if (ret) { | ||
513 | spin_unlock_irqrestore(&priv->lock, flags); | ||
514 | return ret; | ||
515 | } | ||
516 | |||
517 | /* Circular buffer (TFD queue in DRAM) physical base address */ | 508 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
518 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | 509 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), |
519 | txq->q.dma_addr >> 8); | 510 | txq->q.dma_addr >> 8); |
520 | 511 | ||
521 | iwl_release_nic_access(priv); | ||
522 | spin_unlock_irqrestore(&priv->lock, flags); | ||
523 | |||
524 | return 0; | 512 | return 0; |
525 | } | 513 | } |
526 | 514 | ||
@@ -709,6 +697,7 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv, | |||
709 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | 697 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
710 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); | 698 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
711 | unsigned long status = priv->status; | 699 | unsigned long status = priv->status; |
700 | unsigned long reg_flags; | ||
712 | 701 | ||
713 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", | 702 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
714 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", | 703 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
@@ -720,32 +709,25 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv, | |||
720 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, | 709 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
721 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 710 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
722 | 711 | ||
723 | if (!iwl_grab_nic_access(priv)) { | 712 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
724 | iwl_write_direct32( | 713 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
725 | priv, HBUS_TARG_MBX_C, | ||
726 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | ||
727 | |||
728 | iwl_release_nic_access(priv); | ||
729 | } | ||
730 | 714 | ||
731 | if (!(flags & RXON_CARD_DISABLED)) { | 715 | if (!(flags & RXON_CARD_DISABLED)) { |
732 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | 716 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
733 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 717 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
734 | if (!iwl_grab_nic_access(priv)) { | 718 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
735 | iwl_write_direct32( | ||
736 | priv, HBUS_TARG_MBX_C, | ||
737 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | 719 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
738 | 720 | ||
739 | iwl_release_nic_access(priv); | ||
740 | } | ||
741 | } | 721 | } |
742 | 722 | ||
743 | if (flags & RF_CARD_DISABLED) { | 723 | if (flags & RF_CARD_DISABLED) { |
744 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, | 724 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
745 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | 725 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
746 | iwl_read32(priv, CSR_UCODE_DRV_GP1); | 726 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
727 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | ||
747 | if (!iwl_grab_nic_access(priv)) | 728 | if (!iwl_grab_nic_access(priv)) |
748 | iwl_release_nic_access(priv); | 729 | iwl_release_nic_access(priv); |
730 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | ||
749 | } | 731 | } |
750 | } | 732 | } |
751 | 733 | ||
@@ -774,14 +756,6 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv, | |||
774 | 756 | ||
775 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) | 757 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
776 | { | 758 | { |
777 | int ret; | ||
778 | unsigned long flags; | ||
779 | |||
780 | spin_lock_irqsave(&priv->lock, flags); | ||
781 | ret = iwl_grab_nic_access(priv); | ||
782 | if (ret) | ||
783 | goto err; | ||
784 | |||
785 | if (src == IWL_PWR_SRC_VAUX) { | 759 | if (src == IWL_PWR_SRC_VAUX) { |
786 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) | 760 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
787 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | 761 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
@@ -793,10 +767,7 @@ int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) | |||
793 | ~APMG_PS_CTRL_MSK_PWR_SRC); | 767 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
794 | } | 768 | } |
795 | 769 | ||
796 | iwl_release_nic_access(priv); | 770 | return 0; |
797 | err: | ||
798 | spin_unlock_irqrestore(&priv->lock, flags); | ||
799 | return ret; | ||
800 | } | 771 | } |
801 | 772 | ||
802 | /** | 773 | /** |
@@ -1587,13 +1558,8 @@ static void __iwl_down(struct iwl_priv *priv) | |||
1587 | iwl_txq_ctx_stop(priv); | 1558 | iwl_txq_ctx_stop(priv); |
1588 | iwl_rxq_stop(priv); | 1559 | iwl_rxq_stop(priv); |
1589 | 1560 | ||
1590 | spin_lock_irqsave(&priv->lock, flags); | 1561 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
1591 | if (!iwl_grab_nic_access(priv)) { | 1562 | APMG_CLK_VAL_DMA_CLK_RQT); |
1592 | iwl_write_prph(priv, APMG_CLK_DIS_REG, | ||
1593 | APMG_CLK_VAL_DMA_CLK_RQT); | ||
1594 | iwl_release_nic_access(priv); | ||
1595 | } | ||
1596 | spin_unlock_irqrestore(&priv->lock, flags); | ||
1597 | 1563 | ||
1598 | udelay(5); | 1564 | udelay(5); |
1599 | 1565 | ||
@@ -2707,6 +2673,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2707 | (unsigned long long) pci_resource_len(pdev, 0)); | 2673 | (unsigned long long) pci_resource_len(pdev, 0)); |
2708 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); | 2674 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
2709 | 2675 | ||
2676 | /* this spin lock will be used in apm_ops.init and EEPROM access | ||
2677 | * we should init now | ||
2678 | */ | ||
2679 | spin_lock_init(&priv->reg_lock); | ||
2710 | iwl_hw_detect(priv); | 2680 | iwl_hw_detect(priv); |
2711 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", | 2681 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
2712 | priv->cfg->name, priv->hw_rev); | 2682 | priv->cfg->name, priv->hw_rev); |