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authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>2007-10-25 05:15:38 -0400
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:03:18 -0500
commit67dc320d4719501a0a10d222a670f5a59660505b (patch)
tree7cf01835b030e8390554d9f8c1328a61d3659ff7 /drivers/net/wireless/iwlwifi/iwl-4965.c
parentac17a947a4f47b642097d6814d6dcc60c297eb17 (diff)
iwlwifi-ht: move 4965 SCD registers to iwl-prph.h
This patch moves 4965 SCD registers to iwl-prph.h. These registers are assigned from the periphery bus Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 8e9810b72ace..f4113058188a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -382,7 +382,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
382 goto error_reset; 382 goto error_reset;
383 } 383 }
384 384
385 iwl_write_prph(priv, SCD_TXFACT, 0); 385 iwl_write_prph(priv, KDR_SCD_TXFACT, 0);
386 iwl_release_nic_access(priv); 386 iwl_release_nic_access(priv);
387 spin_unlock_irqrestore(&priv->lock, flags); 387 spin_unlock_irqrestore(&priv->lock, flags);
388 388
@@ -1583,7 +1583,7 @@ static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1583{ 1583{
1584 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 1584 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1585 (index & 0xff) | (txq_id << 8)); 1585 (index & 0xff) | (txq_id << 8));
1586 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index); 1586 iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
1587} 1587}
1588 1588
1589/* 1589/*
@@ -1596,7 +1596,7 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1596 int txq_id = txq->q.id; 1596 int txq_id = txq->q.id;
1597 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 1597 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1598 1598
1599 iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id), 1599 iwl_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
1600 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1600 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1601 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | 1601 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1602 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) | 1602 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
@@ -1654,7 +1654,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1654 return rc; 1654 return rc;
1655 } 1655 }
1656 1656
1657 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR); 1657 priv->scd_base_addr = iwl_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
1658 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; 1658 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1659 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) 1659 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1660 iwl_write_targ_mem(priv, a, 0); 1660 iwl_write_targ_mem(priv, a, 0);
@@ -1663,14 +1663,14 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1663 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4) 1663 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
1664 iwl_write_targ_mem(priv, a, 0); 1664 iwl_write_targ_mem(priv, a, 0);
1665 1665
1666 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR, 1666 iwl_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
1667 (priv->hw_setting.shared_phys + 1667 (priv->hw_setting.shared_phys +
1668 offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10); 1668 offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10);
1669 iwl_write_prph(priv, SCD_QUEUECHAIN_SEL, 0); 1669 iwl_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
1670 1670
1671 /* initiate the queues */ 1671 /* initiate the queues */
1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) { 1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0); 1673 iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
1674 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 1674 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1675 iwl_write_targ_mem(priv, priv->scd_base_addr + 1675 iwl_write_targ_mem(priv, priv->scd_base_addr +
1676 SCD_CONTEXT_QUEUE_OFFSET(i), 1676 SCD_CONTEXT_QUEUE_OFFSET(i),
@@ -1685,10 +1685,10 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1685 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 1685 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1686 1686
1687 } 1687 }
1688 iwl_write_prph(priv, SCD_INTERRUPT_MASK, 1688 iwl_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
1689 (1 << priv->hw_setting.max_txq_num) - 1); 1689 (1 << priv->hw_setting.max_txq_num) - 1);
1690 1690
1691 iwl_write_prph(priv, SCD_TXFACT, 1691 iwl_write_prph(priv, KDR_SCD_TXFACT,
1692 SCD_TXFACT_REG_TXFIFO_MASK(0, 7)); 1692 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1693 1693
1694 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 1694 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
@@ -4139,7 +4139,7 @@ static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
4139static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 4139static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
4140{ 4140{
4141 iwl_write_prph(priv, 4141 iwl_write_prph(priv,
4142 SCD_QUEUE_STATUS_BITS(txq_id), 4142 KDR_SCD_QUEUE_STATUS_BITS(txq_id),
4143 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| 4143 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4144 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 4144 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4145} 4145}
@@ -4199,7 +4199,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4199 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 4199 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4200 4200
4201 4201
4202 iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id)); 4202 iwl_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1<<txq_id));
4203 4203
4204 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 4204 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4205 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 4205 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
@@ -4217,7 +4217,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4217 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) 4217 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4218 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 4218 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4219 4219
4220 iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); 4220 iwl_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4221 4221
4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4223 4223
@@ -4251,14 +4251,14 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4251 4251
4252 iwl4965_tx_queue_stop_scheduler(priv, txq_id); 4252 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4253 4253
4254 iwl_clear_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1 << txq_id)); 4254 iwl_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
4255 4255
4256 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 4256 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4257 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 4257 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4258 /* supposes that ssn_idx is valid (!= 0xFFF) */ 4258 /* supposes that ssn_idx is valid (!= 0xFFF) */
4259 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); 4259 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4260 4260
4261 iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); 4261 iwl_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4262 iwl4965_txq_ctx_deactivate(priv, txq_id); 4262 iwl4965_txq_ctx_deactivate(priv, txq_id);
4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4264 4264