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authorBen Cahill <ben.m.cahill@intel.com>2007-11-28 22:10:06 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:05:30 -0500
commit5d5456fe50cb07347dd350fc045dc98677dbc58f (patch)
tree52395022ef1f6d106d108171997c6776ea165961 /drivers/net/wireless/iwlwifi/iwl-4965-hw.h
parent483fd7e5ffa527daeaff006e033225e273d110f8 (diff)
iwlwifi: document shared Tx structures
Document shared Tx structures Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965-hw.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h147
1 files changed, 135 insertions, 12 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index e7c7f71db8e1..b548b7979b42 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -452,6 +452,13 @@ struct iwl4965_eeprom {
452 */ 452 */
453#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) 453#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
454 454
455/* Hardware interface configuration bits */
456#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
457#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
458#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
459#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
460#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
461
455/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 462/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
456 * acknowledged (reset) by host writing "1" to flagged bits. */ 463 * acknowledged (reset) by host writing "1" to flagged bits. */
457#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 464#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
@@ -1574,12 +1581,6 @@ enum {
1574#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1581#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1575#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1582#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1576 1583
1577#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
1578#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
1579#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
1580#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
1581#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
1582
1583static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags) 1584static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
1584{ 1585{
1585 return le32_to_cpu(rate_n_flags) & 0xFF; 1586 return le32_to_cpu(rate_n_flags) & 0xFF;
@@ -1593,6 +1594,53 @@ static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags)
1593 return cpu_to_le32(flags|(u16)rate); 1594 return cpu_to_le32(flags|(u16)rate);
1594} 1595}
1595 1596
1597
1598/**
1599 * Tx/Rx Queues
1600 *
1601 * Most communication between driver and 4965 is via queues of data buffers.
1602 * For example, all commands that the driver issues to device's embedded
1603 * controller (uCode) are via the command queue (one of the Tx queues). All
1604 * uCode command responses/replies/notifications, including Rx frames, are
1605 * conveyed from uCode to driver via the Rx queue.
1606 *
1607 * Most support for these queues, including handshake support, resides in
1608 * structures in host DRAM, shared between the driver and the device. When
1609 * allocating this memory, the driver must make sure that data written by
1610 * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's
1611 * cache memory), so DRAM and cache are consistent, and the device can
1612 * immediately see changes made by the driver.
1613 *
1614 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
1615 * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array
1616 * in DRAM containing 256 Transmit Frame Descriptors (TFDs).
1617 */
1618#define IWL4965_MAX_WIN_SIZE 64
1619#define IWL4965_QUEUE_SIZE 256
1620#define IWL4965_NUM_FIFOS 7
1621#define IWL_MAX_NUM_QUEUES 16
1622
1623
1624/**
1625 * struct iwl4965_tfd_frame_data
1626 *
1627 * Describes up to 2 buffers containing (contiguous) portions of a Tx frame.
1628 * Each buffer must be on dword boundary.
1629 * Up to 10 iwl_tfd_frame_data structures, describing up to 20 buffers,
1630 * may be filled within a TFD (iwl_tfd_frame).
1631 *
1632 * Bit fields in tb1_addr:
1633 * 31- 0: Tx buffer 1 address bits [31:0]
1634 *
1635 * Bit fields in val1:
1636 * 31-16: Tx buffer 2 address bits [15:0]
1637 * 15- 4: Tx buffer 1 length (bytes)
1638 * 3- 0: Tx buffer 1 address bits [32:32]
1639 *
1640 * Bit fields in val2:
1641 * 31-20: Tx buffer 2 length (bytes)
1642 * 19- 0: Tx buffer 2 address bits [35:16]
1643 */
1596struct iwl4965_tfd_frame_data { 1644struct iwl4965_tfd_frame_data {
1597 __le32 tb1_addr; 1645 __le32 tb1_addr;
1598 1646
@@ -1621,6 +1669,35 @@ struct iwl4965_tfd_frame_data {
1621#define IWL_tb2_len_SYM val2 1669#define IWL_tb2_len_SYM val2
1622} __attribute__ ((packed)); 1670} __attribute__ ((packed));
1623 1671
1672
1673/**
1674 * struct iwl4965_tfd_frame
1675 *
1676 * Transmit Frame Descriptor (TFD)
1677 *
1678 * 4965 supports up to 16 Tx queues resident in host DRAM.
1679 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1680 * Both driver and device share these circular buffers, each of which must be
1681 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes for 4965.
1682 *
1683 * Driver must indicate the physical address of the base of each
1684 * circular buffer via the 4965's FH_MEM_CBBC_QUEUE registers.
1685 *
1686 * Each TFD contains pointer/size information for up to 20 data buffers
1687 * in host DRAM. These buffers collectively contain the (one) frame described
1688 * by the TFD. Each buffer must be a single contiguous block of memory within
1689 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1690 * of (4K - 4). The 4965 concatenates all of a TFD's buffers into a single
1691 * Tx frame, up to 8 KBytes in size.
1692 *
1693 * Bit fields in the control dword (val0):
1694 * 31-30: # dwords (0-3) of padding required at end of frame for 16-byte bound
1695 * 29: reserved
1696 * 28-24: # Transmit Buffer Descriptors in TFD
1697 * 23- 0: reserved
1698 *
1699 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1700 */
1624struct iwl4965_tfd_frame { 1701struct iwl4965_tfd_frame {
1625 __le32 val0; 1702 __le32 val0;
1626 /* __le32 rsvd1:24; */ 1703 /* __le32 rsvd1:24; */
@@ -1634,11 +1711,16 @@ struct iwl4965_tfd_frame {
1634 __le32 reserved; 1711 __le32 reserved;
1635} __attribute__ ((packed)); 1712} __attribute__ ((packed));
1636 1713
1637#define IWL4965_MAX_WIN_SIZE 64
1638#define IWL4965_QUEUE_SIZE 256
1639#define IWL4965_NUM_FIFOS 7
1640#define IWL_MAX_NUM_QUEUES 16
1641 1714
1715/**
1716 * struct iwl4965_queue_byte_cnt_entry
1717 *
1718 * Byte Count Table Entry
1719 *
1720 * Bit fields:
1721 * 15-12: reserved
1722 * 11- 0: total to-be-transmitted byte count of frame (does not include command)
1723 */
1642struct iwl4965_queue_byte_cnt_entry { 1724struct iwl4965_queue_byte_cnt_entry {
1643 __le16 val; 1725 __le16 val;
1644 /* __le16 byte_cnt:12; */ 1726 /* __le16 byte_cnt:12; */
@@ -1648,6 +1730,25 @@ struct iwl4965_queue_byte_cnt_entry {
1648 /* __le16 rsvd:4; */ 1730 /* __le16 rsvd:4; */
1649} __attribute__ ((packed)); 1731} __attribute__ ((packed));
1650 1732
1733
1734/**
1735 * struct iwl4965_sched_queue_byte_cnt_tbl
1736 *
1737 * Byte Count table
1738 *
1739 * Each Tx queue uses a byte-count table containing 320 entries:
1740 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
1741 * duplicate the first 64 entries (to avoid wrap-around within a Tx window;
1742 * max Tx window is 64 TFDs).
1743 *
1744 * When driver sets up a new TFD, it must also enter the total byte count
1745 * of the frame to be transmitted into the corresponding entry in the byte
1746 * count table for the chosen Tx queue. If the TFD index is 0-63, the driver
1747 * must duplicate the byte count entry in corresponding index 256-319.
1748 *
1749 * "dont_care" padding puts each byte count table on a 1024-byte boundary;
1750 * 4965 assumes tables are separated by 1024 bytes.
1751 */
1651struct iwl4965_sched_queue_byte_cnt_tbl { 1752struct iwl4965_sched_queue_byte_cnt_tbl {
1652 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE + 1753 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE +
1653 IWL4965_MAX_WIN_SIZE]; 1754 IWL4965_MAX_WIN_SIZE];
@@ -1656,8 +1757,30 @@ struct iwl4965_sched_queue_byte_cnt_tbl {
1656 sizeof(__le16)]; 1757 sizeof(__le16)];
1657} __attribute__ ((packed)); 1758} __attribute__ ((packed));
1658 1759
1659/* Base physical address of iwl4965_shared is provided to KDR_SCD_DRAM_BASE_ADDR 1760
1660 * and &iwl4965_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */ 1761/**
1762 * struct iwl4965_shared - handshake area for Tx and Rx
1763 *
1764 * For convenience in allocating memory, this structure combines 2 areas of
1765 * DRAM which must be shared between driver and 4965. These do not need to
1766 * be combined, if better allocation would result from keeping them separate:
1767 *
1768 * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for
1769 * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find
1770 * the first of these tables. 4965 assumes tables are 1024 bytes apart.
1771 *
1772 * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses
1773 * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area.
1774 * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD)
1775 * that has been filled by the 4965.
1776 *
1777 * Bit fields val0:
1778 * 31-12: Not used
1779 * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads)
1780 *
1781 * Bit fields val1:
1782 * 31- 0: Not used
1783 */
1661struct iwl4965_shared { 1784struct iwl4965_shared {
1662 struct iwl4965_sched_queue_byte_cnt_tbl 1785 struct iwl4965_sched_queue_byte_cnt_tbl
1663 queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES]; 1786 queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];