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authorReinette Chatre <reinette.chatre@intel.com>2008-01-14 20:46:25 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:10:03 -0500
commit8a1b02452862dd30980ad0ef493eed687bc81474 (patch)
treee4be8fd1dc67b6af1370c0a8dc9e640d0d72a7ae /drivers/net/wireless/iwlwifi/iwl-4965-hw.h
parente7a2827cbbdb11717877c44cbbdf0fb1d14e890c (diff)
iwlwifi: style fixes to usage of << and >> operators
The << and >> operators need space on each side. Cc: Stefano Brivio <stefano.brivio@polimi.it> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Acked-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965-hw.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h36
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index 7e7d6e497e0f..ff71c09ab1a7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -461,17 +461,17 @@ struct iwl4965_eeprom {
461 461
462/* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 462/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
463 * acknowledged (reset) by host writing "1" to flagged bits. */ 463 * acknowledged (reset) by host writing "1" to flagged bits. */
464#define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 464#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
465#define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */ 465#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
466#define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */ 466#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */
467#define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ 467#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
468#define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ 468#define CSR_INT_BIT_MAC_CLK_ACTV (1 << 26) /* NIC controller's clock toggled on/off */
469#define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */ 469#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
470#define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 470#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
471#define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ 471#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
472#define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */ 472#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */
473#define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ 473#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
474#define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */ 474#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
475 475
476#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ 476#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
477 CSR_INT_BIT_HW_ERR | \ 477 CSR_INT_BIT_HW_ERR | \
@@ -483,12 +483,12 @@ struct iwl4965_eeprom {
483 CSR_INT_BIT_ALIVE) 483 CSR_INT_BIT_ALIVE)
484 484
485/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 485/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
486#define CSR_FH_INT_BIT_ERR (1<<31) /* Error */ 486#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
487#define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */ 487#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
488#define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */ 488#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
489#define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */ 489#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
490#define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */ 490#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
491#define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */ 491#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
492 492
493#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ 493#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
494 CSR_FH_INT_BIT_RX_CHNL1 | \ 494 CSR_FH_INT_BIT_RX_CHNL1 | \
@@ -1683,7 +1683,7 @@ enum {
1683 1683
1684/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */ 1684/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
1685#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ 1685#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
1686 ((1<<(hi))|((1<<(hi))-(1<<(lo)))) 1686 ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
1687 1687
1688/* 1688/*
1689 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. 1689 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.