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authorRon Rindjunsky <ron.rindjunsky@intel.com>2007-11-26 09:14:42 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:05:46 -0500
commit9ee1ba474fc37bcaf6a958bf7e995006fc69893b (patch)
tree42224488712bfd808909ce48e0a4c2a8bc69c606 /drivers/net/wireless/iwlwifi/iwl-4965-hw.h
parent270243a50574455f593378377c0fa74284730f7d (diff)
iwlwifi: 802.11n add support to 8K A-MSDU Rx frames
This patch give the iwlwifi the ability to support A-MSDU up to 8K Please notice - in order to work in 8K A-MSDU ucode support is needed, version 4.44.1.19 (soon to be published). 4K A-MSDU works in current ucode version as well. Signed-off-by: Ron Rindjunsky <ron.rindjunsky@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965-hw.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index d5d418e61923..7e7d6e497e0f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -609,7 +609,8 @@ struct iwl4965_eeprom {
609#define RX_LOW_WATERMARK 8 609#define RX_LOW_WATERMARK 8
610 610
611/* Size of one Rx buffer in host DRAM */ 611/* Size of one Rx buffer in host DRAM */
612#define IWL_RX_BUF_SIZE (4 * 1024) 612#define IWL_RX_BUF_SIZE_4K (4 * 1024)
613#define IWL_RX_BUF_SIZE_8K (8 * 1024)
613 614
614/* Sizes and addresses for instruction and data memory (SRAM) in 615/* Sizes and addresses for instruction and data memory (SRAM) in
615 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ 616 * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
@@ -1457,13 +1458,17 @@ enum {
1457#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ 1458#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
1458 1459
1459#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) 1460#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
1460#define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16) 1461#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
1462#define RX_RB_TIMEOUT (0x10)
1461 1463
1462#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 1464#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1463#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 1465#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1464#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 1466#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1465 1467
1466#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 1468#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1469#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1470#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1471#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1467 1472
1468#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 1473#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1469#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 1474#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)