diff options
author | Christoph Hellwig <hch@lst.de> | 2008-01-27 19:41:47 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-01-28 18:04:35 -0500 |
commit | bb8c093bdea62f2ae371b98ebff81b0407852faf (patch) | |
tree | 7937a70c333356a85b344f883608eeaf93dd3d2b /drivers/net/wireless/iwlwifi/iwl-3945.c | |
parent | 403ab56b1c2786b0e1d58c27f5ce667b529c7faa (diff) |
iwlwifi: cleanup namespace
Prefix all symbols with iwl3945_ or iwl4965_ and thus allow building
the driver into the kernel. Also remove all the useless default
statements in Kconfig while we're at it.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Zhu Yi <yi.zhu@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-3945.c')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-3945.c | 528 |
1 files changed, 264 insertions, 264 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index 36867a18d5b4..953a9bec0639 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c | |||
@@ -63,7 +63,7 @@ | |||
63 | * maps to IWL_RATE_INVALID | 63 | * maps to IWL_RATE_INVALID |
64 | * | 64 | * |
65 | */ | 65 | */ |
66 | const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { | 66 | const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = { |
67 | IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ | 67 | IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
68 | IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ | 68 | IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ |
69 | IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | 69 | IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ |
@@ -78,12 +78,12 @@ const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { | |||
78 | IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | 78 | IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */ |
79 | }; | 79 | }; |
80 | 80 | ||
81 | /* 1 = enable the iwl_disable_events() function */ | 81 | /* 1 = enable the iwl3945_disable_events() function */ |
82 | #define IWL_EVT_DISABLE (0) | 82 | #define IWL_EVT_DISABLE (0) |
83 | #define IWL_EVT_DISABLE_SIZE (1532/32) | 83 | #define IWL_EVT_DISABLE_SIZE (1532/32) |
84 | 84 | ||
85 | /** | 85 | /** |
86 | * iwl_disable_events - Disable selected events in uCode event log | 86 | * iwl3945_disable_events - Disable selected events in uCode event log |
87 | * | 87 | * |
88 | * Disable an event by writing "1"s into "disable" | 88 | * Disable an event by writing "1"s into "disable" |
89 | * bitmap in SRAM. Bit position corresponds to Event # (id/type). | 89 | * bitmap in SRAM. Bit position corresponds to Event # (id/type). |
@@ -91,7 +91,7 @@ const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = { | |||
91 | * Use for only special debugging. This function is just a placeholder as-is, | 91 | * Use for only special debugging. This function is just a placeholder as-is, |
92 | * you'll need to provide the special bits! ... | 92 | * you'll need to provide the special bits! ... |
93 | * ... and set IWL_EVT_DISABLE to 1. */ | 93 | * ... and set IWL_EVT_DISABLE to 1. */ |
94 | void iwl_disable_events(struct iwl_priv *priv) | 94 | void iwl3945_disable_events(struct iwl3945_priv *priv) |
95 | { | 95 | { |
96 | int ret; | 96 | int ret; |
97 | int i; | 97 | int i; |
@@ -149,31 +149,31 @@ void iwl_disable_events(struct iwl_priv *priv) | |||
149 | }; | 149 | }; |
150 | 150 | ||
151 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | 151 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
152 | if (!iwl_hw_valid_rtc_data_addr(base)) { | 152 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
153 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); | 153 | IWL_ERROR("Invalid event log pointer 0x%08X\n", base); |
154 | return; | 154 | return; |
155 | } | 155 | } |
156 | 156 | ||
157 | ret = iwl_grab_nic_access(priv); | 157 | ret = iwl3945_grab_nic_access(priv); |
158 | if (ret) { | 158 | if (ret) { |
159 | IWL_WARNING("Can not read from adapter at this time.\n"); | 159 | IWL_WARNING("Can not read from adapter at this time.\n"); |
160 | return; | 160 | return; |
161 | } | 161 | } |
162 | 162 | ||
163 | disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32))); | 163 | disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32))); |
164 | array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32))); | 164 | array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32))); |
165 | iwl_release_nic_access(priv); | 165 | iwl3945_release_nic_access(priv); |
166 | 166 | ||
167 | if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { | 167 | if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { |
168 | IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", | 168 | IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", |
169 | disable_ptr); | 169 | disable_ptr); |
170 | ret = iwl_grab_nic_access(priv); | 170 | ret = iwl3945_grab_nic_access(priv); |
171 | for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) | 171 | for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) |
172 | iwl_write_targ_mem(priv, | 172 | iwl3945_write_targ_mem(priv, |
173 | disable_ptr + (i * sizeof(u32)), | 173 | disable_ptr + (i * sizeof(u32)), |
174 | evt_disable[i]); | 174 | evt_disable[i]); |
175 | 175 | ||
176 | iwl_release_nic_access(priv); | 176 | iwl3945_release_nic_access(priv); |
177 | } else { | 177 | } else { |
178 | IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); | 178 | IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); |
179 | IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); | 179 | IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); |
@@ -194,7 +194,7 @@ void iwl_disable_events(struct iwl_priv *priv) | |||
194 | * IWL_ANTENNA_MAIN - Force MAIN antenna | 194 | * IWL_ANTENNA_MAIN - Force MAIN antenna |
195 | * IWL_ANTENNA_AUX - Force AUX antenna | 195 | * IWL_ANTENNA_AUX - Force AUX antenna |
196 | */ | 196 | */ |
197 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | 197 | __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv) |
198 | { | 198 | { |
199 | switch (priv->antenna) { | 199 | switch (priv->antenna) { |
200 | case IWL_ANTENNA_DIVERSITY: | 200 | case IWL_ANTENNA_DIVERSITY: |
@@ -226,11 +226,11 @@ __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) | |||
226 | * | 226 | * |
227 | *****************************************************************************/ | 227 | *****************************************************************************/ |
228 | 228 | ||
229 | void iwl_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | 229 | void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb) |
230 | { | 230 | { |
231 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | 231 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
232 | IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", | 232 | IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", |
233 | (int)sizeof(struct iwl_notif_statistics), | 233 | (int)sizeof(struct iwl3945_notif_statistics), |
234 | le32_to_cpu(pkt->len)); | 234 | le32_to_cpu(pkt->len)); |
235 | 235 | ||
236 | memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics)); | 236 | memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics)); |
@@ -238,15 +238,15 @@ void iwl_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
238 | priv->last_statistics_time = jiffies; | 238 | priv->last_statistics_time = jiffies; |
239 | } | 239 | } |
240 | 240 | ||
241 | static void iwl3945_handle_data_packet(struct iwl_priv *priv, int is_data, | 241 | static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data, |
242 | struct iwl_rx_mem_buffer *rxb, | 242 | struct iwl3945_rx_mem_buffer *rxb, |
243 | struct ieee80211_rx_status *stats, | 243 | struct ieee80211_rx_status *stats, |
244 | u16 phy_flags) | 244 | u16 phy_flags) |
245 | { | 245 | { |
246 | struct ieee80211_hdr *hdr; | 246 | struct ieee80211_hdr *hdr; |
247 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | 247 | struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data; |
248 | struct iwl_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); | 248 | struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); |
249 | struct iwl_rx_frame_end *rx_end = IWL_RX_END(pkt); | 249 | struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); |
250 | short len = le16_to_cpu(rx_hdr->len); | 250 | short len = le16_to_cpu(rx_hdr->len); |
251 | 251 | ||
252 | /* We received data from the HW, so stop the watchdog */ | 252 | /* We received data from the HW, so stop the watchdog */ |
@@ -262,11 +262,11 @@ static void iwl3945_handle_data_packet(struct iwl_priv *priv, int is_data, | |||
262 | return; | 262 | return; |
263 | } | 263 | } |
264 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | 264 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { |
265 | if (iwl_param_hwcrypto) | 265 | if (iwl3945_param_hwcrypto) |
266 | iwl_set_decrypted_flag(priv, rxb->skb, | 266 | iwl3945_set_decrypted_flag(priv, rxb->skb, |
267 | le32_to_cpu(rx_end->status), | 267 | le32_to_cpu(rx_end->status), |
268 | stats); | 268 | stats); |
269 | iwl_handle_data_packet_monitor(priv, rxb, IWL_RX_DATA(pkt), | 269 | iwl3945_handle_data_packet_monitor(priv, rxb, IWL_RX_DATA(pkt), |
270 | len, stats, phy_flags); | 270 | len, stats, phy_flags); |
271 | return; | 271 | return; |
272 | } | 272 | } |
@@ -277,21 +277,21 @@ static void iwl3945_handle_data_packet(struct iwl_priv *priv, int is_data, | |||
277 | 277 | ||
278 | hdr = (void *)rxb->skb->data; | 278 | hdr = (void *)rxb->skb->data; |
279 | 279 | ||
280 | if (iwl_param_hwcrypto) | 280 | if (iwl3945_param_hwcrypto) |
281 | iwl_set_decrypted_flag(priv, rxb->skb, | 281 | iwl3945_set_decrypted_flag(priv, rxb->skb, |
282 | le32_to_cpu(rx_end->status), stats); | 282 | le32_to_cpu(rx_end->status), stats); |
283 | 283 | ||
284 | ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); | 284 | ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); |
285 | rxb->skb = NULL; | 285 | rxb->skb = NULL; |
286 | } | 286 | } |
287 | 287 | ||
288 | static void iwl3945_rx_reply_rx(struct iwl_priv *priv, | 288 | static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv, |
289 | struct iwl_rx_mem_buffer *rxb) | 289 | struct iwl3945_rx_mem_buffer *rxb) |
290 | { | 290 | { |
291 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | 291 | struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; |
292 | struct iwl_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); | 292 | struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); |
293 | struct iwl_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); | 293 | struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); |
294 | struct iwl_rx_frame_end *rx_end = IWL_RX_END(pkt); | 294 | struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); |
295 | struct ieee80211_hdr *header; | 295 | struct ieee80211_hdr *header; |
296 | u16 phy_flags = le16_to_cpu(rx_hdr->phy_flags); | 296 | u16 phy_flags = le16_to_cpu(rx_hdr->phy_flags); |
297 | u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg); | 297 | u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg); |
@@ -347,14 +347,14 @@ static void iwl3945_rx_reply_rx(struct iwl_priv *priv, | |||
347 | * Calculate stats.signal (quality indicator in %) based on SNR. */ | 347 | * Calculate stats.signal (quality indicator in %) based on SNR. */ |
348 | if (rx_stats_noise_diff) { | 348 | if (rx_stats_noise_diff) { |
349 | snr = rx_stats_sig_avg / rx_stats_noise_diff; | 349 | snr = rx_stats_sig_avg / rx_stats_noise_diff; |
350 | stats.noise = stats.ssi - iwl_calc_db_from_ratio(snr); | 350 | stats.noise = stats.ssi - iwl3945_calc_db_from_ratio(snr); |
351 | stats.signal = iwl_calc_sig_qual(stats.ssi, stats.noise); | 351 | stats.signal = iwl3945_calc_sig_qual(stats.ssi, stats.noise); |
352 | 352 | ||
353 | /* If noise info not available, calculate signal quality indicator (%) | 353 | /* If noise info not available, calculate signal quality indicator (%) |
354 | * using just the dBm signal level. */ | 354 | * using just the dBm signal level. */ |
355 | } else { | 355 | } else { |
356 | stats.noise = priv->last_rx_noise; | 356 | stats.noise = priv->last_rx_noise; |
357 | stats.signal = iwl_calc_sig_qual(stats.ssi, 0); | 357 | stats.signal = iwl3945_calc_sig_qual(stats.ssi, 0); |
358 | } | 358 | } |
359 | 359 | ||
360 | 360 | ||
@@ -364,24 +364,24 @@ static void iwl3945_rx_reply_rx(struct iwl_priv *priv, | |||
364 | 364 | ||
365 | stats.freq = ieee80211chan2mhz(stats.channel); | 365 | stats.freq = ieee80211chan2mhz(stats.channel); |
366 | 366 | ||
367 | /* can be covered by iwl_report_frame() in most cases */ | 367 | /* can be covered by iwl3945_report_frame() in most cases */ |
368 | /* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */ | 368 | /* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */ |
369 | 369 | ||
370 | header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); | 370 | header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); |
371 | 371 | ||
372 | network_packet = iwl_is_network_packet(priv, header); | 372 | network_packet = iwl3945_is_network_packet(priv, header); |
373 | 373 | ||
374 | #ifdef CONFIG_IWL3945_DEBUG | 374 | #ifdef CONFIG_IWL3945_DEBUG |
375 | if (iwl_debug_level & IWL_DL_STATS && net_ratelimit()) | 375 | if (iwl3945_debug_level & IWL_DL_STATS && net_ratelimit()) |
376 | IWL_DEBUG_STATS | 376 | IWL_DEBUG_STATS |
377 | ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n", | 377 | ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n", |
378 | network_packet ? '*' : ' ', | 378 | network_packet ? '*' : ' ', |
379 | stats.channel, stats.ssi, stats.ssi, | 379 | stats.channel, stats.ssi, stats.ssi, |
380 | stats.ssi, stats.rate); | 380 | stats.ssi, stats.rate); |
381 | 381 | ||
382 | if (iwl_debug_level & (IWL_DL_RX)) | 382 | if (iwl3945_debug_level & (IWL_DL_RX)) |
383 | /* Set "1" to report good data frames in groups of 100 */ | 383 | /* Set "1" to report good data frames in groups of 100 */ |
384 | iwl_report_frame(priv, pkt, header, 1); | 384 | iwl3945_report_frame(priv, pkt, header, 1); |
385 | #endif | 385 | #endif |
386 | 386 | ||
387 | if (network_packet) { | 387 | if (network_packet) { |
@@ -481,7 +481,7 @@ static void iwl3945_rx_reply_rx(struct iwl_priv *priv, | |||
481 | DECLARE_MAC_BUF(mac2); | 481 | DECLARE_MAC_BUF(mac2); |
482 | DECLARE_MAC_BUF(mac3); | 482 | DECLARE_MAC_BUF(mac3); |
483 | 483 | ||
484 | if (unlikely(is_duplicate_packet(priv, header))) | 484 | if (unlikely(iwl3945_is_duplicate_packet(priv, header))) |
485 | IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n", | 485 | IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n", |
486 | print_mac(mac1, header->addr1), | 486 | print_mac(mac1, header->addr1), |
487 | print_mac(mac2, header->addr2), | 487 | print_mac(mac2, header->addr2), |
@@ -494,12 +494,12 @@ static void iwl3945_rx_reply_rx(struct iwl_priv *priv, | |||
494 | } | 494 | } |
495 | } | 495 | } |
496 | 496 | ||
497 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, | 497 | int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr, |
498 | dma_addr_t addr, u16 len) | 498 | dma_addr_t addr, u16 len) |
499 | { | 499 | { |
500 | int count; | 500 | int count; |
501 | u32 pad; | 501 | u32 pad; |
502 | struct iwl_tfd_frame *tfd = (struct iwl_tfd_frame *)ptr; | 502 | struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr; |
503 | 503 | ||
504 | count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); | 504 | count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); |
505 | pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags)); | 505 | pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags)); |
@@ -522,14 +522,14 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr, | |||
522 | } | 522 | } |
523 | 523 | ||
524 | /** | 524 | /** |
525 | * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr] | 525 | * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr] |
526 | * | 526 | * |
527 | * Does NOT advance any indexes | 527 | * Does NOT advance any indexes |
528 | */ | 528 | */ |
529 | int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | 529 | int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) |
530 | { | 530 | { |
531 | struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0]; | 531 | struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0]; |
532 | struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; | 532 | struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; |
533 | struct pci_dev *dev = priv->pci_dev; | 533 | struct pci_dev *dev = priv->pci_dev; |
534 | int i; | 534 | int i; |
535 | int counter; | 535 | int counter; |
@@ -564,7 +564,7 @@ int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |||
564 | return 0; | 564 | return 0; |
565 | } | 565 | } |
566 | 566 | ||
567 | u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr) | 567 | u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr) |
568 | { | 568 | { |
569 | int i; | 569 | int i; |
570 | int ret = IWL_INVALID_STATION; | 570 | int ret = IWL_INVALID_STATION; |
@@ -588,11 +588,11 @@ u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr) | |||
588 | } | 588 | } |
589 | 589 | ||
590 | /** | 590 | /** |
591 | * iwl_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: | 591 | * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: |
592 | * | 592 | * |
593 | */ | 593 | */ |
594 | void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv, | 594 | void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv, |
595 | struct iwl_cmd *cmd, | 595 | struct iwl3945_cmd *cmd, |
596 | struct ieee80211_tx_control *ctrl, | 596 | struct ieee80211_tx_control *ctrl, |
597 | struct ieee80211_hdr *hdr, int sta_id, int tx_id) | 597 | struct ieee80211_hdr *hdr, int sta_id, int tx_id) |
598 | { | 598 | { |
@@ -605,7 +605,7 @@ void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv, | |||
605 | __le32 tx_flags; | 605 | __le32 tx_flags; |
606 | u16 fc = le16_to_cpu(hdr->frame_control); | 606 | u16 fc = le16_to_cpu(hdr->frame_control); |
607 | 607 | ||
608 | rate = iwl_rates[rate_index].plcp; | 608 | rate = iwl3945_rates[rate_index].plcp; |
609 | tx_flags = cmd->cmd.tx.tx_flags; | 609 | tx_flags = cmd->cmd.tx.tx_flags; |
610 | 610 | ||
611 | /* We need to figure out how to get the sta->supp_rates while | 611 | /* We need to figure out how to get the sta->supp_rates while |
@@ -672,10 +672,10 @@ void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv, | |||
672 | cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]); | 672 | cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]); |
673 | } | 673 | } |
674 | 674 | ||
675 | u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags) | 675 | u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags) |
676 | { | 676 | { |
677 | unsigned long flags_spin; | 677 | unsigned long flags_spin; |
678 | struct iwl_station_entry *station; | 678 | struct iwl3945_station_entry *station; |
679 | 679 | ||
680 | if (sta_id == IWL_INVALID_STATION) | 680 | if (sta_id == IWL_INVALID_STATION) |
681 | return IWL_INVALID_STATION; | 681 | return IWL_INVALID_STATION; |
@@ -690,19 +690,19 @@ u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags) | |||
690 | 690 | ||
691 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | 691 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); |
692 | 692 | ||
693 | iwl_send_add_station(priv, &station->sta, flags); | 693 | iwl3945_send_add_station(priv, &station->sta, flags); |
694 | IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n", | 694 | IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n", |
695 | sta_id, tx_rate); | 695 | sta_id, tx_rate); |
696 | return sta_id; | 696 | return sta_id; |
697 | } | 697 | } |
698 | 698 | ||
699 | static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) | 699 | static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max) |
700 | { | 700 | { |
701 | int rc; | 701 | int rc; |
702 | unsigned long flags; | 702 | unsigned long flags; |
703 | 703 | ||
704 | spin_lock_irqsave(&priv->lock, flags); | 704 | spin_lock_irqsave(&priv->lock, flags); |
705 | rc = iwl_grab_nic_access(priv); | 705 | rc = iwl3945_grab_nic_access(priv); |
706 | if (rc) { | 706 | if (rc) { |
707 | spin_unlock_irqrestore(&priv->lock, flags); | 707 | spin_unlock_irqrestore(&priv->lock, flags); |
708 | return rc; | 708 | return rc; |
@@ -714,23 +714,23 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) | |||
714 | rc = pci_read_config_dword(priv->pci_dev, | 714 | rc = pci_read_config_dword(priv->pci_dev, |
715 | PCI_POWER_SOURCE, &val); | 715 | PCI_POWER_SOURCE, &val); |
716 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { | 716 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { |
717 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | 717 | iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
718 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | 718 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
719 | ~APMG_PS_CTRL_MSK_PWR_SRC); | 719 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
720 | iwl_release_nic_access(priv); | 720 | iwl3945_release_nic_access(priv); |
721 | 721 | ||
722 | iwl_poll_bit(priv, CSR_GPIO_IN, | 722 | iwl3945_poll_bit(priv, CSR_GPIO_IN, |
723 | CSR_GPIO_IN_VAL_VAUX_PWR_SRC, | 723 | CSR_GPIO_IN_VAL_VAUX_PWR_SRC, |
724 | CSR_GPIO_IN_BIT_AUX_POWER, 5000); | 724 | CSR_GPIO_IN_BIT_AUX_POWER, 5000); |
725 | } else | 725 | } else |
726 | iwl_release_nic_access(priv); | 726 | iwl3945_release_nic_access(priv); |
727 | } else { | 727 | } else { |
728 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | 728 | iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
729 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | 729 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
730 | ~APMG_PS_CTRL_MSK_PWR_SRC); | 730 | ~APMG_PS_CTRL_MSK_PWR_SRC); |
731 | 731 | ||
732 | iwl_release_nic_access(priv); | 732 | iwl3945_release_nic_access(priv); |
733 | iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, | 733 | iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, |
734 | CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ | 734 | CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ |
735 | } | 735 | } |
736 | spin_unlock_irqrestore(&priv->lock, flags); | 736 | spin_unlock_irqrestore(&priv->lock, flags); |
@@ -738,24 +738,24 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) | |||
738 | return rc; | 738 | return rc; |
739 | } | 739 | } |
740 | 740 | ||
741 | static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | 741 | static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) |
742 | { | 742 | { |
743 | int rc; | 743 | int rc; |
744 | unsigned long flags; | 744 | unsigned long flags; |
745 | 745 | ||
746 | spin_lock_irqsave(&priv->lock, flags); | 746 | spin_lock_irqsave(&priv->lock, flags); |
747 | rc = iwl_grab_nic_access(priv); | 747 | rc = iwl3945_grab_nic_access(priv); |
748 | if (rc) { | 748 | if (rc) { |
749 | spin_unlock_irqrestore(&priv->lock, flags); | 749 | spin_unlock_irqrestore(&priv->lock, flags); |
750 | return rc; | 750 | return rc; |
751 | } | 751 | } |
752 | 752 | ||
753 | iwl_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); | 753 | iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); |
754 | iwl_write_direct32(priv, FH_RCSR_RPTR_ADDR(0), | 754 | iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0), |
755 | priv->hw_setting.shared_phys + | 755 | priv->hw_setting.shared_phys + |
756 | offsetof(struct iwl_shared, rx_read_ptr[0])); | 756 | offsetof(struct iwl3945_shared, rx_read_ptr[0])); |
757 | iwl_write_direct32(priv, FH_RCSR_WPTR(0), 0); | 757 | iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0); |
758 | iwl_write_direct32(priv, FH_RCSR_CONFIG(0), | 758 | iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), |
759 | ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | | 759 | ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | |
760 | ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | | 760 | ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | |
761 | ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | | 761 | ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | |
@@ -766,44 +766,44 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) | |||
766 | ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); | 766 | ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); |
767 | 767 | ||
768 | /* fake read to flush all prev I/O */ | 768 | /* fake read to flush all prev I/O */ |
769 | iwl_read_direct32(priv, FH_RSSR_CTRL); | 769 | iwl3945_read_direct32(priv, FH_RSSR_CTRL); |
770 | 770 | ||
771 | iwl_release_nic_access(priv); | 771 | iwl3945_release_nic_access(priv); |
772 | spin_unlock_irqrestore(&priv->lock, flags); | 772 | spin_unlock_irqrestore(&priv->lock, flags); |
773 | 773 | ||
774 | return 0; | 774 | return 0; |
775 | } | 775 | } |
776 | 776 | ||
777 | static int iwl3945_tx_reset(struct iwl_priv *priv) | 777 | static int iwl3945_tx_reset(struct iwl3945_priv *priv) |
778 | { | 778 | { |
779 | int rc; | 779 | int rc; |
780 | unsigned long flags; | 780 | unsigned long flags; |
781 | 781 | ||
782 | spin_lock_irqsave(&priv->lock, flags); | 782 | spin_lock_irqsave(&priv->lock, flags); |
783 | rc = iwl_grab_nic_access(priv); | 783 | rc = iwl3945_grab_nic_access(priv); |
784 | if (rc) { | 784 | if (rc) { |
785 | spin_unlock_irqrestore(&priv->lock, flags); | 785 | spin_unlock_irqrestore(&priv->lock, flags); |
786 | return rc; | 786 | return rc; |
787 | } | 787 | } |
788 | 788 | ||
789 | /* bypass mode */ | 789 | /* bypass mode */ |
790 | iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2); | 790 | iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2); |
791 | 791 | ||
792 | /* RA 0 is active */ | 792 | /* RA 0 is active */ |
793 | iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); | 793 | iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); |
794 | 794 | ||
795 | /* all 6 fifo are active */ | 795 | /* all 6 fifo are active */ |
796 | iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); | 796 | iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); |
797 | 797 | ||
798 | iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); | 798 | iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); |
799 | iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); | 799 | iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); |
800 | iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); | 800 | iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); |
801 | iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); | 801 | iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); |
802 | 802 | ||
803 | iwl_write_direct32(priv, FH_TSSR_CBB_BASE, | 803 | iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE, |
804 | priv->hw_setting.shared_phys); | 804 | priv->hw_setting.shared_phys); |
805 | 805 | ||
806 | iwl_write_direct32(priv, FH_TSSR_MSG_CONFIG, | 806 | iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG, |
807 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | | 807 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | |
808 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | | 808 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | |
809 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | | 809 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | |
@@ -812,7 +812,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv) | |||
812 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | | 812 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | |
813 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); | 813 | ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); |
814 | 814 | ||
815 | iwl_release_nic_access(priv); | 815 | iwl3945_release_nic_access(priv); |
816 | spin_unlock_irqrestore(&priv->lock, flags); | 816 | spin_unlock_irqrestore(&priv->lock, flags); |
817 | 817 | ||
818 | return 0; | 818 | return 0; |
@@ -823,12 +823,12 @@ static int iwl3945_tx_reset(struct iwl_priv *priv) | |||
823 | * | 823 | * |
824 | * Destroys all DMA structures and initialize them again | 824 | * Destroys all DMA structures and initialize them again |
825 | */ | 825 | */ |
826 | static int iwl3945_txq_ctx_reset(struct iwl_priv *priv) | 826 | static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv) |
827 | { | 827 | { |
828 | int rc; | 828 | int rc; |
829 | int txq_id, slots_num; | 829 | int txq_id, slots_num; |
830 | 830 | ||
831 | iwl_hw_txq_ctx_free(priv); | 831 | iwl3945_hw_txq_ctx_free(priv); |
832 | 832 | ||
833 | /* Tx CMD queue */ | 833 | /* Tx CMD queue */ |
834 | rc = iwl3945_tx_reset(priv); | 834 | rc = iwl3945_tx_reset(priv); |
@@ -839,7 +839,7 @@ static int iwl3945_txq_ctx_reset(struct iwl_priv *priv) | |||
839 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) { | 839 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) { |
840 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | 840 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? |
841 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | 841 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; |
842 | rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, | 842 | rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num, |
843 | txq_id); | 843 | txq_id); |
844 | if (rc) { | 844 | if (rc) { |
845 | IWL_ERROR("Tx %d queue init failed\n", txq_id); | 845 | IWL_ERROR("Tx %d queue init failed\n", txq_id); |
@@ -850,26 +850,26 @@ static int iwl3945_txq_ctx_reset(struct iwl_priv *priv) | |||
850 | return rc; | 850 | return rc; |
851 | 851 | ||
852 | error: | 852 | error: |
853 | iwl_hw_txq_ctx_free(priv); | 853 | iwl3945_hw_txq_ctx_free(priv); |
854 | return rc; | 854 | return rc; |
855 | } | 855 | } |
856 | 856 | ||
857 | int iwl_hw_nic_init(struct iwl_priv *priv) | 857 | int iwl3945_hw_nic_init(struct iwl3945_priv *priv) |
858 | { | 858 | { |
859 | u8 rev_id; | 859 | u8 rev_id; |
860 | int rc; | 860 | int rc; |
861 | unsigned long flags; | 861 | unsigned long flags; |
862 | struct iwl_rx_queue *rxq = &priv->rxq; | 862 | struct iwl3945_rx_queue *rxq = &priv->rxq; |
863 | 863 | ||
864 | iwl_power_init_handle(priv); | 864 | iwl3945_power_init_handle(priv); |
865 | 865 | ||
866 | spin_lock_irqsave(&priv->lock, flags); | 866 | spin_lock_irqsave(&priv->lock, flags); |
867 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24)); | 867 | iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24)); |
868 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | 868 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
869 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | 869 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
870 | 870 | ||
871 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | 871 | iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
872 | rc = iwl_poll_bit(priv, CSR_GP_CNTRL, | 872 | rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL, |
873 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | 873 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
874 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | 874 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
875 | if (rc < 0) { | 875 | if (rc < 0) { |
@@ -878,18 +878,18 @@ int iwl_hw_nic_init(struct iwl_priv *priv) | |||
878 | return rc; | 878 | return rc; |
879 | } | 879 | } |
880 | 880 | ||
881 | rc = iwl_grab_nic_access(priv); | 881 | rc = iwl3945_grab_nic_access(priv); |
882 | if (rc) { | 882 | if (rc) { |
883 | spin_unlock_irqrestore(&priv->lock, flags); | 883 | spin_unlock_irqrestore(&priv->lock, flags); |
884 | return rc; | 884 | return rc; |
885 | } | 885 | } |
886 | iwl_write_prph(priv, APMG_CLK_EN_REG, | 886 | iwl3945_write_prph(priv, APMG_CLK_EN_REG, |
887 | APMG_CLK_VAL_DMA_CLK_RQT | | 887 | APMG_CLK_VAL_DMA_CLK_RQT | |
888 | APMG_CLK_VAL_BSM_CLK_RQT); | 888 | APMG_CLK_VAL_BSM_CLK_RQT); |
889 | udelay(20); | 889 | udelay(20); |
890 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | 890 | iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
891 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | 891 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
892 | iwl_release_nic_access(priv); | 892 | iwl3945_release_nic_access(priv); |
893 | spin_unlock_irqrestore(&priv->lock, flags); | 893 | spin_unlock_irqrestore(&priv->lock, flags); |
894 | 894 | ||
895 | /* Determine HW type */ | 895 | /* Determine HW type */ |
@@ -905,25 +905,25 @@ int iwl_hw_nic_init(struct iwl_priv *priv) | |||
905 | IWL_DEBUG_INFO("RTP type \n"); | 905 | IWL_DEBUG_INFO("RTP type \n"); |
906 | else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { | 906 | else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { |
907 | IWL_DEBUG_INFO("ALM-MB type\n"); | 907 | IWL_DEBUG_INFO("ALM-MB type\n"); |
908 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | 908 | iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
909 | CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB); | 909 | CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB); |
910 | } else { | 910 | } else { |
911 | IWL_DEBUG_INFO("ALM-MM type\n"); | 911 | IWL_DEBUG_INFO("ALM-MM type\n"); |
912 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | 912 | iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
913 | CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM); | 913 | CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM); |
914 | } | 914 | } |
915 | 915 | ||
916 | spin_unlock_irqrestore(&priv->lock, flags); | 916 | spin_unlock_irqrestore(&priv->lock, flags); |
917 | 917 | ||
918 | /* Initialize the EEPROM */ | 918 | /* Initialize the EEPROM */ |
919 | rc = iwl_eeprom_init(priv); | 919 | rc = iwl3945_eeprom_init(priv); |
920 | if (rc) | 920 | if (rc) |
921 | return rc; | 921 | return rc; |
922 | 922 | ||
923 | spin_lock_irqsave(&priv->lock, flags); | 923 | spin_lock_irqsave(&priv->lock, flags); |
924 | if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) { | 924 | if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) { |
925 | IWL_DEBUG_INFO("SKU OP mode is mrc\n"); | 925 | IWL_DEBUG_INFO("SKU OP mode is mrc\n"); |
926 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | 926 | iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
927 | CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC); | 927 | CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC); |
928 | } else | 928 | } else |
929 | IWL_DEBUG_INFO("SKU OP mode is basic\n"); | 929 | IWL_DEBUG_INFO("SKU OP mode is basic\n"); |
@@ -931,24 +931,24 @@ int iwl_hw_nic_init(struct iwl_priv *priv) | |||
931 | if ((priv->eeprom.board_revision & 0xF0) == 0xD0) { | 931 | if ((priv->eeprom.board_revision & 0xF0) == 0xD0) { |
932 | IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", | 932 | IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", |
933 | priv->eeprom.board_revision); | 933 | priv->eeprom.board_revision); |
934 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | 934 | iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
935 | CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); | 935 | CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); |
936 | } else { | 936 | } else { |
937 | IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", | 937 | IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", |
938 | priv->eeprom.board_revision); | 938 | priv->eeprom.board_revision); |
939 | iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG, | 939 | iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG, |
940 | CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); | 940 | CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); |
941 | } | 941 | } |
942 | 942 | ||
943 | if (priv->eeprom.almgor_m_version <= 1) { | 943 | if (priv->eeprom.almgor_m_version <= 1) { |
944 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | 944 | iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
945 | CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); | 945 | CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); |
946 | IWL_DEBUG_INFO("Card M type A version is 0x%X\n", | 946 | IWL_DEBUG_INFO("Card M type A version is 0x%X\n", |
947 | priv->eeprom.almgor_m_version); | 947 | priv->eeprom.almgor_m_version); |
948 | } else { | 948 | } else { |
949 | IWL_DEBUG_INFO("Card M type B version is 0x%X\n", | 949 | IWL_DEBUG_INFO("Card M type B version is 0x%X\n", |
950 | priv->eeprom.almgor_m_version); | 950 | priv->eeprom.almgor_m_version); |
951 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | 951 | iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
952 | CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); | 952 | CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); |
953 | } | 953 | } |
954 | spin_unlock_irqrestore(&priv->lock, flags); | 954 | spin_unlock_irqrestore(&priv->lock, flags); |
@@ -961,15 +961,15 @@ int iwl_hw_nic_init(struct iwl_priv *priv) | |||
961 | 961 | ||
962 | /* Allocate the RX queue, or reset if it is already allocated */ | 962 | /* Allocate the RX queue, or reset if it is already allocated */ |
963 | if (!rxq->bd) { | 963 | if (!rxq->bd) { |
964 | rc = iwl_rx_queue_alloc(priv); | 964 | rc = iwl3945_rx_queue_alloc(priv); |
965 | if (rc) { | 965 | if (rc) { |
966 | IWL_ERROR("Unable to initialize Rx queue\n"); | 966 | IWL_ERROR("Unable to initialize Rx queue\n"); |
967 | return -ENOMEM; | 967 | return -ENOMEM; |
968 | } | 968 | } |
969 | } else | 969 | } else |
970 | iwl_rx_queue_reset(priv, rxq); | 970 | iwl3945_rx_queue_reset(priv, rxq); |
971 | 971 | ||
972 | iwl_rx_replenish(priv); | 972 | iwl3945_rx_replenish(priv); |
973 | 973 | ||
974 | iwl3945_rx_init(priv, rxq); | 974 | iwl3945_rx_init(priv, rxq); |
975 | 975 | ||
@@ -977,16 +977,16 @@ int iwl_hw_nic_init(struct iwl_priv *priv) | |||
977 | 977 | ||
978 | /* Look at using this instead: | 978 | /* Look at using this instead: |
979 | rxq->need_update = 1; | 979 | rxq->need_update = 1; |
980 | iwl_rx_queue_update_write_ptr(priv, rxq); | 980 | iwl3945_rx_queue_update_write_ptr(priv, rxq); |
981 | */ | 981 | */ |
982 | 982 | ||
983 | rc = iwl_grab_nic_access(priv); | 983 | rc = iwl3945_grab_nic_access(priv); |
984 | if (rc) { | 984 | if (rc) { |
985 | spin_unlock_irqrestore(&priv->lock, flags); | 985 | spin_unlock_irqrestore(&priv->lock, flags); |
986 | return rc; | 986 | return rc; |
987 | } | 987 | } |
988 | iwl_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7); | 988 | iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7); |
989 | iwl_release_nic_access(priv); | 989 | iwl3945_release_nic_access(priv); |
990 | 990 | ||
991 | spin_unlock_irqrestore(&priv->lock, flags); | 991 | spin_unlock_irqrestore(&priv->lock, flags); |
992 | 992 | ||
@@ -1000,49 +1000,49 @@ int iwl_hw_nic_init(struct iwl_priv *priv) | |||
1000 | } | 1000 | } |
1001 | 1001 | ||
1002 | /** | 1002 | /** |
1003 | * iwl_hw_txq_ctx_free - Free TXQ Context | 1003 | * iwl3945_hw_txq_ctx_free - Free TXQ Context |
1004 | * | 1004 | * |
1005 | * Destroy all TX DMA queues and structures | 1005 | * Destroy all TX DMA queues and structures |
1006 | */ | 1006 | */ |
1007 | void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | 1007 | void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv) |
1008 | { | 1008 | { |
1009 | int txq_id; | 1009 | int txq_id; |
1010 | 1010 | ||
1011 | /* Tx queues */ | 1011 | /* Tx queues */ |
1012 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) | 1012 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) |
1013 | iwl_tx_queue_free(priv, &priv->txq[txq_id]); | 1013 | iwl3945_tx_queue_free(priv, &priv->txq[txq_id]); |
1014 | } | 1014 | } |
1015 | 1015 | ||
1016 | void iwl_hw_txq_ctx_stop(struct iwl_priv *priv) | 1016 | void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv) |
1017 | { | 1017 | { |
1018 | int queue; | 1018 | int queue; |
1019 | unsigned long flags; | 1019 | unsigned long flags; |
1020 | 1020 | ||
1021 | spin_lock_irqsave(&priv->lock, flags); | 1021 | spin_lock_irqsave(&priv->lock, flags); |
1022 | if (iwl_grab_nic_access(priv)) { | 1022 | if (iwl3945_grab_nic_access(priv)) { |
1023 | spin_unlock_irqrestore(&priv->lock, flags); | 1023 | spin_unlock_irqrestore(&priv->lock, flags); |
1024 | iwl_hw_txq_ctx_free(priv); | 1024 | iwl3945_hw_txq_ctx_free(priv); |
1025 | return; | 1025 | return; |
1026 | } | 1026 | } |
1027 | 1027 | ||
1028 | /* stop SCD */ | 1028 | /* stop SCD */ |
1029 | iwl_write_prph(priv, ALM_SCD_MODE_REG, 0); | 1029 | iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0); |
1030 | 1030 | ||
1031 | /* reset TFD queues */ | 1031 | /* reset TFD queues */ |
1032 | for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { | 1032 | for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { |
1033 | iwl_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0); | 1033 | iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0); |
1034 | iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS, | 1034 | iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS, |
1035 | ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue), | 1035 | ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue), |
1036 | 1000); | 1036 | 1000); |
1037 | } | 1037 | } |
1038 | 1038 | ||
1039 | iwl_release_nic_access(priv); | 1039 | iwl3945_release_nic_access(priv); |
1040 | spin_unlock_irqrestore(&priv->lock, flags); | 1040 | spin_unlock_irqrestore(&priv->lock, flags); |
1041 | 1041 | ||
1042 | iwl_hw_txq_ctx_free(priv); | 1042 | iwl3945_hw_txq_ctx_free(priv); |
1043 | } | 1043 | } |
1044 | 1044 | ||
1045 | int iwl_hw_nic_stop_master(struct iwl_priv *priv) | 1045 | int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv) |
1046 | { | 1046 | { |
1047 | int rc = 0; | 1047 | int rc = 0; |
1048 | u32 reg_val; | 1048 | u32 reg_val; |
@@ -1051,16 +1051,16 @@ int iwl_hw_nic_stop_master(struct iwl_priv *priv) | |||
1051 | spin_lock_irqsave(&priv->lock, flags); | 1051 | spin_lock_irqsave(&priv->lock, flags); |
1052 | 1052 | ||
1053 | /* set stop master bit */ | 1053 | /* set stop master bit */ |
1054 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | 1054 | iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
1055 | 1055 | ||
1056 | reg_val = iwl_read32(priv, CSR_GP_CNTRL); | 1056 | reg_val = iwl3945_read32(priv, CSR_GP_CNTRL); |
1057 | 1057 | ||
1058 | if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == | 1058 | if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == |
1059 | (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) | 1059 | (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) |
1060 | IWL_DEBUG_INFO("Card in power save, master is already " | 1060 | IWL_DEBUG_INFO("Card in power save, master is already " |
1061 | "stopped\n"); | 1061 | "stopped\n"); |
1062 | else { | 1062 | else { |
1063 | rc = iwl_poll_bit(priv, CSR_RESET, | 1063 | rc = iwl3945_poll_bit(priv, CSR_RESET, |
1064 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | 1064 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
1065 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | 1065 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
1066 | if (rc < 0) { | 1066 | if (rc < 0) { |
@@ -1075,47 +1075,47 @@ int iwl_hw_nic_stop_master(struct iwl_priv *priv) | |||
1075 | return rc; | 1075 | return rc; |
1076 | } | 1076 | } |
1077 | 1077 | ||
1078 | int iwl_hw_nic_reset(struct iwl_priv *priv) | 1078 | int iwl3945_hw_nic_reset(struct iwl3945_priv *priv) |
1079 | { | 1079 | { |
1080 | int rc; | 1080 | int rc; |
1081 | unsigned long flags; | 1081 | unsigned long flags; |
1082 | 1082 | ||
1083 | iwl_hw_nic_stop_master(priv); | 1083 | iwl3945_hw_nic_stop_master(priv); |
1084 | 1084 | ||
1085 | spin_lock_irqsave(&priv->lock, flags); | 1085 | spin_lock_irqsave(&priv->lock, flags); |
1086 | 1086 | ||
1087 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | 1087 | iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
1088 | 1088 | ||
1089 | rc = iwl_poll_bit(priv, CSR_GP_CNTRL, | 1089 | rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL, |
1090 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | 1090 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
1091 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | 1091 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
1092 | 1092 | ||
1093 | rc = iwl_grab_nic_access(priv); | 1093 | rc = iwl3945_grab_nic_access(priv); |
1094 | if (!rc) { | 1094 | if (!rc) { |
1095 | iwl_write_prph(priv, APMG_CLK_CTRL_REG, | 1095 | iwl3945_write_prph(priv, APMG_CLK_CTRL_REG, |
1096 | APMG_CLK_VAL_BSM_CLK_RQT); | 1096 | APMG_CLK_VAL_BSM_CLK_RQT); |
1097 | 1097 | ||
1098 | udelay(10); | 1098 | udelay(10); |
1099 | 1099 | ||
1100 | iwl_set_bit(priv, CSR_GP_CNTRL, | 1100 | iwl3945_set_bit(priv, CSR_GP_CNTRL, |
1101 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | 1101 | CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
1102 | 1102 | ||
1103 | iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); | 1103 | iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); |
1104 | iwl_write_prph(priv, APMG_RTC_INT_STT_REG, | 1104 | iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG, |
1105 | 0xFFFFFFFF); | 1105 | 0xFFFFFFFF); |
1106 | 1106 | ||
1107 | /* enable DMA */ | 1107 | /* enable DMA */ |
1108 | iwl_write_prph(priv, APMG_CLK_EN_REG, | 1108 | iwl3945_write_prph(priv, APMG_CLK_EN_REG, |
1109 | APMG_CLK_VAL_DMA_CLK_RQT | | 1109 | APMG_CLK_VAL_DMA_CLK_RQT | |
1110 | APMG_CLK_VAL_BSM_CLK_RQT); | 1110 | APMG_CLK_VAL_BSM_CLK_RQT); |
1111 | udelay(10); | 1111 | udelay(10); |
1112 | 1112 | ||
1113 | iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, | 1113 | iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG, |
1114 | APMG_PS_CTRL_VAL_RESET_REQ); | 1114 | APMG_PS_CTRL_VAL_RESET_REQ); |
1115 | udelay(5); | 1115 | udelay(5); |
1116 | iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, | 1116 | iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG, |
1117 | APMG_PS_CTRL_VAL_RESET_REQ); | 1117 | APMG_PS_CTRL_VAL_RESET_REQ); |
1118 | iwl_release_nic_access(priv); | 1118 | iwl3945_release_nic_access(priv); |
1119 | } | 1119 | } |
1120 | 1120 | ||
1121 | /* Clear the 'host command active' bit... */ | 1121 | /* Clear the 'host command active' bit... */ |
@@ -1128,43 +1128,43 @@ int iwl_hw_nic_reset(struct iwl_priv *priv) | |||
1128 | } | 1128 | } |
1129 | 1129 | ||
1130 | /** | 1130 | /** |
1131 | * iwl_hw_reg_adjust_power_by_temp | 1131 | * iwl3945_hw_reg_adjust_power_by_temp |
1132 | * return index delta into power gain settings table | 1132 | * return index delta into power gain settings table |
1133 | */ | 1133 | */ |
1134 | static int iwl_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) | 1134 | static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) |
1135 | { | 1135 | { |
1136 | return (new_reading - old_reading) * (-11) / 100; | 1136 | return (new_reading - old_reading) * (-11) / 100; |
1137 | } | 1137 | } |
1138 | 1138 | ||
1139 | /** | 1139 | /** |
1140 | * iwl_hw_reg_temp_out_of_range - Keep temperature in sane range | 1140 | * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range |
1141 | */ | 1141 | */ |
1142 | static inline int iwl_hw_reg_temp_out_of_range(int temperature) | 1142 | static inline int iwl3945_hw_reg_temp_out_of_range(int temperature) |
1143 | { | 1143 | { |
1144 | return (((temperature < -260) || (temperature > 25)) ? 1 : 0); | 1144 | return (((temperature < -260) || (temperature > 25)) ? 1 : 0); |
1145 | } | 1145 | } |
1146 | 1146 | ||
1147 | int iwl_hw_get_temperature(struct iwl_priv *priv) | 1147 | int iwl3945_hw_get_temperature(struct iwl3945_priv *priv) |
1148 | { | 1148 | { |
1149 | return iwl_read32(priv, CSR_UCODE_DRV_GP2); | 1149 | return iwl3945_read32(priv, CSR_UCODE_DRV_GP2); |
1150 | } | 1150 | } |
1151 | 1151 | ||
1152 | /** | 1152 | /** |
1153 | * iwl_hw_reg_txpower_get_temperature | 1153 | * iwl3945_hw_reg_txpower_get_temperature |
1154 | * get the current temperature by reading from NIC | 1154 | * get the current temperature by reading from NIC |
1155 | */ | 1155 | */ |
1156 | static int iwl_hw_reg_txpower_get_temperature(struct iwl_priv *priv) | 1156 | static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv) |
1157 | { | 1157 | { |
1158 | int temperature; | 1158 | int temperature; |
1159 | 1159 | ||
1160 | temperature = iwl_hw_get_temperature(priv); | 1160 | temperature = iwl3945_hw_get_temperature(priv); |
1161 | 1161 | ||
1162 | /* driver's okay range is -260 to +25. | 1162 | /* driver's okay range is -260 to +25. |
1163 | * human readable okay range is 0 to +285 */ | 1163 | * human readable okay range is 0 to +285 */ |
1164 | IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT); | 1164 | IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT); |
1165 | 1165 | ||
1166 | /* handle insane temp reading */ | 1166 | /* handle insane temp reading */ |
1167 | if (iwl_hw_reg_temp_out_of_range(temperature)) { | 1167 | if (iwl3945_hw_reg_temp_out_of_range(temperature)) { |
1168 | IWL_ERROR("Error bad temperature value %d\n", temperature); | 1168 | IWL_ERROR("Error bad temperature value %d\n", temperature); |
1169 | 1169 | ||
1170 | /* if really really hot(?), | 1170 | /* if really really hot(?), |
@@ -1189,11 +1189,11 @@ static int iwl_hw_reg_txpower_get_temperature(struct iwl_priv *priv) | |||
1189 | * records new temperature in tx_mgr->temperature. | 1189 | * records new temperature in tx_mgr->temperature. |
1190 | * replaces tx_mgr->last_temperature *only* if calib needed | 1190 | * replaces tx_mgr->last_temperature *only* if calib needed |
1191 | * (assumes caller will actually do the calibration!). */ | 1191 | * (assumes caller will actually do the calibration!). */ |
1192 | static int is_temp_calib_needed(struct iwl_priv *priv) | 1192 | static int is_temp_calib_needed(struct iwl3945_priv *priv) |
1193 | { | 1193 | { |
1194 | int temp_diff; | 1194 | int temp_diff; |
1195 | 1195 | ||
1196 | priv->temperature = iwl_hw_reg_txpower_get_temperature(priv); | 1196 | priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv); |
1197 | temp_diff = priv->temperature - priv->last_temperature; | 1197 | temp_diff = priv->temperature - priv->last_temperature; |
1198 | 1198 | ||
1199 | /* get absolute value */ | 1199 | /* get absolute value */ |
@@ -1225,7 +1225,7 @@ static int is_temp_calib_needed(struct iwl_priv *priv) | |||
1225 | 1225 | ||
1226 | /* radio and DSP power table, each step is 1/2 dB. | 1226 | /* radio and DSP power table, each step is 1/2 dB. |
1227 | * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */ | 1227 | * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */ |
1228 | static struct iwl_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = { | 1228 | static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = { |
1229 | { | 1229 | { |
1230 | {251, 127}, /* 2.4 GHz, highest power */ | 1230 | {251, 127}, /* 2.4 GHz, highest power */ |
1231 | {251, 127}, | 1231 | {251, 127}, |
@@ -1386,7 +1386,7 @@ static struct iwl_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = { | |||
1386 | {3, 120} } /* 5.x GHz, lowest power */ | 1386 | {3, 120} } /* 5.x GHz, lowest power */ |
1387 | }; | 1387 | }; |
1388 | 1388 | ||
1389 | static inline u8 iwl_hw_reg_fix_power_index(int index) | 1389 | static inline u8 iwl3945_hw_reg_fix_power_index(int index) |
1390 | { | 1390 | { |
1391 | if (index < 0) | 1391 | if (index < 0) |
1392 | return 0; | 1392 | return 0; |
@@ -1399,17 +1399,17 @@ static inline u8 iwl_hw_reg_fix_power_index(int index) | |||
1399 | #define REG_RECALIB_PERIOD (60) | 1399 | #define REG_RECALIB_PERIOD (60) |
1400 | 1400 | ||
1401 | /** | 1401 | /** |
1402 | * iwl_hw_reg_set_scan_power - Set Tx power for scan probe requests | 1402 | * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests |
1403 | * | 1403 | * |
1404 | * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) | 1404 | * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) |
1405 | * or 6 Mbit (OFDM) rates. | 1405 | * or 6 Mbit (OFDM) rates. |
1406 | */ | 1406 | */ |
1407 | static void iwl_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index, | 1407 | static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index, |
1408 | s32 rate_index, const s8 *clip_pwrs, | 1408 | s32 rate_index, const s8 *clip_pwrs, |
1409 | struct iwl_channel_info *ch_info, | 1409 | struct iwl3945_channel_info *ch_info, |
1410 | int band_index) | 1410 | int band_index) |
1411 | { | 1411 | { |
1412 | struct iwl_scan_power_info *scan_power_info; | 1412 | struct iwl3945_scan_power_info *scan_power_info; |
1413 | s8 power; | 1413 | s8 power; |
1414 | u8 power_index; | 1414 | u8 power_index; |
1415 | 1415 | ||
@@ -1445,7 +1445,7 @@ static void iwl_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index, | |||
1445 | * of the table. */ | 1445 | * of the table. */ |
1446 | 1446 | ||
1447 | /* don't exceed table bounds for "real" setting */ | 1447 | /* don't exceed table bounds for "real" setting */ |
1448 | power_index = iwl_hw_reg_fix_power_index(power_index); | 1448 | power_index = iwl3945_hw_reg_fix_power_index(power_index); |
1449 | 1449 | ||
1450 | scan_power_info->power_table_index = power_index; | 1450 | scan_power_info->power_table_index = power_index; |
1451 | scan_power_info->tpc.tx_gain = | 1451 | scan_power_info->tpc.tx_gain = |
@@ -1455,21 +1455,21 @@ static void iwl_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index, | |||
1455 | } | 1455 | } |
1456 | 1456 | ||
1457 | /** | 1457 | /** |
1458 | * iwl_hw_reg_send_txpower - fill in Tx Power command with gain settings | 1458 | * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings |
1459 | * | 1459 | * |
1460 | * Configures power settings for all rates for the current channel, | 1460 | * Configures power settings for all rates for the current channel, |
1461 | * using values from channel info struct, and send to NIC | 1461 | * using values from channel info struct, and send to NIC |
1462 | */ | 1462 | */ |
1463 | int iwl_hw_reg_send_txpower(struct iwl_priv *priv) | 1463 | int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv) |
1464 | { | 1464 | { |
1465 | int rate_idx, i; | 1465 | int rate_idx, i; |
1466 | const struct iwl_channel_info *ch_info = NULL; | 1466 | const struct iwl3945_channel_info *ch_info = NULL; |
1467 | struct iwl_txpowertable_cmd txpower = { | 1467 | struct iwl3945_txpowertable_cmd txpower = { |
1468 | .channel = priv->active_rxon.channel, | 1468 | .channel = priv->active_rxon.channel, |
1469 | }; | 1469 | }; |
1470 | 1470 | ||
1471 | txpower.band = (priv->phymode == MODE_IEEE80211A) ? 0 : 1; | 1471 | txpower.band = (priv->phymode == MODE_IEEE80211A) ? 0 : 1; |
1472 | ch_info = iwl_get_channel_info(priv, | 1472 | ch_info = iwl3945_get_channel_info(priv, |
1473 | priv->phymode, | 1473 | priv->phymode, |
1474 | le16_to_cpu(priv->active_rxon.channel)); | 1474 | le16_to_cpu(priv->active_rxon.channel)); |
1475 | if (!ch_info) { | 1475 | if (!ch_info) { |
@@ -1491,7 +1491,7 @@ int iwl_hw_reg_send_txpower(struct iwl_priv *priv) | |||
1491 | rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) { | 1491 | rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) { |
1492 | 1492 | ||
1493 | txpower.power[i].tpc = ch_info->power_info[i].tpc; | 1493 | txpower.power[i].tpc = ch_info->power_info[i].tpc; |
1494 | txpower.power[i].rate = iwl_rates[rate_idx].plcp; | 1494 | txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; |
1495 | 1495 | ||
1496 | IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", | 1496 | IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", |
1497 | le16_to_cpu(txpower.channel), | 1497 | le16_to_cpu(txpower.channel), |
@@ -1504,7 +1504,7 @@ int iwl_hw_reg_send_txpower(struct iwl_priv *priv) | |||
1504 | for (rate_idx = IWL_FIRST_CCK_RATE; | 1504 | for (rate_idx = IWL_FIRST_CCK_RATE; |
1505 | rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) { | 1505 | rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) { |
1506 | txpower.power[i].tpc = ch_info->power_info[i].tpc; | 1506 | txpower.power[i].tpc = ch_info->power_info[i].tpc; |
1507 | txpower.power[i].rate = iwl_rates[rate_idx].plcp; | 1507 | txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; |
1508 | 1508 | ||
1509 | IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", | 1509 | IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", |
1510 | le16_to_cpu(txpower.channel), | 1510 | le16_to_cpu(txpower.channel), |
@@ -1514,13 +1514,13 @@ int iwl_hw_reg_send_txpower(struct iwl_priv *priv) | |||
1514 | txpower.power[i].rate); | 1514 | txpower.power[i].rate); |
1515 | } | 1515 | } |
1516 | 1516 | ||
1517 | return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, | 1517 | return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, |
1518 | sizeof(struct iwl_txpowertable_cmd), &txpower); | 1518 | sizeof(struct iwl3945_txpowertable_cmd), &txpower); |
1519 | 1519 | ||
1520 | } | 1520 | } |
1521 | 1521 | ||
1522 | /** | 1522 | /** |
1523 | * iwl_hw_reg_set_new_power - Configures power tables at new levels | 1523 | * iwl3945_hw_reg_set_new_power - Configures power tables at new levels |
1524 | * @ch_info: Channel to update. Uses power_info.requested_power. | 1524 | * @ch_info: Channel to update. Uses power_info.requested_power. |
1525 | * | 1525 | * |
1526 | * Replace requested_power and base_power_index ch_info fields for | 1526 | * Replace requested_power and base_power_index ch_info fields for |
@@ -1535,10 +1535,10 @@ int iwl_hw_reg_send_txpower(struct iwl_priv *priv) | |||
1535 | * properly fill out the scan powers, and actual h/w gain settings, | 1535 | * properly fill out the scan powers, and actual h/w gain settings, |
1536 | * and send changes to NIC | 1536 | * and send changes to NIC |
1537 | */ | 1537 | */ |
1538 | static int iwl_hw_reg_set_new_power(struct iwl_priv *priv, | 1538 | static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv, |
1539 | struct iwl_channel_info *ch_info) | 1539 | struct iwl3945_channel_info *ch_info) |
1540 | { | 1540 | { |
1541 | struct iwl_channel_power_info *power_info; | 1541 | struct iwl3945_channel_power_info *power_info; |
1542 | int power_changed = 0; | 1542 | int power_changed = 0; |
1543 | int i; | 1543 | int i; |
1544 | const s8 *clip_pwrs; | 1544 | const s8 *clip_pwrs; |
@@ -1578,7 +1578,7 @@ static int iwl_hw_reg_set_new_power(struct iwl_priv *priv, | |||
1578 | ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]. | 1578 | ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]. |
1579 | requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF; | 1579 | requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF; |
1580 | 1580 | ||
1581 | /* do all CCK rates' iwl_channel_power_info structures */ | 1581 | /* do all CCK rates' iwl3945_channel_power_info structures */ |
1582 | for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) { | 1582 | for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) { |
1583 | power_info->requested_power = power; | 1583 | power_info->requested_power = power; |
1584 | power_info->base_power_index = | 1584 | power_info->base_power_index = |
@@ -1592,13 +1592,13 @@ static int iwl_hw_reg_set_new_power(struct iwl_priv *priv, | |||
1592 | } | 1592 | } |
1593 | 1593 | ||
1594 | /** | 1594 | /** |
1595 | * iwl_hw_reg_get_ch_txpower_limit - returns new power limit for channel | 1595 | * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel |
1596 | * | 1596 | * |
1597 | * NOTE: Returned power limit may be less (but not more) than requested, | 1597 | * NOTE: Returned power limit may be less (but not more) than requested, |
1598 | * based strictly on regulatory (eeprom and spectrum mgt) limitations | 1598 | * based strictly on regulatory (eeprom and spectrum mgt) limitations |
1599 | * (no consideration for h/w clipping limitations). | 1599 | * (no consideration for h/w clipping limitations). |
1600 | */ | 1600 | */ |
1601 | static int iwl_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info) | 1601 | static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info) |
1602 | { | 1602 | { |
1603 | s8 max_power; | 1603 | s8 max_power; |
1604 | 1604 | ||
@@ -1617,7 +1617,7 @@ static int iwl_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info) | |||
1617 | } | 1617 | } |
1618 | 1618 | ||
1619 | /** | 1619 | /** |
1620 | * iwl_hw_reg_comp_txpower_temp - Compensate for temperature | 1620 | * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature |
1621 | * | 1621 | * |
1622 | * Compensate txpower settings of *all* channels for temperature. | 1622 | * Compensate txpower settings of *all* channels for temperature. |
1623 | * This only accounts for the difference between current temperature | 1623 | * This only accounts for the difference between current temperature |
@@ -1626,9 +1626,9 @@ static int iwl_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info) | |||
1626 | * | 1626 | * |
1627 | * If RxOn is "associated", this sends the new Txpower to NIC! | 1627 | * If RxOn is "associated", this sends the new Txpower to NIC! |
1628 | */ | 1628 | */ |
1629 | static int iwl_hw_reg_comp_txpower_temp(struct iwl_priv *priv) | 1629 | static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv) |
1630 | { | 1630 | { |
1631 | struct iwl_channel_info *ch_info = NULL; | 1631 | struct iwl3945_channel_info *ch_info = NULL; |
1632 | int delta_index; | 1632 | int delta_index; |
1633 | const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ | 1633 | const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ |
1634 | u8 a_band; | 1634 | u8 a_band; |
@@ -1649,7 +1649,7 @@ static int iwl_hw_reg_comp_txpower_temp(struct iwl_priv *priv) | |||
1649 | 1649 | ||
1650 | /* get power index adjustment based on curr and factory | 1650 | /* get power index adjustment based on curr and factory |
1651 | * temps */ | 1651 | * temps */ |
1652 | delta_index = iwl_hw_reg_adjust_power_by_temp(temperature, | 1652 | delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, |
1653 | ref_temp); | 1653 | ref_temp); |
1654 | 1654 | ||
1655 | /* set tx power value for all rates, OFDM and CCK */ | 1655 | /* set tx power value for all rates, OFDM and CCK */ |
@@ -1662,7 +1662,7 @@ static int iwl_hw_reg_comp_txpower_temp(struct iwl_priv *priv) | |||
1662 | power_idx += delta_index; | 1662 | power_idx += delta_index; |
1663 | 1663 | ||
1664 | /* stay within table range */ | 1664 | /* stay within table range */ |
1665 | power_idx = iwl_hw_reg_fix_power_index(power_idx); | 1665 | power_idx = iwl3945_hw_reg_fix_power_index(power_idx); |
1666 | ch_info->power_info[rate_index]. | 1666 | ch_info->power_info[rate_index]. |
1667 | power_table_index = (u8) power_idx; | 1667 | power_table_index = (u8) power_idx; |
1668 | ch_info->power_info[rate_index].tpc = | 1668 | ch_info->power_info[rate_index].tpc = |
@@ -1677,19 +1677,19 @@ static int iwl_hw_reg_comp_txpower_temp(struct iwl_priv *priv) | |||
1677 | scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { | 1677 | scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { |
1678 | s32 actual_index = (scan_tbl_index == 0) ? | 1678 | s32 actual_index = (scan_tbl_index == 0) ? |
1679 | IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; | 1679 | IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; |
1680 | iwl_hw_reg_set_scan_power(priv, scan_tbl_index, | 1680 | iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index, |
1681 | actual_index, clip_pwrs, | 1681 | actual_index, clip_pwrs, |
1682 | ch_info, a_band); | 1682 | ch_info, a_band); |
1683 | } | 1683 | } |
1684 | } | 1684 | } |
1685 | 1685 | ||
1686 | /* send Txpower command for current channel to ucode */ | 1686 | /* send Txpower command for current channel to ucode */ |
1687 | return iwl_hw_reg_send_txpower(priv); | 1687 | return iwl3945_hw_reg_send_txpower(priv); |
1688 | } | 1688 | } |
1689 | 1689 | ||
1690 | int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power) | 1690 | int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power) |
1691 | { | 1691 | { |
1692 | struct iwl_channel_info *ch_info; | 1692 | struct iwl3945_channel_info *ch_info; |
1693 | s8 max_power; | 1693 | s8 max_power; |
1694 | u8 a_band; | 1694 | u8 a_band; |
1695 | u8 i; | 1695 | u8 i; |
@@ -1711,26 +1711,26 @@ int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power) | |||
1711 | 1711 | ||
1712 | /* find minimum power of all user and regulatory constraints | 1712 | /* find minimum power of all user and regulatory constraints |
1713 | * (does not consider h/w clipping limitations) */ | 1713 | * (does not consider h/w clipping limitations) */ |
1714 | max_power = iwl_hw_reg_get_ch_txpower_limit(ch_info); | 1714 | max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info); |
1715 | max_power = min(power, max_power); | 1715 | max_power = min(power, max_power); |
1716 | if (max_power != ch_info->curr_txpow) { | 1716 | if (max_power != ch_info->curr_txpow) { |
1717 | ch_info->curr_txpow = max_power; | 1717 | ch_info->curr_txpow = max_power; |
1718 | 1718 | ||
1719 | /* this considers the h/w clipping limitations */ | 1719 | /* this considers the h/w clipping limitations */ |
1720 | iwl_hw_reg_set_new_power(priv, ch_info); | 1720 | iwl3945_hw_reg_set_new_power(priv, ch_info); |
1721 | } | 1721 | } |
1722 | } | 1722 | } |
1723 | 1723 | ||
1724 | /* update txpower settings for all channels, | 1724 | /* update txpower settings for all channels, |
1725 | * send to NIC if associated. */ | 1725 | * send to NIC if associated. */ |
1726 | is_temp_calib_needed(priv); | 1726 | is_temp_calib_needed(priv); |
1727 | iwl_hw_reg_comp_txpower_temp(priv); | 1727 | iwl3945_hw_reg_comp_txpower_temp(priv); |
1728 | 1728 | ||
1729 | return 0; | 1729 | return 0; |
1730 | } | 1730 | } |
1731 | 1731 | ||
1732 | /* will add 3945 channel switch cmd handling later */ | 1732 | /* will add 3945 channel switch cmd handling later */ |
1733 | int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel) | 1733 | int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel) |
1734 | { | 1734 | { |
1735 | return 0; | 1735 | return 0; |
1736 | } | 1736 | } |
@@ -1745,17 +1745,17 @@ int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel) | |||
1745 | * -- send new set of gain settings to NIC | 1745 | * -- send new set of gain settings to NIC |
1746 | * NOTE: This should continue working, even when we're not associated, | 1746 | * NOTE: This should continue working, even when we're not associated, |
1747 | * so we can keep our internal table of scan powers current. */ | 1747 | * so we can keep our internal table of scan powers current. */ |
1748 | void iwl3945_reg_txpower_periodic(struct iwl_priv *priv) | 1748 | void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv) |
1749 | { | 1749 | { |
1750 | /* This will kick in the "brute force" | 1750 | /* This will kick in the "brute force" |
1751 | * iwl_hw_reg_comp_txpower_temp() below */ | 1751 | * iwl3945_hw_reg_comp_txpower_temp() below */ |
1752 | if (!is_temp_calib_needed(priv)) | 1752 | if (!is_temp_calib_needed(priv)) |
1753 | goto reschedule; | 1753 | goto reschedule; |
1754 | 1754 | ||
1755 | /* Set up a new set of temp-adjusted TxPowers, send to NIC. | 1755 | /* Set up a new set of temp-adjusted TxPowers, send to NIC. |
1756 | * This is based *only* on current temperature, | 1756 | * This is based *only* on current temperature, |
1757 | * ignoring any previous power measurements */ | 1757 | * ignoring any previous power measurements */ |
1758 | iwl_hw_reg_comp_txpower_temp(priv); | 1758 | iwl3945_hw_reg_comp_txpower_temp(priv); |
1759 | 1759 | ||
1760 | reschedule: | 1760 | reschedule: |
1761 | queue_delayed_work(priv->workqueue, | 1761 | queue_delayed_work(priv->workqueue, |
@@ -1764,7 +1764,7 @@ void iwl3945_reg_txpower_periodic(struct iwl_priv *priv) | |||
1764 | 1764 | ||
1765 | static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) | 1765 | static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) |
1766 | { | 1766 | { |
1767 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | 1767 | struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, |
1768 | thermal_periodic.work); | 1768 | thermal_periodic.work); |
1769 | 1769 | ||
1770 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | 1770 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
@@ -1776,7 +1776,7 @@ static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) | |||
1776 | } | 1776 | } |
1777 | 1777 | ||
1778 | /** | 1778 | /** |
1779 | * iwl_hw_reg_get_ch_grp_index - find the channel-group index (0-4) | 1779 | * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4) |
1780 | * for the channel. | 1780 | * for the channel. |
1781 | * | 1781 | * |
1782 | * This function is used when initializing channel-info structs. | 1782 | * This function is used when initializing channel-info structs. |
@@ -1786,10 +1786,10 @@ static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) | |||
1786 | * on A-band, EEPROM's "group frequency" entries represent the top | 1786 | * on A-band, EEPROM's "group frequency" entries represent the top |
1787 | * channel in each group 1-4. Group 5 All B/G channels are in group 0. | 1787 | * channel in each group 1-4. Group 5 All B/G channels are in group 0. |
1788 | */ | 1788 | */ |
1789 | static u16 iwl_hw_reg_get_ch_grp_index(struct iwl_priv *priv, | 1789 | static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv, |
1790 | const struct iwl_channel_info *ch_info) | 1790 | const struct iwl3945_channel_info *ch_info) |
1791 | { | 1791 | { |
1792 | struct iwl_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0]; | 1792 | struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0]; |
1793 | u8 group; | 1793 | u8 group; |
1794 | u16 group_index = 0; /* based on factory calib frequencies */ | 1794 | u16 group_index = 0; /* based on factory calib frequencies */ |
1795 | u8 grp_channel; | 1795 | u8 grp_channel; |
@@ -1815,20 +1815,20 @@ static u16 iwl_hw_reg_get_ch_grp_index(struct iwl_priv *priv, | |||
1815 | } | 1815 | } |
1816 | 1816 | ||
1817 | /** | 1817 | /** |
1818 | * iwl_hw_reg_get_matched_power_index - Interpolate to get nominal index | 1818 | * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index |
1819 | * | 1819 | * |
1820 | * Interpolate to get nominal (i.e. at factory calibration temperature) index | 1820 | * Interpolate to get nominal (i.e. at factory calibration temperature) index |
1821 | * into radio/DSP gain settings table for requested power. | 1821 | * into radio/DSP gain settings table for requested power. |
1822 | */ | 1822 | */ |
1823 | static int iwl_hw_reg_get_matched_power_index(struct iwl_priv *priv, | 1823 | static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv, |
1824 | s8 requested_power, | 1824 | s8 requested_power, |
1825 | s32 setting_index, s32 *new_index) | 1825 | s32 setting_index, s32 *new_index) |
1826 | { | 1826 | { |
1827 | const struct iwl_eeprom_txpower_group *chnl_grp = NULL; | 1827 | const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL; |
1828 | s32 index0, index1; | 1828 | s32 index0, index1; |
1829 | s32 power = 2 * requested_power; | 1829 | s32 power = 2 * requested_power; |
1830 | s32 i; | 1830 | s32 i; |
1831 | const struct iwl_eeprom_txpower_sample *samples; | 1831 | const struct iwl3945_eeprom_txpower_sample *samples; |
1832 | s32 gains0, gains1; | 1832 | s32 gains0, gains1; |
1833 | s32 res; | 1833 | s32 res; |
1834 | s32 denominator; | 1834 | s32 denominator; |
@@ -1868,11 +1868,11 @@ static int iwl_hw_reg_get_matched_power_index(struct iwl_priv *priv, | |||
1868 | return 0; | 1868 | return 0; |
1869 | } | 1869 | } |
1870 | 1870 | ||
1871 | static void iwl_hw_reg_init_channel_groups(struct iwl_priv *priv) | 1871 | static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv) |
1872 | { | 1872 | { |
1873 | u32 i; | 1873 | u32 i; |
1874 | s32 rate_index; | 1874 | s32 rate_index; |
1875 | const struct iwl_eeprom_txpower_group *group; | 1875 | const struct iwl3945_eeprom_txpower_group *group; |
1876 | 1876 | ||
1877 | IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n"); | 1877 | IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n"); |
1878 | 1878 | ||
@@ -1948,10 +1948,10 @@ static void iwl_hw_reg_init_channel_groups(struct iwl_priv *priv) | |||
1948 | * | 1948 | * |
1949 | * This does *not* write values to NIC, just sets up our internal table. | 1949 | * This does *not* write values to NIC, just sets up our internal table. |
1950 | */ | 1950 | */ |
1951 | int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | 1951 | int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv) |
1952 | { | 1952 | { |
1953 | struct iwl_channel_info *ch_info = NULL; | 1953 | struct iwl3945_channel_info *ch_info = NULL; |
1954 | struct iwl_channel_power_info *pwr_info; | 1954 | struct iwl3945_channel_power_info *pwr_info; |
1955 | int delta_index; | 1955 | int delta_index; |
1956 | u8 rate_index; | 1956 | u8 rate_index; |
1957 | u8 scan_tbl_index; | 1957 | u8 scan_tbl_index; |
@@ -1964,10 +1964,10 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
1964 | 1964 | ||
1965 | /* save temperature reference, | 1965 | /* save temperature reference, |
1966 | * so we can determine next time to calibrate */ | 1966 | * so we can determine next time to calibrate */ |
1967 | temperature = iwl_hw_reg_txpower_get_temperature(priv); | 1967 | temperature = iwl3945_hw_reg_txpower_get_temperature(priv); |
1968 | priv->last_temperature = temperature; | 1968 | priv->last_temperature = temperature; |
1969 | 1969 | ||
1970 | iwl_hw_reg_init_channel_groups(priv); | 1970 | iwl3945_hw_reg_init_channel_groups(priv); |
1971 | 1971 | ||
1972 | /* initialize Tx power info for each and every channel, 2.4 and 5.x */ | 1972 | /* initialize Tx power info for each and every channel, 2.4 and 5.x */ |
1973 | for (i = 0, ch_info = priv->channel_info; i < priv->channel_count; | 1973 | for (i = 0, ch_info = priv->channel_info; i < priv->channel_count; |
@@ -1978,14 +1978,14 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
1978 | 1978 | ||
1979 | /* find this channel's channel group (*not* "band") index */ | 1979 | /* find this channel's channel group (*not* "band") index */ |
1980 | ch_info->group_index = | 1980 | ch_info->group_index = |
1981 | iwl_hw_reg_get_ch_grp_index(priv, ch_info); | 1981 | iwl3945_hw_reg_get_ch_grp_index(priv, ch_info); |
1982 | 1982 | ||
1983 | /* Get this chnlgrp's rate->max/clip-powers table */ | 1983 | /* Get this chnlgrp's rate->max/clip-powers table */ |
1984 | clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers; | 1984 | clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers; |
1985 | 1985 | ||
1986 | /* calculate power index *adjustment* value according to | 1986 | /* calculate power index *adjustment* value according to |
1987 | * diff between current temperature and factory temperature */ | 1987 | * diff between current temperature and factory temperature */ |
1988 | delta_index = iwl_hw_reg_adjust_power_by_temp(temperature, | 1988 | delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, |
1989 | priv->eeprom.groups[ch_info->group_index]. | 1989 | priv->eeprom.groups[ch_info->group_index]. |
1990 | temperature); | 1990 | temperature); |
1991 | 1991 | ||
@@ -2008,7 +2008,7 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
2008 | 2008 | ||
2009 | /* get base (i.e. at factory-measured temperature) | 2009 | /* get base (i.e. at factory-measured temperature) |
2010 | * power table index for this rate's power */ | 2010 | * power table index for this rate's power */ |
2011 | rc = iwl_hw_reg_get_matched_power_index(priv, pwr, | 2011 | rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr, |
2012 | ch_info->group_index, | 2012 | ch_info->group_index, |
2013 | &power_idx); | 2013 | &power_idx); |
2014 | if (rc) { | 2014 | if (rc) { |
@@ -2021,9 +2021,9 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
2021 | power_idx += delta_index; | 2021 | power_idx += delta_index; |
2022 | 2022 | ||
2023 | /* stay within range of gain table */ | 2023 | /* stay within range of gain table */ |
2024 | power_idx = iwl_hw_reg_fix_power_index(power_idx); | 2024 | power_idx = iwl3945_hw_reg_fix_power_index(power_idx); |
2025 | 2025 | ||
2026 | /* fill 1 OFDM rate's iwl_channel_power_info struct */ | 2026 | /* fill 1 OFDM rate's iwl3945_channel_power_info struct */ |
2027 | pwr_info->requested_power = pwr; | 2027 | pwr_info->requested_power = pwr; |
2028 | pwr_info->power_table_index = (u8) power_idx; | 2028 | pwr_info->power_table_index = (u8) power_idx; |
2029 | pwr_info->tpc.tx_gain = | 2029 | pwr_info->tpc.tx_gain = |
@@ -2042,11 +2042,11 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
2042 | IWL_CCK_FROM_OFDM_INDEX_DIFF; | 2042 | IWL_CCK_FROM_OFDM_INDEX_DIFF; |
2043 | 2043 | ||
2044 | /* stay within table range */ | 2044 | /* stay within table range */ |
2045 | pwr_index = iwl_hw_reg_fix_power_index(pwr_index); | 2045 | pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index); |
2046 | gain = power_gain_table[a_band][pwr_index].tx_gain; | 2046 | gain = power_gain_table[a_band][pwr_index].tx_gain; |
2047 | dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten; | 2047 | dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten; |
2048 | 2048 | ||
2049 | /* fill each CCK rate's iwl_channel_power_info structure | 2049 | /* fill each CCK rate's iwl3945_channel_power_info structure |
2050 | * NOTE: All CCK-rate Txpwrs are the same for a given chnl! | 2050 | * NOTE: All CCK-rate Txpwrs are the same for a given chnl! |
2051 | * NOTE: CCK rates start at end of OFDM rates! */ | 2051 | * NOTE: CCK rates start at end of OFDM rates! */ |
2052 | for (rate_index = 0; | 2052 | for (rate_index = 0; |
@@ -2064,7 +2064,7 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
2064 | scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { | 2064 | scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { |
2065 | s32 actual_index = (scan_tbl_index == 0) ? | 2065 | s32 actual_index = (scan_tbl_index == 0) ? |
2066 | IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; | 2066 | IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; |
2067 | iwl_hw_reg_set_scan_power(priv, scan_tbl_index, | 2067 | iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index, |
2068 | actual_index, clip_pwrs, ch_info, a_band); | 2068 | actual_index, clip_pwrs, ch_info, a_band); |
2069 | } | 2069 | } |
2070 | } | 2070 | } |
@@ -2072,66 +2072,66 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) | |||
2072 | return 0; | 2072 | return 0; |
2073 | } | 2073 | } |
2074 | 2074 | ||
2075 | int iwl_hw_rxq_stop(struct iwl_priv *priv) | 2075 | int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv) |
2076 | { | 2076 | { |
2077 | int rc; | 2077 | int rc; |
2078 | unsigned long flags; | 2078 | unsigned long flags; |
2079 | 2079 | ||
2080 | spin_lock_irqsave(&priv->lock, flags); | 2080 | spin_lock_irqsave(&priv->lock, flags); |
2081 | rc = iwl_grab_nic_access(priv); | 2081 | rc = iwl3945_grab_nic_access(priv); |
2082 | if (rc) { | 2082 | if (rc) { |
2083 | spin_unlock_irqrestore(&priv->lock, flags); | 2083 | spin_unlock_irqrestore(&priv->lock, flags); |
2084 | return rc; | 2084 | return rc; |
2085 | } | 2085 | } |
2086 | 2086 | ||
2087 | iwl_write_direct32(priv, FH_RCSR_CONFIG(0), 0); | 2087 | iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0); |
2088 | rc = iwl_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000); | 2088 | rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000); |
2089 | if (rc < 0) | 2089 | if (rc < 0) |
2090 | IWL_ERROR("Can't stop Rx DMA.\n"); | 2090 | IWL_ERROR("Can't stop Rx DMA.\n"); |
2091 | 2091 | ||
2092 | iwl_release_nic_access(priv); | 2092 | iwl3945_release_nic_access(priv); |
2093 | spin_unlock_irqrestore(&priv->lock, flags); | 2093 | spin_unlock_irqrestore(&priv->lock, flags); |
2094 | 2094 | ||
2095 | return 0; | 2095 | return 0; |
2096 | } | 2096 | } |
2097 | 2097 | ||
2098 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) | 2098 | int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) |
2099 | { | 2099 | { |
2100 | int rc; | 2100 | int rc; |
2101 | unsigned long flags; | 2101 | unsigned long flags; |
2102 | int txq_id = txq->q.id; | 2102 | int txq_id = txq->q.id; |
2103 | 2103 | ||
2104 | struct iwl_shared *shared_data = priv->hw_setting.shared_virt; | 2104 | struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt; |
2105 | 2105 | ||
2106 | shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); | 2106 | shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); |
2107 | 2107 | ||
2108 | spin_lock_irqsave(&priv->lock, flags); | 2108 | spin_lock_irqsave(&priv->lock, flags); |
2109 | rc = iwl_grab_nic_access(priv); | 2109 | rc = iwl3945_grab_nic_access(priv); |
2110 | if (rc) { | 2110 | if (rc) { |
2111 | spin_unlock_irqrestore(&priv->lock, flags); | 2111 | spin_unlock_irqrestore(&priv->lock, flags); |
2112 | return rc; | 2112 | return rc; |
2113 | } | 2113 | } |
2114 | iwl_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0); | 2114 | iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0); |
2115 | iwl_write_direct32(priv, FH_CBCC_BASE(txq_id), 0); | 2115 | iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0); |
2116 | 2116 | ||
2117 | iwl_write_direct32(priv, FH_TCSR_CONFIG(txq_id), | 2117 | iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id), |
2118 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | | 2118 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | |
2119 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | | 2119 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | |
2120 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | | 2120 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | |
2121 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | | 2121 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
2122 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); | 2122 | ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); |
2123 | iwl_release_nic_access(priv); | 2123 | iwl3945_release_nic_access(priv); |
2124 | 2124 | ||
2125 | /* fake read to flush all prev. writes */ | 2125 | /* fake read to flush all prev. writes */ |
2126 | iwl_read32(priv, FH_TSSR_CBB_BASE); | 2126 | iwl3945_read32(priv, FH_TSSR_CBB_BASE); |
2127 | spin_unlock_irqrestore(&priv->lock, flags); | 2127 | spin_unlock_irqrestore(&priv->lock, flags); |
2128 | 2128 | ||
2129 | return 0; | 2129 | return 0; |
2130 | } | 2130 | } |
2131 | 2131 | ||
2132 | int iwl_hw_get_rx_read(struct iwl_priv *priv) | 2132 | int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv) |
2133 | { | 2133 | { |
2134 | struct iwl_shared *shared_data = priv->hw_setting.shared_virt; | 2134 | struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt; |
2135 | 2135 | ||
2136 | return le32_to_cpu(shared_data->rx_read_ptr[0]); | 2136 | return le32_to_cpu(shared_data->rx_read_ptr[0]); |
2137 | } | 2137 | } |
@@ -2139,22 +2139,22 @@ int iwl_hw_get_rx_read(struct iwl_priv *priv) | |||
2139 | /** | 2139 | /** |
2140 | * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table | 2140 | * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table |
2141 | */ | 2141 | */ |
2142 | int iwl3945_init_hw_rate_table(struct iwl_priv *priv) | 2142 | int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv) |
2143 | { | 2143 | { |
2144 | int rc, i, index, prev_index; | 2144 | int rc, i, index, prev_index; |
2145 | struct iwl_rate_scaling_cmd rate_cmd = { | 2145 | struct iwl3945_rate_scaling_cmd rate_cmd = { |
2146 | .reserved = {0, 0, 0}, | 2146 | .reserved = {0, 0, 0}, |
2147 | }; | 2147 | }; |
2148 | struct iwl_rate_scaling_info *table = rate_cmd.table; | 2148 | struct iwl3945_rate_scaling_info *table = rate_cmd.table; |
2149 | 2149 | ||
2150 | for (i = 0; i < ARRAY_SIZE(iwl_rates); i++) { | 2150 | for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) { |
2151 | index = iwl_rates[i].table_rs_index; | 2151 | index = iwl3945_rates[i].table_rs_index; |
2152 | 2152 | ||
2153 | table[index].rate_n_flags = | 2153 | table[index].rate_n_flags = |
2154 | iwl_hw_set_rate_n_flags(iwl_rates[i].plcp, 0); | 2154 | iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0); |
2155 | table[index].try_cnt = priv->retry_rate; | 2155 | table[index].try_cnt = priv->retry_rate; |
2156 | prev_index = iwl_get_prev_ieee_rate(i); | 2156 | prev_index = iwl3945_get_prev_ieee_rate(i); |
2157 | table[index].next_rate_index = iwl_rates[prev_index].table_rs_index; | 2157 | table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index; |
2158 | } | 2158 | } |
2159 | 2159 | ||
2160 | switch (priv->phymode) { | 2160 | switch (priv->phymode) { |
@@ -2163,14 +2163,14 @@ int iwl3945_init_hw_rate_table(struct iwl_priv *priv) | |||
2163 | /* If one of the following CCK rates is used, | 2163 | /* If one of the following CCK rates is used, |
2164 | * have it fall back to the 6M OFDM rate */ | 2164 | * have it fall back to the 6M OFDM rate */ |
2165 | for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) | 2165 | for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) |
2166 | table[i].next_rate_index = iwl_rates[IWL_FIRST_OFDM_RATE].table_rs_index; | 2166 | table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index; |
2167 | 2167 | ||
2168 | /* Don't fall back to CCK rates */ | 2168 | /* Don't fall back to CCK rates */ |
2169 | table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE; | 2169 | table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE; |
2170 | 2170 | ||
2171 | /* Don't drop out of OFDM rates */ | 2171 | /* Don't drop out of OFDM rates */ |
2172 | table[IWL_RATE_6M_INDEX_TABLE].next_rate_index = | 2172 | table[IWL_RATE_6M_INDEX_TABLE].next_rate_index = |
2173 | iwl_rates[IWL_FIRST_OFDM_RATE].table_rs_index; | 2173 | iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index; |
2174 | break; | 2174 | break; |
2175 | 2175 | ||
2176 | case MODE_IEEE80211B: | 2176 | case MODE_IEEE80211B: |
@@ -2178,7 +2178,7 @@ int iwl3945_init_hw_rate_table(struct iwl_priv *priv) | |||
2178 | /* If an OFDM rate is used, have it fall back to the | 2178 | /* If an OFDM rate is used, have it fall back to the |
2179 | * 1M CCK rates */ | 2179 | * 1M CCK rates */ |
2180 | for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++) | 2180 | for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++) |
2181 | table[i].next_rate_index = iwl_rates[IWL_FIRST_CCK_RATE].table_rs_index; | 2181 | table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index; |
2182 | 2182 | ||
2183 | /* CCK shouldn't fall back to OFDM... */ | 2183 | /* CCK shouldn't fall back to OFDM... */ |
2184 | table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE; | 2184 | table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE; |
@@ -2191,25 +2191,25 @@ int iwl3945_init_hw_rate_table(struct iwl_priv *priv) | |||
2191 | 2191 | ||
2192 | /* Update the rate scaling for control frame Tx */ | 2192 | /* Update the rate scaling for control frame Tx */ |
2193 | rate_cmd.table_id = 0; | 2193 | rate_cmd.table_id = 0; |
2194 | rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), | 2194 | rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), |
2195 | &rate_cmd); | 2195 | &rate_cmd); |
2196 | if (rc) | 2196 | if (rc) |
2197 | return rc; | 2197 | return rc; |
2198 | 2198 | ||
2199 | /* Update the rate scaling for data frame Tx */ | 2199 | /* Update the rate scaling for data frame Tx */ |
2200 | rate_cmd.table_id = 1; | 2200 | rate_cmd.table_id = 1; |
2201 | return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), | 2201 | return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), |
2202 | &rate_cmd); | 2202 | &rate_cmd); |
2203 | } | 2203 | } |
2204 | 2204 | ||
2205 | int iwl_hw_set_hw_setting(struct iwl_priv *priv) | 2205 | int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv) |
2206 | { | 2206 | { |
2207 | memset((void *)&priv->hw_setting, 0, | 2207 | memset((void *)&priv->hw_setting, 0, |
2208 | sizeof(struct iwl_driver_hw_info)); | 2208 | sizeof(struct iwl3945_driver_hw_info)); |
2209 | 2209 | ||
2210 | priv->hw_setting.shared_virt = | 2210 | priv->hw_setting.shared_virt = |
2211 | pci_alloc_consistent(priv->pci_dev, | 2211 | pci_alloc_consistent(priv->pci_dev, |
2212 | sizeof(struct iwl_shared), | 2212 | sizeof(struct iwl3945_shared), |
2213 | &priv->hw_setting.shared_phys); | 2213 | &priv->hw_setting.shared_phys); |
2214 | 2214 | ||
2215 | if (!priv->hw_setting.shared_virt) { | 2215 | if (!priv->hw_setting.shared_virt) { |
@@ -2220,7 +2220,7 @@ int iwl_hw_set_hw_setting(struct iwl_priv *priv) | |||
2220 | 2220 | ||
2221 | priv->hw_setting.ac_queue_count = AC_NUM; | 2221 | priv->hw_setting.ac_queue_count = AC_NUM; |
2222 | priv->hw_setting.rx_buffer_size = IWL_RX_BUF_SIZE; | 2222 | priv->hw_setting.rx_buffer_size = IWL_RX_BUF_SIZE; |
2223 | priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd); | 2223 | priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd); |
2224 | priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE; | 2224 | priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE; |
2225 | priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG; | 2225 | priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG; |
2226 | priv->hw_setting.max_stations = IWL3945_STATION_COUNT; | 2226 | priv->hw_setting.max_stations = IWL3945_STATION_COUNT; |
@@ -2228,21 +2228,21 @@ int iwl_hw_set_hw_setting(struct iwl_priv *priv) | |||
2228 | return 0; | 2228 | return 0; |
2229 | } | 2229 | } |
2230 | 2230 | ||
2231 | unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, | 2231 | unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv, |
2232 | struct iwl_frame *frame, u8 rate) | 2232 | struct iwl3945_frame *frame, u8 rate) |
2233 | { | 2233 | { |
2234 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | 2234 | struct iwl3945_tx_beacon_cmd *tx_beacon_cmd; |
2235 | unsigned int frame_size; | 2235 | unsigned int frame_size; |
2236 | 2236 | ||
2237 | tx_beacon_cmd = (struct iwl_tx_beacon_cmd *)&frame->u; | 2237 | tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u; |
2238 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | 2238 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); |
2239 | 2239 | ||
2240 | tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID; | 2240 | tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID; |
2241 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | 2241 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2242 | 2242 | ||
2243 | frame_size = iwl_fill_beacon_frame(priv, | 2243 | frame_size = iwl3945_fill_beacon_frame(priv, |
2244 | tx_beacon_cmd->frame, | 2244 | tx_beacon_cmd->frame, |
2245 | BROADCAST_ADDR, | 2245 | iwl3945_broadcast_addr, |
2246 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); | 2246 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
2247 | 2247 | ||
2248 | BUG_ON(frame_size > MAX_MPDU_SIZE); | 2248 | BUG_ON(frame_size > MAX_MPDU_SIZE); |
@@ -2259,35 +2259,35 @@ unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, | |||
2259 | tx_beacon_cmd->tx.supp_rates[1] = | 2259 | tx_beacon_cmd->tx.supp_rates[1] = |
2260 | (IWL_CCK_BASIC_RATES_MASK & 0xF); | 2260 | (IWL_CCK_BASIC_RATES_MASK & 0xF); |
2261 | 2261 | ||
2262 | return (sizeof(struct iwl_tx_beacon_cmd) + frame_size); | 2262 | return (sizeof(struct iwl3945_tx_beacon_cmd) + frame_size); |
2263 | } | 2263 | } |
2264 | 2264 | ||
2265 | void iwl_hw_rx_handler_setup(struct iwl_priv *priv) | 2265 | void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv) |
2266 | { | 2266 | { |
2267 | priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx; | 2267 | priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx; |
2268 | } | 2268 | } |
2269 | 2269 | ||
2270 | void iwl_hw_setup_deferred_work(struct iwl_priv *priv) | 2270 | void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv) |
2271 | { | 2271 | { |
2272 | INIT_DELAYED_WORK(&priv->thermal_periodic, | 2272 | INIT_DELAYED_WORK(&priv->thermal_periodic, |
2273 | iwl3945_bg_reg_txpower_periodic); | 2273 | iwl3945_bg_reg_txpower_periodic); |
2274 | } | 2274 | } |
2275 | 2275 | ||
2276 | void iwl_hw_cancel_deferred_work(struct iwl_priv *priv) | 2276 | void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv) |
2277 | { | 2277 | { |
2278 | cancel_delayed_work(&priv->thermal_periodic); | 2278 | cancel_delayed_work(&priv->thermal_periodic); |
2279 | } | 2279 | } |
2280 | 2280 | ||
2281 | struct pci_device_id iwl_hw_card_ids[] = { | 2281 | struct pci_device_id iwl3945_hw_card_ids[] = { |
2282 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4222)}, | 2282 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4222)}, |
2283 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4227)}, | 2283 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4227)}, |
2284 | {0} | 2284 | {0} |
2285 | }; | 2285 | }; |
2286 | 2286 | ||
2287 | inline int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv) | 2287 | inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv) |
2288 | { | 2288 | { |
2289 | _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); | 2289 | _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); |
2290 | return 0; | 2290 | return 0; |
2291 | } | 2291 | } |
2292 | 2292 | ||
2293 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | 2293 | MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids); |