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authorWey-Yi Guy <wey-yi.w.guy@intel.com>2011-02-21 14:27:26 -0500
committerWey-Yi Guy <wey-yi.w.guy@intel.com>2011-02-21 14:27:26 -0500
commitbe663ab67077fac8e23eb8e231a8c1c94cb32e54 (patch)
treec1d80a72f86be20135d3e57178e99b9d855f622f /drivers/net/wireless/iwlwifi/iwl-3945.c
parent4bc85c1324aaa4a8bb0171e332ff762b6230bdfe (diff)
iwlwifi: split the drivers for agn and legacy devices 3945/4965
Intel WiFi devices 3945 and 4965 now have their own driver in the folder drivers/net/wireless/iwlegacy Add support to build these drivers independently of the driver for AGN devices. Selecting the 3945 builds iwl3945.ko and iwl_legacy.ko, and selecting the 4965 builds iwl4965.ko and iwl_legacy.ko. iwl-legacy.ko contains code shared between both devices. The 3945 is an ABG/BG device, with no support for 802.11n. The 4965 is a 2x3 ABGN device. Signed-off-by: Meenakshi Venkataraman <meenakshi.venkataraman@intel.com> Acked-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-3945.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c2819
1 files changed, 0 insertions, 2819 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
deleted file mode 100644
index 5b6932c2193a..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ /dev/null
@@ -1,2819 +0,0 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/sched.h>
35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
37#include <linux/wireless.h>
38#include <linux/firmware.h>
39#include <linux/etherdevice.h>
40#include <asm/unaligned.h>
41#include <net/mac80211.h>
42
43#include "iwl-fh.h"
44#include "iwl-3945-fh.h"
45#include "iwl-commands.h"
46#include "iwl-sta.h"
47#include "iwl-3945.h"
48#include "iwl-eeprom.h"
49#include "iwl-core.h"
50#include "iwl-helpers.h"
51#include "iwl-led.h"
52#include "iwl-3945-led.h"
53#include "iwl-3945-debugfs.h"
54#include "iwl-legacy.h"
55
56#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
57 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
58 IWL_RATE_##r##M_IEEE, \
59 IWL_RATE_##ip##M_INDEX, \
60 IWL_RATE_##in##M_INDEX, \
61 IWL_RATE_##rp##M_INDEX, \
62 IWL_RATE_##rn##M_INDEX, \
63 IWL_RATE_##pp##M_INDEX, \
64 IWL_RATE_##np##M_INDEX, \
65 IWL_RATE_##r##M_INDEX_TABLE, \
66 IWL_RATE_##ip##M_INDEX_TABLE }
67
68/*
69 * Parameter order:
70 * rate, prev rate, next rate, prev tgg rate, next tgg rate
71 *
72 * If there isn't a valid next or previous rate then INV is used which
73 * maps to IWL_RATE_INVALID
74 *
75 */
76const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
77 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
78 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
79 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
80 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
81 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
82 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
83 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
84 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
85 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
86 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
87 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
88 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
89};
90
91static inline u8 iwl3945_get_prev_ieee_rate(u8 rate_index)
92{
93 u8 rate = iwl3945_rates[rate_index].prev_ieee;
94
95 if (rate == IWL_RATE_INVALID)
96 rate = rate_index;
97 return rate;
98}
99
100/* 1 = enable the iwl3945_disable_events() function */
101#define IWL_EVT_DISABLE (0)
102#define IWL_EVT_DISABLE_SIZE (1532/32)
103
104/**
105 * iwl3945_disable_events - Disable selected events in uCode event log
106 *
107 * Disable an event by writing "1"s into "disable"
108 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
109 * Default values of 0 enable uCode events to be logged.
110 * Use for only special debugging. This function is just a placeholder as-is,
111 * you'll need to provide the special bits! ...
112 * ... and set IWL_EVT_DISABLE to 1. */
113void iwl3945_disable_events(struct iwl_priv *priv)
114{
115 int i;
116 u32 base; /* SRAM address of event log header */
117 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
118 u32 array_size; /* # of u32 entries in array */
119 static const u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
120 0x00000000, /* 31 - 0 Event id numbers */
121 0x00000000, /* 63 - 32 */
122 0x00000000, /* 95 - 64 */
123 0x00000000, /* 127 - 96 */
124 0x00000000, /* 159 - 128 */
125 0x00000000, /* 191 - 160 */
126 0x00000000, /* 223 - 192 */
127 0x00000000, /* 255 - 224 */
128 0x00000000, /* 287 - 256 */
129 0x00000000, /* 319 - 288 */
130 0x00000000, /* 351 - 320 */
131 0x00000000, /* 383 - 352 */
132 0x00000000, /* 415 - 384 */
133 0x00000000, /* 447 - 416 */
134 0x00000000, /* 479 - 448 */
135 0x00000000, /* 511 - 480 */
136 0x00000000, /* 543 - 512 */
137 0x00000000, /* 575 - 544 */
138 0x00000000, /* 607 - 576 */
139 0x00000000, /* 639 - 608 */
140 0x00000000, /* 671 - 640 */
141 0x00000000, /* 703 - 672 */
142 0x00000000, /* 735 - 704 */
143 0x00000000, /* 767 - 736 */
144 0x00000000, /* 799 - 768 */
145 0x00000000, /* 831 - 800 */
146 0x00000000, /* 863 - 832 */
147 0x00000000, /* 895 - 864 */
148 0x00000000, /* 927 - 896 */
149 0x00000000, /* 959 - 928 */
150 0x00000000, /* 991 - 960 */
151 0x00000000, /* 1023 - 992 */
152 0x00000000, /* 1055 - 1024 */
153 0x00000000, /* 1087 - 1056 */
154 0x00000000, /* 1119 - 1088 */
155 0x00000000, /* 1151 - 1120 */
156 0x00000000, /* 1183 - 1152 */
157 0x00000000, /* 1215 - 1184 */
158 0x00000000, /* 1247 - 1216 */
159 0x00000000, /* 1279 - 1248 */
160 0x00000000, /* 1311 - 1280 */
161 0x00000000, /* 1343 - 1312 */
162 0x00000000, /* 1375 - 1344 */
163 0x00000000, /* 1407 - 1376 */
164 0x00000000, /* 1439 - 1408 */
165 0x00000000, /* 1471 - 1440 */
166 0x00000000, /* 1503 - 1472 */
167 };
168
169 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
170 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
171 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
172 return;
173 }
174
175 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
176 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
177
178 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
179 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
180 disable_ptr);
181 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
182 iwl_write_targ_mem(priv,
183 disable_ptr + (i * sizeof(u32)),
184 evt_disable[i]);
185
186 } else {
187 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
188 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
189 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
190 disable_ptr, array_size);
191 }
192
193}
194
195static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
196{
197 int idx;
198
199 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
200 if (iwl3945_rates[idx].plcp == plcp)
201 return idx;
202 return -1;
203}
204
205#ifdef CONFIG_IWLWIFI_DEBUG
206#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
207
208static const char *iwl3945_get_tx_fail_reason(u32 status)
209{
210 switch (status & TX_STATUS_MSK) {
211 case TX_3945_STATUS_SUCCESS:
212 return "SUCCESS";
213 TX_STATUS_ENTRY(SHORT_LIMIT);
214 TX_STATUS_ENTRY(LONG_LIMIT);
215 TX_STATUS_ENTRY(FIFO_UNDERRUN);
216 TX_STATUS_ENTRY(MGMNT_ABORT);
217 TX_STATUS_ENTRY(NEXT_FRAG);
218 TX_STATUS_ENTRY(LIFE_EXPIRE);
219 TX_STATUS_ENTRY(DEST_PS);
220 TX_STATUS_ENTRY(ABORTED);
221 TX_STATUS_ENTRY(BT_RETRY);
222 TX_STATUS_ENTRY(STA_INVALID);
223 TX_STATUS_ENTRY(FRAG_DROPPED);
224 TX_STATUS_ENTRY(TID_DISABLE);
225 TX_STATUS_ENTRY(FRAME_FLUSHED);
226 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
227 TX_STATUS_ENTRY(TX_LOCKED);
228 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
229 }
230
231 return "UNKNOWN";
232}
233#else
234static inline const char *iwl3945_get_tx_fail_reason(u32 status)
235{
236 return "";
237}
238#endif
239
240/*
241 * get ieee prev rate from rate scale table.
242 * for A and B mode we need to overright prev
243 * value
244 */
245int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
246{
247 int next_rate = iwl3945_get_prev_ieee_rate(rate);
248
249 switch (priv->band) {
250 case IEEE80211_BAND_5GHZ:
251 if (rate == IWL_RATE_12M_INDEX)
252 next_rate = IWL_RATE_9M_INDEX;
253 else if (rate == IWL_RATE_6M_INDEX)
254 next_rate = IWL_RATE_6M_INDEX;
255 break;
256 case IEEE80211_BAND_2GHZ:
257 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
258 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
259 if (rate == IWL_RATE_11M_INDEX)
260 next_rate = IWL_RATE_5M_INDEX;
261 }
262 break;
263
264 default:
265 break;
266 }
267
268 return next_rate;
269}
270
271
272/**
273 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
274 *
275 * When FW advances 'R' index, all entries between old and new 'R' index
276 * need to be reclaimed. As result, some free space forms. If there is
277 * enough free space (> low mark), wake the stack that feeds us.
278 */
279static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
280 int txq_id, int index)
281{
282 struct iwl_tx_queue *txq = &priv->txq[txq_id];
283 struct iwl_queue *q = &txq->q;
284 struct iwl_tx_info *tx_info;
285
286 BUG_ON(txq_id == IWL39_CMD_QUEUE_NUM);
287
288 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
289 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
290
291 tx_info = &txq->txb[txq->q.read_ptr];
292 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
293 tx_info->skb = NULL;
294 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
295 }
296
297 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
298 (txq_id != IWL39_CMD_QUEUE_NUM) &&
299 priv->mac80211_registered)
300 iwl_wake_queue(priv, txq);
301}
302
303/**
304 * iwl3945_rx_reply_tx - Handle Tx response
305 */
306static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
307 struct iwl_rx_mem_buffer *rxb)
308{
309 struct iwl_rx_packet *pkt = rxb_addr(rxb);
310 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
311 int txq_id = SEQ_TO_QUEUE(sequence);
312 int index = SEQ_TO_INDEX(sequence);
313 struct iwl_tx_queue *txq = &priv->txq[txq_id];
314 struct ieee80211_tx_info *info;
315 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
316 u32 status = le32_to_cpu(tx_resp->status);
317 int rate_idx;
318 int fail;
319
320 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
321 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
322 "is out of range [0-%d] %d %d\n", txq_id,
323 index, txq->q.n_bd, txq->q.write_ptr,
324 txq->q.read_ptr);
325 return;
326 }
327
328 txq->time_stamp = jiffies;
329 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
330 ieee80211_tx_info_clear_status(info);
331
332 /* Fill the MRR chain with some info about on-chip retransmissions */
333 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
334 if (info->band == IEEE80211_BAND_5GHZ)
335 rate_idx -= IWL_FIRST_OFDM_RATE;
336
337 fail = tx_resp->failure_frame;
338
339 info->status.rates[0].idx = rate_idx;
340 info->status.rates[0].count = fail + 1; /* add final attempt */
341
342 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
343 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
344 IEEE80211_TX_STAT_ACK : 0;
345
346 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
347 txq_id, iwl3945_get_tx_fail_reason(status), status,
348 tx_resp->rate, tx_resp->failure_frame);
349
350 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
351 iwl3945_tx_queue_reclaim(priv, txq_id, index);
352
353 if (status & TX_ABORT_REQUIRED_MSK)
354 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
355}
356
357
358
359/*****************************************************************************
360 *
361 * Intel PRO/Wireless 3945ABG/BG Network Connection
362 *
363 * RX handler implementations
364 *
365 *****************************************************************************/
366#ifdef CONFIG_IWLWIFI_DEBUGFS
367/*
368 * based on the assumption of all statistics counter are in DWORD
369 * FIXME: This function is for debugging, do not deal with
370 * the case of counters roll-over.
371 */
372static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
373 __le32 *stats)
374{
375 int i;
376 __le32 *prev_stats;
377 u32 *accum_stats;
378 u32 *delta, *max_delta;
379
380 prev_stats = (__le32 *)&priv->_3945.statistics;
381 accum_stats = (u32 *)&priv->_3945.accum_statistics;
382 delta = (u32 *)&priv->_3945.delta_statistics;
383 max_delta = (u32 *)&priv->_3945.max_delta;
384
385 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
386 i += sizeof(__le32), stats++, prev_stats++, delta++,
387 max_delta++, accum_stats++) {
388 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
389 *delta = (le32_to_cpu(*stats) -
390 le32_to_cpu(*prev_stats));
391 *accum_stats += *delta;
392 if (*delta > *max_delta)
393 *max_delta = *delta;
394 }
395 }
396
397 /* reset accumulative statistics for "no-counter" type statistics */
398 priv->_3945.accum_statistics.general.temperature =
399 priv->_3945.statistics.general.temperature;
400 priv->_3945.accum_statistics.general.ttl_timestamp =
401 priv->_3945.statistics.general.ttl_timestamp;
402}
403#endif
404
405/**
406 * iwl3945_good_plcp_health - checks for plcp error.
407 *
408 * When the plcp error is exceeding the thresholds, reset the radio
409 * to improve the throughput.
410 */
411static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
412 struct iwl_rx_packet *pkt)
413{
414 bool rc = true;
415 struct iwl3945_notif_statistics current_stat;
416 int combined_plcp_delta;
417 unsigned int plcp_msec;
418 unsigned long plcp_received_jiffies;
419
420 if (priv->cfg->base_params->plcp_delta_threshold ==
421 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
422 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
423 return rc;
424 }
425 memcpy(&current_stat, pkt->u.raw, sizeof(struct
426 iwl3945_notif_statistics));
427 /*
428 * check for plcp_err and trigger radio reset if it exceeds
429 * the plcp error threshold plcp_delta.
430 */
431 plcp_received_jiffies = jiffies;
432 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
433 (long) priv->plcp_jiffies);
434 priv->plcp_jiffies = plcp_received_jiffies;
435 /*
436 * check to make sure plcp_msec is not 0 to prevent division
437 * by zero.
438 */
439 if (plcp_msec) {
440 combined_plcp_delta =
441 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
442 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
443
444 if ((combined_plcp_delta > 0) &&
445 ((combined_plcp_delta * 100) / plcp_msec) >
446 priv->cfg->base_params->plcp_delta_threshold) {
447 /*
448 * if plcp_err exceed the threshold, the following
449 * data is printed in csv format:
450 * Text: plcp_err exceeded %d,
451 * Received ofdm.plcp_err,
452 * Current ofdm.plcp_err,
453 * combined_plcp_delta,
454 * plcp_msec
455 */
456 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
457 "%u, %d, %u mSecs\n",
458 priv->cfg->base_params->plcp_delta_threshold,
459 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
460 combined_plcp_delta, plcp_msec);
461 /*
462 * Reset the RF radio due to the high plcp
463 * error rate
464 */
465 rc = false;
466 }
467 }
468 return rc;
469}
470
471void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
472 struct iwl_rx_mem_buffer *rxb)
473{
474 struct iwl_rx_packet *pkt = rxb_addr(rxb);
475
476 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
477 (int)sizeof(struct iwl3945_notif_statistics),
478 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
479#ifdef CONFIG_IWLWIFI_DEBUGFS
480 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
481#endif
482 iwl_recover_from_statistics(priv, pkt);
483
484 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
485}
486
487void iwl3945_reply_statistics(struct iwl_priv *priv,
488 struct iwl_rx_mem_buffer *rxb)
489{
490 struct iwl_rx_packet *pkt = rxb_addr(rxb);
491 __le32 *flag = (__le32 *)&pkt->u.raw;
492
493 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
494#ifdef CONFIG_IWLWIFI_DEBUGFS
495 memset(&priv->_3945.accum_statistics, 0,
496 sizeof(struct iwl3945_notif_statistics));
497 memset(&priv->_3945.delta_statistics, 0,
498 sizeof(struct iwl3945_notif_statistics));
499 memset(&priv->_3945.max_delta, 0,
500 sizeof(struct iwl3945_notif_statistics));
501#endif
502 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
503 }
504 iwl3945_hw_rx_statistics(priv, rxb);
505}
506
507
508/******************************************************************************
509 *
510 * Misc. internal state and helper functions
511 *
512 ******************************************************************************/
513
514/* This is necessary only for a number of statistics, see the caller. */
515static int iwl3945_is_network_packet(struct iwl_priv *priv,
516 struct ieee80211_hdr *header)
517{
518 /* Filter incoming packets to determine if they are targeted toward
519 * this network, discarding packets coming from ourselves */
520 switch (priv->iw_mode) {
521 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
522 /* packets to our IBSS update information */
523 return !compare_ether_addr(header->addr3, priv->bssid);
524 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
525 /* packets to our IBSS update information */
526 return !compare_ether_addr(header->addr2, priv->bssid);
527 default:
528 return 1;
529 }
530}
531
532static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
533 struct iwl_rx_mem_buffer *rxb,
534 struct ieee80211_rx_status *stats)
535{
536 struct iwl_rx_packet *pkt = rxb_addr(rxb);
537 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
538 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
539 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
540 u16 len = le16_to_cpu(rx_hdr->len);
541 struct sk_buff *skb;
542 __le16 fc = hdr->frame_control;
543
544 /* We received data from the HW, so stop the watchdog */
545 if (unlikely(len + IWL39_RX_FRAME_SIZE >
546 PAGE_SIZE << priv->hw_params.rx_page_order)) {
547 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
548 return;
549 }
550
551 /* We only process data packets if the interface is open */
552 if (unlikely(!priv->is_open)) {
553 IWL_DEBUG_DROP_LIMIT(priv,
554 "Dropping packet while interface is not open.\n");
555 return;
556 }
557
558 skb = dev_alloc_skb(128);
559 if (!skb) {
560 IWL_ERR(priv, "dev_alloc_skb failed\n");
561 return;
562 }
563
564 if (!iwl3945_mod_params.sw_crypto)
565 iwl_set_decrypted_flag(priv,
566 (struct ieee80211_hdr *)rxb_addr(rxb),
567 le32_to_cpu(rx_end->status), stats);
568
569 skb_add_rx_frag(skb, 0, rxb->page,
570 (void *)rx_hdr->payload - (void *)pkt, len);
571
572 iwl_update_stats(priv, false, fc, len);
573 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
574
575 ieee80211_rx(priv->hw, skb);
576 priv->alloc_rxb_page--;
577 rxb->page = NULL;
578}
579
580#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
581
582static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
583 struct iwl_rx_mem_buffer *rxb)
584{
585 struct ieee80211_hdr *header;
586 struct ieee80211_rx_status rx_status;
587 struct iwl_rx_packet *pkt = rxb_addr(rxb);
588 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
589 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
590 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
591 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
592 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
593 u8 network_packet;
594
595 rx_status.flag = 0;
596 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
597 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
598 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
599 rx_status.freq =
600 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel),
601 rx_status.band);
602
603 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
604 if (rx_status.band == IEEE80211_BAND_5GHZ)
605 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
606
607 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
608 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
609
610 /* set the preamble flag if appropriate */
611 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
612 rx_status.flag |= RX_FLAG_SHORTPRE;
613
614 if ((unlikely(rx_stats->phy_count > 20))) {
615 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
616 rx_stats->phy_count);
617 return;
618 }
619
620 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
621 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
622 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
623 return;
624 }
625
626
627
628 /* Convert 3945's rssi indicator to dBm */
629 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
630
631 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
632 rx_status.signal, rx_stats_sig_avg,
633 rx_stats_noise_diff);
634
635 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
636
637 network_packet = iwl3945_is_network_packet(priv, header);
638
639 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
640 network_packet ? '*' : ' ',
641 le16_to_cpu(rx_hdr->channel),
642 rx_status.signal, rx_status.signal,
643 rx_status.rate_idx);
644
645 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
646
647 if (network_packet) {
648 priv->_3945.last_beacon_time =
649 le32_to_cpu(rx_end->beacon_timestamp);
650 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
651 priv->_3945.last_rx_rssi = rx_status.signal;
652 }
653
654 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
655}
656
657int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
658 struct iwl_tx_queue *txq,
659 dma_addr_t addr, u16 len, u8 reset, u8 pad)
660{
661 int count;
662 struct iwl_queue *q;
663 struct iwl3945_tfd *tfd, *tfd_tmp;
664
665 q = &txq->q;
666 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
667 tfd = &tfd_tmp[q->write_ptr];
668
669 if (reset)
670 memset(tfd, 0, sizeof(*tfd));
671
672 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
673
674 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
675 IWL_ERR(priv, "Error can not send more than %d chunks\n",
676 NUM_TFD_CHUNKS);
677 return -EINVAL;
678 }
679
680 tfd->tbs[count].addr = cpu_to_le32(addr);
681 tfd->tbs[count].len = cpu_to_le32(len);
682
683 count++;
684
685 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
686 TFD_CTL_PAD_SET(pad));
687
688 return 0;
689}
690
691/**
692 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
693 *
694 * Does NOT advance any indexes
695 */
696void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
697{
698 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
699 int index = txq->q.read_ptr;
700 struct iwl3945_tfd *tfd = &tfd_tmp[index];
701 struct pci_dev *dev = priv->pci_dev;
702 int i;
703 int counter;
704
705 /* sanity check */
706 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
707 if (counter > NUM_TFD_CHUNKS) {
708 IWL_ERR(priv, "Too many chunks: %i\n", counter);
709 /* @todo issue fatal error, it is quite serious situation */
710 return;
711 }
712
713 /* Unmap tx_cmd */
714 if (counter)
715 pci_unmap_single(dev,
716 dma_unmap_addr(&txq->meta[index], mapping),
717 dma_unmap_len(&txq->meta[index], len),
718 PCI_DMA_TODEVICE);
719
720 /* unmap chunks if any */
721
722 for (i = 1; i < counter; i++)
723 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
724 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
725
726 /* free SKB */
727 if (txq->txb) {
728 struct sk_buff *skb;
729
730 skb = txq->txb[txq->q.read_ptr].skb;
731
732 /* can be called from irqs-disabled context */
733 if (skb) {
734 dev_kfree_skb_any(skb);
735 txq->txb[txq->q.read_ptr].skb = NULL;
736 }
737 }
738}
739
740/**
741 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
742 *
743*/
744void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
745 struct iwl_device_cmd *cmd,
746 struct ieee80211_tx_info *info,
747 struct ieee80211_hdr *hdr,
748 int sta_id, int tx_id)
749{
750 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
751 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
752 u16 rate_mask;
753 int rate;
754 u8 rts_retry_limit;
755 u8 data_retry_limit;
756 __le32 tx_flags;
757 __le16 fc = hdr->frame_control;
758 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
759
760 rate = iwl3945_rates[rate_index].plcp;
761 tx_flags = tx_cmd->tx_flags;
762
763 /* We need to figure out how to get the sta->supp_rates while
764 * in this running context */
765 rate_mask = IWL_RATES_MASK_3945;
766
767 /* Set retry limit on DATA packets and Probe Responses*/
768 if (ieee80211_is_probe_resp(fc))
769 data_retry_limit = 3;
770 else
771 data_retry_limit = IWL_DEFAULT_TX_RETRY;
772 tx_cmd->data_retry_limit = data_retry_limit;
773
774 if (tx_id >= IWL39_CMD_QUEUE_NUM)
775 rts_retry_limit = 3;
776 else
777 rts_retry_limit = 7;
778
779 if (data_retry_limit < rts_retry_limit)
780 rts_retry_limit = data_retry_limit;
781 tx_cmd->rts_retry_limit = rts_retry_limit;
782
783 tx_cmd->rate = rate;
784 tx_cmd->tx_flags = tx_flags;
785
786 /* OFDM */
787 tx_cmd->supp_rates[0] =
788 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
789
790 /* CCK */
791 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
792
793 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
794 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
795 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
796 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
797}
798
799static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
800{
801 unsigned long flags_spin;
802 struct iwl_station_entry *station;
803
804 if (sta_id == IWL_INVALID_STATION)
805 return IWL_INVALID_STATION;
806
807 spin_lock_irqsave(&priv->sta_lock, flags_spin);
808 station = &priv->stations[sta_id];
809
810 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
811 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
812 station->sta.mode = STA_CONTROL_MODIFY_MSK;
813 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
814 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
815
816 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
817 sta_id, tx_rate);
818 return sta_id;
819}
820
821static void iwl3945_set_pwr_vmain(struct iwl_priv *priv)
822{
823/*
824 * (for documentation purposes)
825 * to set power to V_AUX, do
826
827 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
828 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
829 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
830 ~APMG_PS_CTRL_MSK_PWR_SRC);
831
832 iwl_poll_bit(priv, CSR_GPIO_IN,
833 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
834 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
835 }
836 */
837
838 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
839 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
840 ~APMG_PS_CTRL_MSK_PWR_SRC);
841
842 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
843 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
844}
845
846static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
847{
848 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
849 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
850 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
851 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
852 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
853 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
854 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
855 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
856 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
857 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
858 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
859 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
860
861 /* fake read to flush all prev I/O */
862 iwl_read_direct32(priv, FH39_RSSR_CTRL);
863
864 return 0;
865}
866
867static int iwl3945_tx_reset(struct iwl_priv *priv)
868{
869
870 /* bypass mode */
871 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
872
873 /* RA 0 is active */
874 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
875
876 /* all 6 fifo are active */
877 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
878
879 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
880 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
881 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
882 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
883
884 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
885 priv->_3945.shared_phys);
886
887 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
888 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
889 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
890 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
891 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
892 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
893 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
894 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
895
896
897 return 0;
898}
899
900/**
901 * iwl3945_txq_ctx_reset - Reset TX queue context
902 *
903 * Destroys all DMA structures and initialize them again
904 */
905static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
906{
907 int rc;
908 int txq_id, slots_num;
909
910 iwl3945_hw_txq_ctx_free(priv);
911
912 /* allocate tx queue structure */
913 rc = iwl_alloc_txq_mem(priv);
914 if (rc)
915 return rc;
916
917 /* Tx CMD queue */
918 rc = iwl3945_tx_reset(priv);
919 if (rc)
920 goto error;
921
922 /* Tx queue(s) */
923 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
924 slots_num = (txq_id == IWL39_CMD_QUEUE_NUM) ?
925 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
926 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
927 txq_id);
928 if (rc) {
929 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
930 goto error;
931 }
932 }
933
934 return rc;
935
936 error:
937 iwl3945_hw_txq_ctx_free(priv);
938 return rc;
939}
940
941
942/*
943 * Start up 3945's basic functionality after it has been reset
944 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
945 * NOTE: This does not load uCode nor start the embedded processor
946 */
947static int iwl3945_apm_init(struct iwl_priv *priv)
948{
949 int ret = iwl_apm_init(priv);
950
951 /* Clear APMG (NIC's internal power management) interrupts */
952 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
953 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
954
955 /* Reset radio chip */
956 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
957 udelay(5);
958 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
959
960 return ret;
961}
962
963static void iwl3945_nic_config(struct iwl_priv *priv)
964{
965 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
966 unsigned long flags;
967 u8 rev_id = 0;
968
969 spin_lock_irqsave(&priv->lock, flags);
970
971 /* Determine HW type */
972 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
973
974 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
975
976 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
977 IWL_DEBUG_INFO(priv, "RTP type\n");
978 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
979 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
980 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
981 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
982 } else {
983 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
984 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
985 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
986 }
987
988 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
989 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
990 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
991 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
992 } else
993 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
994
995 if ((eeprom->board_revision & 0xF0) == 0xD0) {
996 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
997 eeprom->board_revision);
998 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
999 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1000 } else {
1001 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1002 eeprom->board_revision);
1003 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1004 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1005 }
1006
1007 if (eeprom->almgor_m_version <= 1) {
1008 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1009 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1010 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1011 eeprom->almgor_m_version);
1012 } else {
1013 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1014 eeprom->almgor_m_version);
1015 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1016 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1017 }
1018 spin_unlock_irqrestore(&priv->lock, flags);
1019
1020 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1021 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1022
1023 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1024 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1025}
1026
1027int iwl3945_hw_nic_init(struct iwl_priv *priv)
1028{
1029 int rc;
1030 unsigned long flags;
1031 struct iwl_rx_queue *rxq = &priv->rxq;
1032
1033 spin_lock_irqsave(&priv->lock, flags);
1034 priv->cfg->ops->lib->apm_ops.init(priv);
1035 spin_unlock_irqrestore(&priv->lock, flags);
1036
1037 iwl3945_set_pwr_vmain(priv);
1038
1039 priv->cfg->ops->lib->apm_ops.config(priv);
1040
1041 /* Allocate the RX queue, or reset if it is already allocated */
1042 if (!rxq->bd) {
1043 rc = iwl_rx_queue_alloc(priv);
1044 if (rc) {
1045 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1046 return -ENOMEM;
1047 }
1048 } else
1049 iwl3945_rx_queue_reset(priv, rxq);
1050
1051 iwl3945_rx_replenish(priv);
1052
1053 iwl3945_rx_init(priv, rxq);
1054
1055
1056 /* Look at using this instead:
1057 rxq->need_update = 1;
1058 iwl_rx_queue_update_write_ptr(priv, rxq);
1059 */
1060
1061 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1062
1063 rc = iwl3945_txq_ctx_reset(priv);
1064 if (rc)
1065 return rc;
1066
1067 set_bit(STATUS_INIT, &priv->status);
1068
1069 return 0;
1070}
1071
1072/**
1073 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1074 *
1075 * Destroy all TX DMA queues and structures
1076 */
1077void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1078{
1079 int txq_id;
1080
1081 /* Tx queues */
1082 if (priv->txq)
1083 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1084 txq_id++)
1085 if (txq_id == IWL39_CMD_QUEUE_NUM)
1086 iwl_cmd_queue_free(priv);
1087 else
1088 iwl_tx_queue_free(priv, txq_id);
1089
1090 /* free tx queue structure */
1091 iwl_free_txq_mem(priv);
1092}
1093
1094void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1095{
1096 int txq_id;
1097
1098 /* stop SCD */
1099 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1100 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
1101
1102 /* reset TFD queues */
1103 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1104 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1105 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1106 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1107 1000);
1108 }
1109
1110 iwl3945_hw_txq_ctx_free(priv);
1111}
1112
1113/**
1114 * iwl3945_hw_reg_adjust_power_by_temp
1115 * return index delta into power gain settings table
1116*/
1117static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1118{
1119 return (new_reading - old_reading) * (-11) / 100;
1120}
1121
1122/**
1123 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1124 */
1125static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1126{
1127 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1128}
1129
1130int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1131{
1132 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1133}
1134
1135/**
1136 * iwl3945_hw_reg_txpower_get_temperature
1137 * get the current temperature by reading from NIC
1138*/
1139static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1140{
1141 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1142 int temperature;
1143
1144 temperature = iwl3945_hw_get_temperature(priv);
1145
1146 /* driver's okay range is -260 to +25.
1147 * human readable okay range is 0 to +285 */
1148 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1149
1150 /* handle insane temp reading */
1151 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1152 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1153
1154 /* if really really hot(?),
1155 * substitute the 3rd band/group's temp measured at factory */
1156 if (priv->last_temperature > 100)
1157 temperature = eeprom->groups[2].temperature;
1158 else /* else use most recent "sane" value from driver */
1159 temperature = priv->last_temperature;
1160 }
1161
1162 return temperature; /* raw, not "human readable" */
1163}
1164
1165/* Adjust Txpower only if temperature variance is greater than threshold.
1166 *
1167 * Both are lower than older versions' 9 degrees */
1168#define IWL_TEMPERATURE_LIMIT_TIMER 6
1169
1170/**
1171 * is_temp_calib_needed - determines if new calibration is needed
1172 *
1173 * records new temperature in tx_mgr->temperature.
1174 * replaces tx_mgr->last_temperature *only* if calib needed
1175 * (assumes caller will actually do the calibration!). */
1176static int is_temp_calib_needed(struct iwl_priv *priv)
1177{
1178 int temp_diff;
1179
1180 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1181 temp_diff = priv->temperature - priv->last_temperature;
1182
1183 /* get absolute value */
1184 if (temp_diff < 0) {
1185 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1186 temp_diff = -temp_diff;
1187 } else if (temp_diff == 0)
1188 IWL_DEBUG_POWER(priv, "Same temp,\n");
1189 else
1190 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1191
1192 /* if we don't need calibration, *don't* update last_temperature */
1193 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1194 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1195 return 0;
1196 }
1197
1198 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1199
1200 /* assume that caller will actually do calib ...
1201 * update the "last temperature" value */
1202 priv->last_temperature = priv->temperature;
1203 return 1;
1204}
1205
1206#define IWL_MAX_GAIN_ENTRIES 78
1207#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1208#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1209
1210/* radio and DSP power table, each step is 1/2 dB.
1211 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1212static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1213 {
1214 {251, 127}, /* 2.4 GHz, highest power */
1215 {251, 127},
1216 {251, 127},
1217 {251, 127},
1218 {251, 125},
1219 {251, 110},
1220 {251, 105},
1221 {251, 98},
1222 {187, 125},
1223 {187, 115},
1224 {187, 108},
1225 {187, 99},
1226 {243, 119},
1227 {243, 111},
1228 {243, 105},
1229 {243, 97},
1230 {243, 92},
1231 {211, 106},
1232 {211, 100},
1233 {179, 120},
1234 {179, 113},
1235 {179, 107},
1236 {147, 125},
1237 {147, 119},
1238 {147, 112},
1239 {147, 106},
1240 {147, 101},
1241 {147, 97},
1242 {147, 91},
1243 {115, 107},
1244 {235, 121},
1245 {235, 115},
1246 {235, 109},
1247 {203, 127},
1248 {203, 121},
1249 {203, 115},
1250 {203, 108},
1251 {203, 102},
1252 {203, 96},
1253 {203, 92},
1254 {171, 110},
1255 {171, 104},
1256 {171, 98},
1257 {139, 116},
1258 {227, 125},
1259 {227, 119},
1260 {227, 113},
1261 {227, 107},
1262 {227, 101},
1263 {227, 96},
1264 {195, 113},
1265 {195, 106},
1266 {195, 102},
1267 {195, 95},
1268 {163, 113},
1269 {163, 106},
1270 {163, 102},
1271 {163, 95},
1272 {131, 113},
1273 {131, 106},
1274 {131, 102},
1275 {131, 95},
1276 {99, 113},
1277 {99, 106},
1278 {99, 102},
1279 {99, 95},
1280 {67, 113},
1281 {67, 106},
1282 {67, 102},
1283 {67, 95},
1284 {35, 113},
1285 {35, 106},
1286 {35, 102},
1287 {35, 95},
1288 {3, 113},
1289 {3, 106},
1290 {3, 102},
1291 {3, 95} }, /* 2.4 GHz, lowest power */
1292 {
1293 {251, 127}, /* 5.x GHz, highest power */
1294 {251, 120},
1295 {251, 114},
1296 {219, 119},
1297 {219, 101},
1298 {187, 113},
1299 {187, 102},
1300 {155, 114},
1301 {155, 103},
1302 {123, 117},
1303 {123, 107},
1304 {123, 99},
1305 {123, 92},
1306 {91, 108},
1307 {59, 125},
1308 {59, 118},
1309 {59, 109},
1310 {59, 102},
1311 {59, 96},
1312 {59, 90},
1313 {27, 104},
1314 {27, 98},
1315 {27, 92},
1316 {115, 118},
1317 {115, 111},
1318 {115, 104},
1319 {83, 126},
1320 {83, 121},
1321 {83, 113},
1322 {83, 105},
1323 {83, 99},
1324 {51, 118},
1325 {51, 111},
1326 {51, 104},
1327 {51, 98},
1328 {19, 116},
1329 {19, 109},
1330 {19, 102},
1331 {19, 98},
1332 {19, 93},
1333 {171, 113},
1334 {171, 107},
1335 {171, 99},
1336 {139, 120},
1337 {139, 113},
1338 {139, 107},
1339 {139, 99},
1340 {107, 120},
1341 {107, 113},
1342 {107, 107},
1343 {107, 99},
1344 {75, 120},
1345 {75, 113},
1346 {75, 107},
1347 {75, 99},
1348 {43, 120},
1349 {43, 113},
1350 {43, 107},
1351 {43, 99},
1352 {11, 120},
1353 {11, 113},
1354 {11, 107},
1355 {11, 99},
1356 {131, 107},
1357 {131, 99},
1358 {99, 120},
1359 {99, 113},
1360 {99, 107},
1361 {99, 99},
1362 {67, 120},
1363 {67, 113},
1364 {67, 107},
1365 {67, 99},
1366 {35, 120},
1367 {35, 113},
1368 {35, 107},
1369 {35, 99},
1370 {3, 120} } /* 5.x GHz, lowest power */
1371};
1372
1373static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1374{
1375 if (index < 0)
1376 return 0;
1377 if (index >= IWL_MAX_GAIN_ENTRIES)
1378 return IWL_MAX_GAIN_ENTRIES - 1;
1379 return (u8) index;
1380}
1381
1382/* Kick off thermal recalibration check every 60 seconds */
1383#define REG_RECALIB_PERIOD (60)
1384
1385/**
1386 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1387 *
1388 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1389 * or 6 Mbit (OFDM) rates.
1390 */
1391static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1392 s32 rate_index, const s8 *clip_pwrs,
1393 struct iwl_channel_info *ch_info,
1394 int band_index)
1395{
1396 struct iwl3945_scan_power_info *scan_power_info;
1397 s8 power;
1398 u8 power_index;
1399
1400 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1401
1402 /* use this channel group's 6Mbit clipping/saturation pwr,
1403 * but cap at regulatory scan power restriction (set during init
1404 * based on eeprom channel data) for this channel. */
1405 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1406
1407 /* further limit to user's max power preference.
1408 * FIXME: Other spectrum management power limitations do not
1409 * seem to apply?? */
1410 power = min(power, priv->tx_power_user_lmt);
1411 scan_power_info->requested_power = power;
1412
1413 /* find difference between new scan *power* and current "normal"
1414 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1415 * current "normal" temperature-compensated Tx power *index* for
1416 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1417 * *index*. */
1418 power_index = ch_info->power_info[rate_index].power_table_index
1419 - (power - ch_info->power_info
1420 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1421
1422 /* store reference index that we use when adjusting *all* scan
1423 * powers. So we can accommodate user (all channel) or spectrum
1424 * management (single channel) power changes "between" temperature
1425 * feedback compensation procedures.
1426 * don't force fit this reference index into gain table; it may be a
1427 * negative number. This will help avoid errors when we're at
1428 * the lower bounds (highest gains, for warmest temperatures)
1429 * of the table. */
1430
1431 /* don't exceed table bounds for "real" setting */
1432 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1433
1434 scan_power_info->power_table_index = power_index;
1435 scan_power_info->tpc.tx_gain =
1436 power_gain_table[band_index][power_index].tx_gain;
1437 scan_power_info->tpc.dsp_atten =
1438 power_gain_table[band_index][power_index].dsp_atten;
1439}
1440
1441/**
1442 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1443 *
1444 * Configures power settings for all rates for the current channel,
1445 * using values from channel info struct, and send to NIC
1446 */
1447static int iwl3945_send_tx_power(struct iwl_priv *priv)
1448{
1449 int rate_idx, i;
1450 const struct iwl_channel_info *ch_info = NULL;
1451 struct iwl3945_txpowertable_cmd txpower = {
1452 .channel = priv->contexts[IWL_RXON_CTX_BSS].active.channel,
1453 };
1454 u16 chan;
1455
1456 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
1457 "TX Power requested while scanning!\n"))
1458 return -EAGAIN;
1459
1460 chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
1461
1462 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1463 ch_info = iwl_get_channel_info(priv, priv->band, chan);
1464 if (!ch_info) {
1465 IWL_ERR(priv,
1466 "Failed to get channel info for channel %d [%d]\n",
1467 chan, priv->band);
1468 return -EINVAL;
1469 }
1470
1471 if (!is_channel_valid(ch_info)) {
1472 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1473 "non-Tx channel.\n");
1474 return 0;
1475 }
1476
1477 /* fill cmd with power settings for all rates for current channel */
1478 /* Fill OFDM rate */
1479 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1480 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1481
1482 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1483 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1484
1485 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1486 le16_to_cpu(txpower.channel),
1487 txpower.band,
1488 txpower.power[i].tpc.tx_gain,
1489 txpower.power[i].tpc.dsp_atten,
1490 txpower.power[i].rate);
1491 }
1492 /* Fill CCK rates */
1493 for (rate_idx = IWL_FIRST_CCK_RATE;
1494 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1495 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1496 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1497
1498 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1499 le16_to_cpu(txpower.channel),
1500 txpower.band,
1501 txpower.power[i].tpc.tx_gain,
1502 txpower.power[i].tpc.dsp_atten,
1503 txpower.power[i].rate);
1504 }
1505
1506 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1507 sizeof(struct iwl3945_txpowertable_cmd),
1508 &txpower);
1509
1510}
1511
1512/**
1513 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1514 * @ch_info: Channel to update. Uses power_info.requested_power.
1515 *
1516 * Replace requested_power and base_power_index ch_info fields for
1517 * one channel.
1518 *
1519 * Called if user or spectrum management changes power preferences.
1520 * Takes into account h/w and modulation limitations (clip power).
1521 *
1522 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1523 *
1524 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1525 * properly fill out the scan powers, and actual h/w gain settings,
1526 * and send changes to NIC
1527 */
1528static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1529 struct iwl_channel_info *ch_info)
1530{
1531 struct iwl3945_channel_power_info *power_info;
1532 int power_changed = 0;
1533 int i;
1534 const s8 *clip_pwrs;
1535 int power;
1536
1537 /* Get this chnlgrp's rate-to-max/clip-powers table */
1538 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1539
1540 /* Get this channel's rate-to-current-power settings table */
1541 power_info = ch_info->power_info;
1542
1543 /* update OFDM Txpower settings */
1544 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1545 i++, ++power_info) {
1546 int delta_idx;
1547
1548 /* limit new power to be no more than h/w capability */
1549 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1550 if (power == power_info->requested_power)
1551 continue;
1552
1553 /* find difference between old and new requested powers,
1554 * update base (non-temp-compensated) power index */
1555 delta_idx = (power - power_info->requested_power) * 2;
1556 power_info->base_power_index -= delta_idx;
1557
1558 /* save new requested power value */
1559 power_info->requested_power = power;
1560
1561 power_changed = 1;
1562 }
1563
1564 /* update CCK Txpower settings, based on OFDM 12M setting ...
1565 * ... all CCK power settings for a given channel are the *same*. */
1566 if (power_changed) {
1567 power =
1568 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1569 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1570
1571 /* do all CCK rates' iwl3945_channel_power_info structures */
1572 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1573 power_info->requested_power = power;
1574 power_info->base_power_index =
1575 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1576 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1577 ++power_info;
1578 }
1579 }
1580
1581 return 0;
1582}
1583
1584/**
1585 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1586 *
1587 * NOTE: Returned power limit may be less (but not more) than requested,
1588 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1589 * (no consideration for h/w clipping limitations).
1590 */
1591static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1592{
1593 s8 max_power;
1594
1595#if 0
1596 /* if we're using TGd limits, use lower of TGd or EEPROM */
1597 if (ch_info->tgd_data.max_power != 0)
1598 max_power = min(ch_info->tgd_data.max_power,
1599 ch_info->eeprom.max_power_avg);
1600
1601 /* else just use EEPROM limits */
1602 else
1603#endif
1604 max_power = ch_info->eeprom.max_power_avg;
1605
1606 return min(max_power, ch_info->max_power_avg);
1607}
1608
1609/**
1610 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1611 *
1612 * Compensate txpower settings of *all* channels for temperature.
1613 * This only accounts for the difference between current temperature
1614 * and the factory calibration temperatures, and bases the new settings
1615 * on the channel's base_power_index.
1616 *
1617 * If RxOn is "associated", this sends the new Txpower to NIC!
1618 */
1619static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1620{
1621 struct iwl_channel_info *ch_info = NULL;
1622 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1623 int delta_index;
1624 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1625 u8 a_band;
1626 u8 rate_index;
1627 u8 scan_tbl_index;
1628 u8 i;
1629 int ref_temp;
1630 int temperature = priv->temperature;
1631
1632 if (priv->disable_tx_power_cal ||
1633 test_bit(STATUS_SCANNING, &priv->status)) {
1634 /* do not perform tx power calibration */
1635 return 0;
1636 }
1637 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1638 for (i = 0; i < priv->channel_count; i++) {
1639 ch_info = &priv->channel_info[i];
1640 a_band = is_channel_a_band(ch_info);
1641
1642 /* Get this chnlgrp's factory calibration temperature */
1643 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1644 temperature;
1645
1646 /* get power index adjustment based on current and factory
1647 * temps */
1648 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1649 ref_temp);
1650
1651 /* set tx power value for all rates, OFDM and CCK */
1652 for (rate_index = 0; rate_index < IWL_RATE_COUNT_3945;
1653 rate_index++) {
1654 int power_idx =
1655 ch_info->power_info[rate_index].base_power_index;
1656
1657 /* temperature compensate */
1658 power_idx += delta_index;
1659
1660 /* stay within table range */
1661 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1662 ch_info->power_info[rate_index].
1663 power_table_index = (u8) power_idx;
1664 ch_info->power_info[rate_index].tpc =
1665 power_gain_table[a_band][power_idx];
1666 }
1667
1668 /* Get this chnlgrp's rate-to-max/clip-powers table */
1669 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
1670
1671 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1672 for (scan_tbl_index = 0;
1673 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1674 s32 actual_index = (scan_tbl_index == 0) ?
1675 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1676 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1677 actual_index, clip_pwrs,
1678 ch_info, a_band);
1679 }
1680 }
1681
1682 /* send Txpower command for current channel to ucode */
1683 return priv->cfg->ops->lib->send_tx_power(priv);
1684}
1685
1686int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1687{
1688 struct iwl_channel_info *ch_info;
1689 s8 max_power;
1690 u8 a_band;
1691 u8 i;
1692
1693 if (priv->tx_power_user_lmt == power) {
1694 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1695 "limit: %ddBm.\n", power);
1696 return 0;
1697 }
1698
1699 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1700 priv->tx_power_user_lmt = power;
1701
1702 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1703
1704 for (i = 0; i < priv->channel_count; i++) {
1705 ch_info = &priv->channel_info[i];
1706 a_band = is_channel_a_band(ch_info);
1707
1708 /* find minimum power of all user and regulatory constraints
1709 * (does not consider h/w clipping limitations) */
1710 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1711 max_power = min(power, max_power);
1712 if (max_power != ch_info->curr_txpow) {
1713 ch_info->curr_txpow = max_power;
1714
1715 /* this considers the h/w clipping limitations */
1716 iwl3945_hw_reg_set_new_power(priv, ch_info);
1717 }
1718 }
1719
1720 /* update txpower settings for all channels,
1721 * send to NIC if associated. */
1722 is_temp_calib_needed(priv);
1723 iwl3945_hw_reg_comp_txpower_temp(priv);
1724
1725 return 0;
1726}
1727
1728static int iwl3945_send_rxon_assoc(struct iwl_priv *priv,
1729 struct iwl_rxon_context *ctx)
1730{
1731 int rc = 0;
1732 struct iwl_rx_packet *pkt;
1733 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1734 struct iwl_host_cmd cmd = {
1735 .id = REPLY_RXON_ASSOC,
1736 .len = sizeof(rxon_assoc),
1737 .flags = CMD_WANT_SKB,
1738 .data = &rxon_assoc,
1739 };
1740 const struct iwl_rxon_cmd *rxon1 = &ctx->staging;
1741 const struct iwl_rxon_cmd *rxon2 = &ctx->active;
1742
1743 if ((rxon1->flags == rxon2->flags) &&
1744 (rxon1->filter_flags == rxon2->filter_flags) &&
1745 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1746 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1747 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1748 return 0;
1749 }
1750
1751 rxon_assoc.flags = ctx->staging.flags;
1752 rxon_assoc.filter_flags = ctx->staging.filter_flags;
1753 rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates;
1754 rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates;
1755 rxon_assoc.reserved = 0;
1756
1757 rc = iwl_send_cmd_sync(priv, &cmd);
1758 if (rc)
1759 return rc;
1760
1761 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1762 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
1763 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1764 rc = -EIO;
1765 }
1766
1767 iwl_free_pages(priv, cmd.reply_page);
1768
1769 return rc;
1770}
1771
1772/**
1773 * iwl3945_commit_rxon - commit staging_rxon to hardware
1774 *
1775 * The RXON command in staging_rxon is committed to the hardware and
1776 * the active_rxon structure is updated with the new data. This
1777 * function correctly transitions out of the RXON_ASSOC_MSK state if
1778 * a HW tune is required based on the RXON structure changes.
1779 */
1780int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1781{
1782 /* cast away the const for active_rxon in this function */
1783 struct iwl3945_rxon_cmd *active_rxon = (void *)&ctx->active;
1784 struct iwl3945_rxon_cmd *staging_rxon = (void *)&ctx->staging;
1785 int rc = 0;
1786 bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
1787
1788 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1789 return -EINVAL;
1790
1791 if (!iwl_is_alive(priv))
1792 return -1;
1793
1794 /* always get timestamp with Rx frame */
1795 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1796
1797 /* select antenna */
1798 staging_rxon->flags &=
1799 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1800 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1801
1802 rc = iwl_check_rxon_cmd(priv, ctx);
1803 if (rc) {
1804 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1805 return -EINVAL;
1806 }
1807
1808 /* If we don't need to send a full RXON, we can use
1809 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1810 * and other flags for the current radio configuration. */
1811 if (!iwl_full_rxon_required(priv, &priv->contexts[IWL_RXON_CTX_BSS])) {
1812 rc = iwl_send_rxon_assoc(priv,
1813 &priv->contexts[IWL_RXON_CTX_BSS]);
1814 if (rc) {
1815 IWL_ERR(priv, "Error setting RXON_ASSOC "
1816 "configuration (%d).\n", rc);
1817 return rc;
1818 }
1819
1820 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1821
1822 return 0;
1823 }
1824
1825 /* If we are currently associated and the new config requires
1826 * an RXON_ASSOC and the new config wants the associated mask enabled,
1827 * we must clear the associated from the active configuration
1828 * before we apply the new config */
1829 if (iwl_is_associated(priv, IWL_RXON_CTX_BSS) && new_assoc) {
1830 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1831 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1832
1833 /*
1834 * reserved4 and 5 could have been filled by the iwlcore code.
1835 * Let's clear them before pushing to the 3945.
1836 */
1837 active_rxon->reserved4 = 0;
1838 active_rxon->reserved5 = 0;
1839 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1840 sizeof(struct iwl3945_rxon_cmd),
1841 &priv->contexts[IWL_RXON_CTX_BSS].active);
1842
1843 /* If the mask clearing failed then we set
1844 * active_rxon back to what it was previously */
1845 if (rc) {
1846 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1847 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1848 "configuration (%d).\n", rc);
1849 return rc;
1850 }
1851 iwl_clear_ucode_stations(priv,
1852 &priv->contexts[IWL_RXON_CTX_BSS]);
1853 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1854 }
1855
1856 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1857 "* with%s RXON_FILTER_ASSOC_MSK\n"
1858 "* channel = %d\n"
1859 "* bssid = %pM\n",
1860 (new_assoc ? "" : "out"),
1861 le16_to_cpu(staging_rxon->channel),
1862 staging_rxon->bssid_addr);
1863
1864 /*
1865 * reserved4 and 5 could have been filled by the iwlcore code.
1866 * Let's clear them before pushing to the 3945.
1867 */
1868 staging_rxon->reserved4 = 0;
1869 staging_rxon->reserved5 = 0;
1870
1871 iwl_set_rxon_hwcrypto(priv, ctx, !iwl3945_mod_params.sw_crypto);
1872
1873 /* Apply the new configuration */
1874 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1875 sizeof(struct iwl3945_rxon_cmd),
1876 staging_rxon);
1877 if (rc) {
1878 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1879 return rc;
1880 }
1881
1882 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1883
1884 if (!new_assoc) {
1885 iwl_clear_ucode_stations(priv,
1886 &priv->contexts[IWL_RXON_CTX_BSS]);
1887 iwl_restore_stations(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
1888 }
1889
1890 /* If we issue a new RXON command which required a tune then we must
1891 * send a new TXPOWER command or we won't be able to Tx any frames */
1892 rc = iwl_set_tx_power(priv, priv->tx_power_next, true);
1893 if (rc) {
1894 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1895 return rc;
1896 }
1897
1898 /* Init the hardware's rate fallback order based on the band */
1899 rc = iwl3945_init_hw_rate_table(priv);
1900 if (rc) {
1901 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1902 return -EIO;
1903 }
1904
1905 return 0;
1906}
1907
1908/**
1909 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1910 *
1911 * -- reset periodic timer
1912 * -- see if temp has changed enough to warrant re-calibration ... if so:
1913 * -- correct coeffs for temp (can reset temp timer)
1914 * -- save this temp as "last",
1915 * -- send new set of gain settings to NIC
1916 * NOTE: This should continue working, even when we're not associated,
1917 * so we can keep our internal table of scan powers current. */
1918void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1919{
1920 /* This will kick in the "brute force"
1921 * iwl3945_hw_reg_comp_txpower_temp() below */
1922 if (!is_temp_calib_needed(priv))
1923 goto reschedule;
1924
1925 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1926 * This is based *only* on current temperature,
1927 * ignoring any previous power measurements */
1928 iwl3945_hw_reg_comp_txpower_temp(priv);
1929
1930 reschedule:
1931 queue_delayed_work(priv->workqueue,
1932 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
1933}
1934
1935static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1936{
1937 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1938 _3945.thermal_periodic.work);
1939
1940 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1941 return;
1942
1943 mutex_lock(&priv->mutex);
1944 iwl3945_reg_txpower_periodic(priv);
1945 mutex_unlock(&priv->mutex);
1946}
1947
1948/**
1949 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1950 * for the channel.
1951 *
1952 * This function is used when initializing channel-info structs.
1953 *
1954 * NOTE: These channel groups do *NOT* match the bands above!
1955 * These channel groups are based on factory-tested channels;
1956 * on A-band, EEPROM's "group frequency" entries represent the top
1957 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1958 */
1959static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1960 const struct iwl_channel_info *ch_info)
1961{
1962 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1963 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
1964 u8 group;
1965 u16 group_index = 0; /* based on factory calib frequencies */
1966 u8 grp_channel;
1967
1968 /* Find the group index for the channel ... don't use index 1(?) */
1969 if (is_channel_a_band(ch_info)) {
1970 for (group = 1; group < 5; group++) {
1971 grp_channel = ch_grp[group].group_channel;
1972 if (ch_info->channel <= grp_channel) {
1973 group_index = group;
1974 break;
1975 }
1976 }
1977 /* group 4 has a few channels *above* its factory cal freq */
1978 if (group == 5)
1979 group_index = 4;
1980 } else
1981 group_index = 0; /* 2.4 GHz, group 0 */
1982
1983 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
1984 group_index);
1985 return group_index;
1986}
1987
1988/**
1989 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
1990 *
1991 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1992 * into radio/DSP gain settings table for requested power.
1993 */
1994static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1995 s8 requested_power,
1996 s32 setting_index, s32 *new_index)
1997{
1998 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
1999 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2000 s32 index0, index1;
2001 s32 power = 2 * requested_power;
2002 s32 i;
2003 const struct iwl3945_eeprom_txpower_sample *samples;
2004 s32 gains0, gains1;
2005 s32 res;
2006 s32 denominator;
2007
2008 chnl_grp = &eeprom->groups[setting_index];
2009 samples = chnl_grp->samples;
2010 for (i = 0; i < 5; i++) {
2011 if (power == samples[i].power) {
2012 *new_index = samples[i].gain_index;
2013 return 0;
2014 }
2015 }
2016
2017 if (power > samples[1].power) {
2018 index0 = 0;
2019 index1 = 1;
2020 } else if (power > samples[2].power) {
2021 index0 = 1;
2022 index1 = 2;
2023 } else if (power > samples[3].power) {
2024 index0 = 2;
2025 index1 = 3;
2026 } else {
2027 index0 = 3;
2028 index1 = 4;
2029 }
2030
2031 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2032 if (denominator == 0)
2033 return -EINVAL;
2034 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2035 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2036 res = gains0 + (gains1 - gains0) *
2037 ((s32) power - (s32) samples[index0].power) / denominator +
2038 (1 << 18);
2039 *new_index = res >> 19;
2040 return 0;
2041}
2042
2043static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2044{
2045 u32 i;
2046 s32 rate_index;
2047 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2048 const struct iwl3945_eeprom_txpower_group *group;
2049
2050 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2051
2052 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2053 s8 *clip_pwrs; /* table of power levels for each rate */
2054 s8 satur_pwr; /* saturation power for each chnl group */
2055 group = &eeprom->groups[i];
2056
2057 /* sanity check on factory saturation power value */
2058 if (group->saturation_power < 40) {
2059 IWL_WARN(priv, "Error: saturation power is %d, "
2060 "less than minimum expected 40\n",
2061 group->saturation_power);
2062 return;
2063 }
2064
2065 /*
2066 * Derive requested power levels for each rate, based on
2067 * hardware capabilities (saturation power for band).
2068 * Basic value is 3dB down from saturation, with further
2069 * power reductions for highest 3 data rates. These
2070 * backoffs provide headroom for high rate modulation
2071 * power peaks, without too much distortion (clipping).
2072 */
2073 /* we'll fill in this array with h/w max power levels */
2074 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
2075
2076 /* divide factory saturation power by 2 to find -3dB level */
2077 satur_pwr = (s8) (group->saturation_power >> 1);
2078
2079 /* fill in channel group's nominal powers for each rate */
2080 for (rate_index = 0;
2081 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
2082 switch (rate_index) {
2083 case IWL_RATE_36M_INDEX_TABLE:
2084 if (i == 0) /* B/G */
2085 *clip_pwrs = satur_pwr;
2086 else /* A */
2087 *clip_pwrs = satur_pwr - 5;
2088 break;
2089 case IWL_RATE_48M_INDEX_TABLE:
2090 if (i == 0)
2091 *clip_pwrs = satur_pwr - 7;
2092 else
2093 *clip_pwrs = satur_pwr - 10;
2094 break;
2095 case IWL_RATE_54M_INDEX_TABLE:
2096 if (i == 0)
2097 *clip_pwrs = satur_pwr - 9;
2098 else
2099 *clip_pwrs = satur_pwr - 12;
2100 break;
2101 default:
2102 *clip_pwrs = satur_pwr;
2103 break;
2104 }
2105 }
2106 }
2107}
2108
2109/**
2110 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2111 *
2112 * Second pass (during init) to set up priv->channel_info
2113 *
2114 * Set up Tx-power settings in our channel info database for each VALID
2115 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2116 * and current temperature.
2117 *
2118 * Since this is based on current temperature (at init time), these values may
2119 * not be valid for very long, but it gives us a starting/default point,
2120 * and allows us to active (i.e. using Tx) scan.
2121 *
2122 * This does *not* write values to NIC, just sets up our internal table.
2123 */
2124int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2125{
2126 struct iwl_channel_info *ch_info = NULL;
2127 struct iwl3945_channel_power_info *pwr_info;
2128 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2129 int delta_index;
2130 u8 rate_index;
2131 u8 scan_tbl_index;
2132 const s8 *clip_pwrs; /* array of power levels for each rate */
2133 u8 gain, dsp_atten;
2134 s8 power;
2135 u8 pwr_index, base_pwr_index, a_band;
2136 u8 i;
2137 int temperature;
2138
2139 /* save temperature reference,
2140 * so we can determine next time to calibrate */
2141 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2142 priv->last_temperature = temperature;
2143
2144 iwl3945_hw_reg_init_channel_groups(priv);
2145
2146 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2147 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2148 i++, ch_info++) {
2149 a_band = is_channel_a_band(ch_info);
2150 if (!is_channel_valid(ch_info))
2151 continue;
2152
2153 /* find this channel's channel group (*not* "band") index */
2154 ch_info->group_index =
2155 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2156
2157 /* Get this chnlgrp's rate->max/clip-powers table */
2158 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
2159
2160 /* calculate power index *adjustment* value according to
2161 * diff between current temperature and factory temperature */
2162 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2163 eeprom->groups[ch_info->group_index].
2164 temperature);
2165
2166 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2167 ch_info->channel, delta_index, temperature +
2168 IWL_TEMP_CONVERT);
2169
2170 /* set tx power value for all OFDM rates */
2171 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2172 rate_index++) {
2173 s32 uninitialized_var(power_idx);
2174 int rc;
2175
2176 /* use channel group's clip-power table,
2177 * but don't exceed channel's max power */
2178 s8 pwr = min(ch_info->max_power_avg,
2179 clip_pwrs[rate_index]);
2180
2181 pwr_info = &ch_info->power_info[rate_index];
2182
2183 /* get base (i.e. at factory-measured temperature)
2184 * power table index for this rate's power */
2185 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2186 ch_info->group_index,
2187 &power_idx);
2188 if (rc) {
2189 IWL_ERR(priv, "Invalid power index\n");
2190 return rc;
2191 }
2192 pwr_info->base_power_index = (u8) power_idx;
2193
2194 /* temperature compensate */
2195 power_idx += delta_index;
2196
2197 /* stay within range of gain table */
2198 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2199
2200 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2201 pwr_info->requested_power = pwr;
2202 pwr_info->power_table_index = (u8) power_idx;
2203 pwr_info->tpc.tx_gain =
2204 power_gain_table[a_band][power_idx].tx_gain;
2205 pwr_info->tpc.dsp_atten =
2206 power_gain_table[a_band][power_idx].dsp_atten;
2207 }
2208
2209 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2210 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2211 power = pwr_info->requested_power +
2212 IWL_CCK_FROM_OFDM_POWER_DIFF;
2213 pwr_index = pwr_info->power_table_index +
2214 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2215 base_pwr_index = pwr_info->base_power_index +
2216 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2217
2218 /* stay within table range */
2219 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2220 gain = power_gain_table[a_band][pwr_index].tx_gain;
2221 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2222
2223 /* fill each CCK rate's iwl3945_channel_power_info structure
2224 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2225 * NOTE: CCK rates start at end of OFDM rates! */
2226 for (rate_index = 0;
2227 rate_index < IWL_CCK_RATES; rate_index++) {
2228 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2229 pwr_info->requested_power = power;
2230 pwr_info->power_table_index = pwr_index;
2231 pwr_info->base_power_index = base_pwr_index;
2232 pwr_info->tpc.tx_gain = gain;
2233 pwr_info->tpc.dsp_atten = dsp_atten;
2234 }
2235
2236 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2237 for (scan_tbl_index = 0;
2238 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2239 s32 actual_index = (scan_tbl_index == 0) ?
2240 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2241 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2242 actual_index, clip_pwrs, ch_info, a_band);
2243 }
2244 }
2245
2246 return 0;
2247}
2248
2249int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2250{
2251 int rc;
2252
2253 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2254 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2255 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2256 if (rc < 0)
2257 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2258
2259 return 0;
2260}
2261
2262int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2263{
2264 int txq_id = txq->q.id;
2265
2266 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
2267
2268 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2269
2270 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2271 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2272
2273 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2274 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2275 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2276 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2277 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2278 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2279
2280 /* fake read to flush all prev. writes */
2281 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2282
2283 return 0;
2284}
2285
2286/*
2287 * HCMD utils
2288 */
2289static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2290{
2291 switch (cmd_id) {
2292 case REPLY_RXON:
2293 return sizeof(struct iwl3945_rxon_cmd);
2294 case POWER_TABLE_CMD:
2295 return sizeof(struct iwl3945_powertable_cmd);
2296 default:
2297 return len;
2298 }
2299}
2300
2301
2302static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2303{
2304 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2305 addsta->mode = cmd->mode;
2306 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2307 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2308 addsta->station_flags = cmd->station_flags;
2309 addsta->station_flags_msk = cmd->station_flags_msk;
2310 addsta->tid_disable_tx = cpu_to_le16(0);
2311 addsta->rate_n_flags = cmd->rate_n_flags;
2312 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2313 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2314 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2315
2316 return (u16)sizeof(struct iwl3945_addsta_cmd);
2317}
2318
2319static int iwl3945_add_bssid_station(struct iwl_priv *priv,
2320 const u8 *addr, u8 *sta_id_r)
2321{
2322 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2323 int ret;
2324 u8 sta_id;
2325 unsigned long flags;
2326
2327 if (sta_id_r)
2328 *sta_id_r = IWL_INVALID_STATION;
2329
2330 ret = iwl_add_station_common(priv, ctx, addr, 0, NULL, &sta_id);
2331 if (ret) {
2332 IWL_ERR(priv, "Unable to add station %pM\n", addr);
2333 return ret;
2334 }
2335
2336 if (sta_id_r)
2337 *sta_id_r = sta_id;
2338
2339 spin_lock_irqsave(&priv->sta_lock, flags);
2340 priv->stations[sta_id].used |= IWL_STA_LOCAL;
2341 spin_unlock_irqrestore(&priv->sta_lock, flags);
2342
2343 return 0;
2344}
2345static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2346 struct ieee80211_vif *vif, bool add)
2347{
2348 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2349 int ret;
2350
2351 if (add) {
2352 ret = iwl3945_add_bssid_station(priv, vif->bss_conf.bssid,
2353 &vif_priv->ibss_bssid_sta_id);
2354 if (ret)
2355 return ret;
2356
2357 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
2358 (priv->band == IEEE80211_BAND_5GHZ) ?
2359 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
2360 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
2361
2362 return 0;
2363 }
2364
2365 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2366 vif->bss_conf.bssid);
2367}
2368
2369/**
2370 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2371 */
2372int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2373{
2374 int rc, i, index, prev_index;
2375 struct iwl3945_rate_scaling_cmd rate_cmd = {
2376 .reserved = {0, 0, 0},
2377 };
2378 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2379
2380 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2381 index = iwl3945_rates[i].table_rs_index;
2382
2383 table[index].rate_n_flags =
2384 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2385 table[index].try_cnt = priv->retry_rate;
2386 prev_index = iwl3945_get_prev_ieee_rate(i);
2387 table[index].next_rate_index =
2388 iwl3945_rates[prev_index].table_rs_index;
2389 }
2390
2391 switch (priv->band) {
2392 case IEEE80211_BAND_5GHZ:
2393 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2394 /* If one of the following CCK rates is used,
2395 * have it fall back to the 6M OFDM rate */
2396 for (i = IWL_RATE_1M_INDEX_TABLE;
2397 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2398 table[i].next_rate_index =
2399 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2400
2401 /* Don't fall back to CCK rates */
2402 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2403 IWL_RATE_9M_INDEX_TABLE;
2404
2405 /* Don't drop out of OFDM rates */
2406 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2407 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2408 break;
2409
2410 case IEEE80211_BAND_2GHZ:
2411 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2412 /* If an OFDM rate is used, have it fall back to the
2413 * 1M CCK rates */
2414
2415 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2416 iwl_is_associated(priv, IWL_RXON_CTX_BSS)) {
2417
2418 index = IWL_FIRST_CCK_RATE;
2419 for (i = IWL_RATE_6M_INDEX_TABLE;
2420 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2421 table[i].next_rate_index =
2422 iwl3945_rates[index].table_rs_index;
2423
2424 index = IWL_RATE_11M_INDEX_TABLE;
2425 /* CCK shouldn't fall back to OFDM... */
2426 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2427 }
2428 break;
2429
2430 default:
2431 WARN_ON(1);
2432 break;
2433 }
2434
2435 /* Update the rate scaling for control frame Tx */
2436 rate_cmd.table_id = 0;
2437 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2438 &rate_cmd);
2439 if (rc)
2440 return rc;
2441
2442 /* Update the rate scaling for data frame Tx */
2443 rate_cmd.table_id = 1;
2444 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2445 &rate_cmd);
2446}
2447
2448/* Called when initializing driver */
2449int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2450{
2451 memset((void *)&priv->hw_params, 0,
2452 sizeof(struct iwl_hw_params));
2453
2454 priv->_3945.shared_virt =
2455 dma_alloc_coherent(&priv->pci_dev->dev,
2456 sizeof(struct iwl3945_shared),
2457 &priv->_3945.shared_phys, GFP_KERNEL);
2458 if (!priv->_3945.shared_virt) {
2459 IWL_ERR(priv, "failed to allocate pci memory\n");
2460 return -ENOMEM;
2461 }
2462
2463 /* Assign number of Usable TX queues */
2464 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
2465
2466 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2467 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
2468 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2469 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2470 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2471 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id = IWL3945_BROADCAST_ID;
2472
2473 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2474
2475 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2476 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2477 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
2478
2479 return 0;
2480}
2481
2482unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2483 struct iwl3945_frame *frame, u8 rate)
2484{
2485 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2486 unsigned int frame_size;
2487
2488 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2489 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2490
2491 tx_beacon_cmd->tx.sta_id =
2492 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
2493 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2494
2495 frame_size = iwl3945_fill_beacon_frame(priv,
2496 tx_beacon_cmd->frame,
2497 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2498
2499 BUG_ON(frame_size > MAX_MPDU_SIZE);
2500 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2501
2502 tx_beacon_cmd->tx.rate = rate;
2503 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2504 TX_CMD_FLG_TSF_MSK);
2505
2506 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2507 tx_beacon_cmd->tx.supp_rates[0] =
2508 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2509
2510 tx_beacon_cmd->tx.supp_rates[1] =
2511 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2512
2513 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2514}
2515
2516void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2517{
2518 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2519 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2520}
2521
2522void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2523{
2524 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
2525 iwl3945_bg_reg_txpower_periodic);
2526}
2527
2528void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2529{
2530 cancel_delayed_work(&priv->_3945.thermal_periodic);
2531}
2532
2533/* check contents of special bootstrap uCode SRAM */
2534static int iwl3945_verify_bsm(struct iwl_priv *priv)
2535 {
2536 __le32 *image = priv->ucode_boot.v_addr;
2537 u32 len = priv->ucode_boot.len;
2538 u32 reg;
2539 u32 val;
2540
2541 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2542
2543 /* verify BSM SRAM contents */
2544 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2545 for (reg = BSM_SRAM_LOWER_BOUND;
2546 reg < BSM_SRAM_LOWER_BOUND + len;
2547 reg += sizeof(u32), image++) {
2548 val = iwl_read_prph(priv, reg);
2549 if (val != le32_to_cpu(*image)) {
2550 IWL_ERR(priv, "BSM uCode verification failed at "
2551 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2552 BSM_SRAM_LOWER_BOUND,
2553 reg - BSM_SRAM_LOWER_BOUND, len,
2554 val, le32_to_cpu(*image));
2555 return -EIO;
2556 }
2557 }
2558
2559 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2560
2561 return 0;
2562}
2563
2564
2565/******************************************************************************
2566 *
2567 * EEPROM related functions
2568 *
2569 ******************************************************************************/
2570
2571/*
2572 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2573 * embedded controller) as EEPROM reader; each read is a series of pulses
2574 * to/from the EEPROM chip, not a single event, so even reads could conflict
2575 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2576 * simply claims ownership, which should be safe when this function is called
2577 * (i.e. before loading uCode!).
2578 */
2579static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2580{
2581 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2582 return 0;
2583}
2584
2585
2586static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2587{
2588 return;
2589}
2590
2591 /**
2592 * iwl3945_load_bsm - Load bootstrap instructions
2593 *
2594 * BSM operation:
2595 *
2596 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2597 * in special SRAM that does not power down during RFKILL. When powering back
2598 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2599 * the bootstrap program into the on-board processor, and starts it.
2600 *
2601 * The bootstrap program loads (via DMA) instructions and data for a new
2602 * program from host DRAM locations indicated by the host driver in the
2603 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2604 * automatically.
2605 *
2606 * When initializing the NIC, the host driver points the BSM to the
2607 * "initialize" uCode image. This uCode sets up some internal data, then
2608 * notifies host via "initialize alive" that it is complete.
2609 *
2610 * The host then replaces the BSM_DRAM_* pointer values to point to the
2611 * normal runtime uCode instructions and a backup uCode data cache buffer
2612 * (filled initially with starting data values for the on-board processor),
2613 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2614 * which begins normal operation.
2615 *
2616 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2617 * the backup data cache in DRAM before SRAM is powered down.
2618 *
2619 * When powering back up, the BSM loads the bootstrap program. This reloads
2620 * the runtime uCode instructions and the backup data cache into SRAM,
2621 * and re-launches the runtime uCode from where it left off.
2622 */
2623static int iwl3945_load_bsm(struct iwl_priv *priv)
2624{
2625 __le32 *image = priv->ucode_boot.v_addr;
2626 u32 len = priv->ucode_boot.len;
2627 dma_addr_t pinst;
2628 dma_addr_t pdata;
2629 u32 inst_len;
2630 u32 data_len;
2631 int rc;
2632 int i;
2633 u32 done;
2634 u32 reg_offset;
2635
2636 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2637
2638 /* make sure bootstrap program is no larger than BSM's SRAM size */
2639 if (len > IWL39_MAX_BSM_SIZE)
2640 return -EINVAL;
2641
2642 /* Tell bootstrap uCode where to find the "Initialize" uCode
2643 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2644 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2645 * after the "initialize" uCode has run, to point to
2646 * runtime/protocol instructions and backup data cache. */
2647 pinst = priv->ucode_init.p_addr;
2648 pdata = priv->ucode_init_data.p_addr;
2649 inst_len = priv->ucode_init.len;
2650 data_len = priv->ucode_init_data.len;
2651
2652 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2653 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2654 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2655 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2656
2657 /* Fill BSM memory with bootstrap instructions */
2658 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2659 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2660 reg_offset += sizeof(u32), image++)
2661 _iwl_write_prph(priv, reg_offset,
2662 le32_to_cpu(*image));
2663
2664 rc = iwl3945_verify_bsm(priv);
2665 if (rc)
2666 return rc;
2667
2668 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2669 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2670 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2671 IWL39_RTC_INST_LOWER_BOUND);
2672 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2673
2674 /* Load bootstrap code into instruction SRAM now,
2675 * to prepare to load "initialize" uCode */
2676 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2677 BSM_WR_CTRL_REG_BIT_START);
2678
2679 /* Wait for load of bootstrap uCode to finish */
2680 for (i = 0; i < 100; i++) {
2681 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2682 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2683 break;
2684 udelay(10);
2685 }
2686 if (i < 100)
2687 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2688 else {
2689 IWL_ERR(priv, "BSM write did not complete!\n");
2690 return -EIO;
2691 }
2692
2693 /* Enable future boot loads whenever power management unit triggers it
2694 * (e.g. when powering back up after power-save shutdown) */
2695 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2696 BSM_WR_CTRL_REG_BIT_START_EN);
2697
2698 return 0;
2699}
2700
2701static struct iwl_hcmd_ops iwl3945_hcmd = {
2702 .rxon_assoc = iwl3945_send_rxon_assoc,
2703 .commit_rxon = iwl3945_commit_rxon,
2704 .send_bt_config = iwl_send_bt_config,
2705};
2706
2707static struct iwl_lib_ops iwl3945_lib = {
2708 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2709 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2710 .txq_init = iwl3945_hw_tx_queue_init,
2711 .load_ucode = iwl3945_load_bsm,
2712 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2713 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2714 .apm_ops = {
2715 .init = iwl3945_apm_init,
2716 .config = iwl3945_nic_config,
2717 },
2718 .eeprom_ops = {
2719 .regulatory_bands = {
2720 EEPROM_REGULATORY_BAND_1_CHANNELS,
2721 EEPROM_REGULATORY_BAND_2_CHANNELS,
2722 EEPROM_REGULATORY_BAND_3_CHANNELS,
2723 EEPROM_REGULATORY_BAND_4_CHANNELS,
2724 EEPROM_REGULATORY_BAND_5_CHANNELS,
2725 EEPROM_REGULATORY_BAND_NO_HT40,
2726 EEPROM_REGULATORY_BAND_NO_HT40,
2727 },
2728 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2729 .release_semaphore = iwl3945_eeprom_release_semaphore,
2730 .query_addr = iwlcore_eeprom_query_addr,
2731 },
2732 .send_tx_power = iwl3945_send_tx_power,
2733 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2734 .isr_ops = {
2735 .isr = iwl_isr_legacy,
2736 },
2737
2738 .debugfs_ops = {
2739 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2740 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2741 .general_stats_read = iwl3945_ucode_general_stats_read,
2742 },
2743};
2744
2745static const struct iwl_legacy_ops iwl3945_legacy_ops = {
2746 .post_associate = iwl3945_post_associate,
2747 .config_ap = iwl3945_config_ap,
2748 .manage_ibss_station = iwl3945_manage_ibss_station,
2749};
2750
2751static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2752 .get_hcmd_size = iwl3945_get_hcmd_size,
2753 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2754 .tx_cmd_protection = iwl_legacy_tx_cmd_protection,
2755 .request_scan = iwl3945_request_scan,
2756 .post_scan = iwl3945_post_scan,
2757};
2758
2759static const struct iwl_ops iwl3945_ops = {
2760 .lib = &iwl3945_lib,
2761 .hcmd = &iwl3945_hcmd,
2762 .utils = &iwl3945_hcmd_utils,
2763 .led = &iwl3945_led_ops,
2764 .legacy = &iwl3945_legacy_ops,
2765 .ieee80211_ops = &iwl3945_hw_ops,
2766};
2767
2768static struct iwl_base_params iwl3945_base_params = {
2769 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2770 .num_of_queues = IWL39_NUM_QUEUES,
2771 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2772 .set_l0s = false,
2773 .use_bsm = true,
2774 .use_isr_legacy = true,
2775 .led_compensation = 64,
2776 .broken_powersave = true,
2777 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2778 .wd_timeout = IWL_DEF_WD_TIMEOUT,
2779 .max_event_log_size = 512,
2780 .tx_power_by_driver = true,
2781};
2782
2783static struct iwl_cfg iwl3945_bg_cfg = {
2784 .name = "3945BG",
2785 .fw_name_pre = IWL3945_FW_PRE,
2786 .ucode_api_max = IWL3945_UCODE_API_MAX,
2787 .ucode_api_min = IWL3945_UCODE_API_MIN,
2788 .sku = IWL_SKU_G,
2789 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2790 .ops = &iwl3945_ops,
2791 .mod_params = &iwl3945_mod_params,
2792 .base_params = &iwl3945_base_params,
2793 .led_mode = IWL_LED_BLINK,
2794};
2795
2796static struct iwl_cfg iwl3945_abg_cfg = {
2797 .name = "3945ABG",
2798 .fw_name_pre = IWL3945_FW_PRE,
2799 .ucode_api_max = IWL3945_UCODE_API_MAX,
2800 .ucode_api_min = IWL3945_UCODE_API_MIN,
2801 .sku = IWL_SKU_A|IWL_SKU_G,
2802 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2803 .ops = &iwl3945_ops,
2804 .mod_params = &iwl3945_mod_params,
2805 .base_params = &iwl3945_base_params,
2806 .led_mode = IWL_LED_BLINK,
2807};
2808
2809DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
2810 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2811 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2812 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2813 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2814 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2815 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2816 {0}
2817};
2818
2819MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 01:36:22 -0500