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authorStanislaw Gruszka <sgruszka@redhat.com>2011-08-30 07:06:03 -0400
committerStanislaw Gruszka <sgruszka@redhat.com>2011-11-15 06:54:18 -0500
commitfcb74588dccb06d8e3e13afb36c5401cae470518 (patch)
treeed534e4e62ee849efde390867d93dfda0f46574f /drivers/net/wireless/iwlegacy
parenta1751b22a82e6cd2da6c9e79611cfd6d6aba1d39 (diff)
iwlegacy: merge iwl-4965-lib.c into 4965-mac.c
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Diffstat (limited to 'drivers/net/wireless/iwlegacy')
-rw-r--r--drivers/net/wireless/iwlegacy/4965-mac.c1152
-rw-r--r--drivers/net/wireless/iwlegacy/Makefile2
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-4965-lib.c1194
3 files changed, 1153 insertions, 1195 deletions
diff --git a/drivers/net/wireless/iwlegacy/4965-mac.c b/drivers/net/wireless/iwlegacy/4965-mac.c
index b6f96b4b1f5c..d817d8d3fe18 100644
--- a/drivers/net/wireless/iwlegacy/4965-mac.c
+++ b/drivers/net/wireless/iwlegacy/4965-mac.c
@@ -86,6 +86,1158 @@ MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
86MODULE_LICENSE("GPL"); 86MODULE_LICENSE("GPL");
87MODULE_ALIAS("iwl4965"); 87MODULE_ALIAS("iwl4965");
88 88
89void il4965_check_abort_status(struct il_priv *il,
90 u8 frame_count, u32 status)
91{
92 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
93 IL_ERR("Tx flush command to flush out all frames\n");
94 if (!test_bit(STATUS_EXIT_PENDING, &il->status))
95 queue_work(il->workqueue, &il->tx_flush);
96 }
97}
98
99/*
100 * EEPROM
101 */
102struct il_mod_params il4965_mod_params = {
103 .amsdu_size_8K = 1,
104 .restart_fw = 1,
105 /* the rest are 0 by default */
106};
107
108void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
109{
110 unsigned long flags;
111 int i;
112 spin_lock_irqsave(&rxq->lock, flags);
113 INIT_LIST_HEAD(&rxq->rx_free);
114 INIT_LIST_HEAD(&rxq->rx_used);
115 /* Fill the rx_used queue with _all_ of the Rx buffers */
116 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
117 /* In the reset function, these buffers may have been allocated
118 * to an SKB, so we need to unmap and free potential storage */
119 if (rxq->pool[i].page != NULL) {
120 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
121 PAGE_SIZE << il->hw_params.rx_page_order,
122 PCI_DMA_FROMDEVICE);
123 __il_free_pages(il, rxq->pool[i].page);
124 rxq->pool[i].page = NULL;
125 }
126 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
127 }
128
129 for (i = 0; i < RX_QUEUE_SIZE; i++)
130 rxq->queue[i] = NULL;
131
132 /* Set us so that we have processed and used all buffers, but have
133 * not restocked the Rx queue with fresh buffers */
134 rxq->read = rxq->write = 0;
135 rxq->write_actual = 0;
136 rxq->free_count = 0;
137 spin_unlock_irqrestore(&rxq->lock, flags);
138}
139
140int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
141{
142 u32 rb_size;
143 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
144 u32 rb_timeout = 0;
145
146 if (il->cfg->mod_params->amsdu_size_8K)
147 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
148 else
149 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
150
151 /* Stop Rx DMA */
152 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
153
154 /* Reset driver's Rx queue write idx */
155 il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
156
157 /* Tell device where to find RBD circular buffer in DRAM */
158 il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
159 (u32)(rxq->bd_dma >> 8));
160
161 /* Tell device where in DRAM to update its Rx status */
162 il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG,
163 rxq->rb_stts_dma >> 4);
164
165 /* Enable Rx DMA
166 * Direct rx interrupts to hosts
167 * Rx buffer size 4 or 8k
168 * RB timeout 0x10
169 * 256 RBDs
170 */
171 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG,
172 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
173 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
174 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
175 rb_size|
176 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
177 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
178
179 /* Set interrupt coalescing timer to default (2048 usecs) */
180 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
181
182 return 0;
183}
184
185static void il4965_set_pwr_vmain(struct il_priv *il)
186{
187/*
188 * (for documentation purposes)
189 * to set power to V_AUX, do:
190
191 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
192 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
195 */
196
197 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
198 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
199 ~APMG_PS_CTRL_MSK_PWR_SRC);
200}
201
202int il4965_hw_nic_init(struct il_priv *il)
203{
204 unsigned long flags;
205 struct il_rx_queue *rxq = &il->rxq;
206 int ret;
207
208 /* nic_init */
209 spin_lock_irqsave(&il->lock, flags);
210 il->cfg->ops->lib->apm_ops.init(il);
211
212 /* Set interrupt coalescing calibration timer to default (512 usecs) */
213 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
214
215 spin_unlock_irqrestore(&il->lock, flags);
216
217 il4965_set_pwr_vmain(il);
218
219 il->cfg->ops->lib->apm_ops.config(il);
220
221 /* Allocate the RX queue, or reset if it is already allocated */
222 if (!rxq->bd) {
223 ret = il_rx_queue_alloc(il);
224 if (ret) {
225 IL_ERR("Unable to initialize Rx queue\n");
226 return -ENOMEM;
227 }
228 } else
229 il4965_rx_queue_reset(il, rxq);
230
231 il4965_rx_replenish(il);
232
233 il4965_rx_init(il, rxq);
234
235 spin_lock_irqsave(&il->lock, flags);
236
237 rxq->need_update = 1;
238 il_rx_queue_update_write_ptr(il, rxq);
239
240 spin_unlock_irqrestore(&il->lock, flags);
241
242 /* Allocate or reset and init all Tx and Command queues */
243 if (!il->txq) {
244 ret = il4965_txq_ctx_alloc(il);
245 if (ret)
246 return ret;
247 } else
248 il4965_txq_ctx_reset(il);
249
250 set_bit(STATUS_INIT, &il->status);
251
252 return 0;
253}
254
255/**
256 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
257 */
258static inline __le32 il4965_dma_addr2rbd_ptr(struct il_priv *il,
259 dma_addr_t dma_addr)
260{
261 return cpu_to_le32((u32)(dma_addr >> 8));
262}
263
264/**
265 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
266 *
267 * If there are slots in the RX queue that need to be restocked,
268 * and we have free pre-allocated buffers, fill the ranks as much
269 * as we can, pulling from rx_free.
270 *
271 * This moves the 'write' idx forward to catch up with 'processed', and
272 * also updates the memory address in the firmware to reference the new
273 * target buffer.
274 */
275void il4965_rx_queue_restock(struct il_priv *il)
276{
277 struct il_rx_queue *rxq = &il->rxq;
278 struct list_head *element;
279 struct il_rx_buf *rxb;
280 unsigned long flags;
281
282 spin_lock_irqsave(&rxq->lock, flags);
283 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
284 /* The overwritten rxb must be a used one */
285 rxb = rxq->queue[rxq->write];
286 BUG_ON(rxb && rxb->page);
287
288 /* Get next free Rx buffer, remove from free list */
289 element = rxq->rx_free.next;
290 rxb = list_entry(element, struct il_rx_buf, list);
291 list_del(element);
292
293 /* Point to Rx buffer via next RBD in circular buffer */
294 rxq->bd[rxq->write] = il4965_dma_addr2rbd_ptr(il,
295 rxb->page_dma);
296 rxq->queue[rxq->write] = rxb;
297 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
298 rxq->free_count--;
299 }
300 spin_unlock_irqrestore(&rxq->lock, flags);
301 /* If the pre-allocated buffer pool is dropping low, schedule to
302 * refill it */
303 if (rxq->free_count <= RX_LOW_WATERMARK)
304 queue_work(il->workqueue, &il->rx_replenish);
305
306
307 /* If we've added more space for the firmware to place data, tell it.
308 * Increment device's write pointer in multiples of 8. */
309 if (rxq->write_actual != (rxq->write & ~0x7)) {
310 spin_lock_irqsave(&rxq->lock, flags);
311 rxq->need_update = 1;
312 spin_unlock_irqrestore(&rxq->lock, flags);
313 il_rx_queue_update_write_ptr(il, rxq);
314 }
315}
316
317/**
318 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
319 *
320 * When moving to rx_free an SKB is allocated for the slot.
321 *
322 * Also restock the Rx queue via il_rx_queue_restock.
323 * This is called as a scheduled work item (except for during initialization)
324 */
325static void il4965_rx_allocate(struct il_priv *il, gfp_t priority)
326{
327 struct il_rx_queue *rxq = &il->rxq;
328 struct list_head *element;
329 struct il_rx_buf *rxb;
330 struct page *page;
331 unsigned long flags;
332 gfp_t gfp_mask = priority;
333
334 while (1) {
335 spin_lock_irqsave(&rxq->lock, flags);
336 if (list_empty(&rxq->rx_used)) {
337 spin_unlock_irqrestore(&rxq->lock, flags);
338 return;
339 }
340 spin_unlock_irqrestore(&rxq->lock, flags);
341
342 if (rxq->free_count > RX_LOW_WATERMARK)
343 gfp_mask |= __GFP_NOWARN;
344
345 if (il->hw_params.rx_page_order > 0)
346 gfp_mask |= __GFP_COMP;
347
348 /* Alloc a new receive buffer */
349 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
350 if (!page) {
351 if (net_ratelimit())
352 D_INFO("alloc_pages failed, "
353 "order: %d\n",
354 il->hw_params.rx_page_order);
355
356 if (rxq->free_count <= RX_LOW_WATERMARK &&
357 net_ratelimit())
358 IL_ERR(
359 "Failed to alloc_pages with %s. "
360 "Only %u free buffers remaining.\n",
361 priority == GFP_ATOMIC ?
362 "GFP_ATOMIC" : "GFP_KERNEL",
363 rxq->free_count);
364 /* We don't reschedule replenish work here -- we will
365 * call the restock method and if it still needs
366 * more buffers it will schedule replenish */
367 return;
368 }
369
370 spin_lock_irqsave(&rxq->lock, flags);
371
372 if (list_empty(&rxq->rx_used)) {
373 spin_unlock_irqrestore(&rxq->lock, flags);
374 __free_pages(page, il->hw_params.rx_page_order);
375 return;
376 }
377 element = rxq->rx_used.next;
378 rxb = list_entry(element, struct il_rx_buf, list);
379 list_del(element);
380
381 spin_unlock_irqrestore(&rxq->lock, flags);
382
383 BUG_ON(rxb->page);
384 rxb->page = page;
385 /* Get physical address of the RB */
386 rxb->page_dma = pci_map_page(il->pci_dev, page, 0,
387 PAGE_SIZE << il->hw_params.rx_page_order,
388 PCI_DMA_FROMDEVICE);
389 /* dma address must be no more than 36 bits */
390 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
391 /* and also 256 byte aligned! */
392 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
393
394 spin_lock_irqsave(&rxq->lock, flags);
395
396 list_add_tail(&rxb->list, &rxq->rx_free);
397 rxq->free_count++;
398 il->alloc_rxb_page++;
399
400 spin_unlock_irqrestore(&rxq->lock, flags);
401 }
402}
403
404void il4965_rx_replenish(struct il_priv *il)
405{
406 unsigned long flags;
407
408 il4965_rx_allocate(il, GFP_KERNEL);
409
410 spin_lock_irqsave(&il->lock, flags);
411 il4965_rx_queue_restock(il);
412 spin_unlock_irqrestore(&il->lock, flags);
413}
414
415void il4965_rx_replenish_now(struct il_priv *il)
416{
417 il4965_rx_allocate(il, GFP_ATOMIC);
418
419 il4965_rx_queue_restock(il);
420}
421
422/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
423 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
424 * This free routine walks the list of POOL entries and if SKB is set to
425 * non NULL it is unmapped and freed
426 */
427void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
428{
429 int i;
430 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
431 if (rxq->pool[i].page != NULL) {
432 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
433 PAGE_SIZE << il->hw_params.rx_page_order,
434 PCI_DMA_FROMDEVICE);
435 __il_free_pages(il, rxq->pool[i].page);
436 rxq->pool[i].page = NULL;
437 }
438 }
439
440 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
441 rxq->bd_dma);
442 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
443 rxq->rb_stts, rxq->rb_stts_dma);
444 rxq->bd = NULL;
445 rxq->rb_stts = NULL;
446}
447
448int il4965_rxq_stop(struct il_priv *il)
449{
450
451 /* stop Rx DMA */
452 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
453 il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG,
454 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
455
456 return 0;
457}
458
459int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
460{
461 int idx = 0;
462 int band_offset = 0;
463
464 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
465 if (rate_n_flags & RATE_MCS_HT_MSK) {
466 idx = (rate_n_flags & 0xff);
467 return idx;
468 /* Legacy rate format, search for match in table */
469 } else {
470 if (band == IEEE80211_BAND_5GHZ)
471 band_offset = IL_FIRST_OFDM_RATE;
472 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
473 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
474 return idx - band_offset;
475 }
476
477 return -1;
478}
479
480static int il4965_calc_rssi(struct il_priv *il,
481 struct il_rx_phy_res *rx_resp)
482{
483 /* data from PHY/DSP regarding signal strength, etc.,
484 * contents are always there, not configurable by host. */
485 struct il4965_rx_non_cfg_phy *ncphy =
486 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
487 u32 agc = (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK)
488 >> IL49_AGC_DB_POS;
489
490 u32 valid_antennae =
491 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
492 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
493 u8 max_rssi = 0;
494 u32 i;
495
496 /* Find max rssi among 3 possible receivers.
497 * These values are measured by the digital signal processor (DSP).
498 * They should stay fairly constant even as the signal strength varies,
499 * if the radio's automatic gain control (AGC) is working right.
500 * AGC value (see below) will provide the "interesting" info. */
501 for (i = 0; i < 3; i++)
502 if (valid_antennae & (1 << i))
503 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
504
505 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
506 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
507 max_rssi, agc);
508
509 /* dBm = max_rssi dB - agc dB - constant.
510 * Higher AGC (higher radio gain) means lower signal. */
511 return max_rssi - agc - IL4965_RSSI_OFFSET;
512}
513
514
515static u32 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
516{
517 u32 decrypt_out = 0;
518
519 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
520 RX_RES_STATUS_STATION_FOUND)
521 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
522 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
523
524 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
525
526 /* packet was not encrypted */
527 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
528 RX_RES_STATUS_SEC_TYPE_NONE)
529 return decrypt_out;
530
531 /* packet was encrypted with unknown alg */
532 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
533 RX_RES_STATUS_SEC_TYPE_ERR)
534 return decrypt_out;
535
536 /* decryption was not done in HW */
537 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
538 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
539 return decrypt_out;
540
541 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
542
543 case RX_RES_STATUS_SEC_TYPE_CCMP:
544 /* alg is CCM: check MIC only */
545 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
546 /* Bad MIC */
547 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
548 else
549 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
550
551 break;
552
553 case RX_RES_STATUS_SEC_TYPE_TKIP:
554 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
555 /* Bad TTAK */
556 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
557 break;
558 }
559 /* fall through if TTAK OK */
560 default:
561 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
562 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
563 else
564 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
565 break;
566 }
567
568 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
569 decrypt_in, decrypt_out);
570
571 return decrypt_out;
572}
573
574static void il4965_pass_packet_to_mac80211(struct il_priv *il,
575 struct ieee80211_hdr *hdr,
576 u16 len,
577 u32 ampdu_status,
578 struct il_rx_buf *rxb,
579 struct ieee80211_rx_status *stats)
580{
581 struct sk_buff *skb;
582 __le16 fc = hdr->frame_control;
583
584 /* We only process data packets if the interface is open */
585 if (unlikely(!il->is_open)) {
586 D_DROP(
587 "Dropping packet while interface is not open.\n");
588 return;
589 }
590
591 /* In case of HW accelerated crypto and bad decryption, drop */
592 if (!il->cfg->mod_params->sw_crypto &&
593 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
594 return;
595
596 skb = dev_alloc_skb(128);
597 if (!skb) {
598 IL_ERR("dev_alloc_skb failed\n");
599 return;
600 }
601
602 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
603
604 il_update_stats(il, false, fc, len);
605 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
606
607 ieee80211_rx(il->hw, skb);
608 il->alloc_rxb_page--;
609 rxb->page = NULL;
610}
611
612/* Called for REPLY_RX (legacy ABG frames), or
613 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
614void il4965_rx_reply_rx(struct il_priv *il,
615 struct il_rx_buf *rxb)
616{
617 struct ieee80211_hdr *header;
618 struct ieee80211_rx_status rx_status;
619 struct il_rx_pkt *pkt = rxb_addr(rxb);
620 struct il_rx_phy_res *phy_res;
621 __le32 rx_pkt_status;
622 struct il_rx_mpdu_res_start *amsdu;
623 u32 len;
624 u32 ampdu_status;
625 u32 rate_n_flags;
626
627 /**
628 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
629 * REPLY_RX: physical layer info is in this buffer
630 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
631 * command and cached in il->last_phy_res
632 *
633 * Here we set up local variables depending on which command is
634 * received.
635 */
636 if (pkt->hdr.cmd == REPLY_RX) {
637 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
638 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
639 + phy_res->cfg_phy_cnt);
640
641 len = le16_to_cpu(phy_res->byte_count);
642 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
643 phy_res->cfg_phy_cnt + len);
644 ampdu_status = le32_to_cpu(rx_pkt_status);
645 } else {
646 if (!il->_4965.last_phy_res_valid) {
647 IL_ERR("MPDU frame without cached PHY data\n");
648 return;
649 }
650 phy_res = &il->_4965.last_phy_res;
651 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
652 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
653 len = le16_to_cpu(amsdu->byte_count);
654 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
655 ampdu_status = il4965_translate_rx_status(il,
656 le32_to_cpu(rx_pkt_status));
657 }
658
659 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
660 D_DROP("dsp size out of range [0,20]: %d/n",
661 phy_res->cfg_phy_cnt);
662 return;
663 }
664
665 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
666 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
667 D_RX("Bad CRC or FIFO: 0x%08X.\n",
668 le32_to_cpu(rx_pkt_status));
669 return;
670 }
671
672 /* This will be used in several places later */
673 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
674
675 /* rx_status carries information about the packet to mac80211 */
676 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
677 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
678 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
679 rx_status.freq =
680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
681 rx_status.band);
682 rx_status.rate_idx =
683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
684 rx_status.flag = 0;
685
686 /* TSF isn't reliable. In order to allow smooth user experience,
687 * this W/A doesn't propagate it to the mac80211 */
688 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU;*/
689
690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
691
692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
693 rx_status.signal = il4965_calc_rssi(il, phy_res);
694
695 il_dbg_log_rx_data_frame(il, len, header);
696 D_STATS("Rssi %d, TSF %llu\n",
697 rx_status.signal, (unsigned long long)rx_status.mactime);
698
699 /*
700 * "antenna number"
701 *
702 * It seems that the antenna field in the phy flags value
703 * is actually a bit field. This is undefined by radiotap,
704 * it wants an actual antenna number but I always get "7"
705 * for most legacy frames I receive indicating that the
706 * same frame was received on all three RX chains.
707 *
708 * I think this field should be removed in favor of a
709 * new 802.11n radiotap field "RX chains" that is defined
710 * as a bitmask.
711 */
712 rx_status.antenna =
713 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
714 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
715
716 /* set the preamble flag if appropriate */
717 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
718 rx_status.flag |= RX_FLAG_SHORTPRE;
719
720 /* Set up the HT phy flags */
721 if (rate_n_flags & RATE_MCS_HT_MSK)
722 rx_status.flag |= RX_FLAG_HT;
723 if (rate_n_flags & RATE_MCS_HT40_MSK)
724 rx_status.flag |= RX_FLAG_40MHZ;
725 if (rate_n_flags & RATE_MCS_SGI_MSK)
726 rx_status.flag |= RX_FLAG_SHORT_GI;
727
728 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status,
729 rxb, &rx_status);
730}
731
732/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
733 * This will be used later in il_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
734void il4965_rx_reply_rx_phy(struct il_priv *il,
735 struct il_rx_buf *rxb)
736{
737 struct il_rx_pkt *pkt = rxb_addr(rxb);
738 il->_4965.last_phy_res_valid = true;
739 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
740 sizeof(struct il_rx_phy_res));
741}
742
743static int il4965_get_channels_for_scan(struct il_priv *il,
744 struct ieee80211_vif *vif,
745 enum ieee80211_band band,
746 u8 is_active, u8 n_probes,
747 struct il_scan_channel *scan_ch)
748{
749 struct ieee80211_channel *chan;
750 const struct ieee80211_supported_band *sband;
751 const struct il_channel_info *ch_info;
752 u16 passive_dwell = 0;
753 u16 active_dwell = 0;
754 int added, i;
755 u16 channel;
756
757 sband = il_get_hw_mode(il, band);
758 if (!sband)
759 return 0;
760
761 active_dwell = il_get_active_dwell_time(il, band, n_probes);
762 passive_dwell = il_get_passive_dwell_time(il, band, vif);
763
764 if (passive_dwell <= active_dwell)
765 passive_dwell = active_dwell + 1;
766
767 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
768 chan = il->scan_request->channels[i];
769
770 if (chan->band != band)
771 continue;
772
773 channel = chan->hw_value;
774 scan_ch->channel = cpu_to_le16(channel);
775
776 ch_info = il_get_channel_info(il, band, channel);
777 if (!il_is_channel_valid(ch_info)) {
778 D_SCAN(
779 "Channel %d is INVALID for this band.\n",
780 channel);
781 continue;
782 }
783
784 if (!is_active || il_is_channel_passive(ch_info) ||
785 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
786 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
787 else
788 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
789
790 if (n_probes)
791 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
792
793 scan_ch->active_dwell = cpu_to_le16(active_dwell);
794 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
795
796 /* Set txpower levels to defaults */
797 scan_ch->dsp_atten = 110;
798
799 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
800 * power level:
801 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
802 */
803 if (band == IEEE80211_BAND_5GHZ)
804 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
805 else
806 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
807
808 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n",
809 channel, le32_to_cpu(scan_ch->type),
810 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
811 "ACTIVE" : "PASSIVE",
812 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
813 active_dwell : passive_dwell);
814
815 scan_ch++;
816 added++;
817 }
818
819 D_SCAN("total channels to scan %d\n", added);
820 return added;
821}
822
823int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
824{
825 struct il_host_cmd cmd = {
826 .id = REPLY_SCAN_CMD,
827 .len = sizeof(struct il_scan_cmd),
828 .flags = CMD_SIZE_HUGE,
829 };
830 struct il_scan_cmd *scan;
831 struct il_rxon_context *ctx = &il->ctx;
832 u32 rate_flags = 0;
833 u16 cmd_len;
834 u16 rx_chain = 0;
835 enum ieee80211_band band;
836 u8 n_probes = 0;
837 u8 rx_ant = il->hw_params.valid_rx_ant;
838 u8 rate;
839 bool is_active = false;
840 int chan_mod;
841 u8 active_chains;
842 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
843 int ret;
844
845 lockdep_assert_held(&il->mutex);
846
847 if (vif)
848 ctx = il_rxon_ctx_from_vif(vif);
849
850 if (!il->scan_cmd) {
851 il->scan_cmd = kmalloc(sizeof(struct il_scan_cmd) +
852 IL_MAX_SCAN_SIZE, GFP_KERNEL);
853 if (!il->scan_cmd) {
854 D_SCAN(
855 "fail to allocate memory for scan\n");
856 return -ENOMEM;
857 }
858 }
859 scan = il->scan_cmd;
860 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
861
862 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
863 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
864
865 if (il_is_any_associated(il)) {
866 u16 interval;
867 u32 extra;
868 u32 suspend_time = 100;
869 u32 scan_suspend_time = 100;
870
871 D_INFO("Scanning while associated...\n");
872 interval = vif->bss_conf.beacon_int;
873
874 scan->suspend_time = 0;
875 scan->max_out_time = cpu_to_le32(200 * 1024);
876 if (!interval)
877 interval = suspend_time;
878
879 extra = (suspend_time / interval) << 22;
880 scan_suspend_time = (extra |
881 ((suspend_time % interval) * 1024));
882 scan->suspend_time = cpu_to_le32(scan_suspend_time);
883 D_SCAN("suspend_time 0x%X beacon interval %d\n",
884 scan_suspend_time, interval);
885 }
886
887 if (il->scan_request->n_ssids) {
888 int i, p = 0;
889 D_SCAN("Kicking off active scan\n");
890 for (i = 0; i < il->scan_request->n_ssids; i++) {
891 /* always does wildcard anyway */
892 if (!il->scan_request->ssids[i].ssid_len)
893 continue;
894 scan->direct_scan[p].id = WLAN_EID_SSID;
895 scan->direct_scan[p].len =
896 il->scan_request->ssids[i].ssid_len;
897 memcpy(scan->direct_scan[p].ssid,
898 il->scan_request->ssids[i].ssid,
899 il->scan_request->ssids[i].ssid_len);
900 n_probes++;
901 p++;
902 }
903 is_active = true;
904 } else
905 D_SCAN("Start passive scan.\n");
906
907 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
908 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
909 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
910
911 switch (il->scan_band) {
912 case IEEE80211_BAND_2GHZ:
913 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
914 chan_mod = le32_to_cpu(
915 il->ctx.active.flags &
916 RXON_FLG_CHANNEL_MODE_MSK)
917 >> RXON_FLG_CHANNEL_MODE_POS;
918 if (chan_mod == CHANNEL_MODE_PURE_40) {
919 rate = RATE_6M_PLCP;
920 } else {
921 rate = RATE_1M_PLCP;
922 rate_flags = RATE_MCS_CCK_MSK;
923 }
924 break;
925 case IEEE80211_BAND_5GHZ:
926 rate = RATE_6M_PLCP;
927 break;
928 default:
929 IL_WARN("Invalid scan band\n");
930 return -EIO;
931 }
932
933 /*
934 * If active scanning is requested but a certain channel is
935 * marked passive, we can do active scanning if we detect
936 * transmissions.
937 *
938 * There is an issue with some firmware versions that triggers
939 * a sysassert on a "good CRC threshold" of zero (== disabled),
940 * on a radar channel even though this means that we should NOT
941 * send probes.
942 *
943 * The "good CRC threshold" is the number of frames that we
944 * need to receive during our dwell time on a channel before
945 * sending out probes -- setting this to a huge value will
946 * mean we never reach it, but at the same time work around
947 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
948 * here instead of IL_GOOD_CRC_TH_DISABLED.
949 */
950 scan->good_CRC_th = is_active ? IL_GOOD_CRC_TH_DEFAULT :
951 IL_GOOD_CRC_TH_NEVER;
952
953 band = il->scan_band;
954
955 if (il->cfg->scan_rx_antennas[band])
956 rx_ant = il->cfg->scan_rx_antennas[band];
957
958 il->scan_tx_ant[band] = il4965_toggle_tx_ant(il,
959 il->scan_tx_ant[band],
960 scan_tx_antennas);
961 rate_flags |= il4965_ant_idx_to_flags(il->scan_tx_ant[band]);
962 scan->tx_cmd.rate_n_flags = il4965_hw_set_rate_n_flags(rate, rate_flags);
963
964 /* In power save mode use one chain, otherwise use all chains */
965 if (test_bit(STATUS_POWER_PMI, &il->status)) {
966 /* rx_ant has been set to all valid chains previously */
967 active_chains = rx_ant &
968 ((u8)(il->chain_noise_data.active_chains));
969 if (!active_chains)
970 active_chains = rx_ant;
971
972 D_SCAN("chain_noise_data.active_chains: %u\n",
973 il->chain_noise_data.active_chains);
974
975 rx_ant = il4965_first_antenna(active_chains);
976 }
977
978 /* MIMO is not used here, but value is required */
979 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
980 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
981 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
982 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
983 scan->rx_chain = cpu_to_le16(rx_chain);
984
985 cmd_len = il_fill_probe_req(il,
986 (struct ieee80211_mgmt *)scan->data,
987 vif->addr,
988 il->scan_request->ie,
989 il->scan_request->ie_len,
990 IL_MAX_SCAN_SIZE - sizeof(*scan));
991 scan->tx_cmd.len = cpu_to_le16(cmd_len);
992
993 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
994 RXON_FILTER_BCON_AWARE_MSK);
995
996 scan->channel_count = il4965_get_channels_for_scan(il, vif, band,
997 is_active, n_probes,
998 (void *)&scan->data[cmd_len]);
999 if (scan->channel_count == 0) {
1000 D_SCAN("channel count %d\n", scan->channel_count);
1001 return -EIO;
1002 }
1003
1004 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1005 scan->channel_count * sizeof(struct il_scan_channel);
1006 cmd.data = scan;
1007 scan->len = cpu_to_le16(cmd.len);
1008
1009 set_bit(STATUS_SCAN_HW, &il->status);
1010
1011 ret = il_send_cmd_sync(il, &cmd);
1012 if (ret)
1013 clear_bit(STATUS_SCAN_HW, &il->status);
1014
1015 return ret;
1016}
1017
1018int il4965_manage_ibss_station(struct il_priv *il,
1019 struct ieee80211_vif *vif, bool add)
1020{
1021 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
1022
1023 if (add)
1024 return il4965_add_bssid_station(il, vif_priv->ctx,
1025 vif->bss_conf.bssid,
1026 &vif_priv->ibss_bssid_sta_id);
1027 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
1028 vif->bss_conf.bssid);
1029}
1030
1031void il4965_free_tfds_in_queue(struct il_priv *il,
1032 int sta_id, int tid, int freed)
1033{
1034 lockdep_assert_held(&il->sta_lock);
1035
1036 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1037 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1038 else {
1039 D_TX("free more than tfds_in_queue (%u:%d)\n",
1040 il->stations[sta_id].tid[tid].tfds_in_queue,
1041 freed);
1042 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
1043 }
1044}
1045
1046#define IL_TX_QUEUE_MSK 0xfffff
1047
1048static bool il4965_is_single_rx_stream(struct il_priv *il)
1049{
1050 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1051 il->current_ht_config.single_chain_sufficient;
1052}
1053
1054#define IL_NUM_RX_CHAINS_MULTIPLE 3
1055#define IL_NUM_RX_CHAINS_SINGLE 2
1056#define IL_NUM_IDLE_CHAINS_DUAL 2
1057#define IL_NUM_IDLE_CHAINS_SINGLE 1
1058
1059/*
1060 * Determine how many receiver/antenna chains to use.
1061 *
1062 * More provides better reception via diversity. Fewer saves power
1063 * at the expense of throughput, but only when not in powersave to
1064 * start with.
1065 *
1066 * MIMO (dual stream) requires at least 2, but works better with 3.
1067 * This does not determine *which* chains to use, just how many.
1068 */
1069static int il4965_get_active_rx_chain_count(struct il_priv *il)
1070{
1071 /* # of Rx chains to use when expecting MIMO. */
1072 if (il4965_is_single_rx_stream(il))
1073 return IL_NUM_RX_CHAINS_SINGLE;
1074 else
1075 return IL_NUM_RX_CHAINS_MULTIPLE;
1076}
1077
1078/*
1079 * When we are in power saving mode, unless device support spatial
1080 * multiplexing power save, use the active count for rx chain count.
1081 */
1082static int
1083il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1084{
1085 /* # Rx chains when idling, depending on SMPS mode */
1086 switch (il->current_ht_config.smps) {
1087 case IEEE80211_SMPS_STATIC:
1088 case IEEE80211_SMPS_DYNAMIC:
1089 return IL_NUM_IDLE_CHAINS_SINGLE;
1090 case IEEE80211_SMPS_OFF:
1091 return active_cnt;
1092 default:
1093 WARN(1, "invalid SMPS mode %d",
1094 il->current_ht_config.smps);
1095 return active_cnt;
1096 }
1097}
1098
1099/* up to 4 chains */
1100static u8 il4965_count_chain_bitmap(u32 chain_bitmap)
1101{
1102 u8 res;
1103 res = (chain_bitmap & BIT(0)) >> 0;
1104 res += (chain_bitmap & BIT(1)) >> 1;
1105 res += (chain_bitmap & BIT(2)) >> 2;
1106 res += (chain_bitmap & BIT(3)) >> 3;
1107 return res;
1108}
1109
1110/**
1111 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1112 *
1113 * Selects how many and which Rx receivers/antennas/chains to use.
1114 * This should not be used for scan command ... it puts data in wrong place.
1115 */
1116void il4965_set_rxon_chain(struct il_priv *il, struct il_rxon_context *ctx)
1117{
1118 bool is_single = il4965_is_single_rx_stream(il);
1119 bool is_cam = !test_bit(STATUS_POWER_PMI, &il->status);
1120 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1121 u32 active_chains;
1122 u16 rx_chain;
1123
1124 /* Tell uCode which antennas are actually connected.
1125 * Before first association, we assume all antennas are connected.
1126 * Just after first association, il4965_chain_noise_calibration()
1127 * checks which antennas actually *are* connected. */
1128 if (il->chain_noise_data.active_chains)
1129 active_chains = il->chain_noise_data.active_chains;
1130 else
1131 active_chains = il->hw_params.valid_rx_ant;
1132
1133 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1134
1135 /* How many receivers should we use? */
1136 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1137 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1138
1139
1140 /* correct rx chain count according hw settings
1141 * and chain noise calibration
1142 */
1143 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1144 if (valid_rx_cnt < active_rx_cnt)
1145 active_rx_cnt = valid_rx_cnt;
1146
1147 if (valid_rx_cnt < idle_rx_cnt)
1148 idle_rx_cnt = valid_rx_cnt;
1149
1150 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1151 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1152
1153 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
1154
1155 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1156 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1157 else
1158 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1159
1160 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
1161 ctx->staging.rx_chain,
1162 active_rx_cnt, idle_rx_cnt);
1163
1164 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1165 active_rx_cnt < idle_rx_cnt);
1166}
1167
1168u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant, u8 valid)
1169{
1170 int i;
1171 u8 ind = ant;
1172
1173 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
1174 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
1175 if (valid & BIT(ind))
1176 return ind;
1177 }
1178 return ant;
1179}
1180
1181static const char *il4965_get_fh_string(int cmd)
1182{
1183 switch (cmd) {
1184 IL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1185 IL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1186 IL_CMD(FH_RSCSR_CHNL0_WPTR);
1187 IL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1188 IL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1189 IL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1190 IL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1191 IL_CMD(FH_TSSR_TX_STATUS_REG);
1192 IL_CMD(FH_TSSR_TX_ERROR_REG);
1193 default:
1194 return "UNKNOWN";
1195 }
1196}
1197
1198int il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1199{
1200 int i;
1201#ifdef CONFIG_IWLEGACY_DEBUG
1202 int pos = 0;
1203 size_t bufsz = 0;
1204#endif
1205 static const u32 fh_tbl[] = {
1206 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1207 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1208 FH_RSCSR_CHNL0_WPTR,
1209 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1210 FH_MEM_RSSR_SHARED_CTRL_REG,
1211 FH_MEM_RSSR_RX_STATUS_REG,
1212 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1213 FH_TSSR_TX_STATUS_REG,
1214 FH_TSSR_TX_ERROR_REG
1215 };
1216#ifdef CONFIG_IWLEGACY_DEBUG
1217 if (display) {
1218 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1219 *buf = kmalloc(bufsz, GFP_KERNEL);
1220 if (!*buf)
1221 return -ENOMEM;
1222 pos += scnprintf(*buf + pos, bufsz - pos,
1223 "FH register values:\n");
1224 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1225 pos += scnprintf(*buf + pos, bufsz - pos,
1226 " %34s: 0X%08x\n",
1227 il4965_get_fh_string(fh_tbl[i]),
1228 il_rd(il, fh_tbl[i]));
1229 }
1230 return pos;
1231 }
1232#endif
1233 IL_ERR("FH register values:\n");
1234 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1235 IL_ERR(" %34s: 0X%08x\n",
1236 il4965_get_fh_string(fh_tbl[i]),
1237 il_rd(il, fh_tbl[i]));
1238 }
1239 return 0;
1240}
89void il4965_rx_missed_beacon_notif(struct il_priv *il, 1241void il4965_rx_missed_beacon_notif(struct il_priv *il,
90 struct il_rx_buf *rxb) 1242 struct il_rx_buf *rxb)
91 1243
diff --git a/drivers/net/wireless/iwlegacy/Makefile b/drivers/net/wireless/iwlegacy/Makefile
index 884470479223..d0f9f23feea9 100644
--- a/drivers/net/wireless/iwlegacy/Makefile
+++ b/drivers/net/wireless/iwlegacy/Makefile
@@ -9,7 +9,7 @@ iwl-legacy-objs += $(iwl-legacy-m)
9# 4965 9# 4965
10obj-$(CONFIG_IWL4965) += iwl4965.o 10obj-$(CONFIG_IWL4965) += iwl4965.o
11iwl4965-objs := 4965.o 4965-mac.o iwl-4965-rs.o 11iwl4965-objs := 4965.o 4965-mac.o iwl-4965-rs.o
12iwl4965-objs += iwl-4965-lib.o iwl-4965-calib.o 12iwl4965-objs += iwl-4965-calib.o
13iwl4965-$(CONFIG_IWLEGACY_DEBUGFS) += iwl-4965-debugfs.o 13iwl4965-$(CONFIG_IWLEGACY_DEBUGFS) += iwl-4965-debugfs.o
14 14
15# 3945 15# 3945
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-lib.c b/drivers/net/wireless/iwlegacy/iwl-4965-lib.c
deleted file mode 100644
index bbec6bd550d3..000000000000
--- a/drivers/net/wireless/iwlegacy/iwl-4965-lib.c
+++ /dev/null
@@ -1,1194 +0,0 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29#include <linux/etherdevice.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-helpers.h"
39#include "iwl-4965-hw.h"
40#include "iwl-4965.h"
41#include "iwl-sta.h"
42
43void il4965_check_abort_status(struct il_priv *il,
44 u8 frame_count, u32 status)
45{
46 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
47 IL_ERR("Tx flush command to flush out all frames\n");
48 if (!test_bit(STATUS_EXIT_PENDING, &il->status))
49 queue_work(il->workqueue, &il->tx_flush);
50 }
51}
52
53/*
54 * EEPROM
55 */
56struct il_mod_params il4965_mod_params = {
57 .amsdu_size_8K = 1,
58 .restart_fw = 1,
59 /* the rest are 0 by default */
60};
61
62void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq)
63{
64 unsigned long flags;
65 int i;
66 spin_lock_irqsave(&rxq->lock, flags);
67 INIT_LIST_HEAD(&rxq->rx_free);
68 INIT_LIST_HEAD(&rxq->rx_used);
69 /* Fill the rx_used queue with _all_ of the Rx buffers */
70 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
71 /* In the reset function, these buffers may have been allocated
72 * to an SKB, so we need to unmap and free potential storage */
73 if (rxq->pool[i].page != NULL) {
74 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
75 PAGE_SIZE << il->hw_params.rx_page_order,
76 PCI_DMA_FROMDEVICE);
77 __il_free_pages(il, rxq->pool[i].page);
78 rxq->pool[i].page = NULL;
79 }
80 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
81 }
82
83 for (i = 0; i < RX_QUEUE_SIZE; i++)
84 rxq->queue[i] = NULL;
85
86 /* Set us so that we have processed and used all buffers, but have
87 * not restocked the Rx queue with fresh buffers */
88 rxq->read = rxq->write = 0;
89 rxq->write_actual = 0;
90 rxq->free_count = 0;
91 spin_unlock_irqrestore(&rxq->lock, flags);
92}
93
94int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq)
95{
96 u32 rb_size;
97 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
98 u32 rb_timeout = 0;
99
100 if (il->cfg->mod_params->amsdu_size_8K)
101 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
102 else
103 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
104
105 /* Stop Rx DMA */
106 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
107
108 /* Reset driver's Rx queue write idx */
109 il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
110
111 /* Tell device where to find RBD circular buffer in DRAM */
112 il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
113 (u32)(rxq->bd_dma >> 8));
114
115 /* Tell device where in DRAM to update its Rx status */
116 il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG,
117 rxq->rb_stts_dma >> 4);
118
119 /* Enable Rx DMA
120 * Direct rx interrupts to hosts
121 * Rx buffer size 4 or 8k
122 * RB timeout 0x10
123 * 256 RBDs
124 */
125 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG,
126 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
127 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
128 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
129 rb_size|
130 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
131 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
132
133 /* Set interrupt coalescing timer to default (2048 usecs) */
134 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF);
135
136 return 0;
137}
138
139static void il4965_set_pwr_vmain(struct il_priv *il)
140{
141/*
142 * (for documentation purposes)
143 * to set power to V_AUX, do:
144
145 if (pci_pme_capable(il->pci_dev, PCI_D3cold))
146 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
147 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
148 ~APMG_PS_CTRL_MSK_PWR_SRC);
149 */
150
151 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG,
152 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
153 ~APMG_PS_CTRL_MSK_PWR_SRC);
154}
155
156int il4965_hw_nic_init(struct il_priv *il)
157{
158 unsigned long flags;
159 struct il_rx_queue *rxq = &il->rxq;
160 int ret;
161
162 /* nic_init */
163 spin_lock_irqsave(&il->lock, flags);
164 il->cfg->ops->lib->apm_ops.init(il);
165
166 /* Set interrupt coalescing calibration timer to default (512 usecs) */
167 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF);
168
169 spin_unlock_irqrestore(&il->lock, flags);
170
171 il4965_set_pwr_vmain(il);
172
173 il->cfg->ops->lib->apm_ops.config(il);
174
175 /* Allocate the RX queue, or reset if it is already allocated */
176 if (!rxq->bd) {
177 ret = il_rx_queue_alloc(il);
178 if (ret) {
179 IL_ERR("Unable to initialize Rx queue\n");
180 return -ENOMEM;
181 }
182 } else
183 il4965_rx_queue_reset(il, rxq);
184
185 il4965_rx_replenish(il);
186
187 il4965_rx_init(il, rxq);
188
189 spin_lock_irqsave(&il->lock, flags);
190
191 rxq->need_update = 1;
192 il_rx_queue_update_write_ptr(il, rxq);
193
194 spin_unlock_irqrestore(&il->lock, flags);
195
196 /* Allocate or reset and init all Tx and Command queues */
197 if (!il->txq) {
198 ret = il4965_txq_ctx_alloc(il);
199 if (ret)
200 return ret;
201 } else
202 il4965_txq_ctx_reset(il);
203
204 set_bit(STATUS_INIT, &il->status);
205
206 return 0;
207}
208
209/**
210 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
211 */
212static inline __le32 il4965_dma_addr2rbd_ptr(struct il_priv *il,
213 dma_addr_t dma_addr)
214{
215 return cpu_to_le32((u32)(dma_addr >> 8));
216}
217
218/**
219 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool
220 *
221 * If there are slots in the RX queue that need to be restocked,
222 * and we have free pre-allocated buffers, fill the ranks as much
223 * as we can, pulling from rx_free.
224 *
225 * This moves the 'write' idx forward to catch up with 'processed', and
226 * also updates the memory address in the firmware to reference the new
227 * target buffer.
228 */
229void il4965_rx_queue_restock(struct il_priv *il)
230{
231 struct il_rx_queue *rxq = &il->rxq;
232 struct list_head *element;
233 struct il_rx_buf *rxb;
234 unsigned long flags;
235
236 spin_lock_irqsave(&rxq->lock, flags);
237 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) {
238 /* The overwritten rxb must be a used one */
239 rxb = rxq->queue[rxq->write];
240 BUG_ON(rxb && rxb->page);
241
242 /* Get next free Rx buffer, remove from free list */
243 element = rxq->rx_free.next;
244 rxb = list_entry(element, struct il_rx_buf, list);
245 list_del(element);
246
247 /* Point to Rx buffer via next RBD in circular buffer */
248 rxq->bd[rxq->write] = il4965_dma_addr2rbd_ptr(il,
249 rxb->page_dma);
250 rxq->queue[rxq->write] = rxb;
251 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
252 rxq->free_count--;
253 }
254 spin_unlock_irqrestore(&rxq->lock, flags);
255 /* If the pre-allocated buffer pool is dropping low, schedule to
256 * refill it */
257 if (rxq->free_count <= RX_LOW_WATERMARK)
258 queue_work(il->workqueue, &il->rx_replenish);
259
260
261 /* If we've added more space for the firmware to place data, tell it.
262 * Increment device's write pointer in multiples of 8. */
263 if (rxq->write_actual != (rxq->write & ~0x7)) {
264 spin_lock_irqsave(&rxq->lock, flags);
265 rxq->need_update = 1;
266 spin_unlock_irqrestore(&rxq->lock, flags);
267 il_rx_queue_update_write_ptr(il, rxq);
268 }
269}
270
271/**
272 * il4965_rx_replenish - Move all used packet from rx_used to rx_free
273 *
274 * When moving to rx_free an SKB is allocated for the slot.
275 *
276 * Also restock the Rx queue via il_rx_queue_restock.
277 * This is called as a scheduled work item (except for during initialization)
278 */
279static void il4965_rx_allocate(struct il_priv *il, gfp_t priority)
280{
281 struct il_rx_queue *rxq = &il->rxq;
282 struct list_head *element;
283 struct il_rx_buf *rxb;
284 struct page *page;
285 unsigned long flags;
286 gfp_t gfp_mask = priority;
287
288 while (1) {
289 spin_lock_irqsave(&rxq->lock, flags);
290 if (list_empty(&rxq->rx_used)) {
291 spin_unlock_irqrestore(&rxq->lock, flags);
292 return;
293 }
294 spin_unlock_irqrestore(&rxq->lock, flags);
295
296 if (rxq->free_count > RX_LOW_WATERMARK)
297 gfp_mask |= __GFP_NOWARN;
298
299 if (il->hw_params.rx_page_order > 0)
300 gfp_mask |= __GFP_COMP;
301
302 /* Alloc a new receive buffer */
303 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order);
304 if (!page) {
305 if (net_ratelimit())
306 D_INFO("alloc_pages failed, "
307 "order: %d\n",
308 il->hw_params.rx_page_order);
309
310 if (rxq->free_count <= RX_LOW_WATERMARK &&
311 net_ratelimit())
312 IL_ERR(
313 "Failed to alloc_pages with %s. "
314 "Only %u free buffers remaining.\n",
315 priority == GFP_ATOMIC ?
316 "GFP_ATOMIC" : "GFP_KERNEL",
317 rxq->free_count);
318 /* We don't reschedule replenish work here -- we will
319 * call the restock method and if it still needs
320 * more buffers it will schedule replenish */
321 return;
322 }
323
324 spin_lock_irqsave(&rxq->lock, flags);
325
326 if (list_empty(&rxq->rx_used)) {
327 spin_unlock_irqrestore(&rxq->lock, flags);
328 __free_pages(page, il->hw_params.rx_page_order);
329 return;
330 }
331 element = rxq->rx_used.next;
332 rxb = list_entry(element, struct il_rx_buf, list);
333 list_del(element);
334
335 spin_unlock_irqrestore(&rxq->lock, flags);
336
337 BUG_ON(rxb->page);
338 rxb->page = page;
339 /* Get physical address of the RB */
340 rxb->page_dma = pci_map_page(il->pci_dev, page, 0,
341 PAGE_SIZE << il->hw_params.rx_page_order,
342 PCI_DMA_FROMDEVICE);
343 /* dma address must be no more than 36 bits */
344 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
345 /* and also 256 byte aligned! */
346 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
347
348 spin_lock_irqsave(&rxq->lock, flags);
349
350 list_add_tail(&rxb->list, &rxq->rx_free);
351 rxq->free_count++;
352 il->alloc_rxb_page++;
353
354 spin_unlock_irqrestore(&rxq->lock, flags);
355 }
356}
357
358void il4965_rx_replenish(struct il_priv *il)
359{
360 unsigned long flags;
361
362 il4965_rx_allocate(il, GFP_KERNEL);
363
364 spin_lock_irqsave(&il->lock, flags);
365 il4965_rx_queue_restock(il);
366 spin_unlock_irqrestore(&il->lock, flags);
367}
368
369void il4965_rx_replenish_now(struct il_priv *il)
370{
371 il4965_rx_allocate(il, GFP_ATOMIC);
372
373 il4965_rx_queue_restock(il);
374}
375
376/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
377 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
378 * This free routine walks the list of POOL entries and if SKB is set to
379 * non NULL it is unmapped and freed
380 */
381void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq)
382{
383 int i;
384 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
385 if (rxq->pool[i].page != NULL) {
386 pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma,
387 PAGE_SIZE << il->hw_params.rx_page_order,
388 PCI_DMA_FROMDEVICE);
389 __il_free_pages(il, rxq->pool[i].page);
390 rxq->pool[i].page = NULL;
391 }
392 }
393
394 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
395 rxq->bd_dma);
396 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status),
397 rxq->rb_stts, rxq->rb_stts_dma);
398 rxq->bd = NULL;
399 rxq->rb_stts = NULL;
400}
401
402int il4965_rxq_stop(struct il_priv *il)
403{
404
405 /* stop Rx DMA */
406 il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
407 il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG,
408 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
409
410 return 0;
411}
412
413int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
414{
415 int idx = 0;
416 int band_offset = 0;
417
418 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
419 if (rate_n_flags & RATE_MCS_HT_MSK) {
420 idx = (rate_n_flags & 0xff);
421 return idx;
422 /* Legacy rate format, search for match in table */
423 } else {
424 if (band == IEEE80211_BAND_5GHZ)
425 band_offset = IL_FIRST_OFDM_RATE;
426 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++)
427 if (il_rates[idx].plcp == (rate_n_flags & 0xFF))
428 return idx - band_offset;
429 }
430
431 return -1;
432}
433
434static int il4965_calc_rssi(struct il_priv *il,
435 struct il_rx_phy_res *rx_resp)
436{
437 /* data from PHY/DSP regarding signal strength, etc.,
438 * contents are always there, not configurable by host. */
439 struct il4965_rx_non_cfg_phy *ncphy =
440 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
441 u32 agc = (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK)
442 >> IL49_AGC_DB_POS;
443
444 u32 valid_antennae =
445 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK)
446 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
447 u8 max_rssi = 0;
448 u32 i;
449
450 /* Find max rssi among 3 possible receivers.
451 * These values are measured by the digital signal processor (DSP).
452 * They should stay fairly constant even as the signal strength varies,
453 * if the radio's automatic gain control (AGC) is working right.
454 * AGC value (see below) will provide the "interesting" info. */
455 for (i = 0; i < 3; i++)
456 if (valid_antennae & (1 << i))
457 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
458
459 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
460 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
461 max_rssi, agc);
462
463 /* dBm = max_rssi dB - agc dB - constant.
464 * Higher AGC (higher radio gain) means lower signal. */
465 return max_rssi - agc - IL4965_RSSI_OFFSET;
466}
467
468
469static u32 il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in)
470{
471 u32 decrypt_out = 0;
472
473 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
474 RX_RES_STATUS_STATION_FOUND)
475 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
476 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
477
478 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
479
480 /* packet was not encrypted */
481 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
482 RX_RES_STATUS_SEC_TYPE_NONE)
483 return decrypt_out;
484
485 /* packet was encrypted with unknown alg */
486 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
487 RX_RES_STATUS_SEC_TYPE_ERR)
488 return decrypt_out;
489
490 /* decryption was not done in HW */
491 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
492 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
493 return decrypt_out;
494
495 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
496
497 case RX_RES_STATUS_SEC_TYPE_CCMP:
498 /* alg is CCM: check MIC only */
499 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
500 /* Bad MIC */
501 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
502 else
503 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
504
505 break;
506
507 case RX_RES_STATUS_SEC_TYPE_TKIP:
508 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
509 /* Bad TTAK */
510 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
511 break;
512 }
513 /* fall through if TTAK OK */
514 default:
515 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
516 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
517 else
518 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
519 break;
520 }
521
522 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
523 decrypt_in, decrypt_out);
524
525 return decrypt_out;
526}
527
528static void il4965_pass_packet_to_mac80211(struct il_priv *il,
529 struct ieee80211_hdr *hdr,
530 u16 len,
531 u32 ampdu_status,
532 struct il_rx_buf *rxb,
533 struct ieee80211_rx_status *stats)
534{
535 struct sk_buff *skb;
536 __le16 fc = hdr->frame_control;
537
538 /* We only process data packets if the interface is open */
539 if (unlikely(!il->is_open)) {
540 D_DROP(
541 "Dropping packet while interface is not open.\n");
542 return;
543 }
544
545 /* In case of HW accelerated crypto and bad decryption, drop */
546 if (!il->cfg->mod_params->sw_crypto &&
547 il_set_decrypted_flag(il, hdr, ampdu_status, stats))
548 return;
549
550 skb = dev_alloc_skb(128);
551 if (!skb) {
552 IL_ERR("dev_alloc_skb failed\n");
553 return;
554 }
555
556 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
557
558 il_update_stats(il, false, fc, len);
559 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
560
561 ieee80211_rx(il->hw, skb);
562 il->alloc_rxb_page--;
563 rxb->page = NULL;
564}
565
566/* Called for REPLY_RX (legacy ABG frames), or
567 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
568void il4965_rx_reply_rx(struct il_priv *il,
569 struct il_rx_buf *rxb)
570{
571 struct ieee80211_hdr *header;
572 struct ieee80211_rx_status rx_status;
573 struct il_rx_pkt *pkt = rxb_addr(rxb);
574 struct il_rx_phy_res *phy_res;
575 __le32 rx_pkt_status;
576 struct il_rx_mpdu_res_start *amsdu;
577 u32 len;
578 u32 ampdu_status;
579 u32 rate_n_flags;
580
581 /**
582 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
583 * REPLY_RX: physical layer info is in this buffer
584 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
585 * command and cached in il->last_phy_res
586 *
587 * Here we set up local variables depending on which command is
588 * received.
589 */
590 if (pkt->hdr.cmd == REPLY_RX) {
591 phy_res = (struct il_rx_phy_res *)pkt->u.raw;
592 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
593 + phy_res->cfg_phy_cnt);
594
595 len = le16_to_cpu(phy_res->byte_count);
596 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
597 phy_res->cfg_phy_cnt + len);
598 ampdu_status = le32_to_cpu(rx_pkt_status);
599 } else {
600 if (!il->_4965.last_phy_res_valid) {
601 IL_ERR("MPDU frame without cached PHY data\n");
602 return;
603 }
604 phy_res = &il->_4965.last_phy_res;
605 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw;
606 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
607 len = le16_to_cpu(amsdu->byte_count);
608 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
609 ampdu_status = il4965_translate_rx_status(il,
610 le32_to_cpu(rx_pkt_status));
611 }
612
613 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
614 D_DROP("dsp size out of range [0,20]: %d/n",
615 phy_res->cfg_phy_cnt);
616 return;
617 }
618
619 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
620 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
621 D_RX("Bad CRC or FIFO: 0x%08X.\n",
622 le32_to_cpu(rx_pkt_status));
623 return;
624 }
625
626 /* This will be used in several places later */
627 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
628
629 /* rx_status carries information about the packet to mac80211 */
630 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
631 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
632 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
633 rx_status.freq =
634 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel),
635 rx_status.band);
636 rx_status.rate_idx =
637 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
638 rx_status.flag = 0;
639
640 /* TSF isn't reliable. In order to allow smooth user experience,
641 * this W/A doesn't propagate it to the mac80211 */
642 /*rx_status.flag |= RX_FLAG_MACTIME_MPDU;*/
643
644 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
645
646 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
647 rx_status.signal = il4965_calc_rssi(il, phy_res);
648
649 il_dbg_log_rx_data_frame(il, len, header);
650 D_STATS("Rssi %d, TSF %llu\n",
651 rx_status.signal, (unsigned long long)rx_status.mactime);
652
653 /*
654 * "antenna number"
655 *
656 * It seems that the antenna field in the phy flags value
657 * is actually a bit field. This is undefined by radiotap,
658 * it wants an actual antenna number but I always get "7"
659 * for most legacy frames I receive indicating that the
660 * same frame was received on all three RX chains.
661 *
662 * I think this field should be removed in favor of a
663 * new 802.11n radiotap field "RX chains" that is defined
664 * as a bitmask.
665 */
666 rx_status.antenna =
667 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
668 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
669
670 /* set the preamble flag if appropriate */
671 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
672 rx_status.flag |= RX_FLAG_SHORTPRE;
673
674 /* Set up the HT phy flags */
675 if (rate_n_flags & RATE_MCS_HT_MSK)
676 rx_status.flag |= RX_FLAG_HT;
677 if (rate_n_flags & RATE_MCS_HT40_MSK)
678 rx_status.flag |= RX_FLAG_40MHZ;
679 if (rate_n_flags & RATE_MCS_SGI_MSK)
680 rx_status.flag |= RX_FLAG_SHORT_GI;
681
682 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status,
683 rxb, &rx_status);
684}
685
686/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
687 * This will be used later in il_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
688void il4965_rx_reply_rx_phy(struct il_priv *il,
689 struct il_rx_buf *rxb)
690{
691 struct il_rx_pkt *pkt = rxb_addr(rxb);
692 il->_4965.last_phy_res_valid = true;
693 memcpy(&il->_4965.last_phy_res, pkt->u.raw,
694 sizeof(struct il_rx_phy_res));
695}
696
697static int il4965_get_channels_for_scan(struct il_priv *il,
698 struct ieee80211_vif *vif,
699 enum ieee80211_band band,
700 u8 is_active, u8 n_probes,
701 struct il_scan_channel *scan_ch)
702{
703 struct ieee80211_channel *chan;
704 const struct ieee80211_supported_band *sband;
705 const struct il_channel_info *ch_info;
706 u16 passive_dwell = 0;
707 u16 active_dwell = 0;
708 int added, i;
709 u16 channel;
710
711 sband = il_get_hw_mode(il, band);
712 if (!sband)
713 return 0;
714
715 active_dwell = il_get_active_dwell_time(il, band, n_probes);
716 passive_dwell = il_get_passive_dwell_time(il, band, vif);
717
718 if (passive_dwell <= active_dwell)
719 passive_dwell = active_dwell + 1;
720
721 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) {
722 chan = il->scan_request->channels[i];
723
724 if (chan->band != band)
725 continue;
726
727 channel = chan->hw_value;
728 scan_ch->channel = cpu_to_le16(channel);
729
730 ch_info = il_get_channel_info(il, band, channel);
731 if (!il_is_channel_valid(ch_info)) {
732 D_SCAN(
733 "Channel %d is INVALID for this band.\n",
734 channel);
735 continue;
736 }
737
738 if (!is_active || il_is_channel_passive(ch_info) ||
739 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
740 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
741 else
742 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
743
744 if (n_probes)
745 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes);
746
747 scan_ch->active_dwell = cpu_to_le16(active_dwell);
748 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
749
750 /* Set txpower levels to defaults */
751 scan_ch->dsp_atten = 110;
752
753 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
754 * power level:
755 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
756 */
757 if (band == IEEE80211_BAND_5GHZ)
758 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
759 else
760 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
761
762 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n",
763 channel, le32_to_cpu(scan_ch->type),
764 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
765 "ACTIVE" : "PASSIVE",
766 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
767 active_dwell : passive_dwell);
768
769 scan_ch++;
770 added++;
771 }
772
773 D_SCAN("total channels to scan %d\n", added);
774 return added;
775}
776
777int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif)
778{
779 struct il_host_cmd cmd = {
780 .id = REPLY_SCAN_CMD,
781 .len = sizeof(struct il_scan_cmd),
782 .flags = CMD_SIZE_HUGE,
783 };
784 struct il_scan_cmd *scan;
785 struct il_rxon_context *ctx = &il->ctx;
786 u32 rate_flags = 0;
787 u16 cmd_len;
788 u16 rx_chain = 0;
789 enum ieee80211_band band;
790 u8 n_probes = 0;
791 u8 rx_ant = il->hw_params.valid_rx_ant;
792 u8 rate;
793 bool is_active = false;
794 int chan_mod;
795 u8 active_chains;
796 u8 scan_tx_antennas = il->hw_params.valid_tx_ant;
797 int ret;
798
799 lockdep_assert_held(&il->mutex);
800
801 if (vif)
802 ctx = il_rxon_ctx_from_vif(vif);
803
804 if (!il->scan_cmd) {
805 il->scan_cmd = kmalloc(sizeof(struct il_scan_cmd) +
806 IL_MAX_SCAN_SIZE, GFP_KERNEL);
807 if (!il->scan_cmd) {
808 D_SCAN(
809 "fail to allocate memory for scan\n");
810 return -ENOMEM;
811 }
812 }
813 scan = il->scan_cmd;
814 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE);
815
816 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH;
817 scan->quiet_time = IL_ACTIVE_QUIET_TIME;
818
819 if (il_is_any_associated(il)) {
820 u16 interval;
821 u32 extra;
822 u32 suspend_time = 100;
823 u32 scan_suspend_time = 100;
824
825 D_INFO("Scanning while associated...\n");
826 interval = vif->bss_conf.beacon_int;
827
828 scan->suspend_time = 0;
829 scan->max_out_time = cpu_to_le32(200 * 1024);
830 if (!interval)
831 interval = suspend_time;
832
833 extra = (suspend_time / interval) << 22;
834 scan_suspend_time = (extra |
835 ((suspend_time % interval) * 1024));
836 scan->suspend_time = cpu_to_le32(scan_suspend_time);
837 D_SCAN("suspend_time 0x%X beacon interval %d\n",
838 scan_suspend_time, interval);
839 }
840
841 if (il->scan_request->n_ssids) {
842 int i, p = 0;
843 D_SCAN("Kicking off active scan\n");
844 for (i = 0; i < il->scan_request->n_ssids; i++) {
845 /* always does wildcard anyway */
846 if (!il->scan_request->ssids[i].ssid_len)
847 continue;
848 scan->direct_scan[p].id = WLAN_EID_SSID;
849 scan->direct_scan[p].len =
850 il->scan_request->ssids[i].ssid_len;
851 memcpy(scan->direct_scan[p].ssid,
852 il->scan_request->ssids[i].ssid,
853 il->scan_request->ssids[i].ssid_len);
854 n_probes++;
855 p++;
856 }
857 is_active = true;
858 } else
859 D_SCAN("Start passive scan.\n");
860
861 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
862 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
863 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
864
865 switch (il->scan_band) {
866 case IEEE80211_BAND_2GHZ:
867 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
868 chan_mod = le32_to_cpu(
869 il->ctx.active.flags &
870 RXON_FLG_CHANNEL_MODE_MSK)
871 >> RXON_FLG_CHANNEL_MODE_POS;
872 if (chan_mod == CHANNEL_MODE_PURE_40) {
873 rate = RATE_6M_PLCP;
874 } else {
875 rate = RATE_1M_PLCP;
876 rate_flags = RATE_MCS_CCK_MSK;
877 }
878 break;
879 case IEEE80211_BAND_5GHZ:
880 rate = RATE_6M_PLCP;
881 break;
882 default:
883 IL_WARN("Invalid scan band\n");
884 return -EIO;
885 }
886
887 /*
888 * If active scanning is requested but a certain channel is
889 * marked passive, we can do active scanning if we detect
890 * transmissions.
891 *
892 * There is an issue with some firmware versions that triggers
893 * a sysassert on a "good CRC threshold" of zero (== disabled),
894 * on a radar channel even though this means that we should NOT
895 * send probes.
896 *
897 * The "good CRC threshold" is the number of frames that we
898 * need to receive during our dwell time on a channel before
899 * sending out probes -- setting this to a huge value will
900 * mean we never reach it, but at the same time work around
901 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER
902 * here instead of IL_GOOD_CRC_TH_DISABLED.
903 */
904 scan->good_CRC_th = is_active ? IL_GOOD_CRC_TH_DEFAULT :
905 IL_GOOD_CRC_TH_NEVER;
906
907 band = il->scan_band;
908
909 if (il->cfg->scan_rx_antennas[band])
910 rx_ant = il->cfg->scan_rx_antennas[band];
911
912 il->scan_tx_ant[band] = il4965_toggle_tx_ant(il,
913 il->scan_tx_ant[band],
914 scan_tx_antennas);
915 rate_flags |= il4965_ant_idx_to_flags(il->scan_tx_ant[band]);
916 scan->tx_cmd.rate_n_flags = il4965_hw_set_rate_n_flags(rate, rate_flags);
917
918 /* In power save mode use one chain, otherwise use all chains */
919 if (test_bit(STATUS_POWER_PMI, &il->status)) {
920 /* rx_ant has been set to all valid chains previously */
921 active_chains = rx_ant &
922 ((u8)(il->chain_noise_data.active_chains));
923 if (!active_chains)
924 active_chains = rx_ant;
925
926 D_SCAN("chain_noise_data.active_chains: %u\n",
927 il->chain_noise_data.active_chains);
928
929 rx_ant = il4965_first_antenna(active_chains);
930 }
931
932 /* MIMO is not used here, but value is required */
933 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
934 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
935 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
936 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
937 scan->rx_chain = cpu_to_le16(rx_chain);
938
939 cmd_len = il_fill_probe_req(il,
940 (struct ieee80211_mgmt *)scan->data,
941 vif->addr,
942 il->scan_request->ie,
943 il->scan_request->ie_len,
944 IL_MAX_SCAN_SIZE - sizeof(*scan));
945 scan->tx_cmd.len = cpu_to_le16(cmd_len);
946
947 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
948 RXON_FILTER_BCON_AWARE_MSK);
949
950 scan->channel_count = il4965_get_channels_for_scan(il, vif, band,
951 is_active, n_probes,
952 (void *)&scan->data[cmd_len]);
953 if (scan->channel_count == 0) {
954 D_SCAN("channel count %d\n", scan->channel_count);
955 return -EIO;
956 }
957
958 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
959 scan->channel_count * sizeof(struct il_scan_channel);
960 cmd.data = scan;
961 scan->len = cpu_to_le16(cmd.len);
962
963 set_bit(STATUS_SCAN_HW, &il->status);
964
965 ret = il_send_cmd_sync(il, &cmd);
966 if (ret)
967 clear_bit(STATUS_SCAN_HW, &il->status);
968
969 return ret;
970}
971
972int il4965_manage_ibss_station(struct il_priv *il,
973 struct ieee80211_vif *vif, bool add)
974{
975 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
976
977 if (add)
978 return il4965_add_bssid_station(il, vif_priv->ctx,
979 vif->bss_conf.bssid,
980 &vif_priv->ibss_bssid_sta_id);
981 return il_remove_station(il, vif_priv->ibss_bssid_sta_id,
982 vif->bss_conf.bssid);
983}
984
985void il4965_free_tfds_in_queue(struct il_priv *il,
986 int sta_id, int tid, int freed)
987{
988 lockdep_assert_held(&il->sta_lock);
989
990 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed)
991 il->stations[sta_id].tid[tid].tfds_in_queue -= freed;
992 else {
993 D_TX("free more than tfds_in_queue (%u:%d)\n",
994 il->stations[sta_id].tid[tid].tfds_in_queue,
995 freed);
996 il->stations[sta_id].tid[tid].tfds_in_queue = 0;
997 }
998}
999
1000#define IL_TX_QUEUE_MSK 0xfffff
1001
1002static bool il4965_is_single_rx_stream(struct il_priv *il)
1003{
1004 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1005 il->current_ht_config.single_chain_sufficient;
1006}
1007
1008#define IL_NUM_RX_CHAINS_MULTIPLE 3
1009#define IL_NUM_RX_CHAINS_SINGLE 2
1010#define IL_NUM_IDLE_CHAINS_DUAL 2
1011#define IL_NUM_IDLE_CHAINS_SINGLE 1
1012
1013/*
1014 * Determine how many receiver/antenna chains to use.
1015 *
1016 * More provides better reception via diversity. Fewer saves power
1017 * at the expense of throughput, but only when not in powersave to
1018 * start with.
1019 *
1020 * MIMO (dual stream) requires at least 2, but works better with 3.
1021 * This does not determine *which* chains to use, just how many.
1022 */
1023static int il4965_get_active_rx_chain_count(struct il_priv *il)
1024{
1025 /* # of Rx chains to use when expecting MIMO. */
1026 if (il4965_is_single_rx_stream(il))
1027 return IL_NUM_RX_CHAINS_SINGLE;
1028 else
1029 return IL_NUM_RX_CHAINS_MULTIPLE;
1030}
1031
1032/*
1033 * When we are in power saving mode, unless device support spatial
1034 * multiplexing power save, use the active count for rx chain count.
1035 */
1036static int
1037il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt)
1038{
1039 /* # Rx chains when idling, depending on SMPS mode */
1040 switch (il->current_ht_config.smps) {
1041 case IEEE80211_SMPS_STATIC:
1042 case IEEE80211_SMPS_DYNAMIC:
1043 return IL_NUM_IDLE_CHAINS_SINGLE;
1044 case IEEE80211_SMPS_OFF:
1045 return active_cnt;
1046 default:
1047 WARN(1, "invalid SMPS mode %d",
1048 il->current_ht_config.smps);
1049 return active_cnt;
1050 }
1051}
1052
1053/* up to 4 chains */
1054static u8 il4965_count_chain_bitmap(u32 chain_bitmap)
1055{
1056 u8 res;
1057 res = (chain_bitmap & BIT(0)) >> 0;
1058 res += (chain_bitmap & BIT(1)) >> 1;
1059 res += (chain_bitmap & BIT(2)) >> 2;
1060 res += (chain_bitmap & BIT(3)) >> 3;
1061 return res;
1062}
1063
1064/**
1065 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1066 *
1067 * Selects how many and which Rx receivers/antennas/chains to use.
1068 * This should not be used for scan command ... it puts data in wrong place.
1069 */
1070void il4965_set_rxon_chain(struct il_priv *il, struct il_rxon_context *ctx)
1071{
1072 bool is_single = il4965_is_single_rx_stream(il);
1073 bool is_cam = !test_bit(STATUS_POWER_PMI, &il->status);
1074 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1075 u32 active_chains;
1076 u16 rx_chain;
1077
1078 /* Tell uCode which antennas are actually connected.
1079 * Before first association, we assume all antennas are connected.
1080 * Just after first association, il4965_chain_noise_calibration()
1081 * checks which antennas actually *are* connected. */
1082 if (il->chain_noise_data.active_chains)
1083 active_chains = il->chain_noise_data.active_chains;
1084 else
1085 active_chains = il->hw_params.valid_rx_ant;
1086
1087 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1088
1089 /* How many receivers should we use? */
1090 active_rx_cnt = il4965_get_active_rx_chain_count(il);
1091 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt);
1092
1093
1094 /* correct rx chain count according hw settings
1095 * and chain noise calibration
1096 */
1097 valid_rx_cnt = il4965_count_chain_bitmap(active_chains);
1098 if (valid_rx_cnt < active_rx_cnt)
1099 active_rx_cnt = valid_rx_cnt;
1100
1101 if (valid_rx_cnt < idle_rx_cnt)
1102 idle_rx_cnt = valid_rx_cnt;
1103
1104 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
1105 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
1106
1107 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
1108
1109 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam)
1110 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
1111 else
1112 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
1113
1114 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
1115 ctx->staging.rx_chain,
1116 active_rx_cnt, idle_rx_cnt);
1117
1118 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
1119 active_rx_cnt < idle_rx_cnt);
1120}
1121
1122u8 il4965_toggle_tx_ant(struct il_priv *il, u8 ant, u8 valid)
1123{
1124 int i;
1125 u8 ind = ant;
1126
1127 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
1128 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
1129 if (valid & BIT(ind))
1130 return ind;
1131 }
1132 return ant;
1133}
1134
1135static const char *il4965_get_fh_string(int cmd)
1136{
1137 switch (cmd) {
1138 IL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1139 IL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1140 IL_CMD(FH_RSCSR_CHNL0_WPTR);
1141 IL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1142 IL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1143 IL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1144 IL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1145 IL_CMD(FH_TSSR_TX_STATUS_REG);
1146 IL_CMD(FH_TSSR_TX_ERROR_REG);
1147 default:
1148 return "UNKNOWN";
1149 }
1150}
1151
1152int il4965_dump_fh(struct il_priv *il, char **buf, bool display)
1153{
1154 int i;
1155#ifdef CONFIG_IWLEGACY_DEBUG
1156 int pos = 0;
1157 size_t bufsz = 0;
1158#endif
1159 static const u32 fh_tbl[] = {
1160 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1161 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1162 FH_RSCSR_CHNL0_WPTR,
1163 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1164 FH_MEM_RSSR_SHARED_CTRL_REG,
1165 FH_MEM_RSSR_RX_STATUS_REG,
1166 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1167 FH_TSSR_TX_STATUS_REG,
1168 FH_TSSR_TX_ERROR_REG
1169 };
1170#ifdef CONFIG_IWLEGACY_DEBUG
1171 if (display) {
1172 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1173 *buf = kmalloc(bufsz, GFP_KERNEL);
1174 if (!*buf)
1175 return -ENOMEM;
1176 pos += scnprintf(*buf + pos, bufsz - pos,
1177 "FH register values:\n");
1178 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1179 pos += scnprintf(*buf + pos, bufsz - pos,
1180 " %34s: 0X%08x\n",
1181 il4965_get_fh_string(fh_tbl[i]),
1182 il_rd(il, fh_tbl[i]));
1183 }
1184 return pos;
1185 }
1186#endif
1187 IL_ERR("FH register values:\n");
1188 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1189 IL_ERR(" %34s: 0X%08x\n",
1190 il4965_get_fh_string(fh_tbl[i]),
1191 il_rd(il, fh_tbl[i]));
1192 }
1193 return 0;
1194}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 13:15:19 -0500