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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/wireless/i82593.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/wireless/i82593.h')
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1 files changed, 224 insertions, 0 deletions
diff --git a/drivers/net/wireless/i82593.h b/drivers/net/wireless/i82593.h
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index 000000000000..33acb8add4d6
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+++ b/drivers/net/wireless/i82593.h
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1/*
2 * Definitions for Intel 82593 CSMA/CD Core LAN Controller
3 * The definitions are taken from the 1992 users manual with Intel
4 * order number 297125-001.
5 *
6 * /usr/src/pc/RCS/i82593.h,v 1.1 1996/07/17 15:23:12 root Exp
7 *
8 * Copyright 1994, Anders Klemets <klemets@it.kth.se>
9 *
10 * This software may be freely distributed for noncommercial purposes
11 * as long as this notice is retained.
12 *
13 * HISTORY
14 * i82593.h,v
15 * Revision 1.1 1996/07/17 15:23:12 root
16 * Initial revision
17 *
18 * Revision 1.3 1995/04/05 15:13:58 adj
19 * Initial alpha release
20 *
21 * Revision 1.2 1994/06/16 23:57:31 klemets
22 * Mirrored all the fields in the configuration block.
23 *
24 * Revision 1.1 1994/06/02 20:25:34 klemets
25 * Initial revision
26 *
27 *
28 */
29#ifndef _I82593_H
30#define _I82593_H
31
32/* Intel 82593 CSMA/CD Core LAN Controller */
33
34/* Port 0 Command Register definitions */
35
36/* Execution operations */
37#define OP0_NOP 0 /* CHNL = 0 */
38#define OP0_SWIT_TO_PORT_1 0 /* CHNL = 1 */
39#define OP0_IA_SETUP 1
40#define OP0_CONFIGURE 2
41#define OP0_MC_SETUP 3
42#define OP0_TRANSMIT 4
43#define OP0_TDR 5
44#define OP0_DUMP 6
45#define OP0_DIAGNOSE 7
46#define OP0_TRANSMIT_NO_CRC 9
47#define OP0_RETRANSMIT 12
48#define OP0_ABORT 13
49/* Reception operations */
50#define OP0_RCV_ENABLE 8
51#define OP0_RCV_DISABLE 10
52#define OP0_STOP_RCV 11
53/* Status pointer control operations */
54#define OP0_FIX_PTR 15 /* CHNL = 1 */
55#define OP0_RLS_PTR 15 /* CHNL = 0 */
56#define OP0_RESET 14
57
58#define CR0_CHNL (1 << 4) /* 0=Channel 0, 1=Channel 1 */
59#define CR0_STATUS_0 0x00
60#define CR0_STATUS_1 0x20
61#define CR0_STATUS_2 0x40
62#define CR0_STATUS_3 0x60
63#define CR0_INT_ACK (1 << 7) /* 0=No ack, 1=acknowledge */
64
65/* Port 0 Status Register definitions */
66
67#define SR0_NO_RESULT 0 /* dummy */
68#define SR0_EVENT_MASK 0x0f
69#define SR0_IA_SETUP_DONE 1
70#define SR0_CONFIGURE_DONE 2
71#define SR0_MC_SETUP_DONE 3
72#define SR0_TRANSMIT_DONE 4
73#define SR0_TDR_DONE 5
74#define SR0_DUMP_DONE 6
75#define SR0_DIAGNOSE_PASSED 7
76#define SR0_TRANSMIT_NO_CRC_DONE 9
77#define SR0_RETRANSMIT_DONE 12
78#define SR0_EXECUTION_ABORTED 13
79#define SR0_END_OF_FRAME 8
80#define SR0_RECEPTION_ABORTED 10
81#define SR0_DIAGNOSE_FAILED 15
82#define SR0_STOP_REG_HIT 11
83
84#define SR0_CHNL (1 << 4)
85#define SR0_EXECUTION (1 << 5)
86#define SR0_RECEPTION (1 << 6)
87#define SR0_INTERRUPT (1 << 7)
88#define SR0_BOTH_RX_TX (SR0_EXECUTION | SR0_RECEPTION)
89
90#define SR3_EXEC_STATE_MASK 0x03
91#define SR3_EXEC_IDLE 0
92#define SR3_TX_ABORT_IN_PROGRESS 1
93#define SR3_EXEC_ACTIVE 2
94#define SR3_ABORT_IN_PROGRESS 3
95#define SR3_EXEC_CHNL (1 << 2)
96#define SR3_STP_ON_NO_RSRC (1 << 3)
97#define SR3_RCVING_NO_RSRC (1 << 4)
98#define SR3_RCV_STATE_MASK 0x60
99#define SR3_RCV_IDLE 0x00
100#define SR3_RCV_READY 0x20
101#define SR3_RCV_ACTIVE 0x40
102#define SR3_RCV_STOP_IN_PROG 0x60
103#define SR3_RCV_CHNL (1 << 7)
104
105/* Port 1 Command Register definitions */
106
107#define OP1_NOP 0
108#define OP1_SWIT_TO_PORT_0 1
109#define OP1_INT_DISABLE 2
110#define OP1_INT_ENABLE 3
111#define OP1_SET_TS 5
112#define OP1_RST_TS 7
113#define OP1_POWER_DOWN 8
114#define OP1_RESET_RING_MNGMT 11
115#define OP1_RESET 14
116#define OP1_SEL_RST 15
117
118#define CR1_STATUS_4 0x00
119#define CR1_STATUS_5 0x20
120#define CR1_STATUS_6 0x40
121#define CR1_STOP_REG_UPDATE (1 << 7)
122
123/* Receive frame status bits */
124
125#define RX_RCLD (1 << 0)
126#define RX_IA_MATCH (1 << 1)
127#define RX_NO_AD_MATCH (1 << 2)
128#define RX_NO_SFD (1 << 3)
129#define RX_SRT_FRM (1 << 7)
130#define RX_OVRRUN (1 << 8)
131#define RX_ALG_ERR (1 << 10)
132#define RX_CRC_ERR (1 << 11)
133#define RX_LEN_ERR (1 << 12)
134#define RX_RCV_OK (1 << 13)
135#define RX_TYP_LEN (1 << 15)
136
137/* Transmit status bits */
138
139#define TX_NCOL_MASK 0x0f
140#define TX_FRTL (1 << 4)
141#define TX_MAX_COL (1 << 5)
142#define TX_HRT_BEAT (1 << 6)
143#define TX_DEFER (1 << 7)
144#define TX_UND_RUN (1 << 8)
145#define TX_LOST_CTS (1 << 9)
146#define TX_LOST_CRS (1 << 10)
147#define TX_LTCOL (1 << 11)
148#define TX_OK (1 << 13)
149#define TX_COLL (1 << 15)
150
151struct i82593_conf_block {
152 u_char fifo_limit : 4,
153 forgnesi : 1,
154 fifo_32 : 1,
155 d6mod : 1,
156 throttle_enb : 1;
157 u_char throttle : 6,
158 cntrxint : 1,
159 contin : 1;
160 u_char addr_len : 3,
161 acloc : 1,
162 preamb_len : 2,
163 loopback : 2;
164 u_char lin_prio : 3,
165 tbofstop : 1,
166 exp_prio : 3,
167 bof_met : 1;
168 u_char : 4,
169 ifrm_spc : 4;
170 u_char : 5,
171 slottim_low : 3;
172 u_char slottim_hi : 3,
173 : 1,
174 max_retr : 4;
175 u_char prmisc : 1,
176 bc_dis : 1,
177 : 1,
178 crs_1 : 1,
179 nocrc_ins : 1,
180 crc_1632 : 1,
181 : 1,
182 crs_cdt : 1;
183 u_char cs_filter : 3,
184 crs_src : 1,
185 cd_filter : 3,
186 : 1;
187 u_char : 2,
188 min_fr_len : 6;
189 u_char lng_typ : 1,
190 lng_fld : 1,
191 rxcrc_xf : 1,
192 artx : 1,
193 sarec : 1,
194 tx_jabber : 1, /* why is this called max_len in the manual? */
195 hash_1 : 1,
196 lbpkpol : 1;
197 u_char : 6,
198 fdx : 1,
199 : 1;
200 u_char dummy_6 : 6, /* supposed to be ones */
201 mult_ia : 1,
202 dis_bof : 1;
203 u_char dummy_1 : 1, /* supposed to be one */
204 tx_ifs_retrig : 2,
205 mc_all : 1,
206 rcv_mon : 2,
207 frag_acpt : 1,
208 tstrttrs : 1;
209 u_char fretx : 1,
210 runt_eop : 1,
211 hw_sw_pin : 1,
212 big_endn : 1,
213 syncrqs : 1,
214 sttlen : 1,
215 tx_eop : 1,
216 rx_eop : 1;
217 u_char rbuf_size : 5,
218 rcvstop : 1,
219 : 2;
220};
221
222#define I82593_MAX_MULTICAST_ADDRESSES 128 /* Hardware hashed filter */
223
224#endif /* _I82593_H */