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authorDavid Howells <dhowells@redhat.com>2006-12-05 09:37:56 -0500
committerDavid Howells <dhowells@warthog.cambridge.redhat.com>2006-12-05 09:37:56 -0500
commit4c1ac1b49122b805adfa4efc620592f68dccf5db (patch)
tree87557f4bc2fd4fe65b7570489c2f610c45c0adcd /drivers/net/wireless/bcm43xx
parentc4028958b6ecad064b1a6303a6a5906d4fe48d73 (diff)
parentd916faace3efc0bf19fe9a615a1ab8fa1a24cd93 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: drivers/infiniband/core/iwcm.c drivers/net/chelsio/cxgb2.c drivers/net/wireless/bcm43xx/bcm43xx_main.c drivers/net/wireless/prism54/islpci_eth.c drivers/usb/core/hub.h drivers/usb/input/hid-core.c net/core/netpoll.c Fix up merge failures with Linus's head and fix new compilation failures. Signed-Off-By: David Howells <dhowells@redhat.com>
Diffstat (limited to 'drivers/net/wireless/bcm43xx')
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx.h32
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_main.c207
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_power.c28
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_wx.c4
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_xmit.c18
5 files changed, 174 insertions, 115 deletions
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx.h b/drivers/net/wireless/bcm43xx/bcm43xx.h
index fbc0c087f53c..8286678513b9 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx.h
+++ b/drivers/net/wireless/bcm43xx/bcm43xx.h
@@ -159,6 +159,7 @@
159 159
160/* Chipcommon registers. */ 160/* Chipcommon registers. */
161#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 161#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
162#define BCM43xx_CHIPCOMMON_CTL 0x28
162#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 163#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
163#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 164#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
164#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 165#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
@@ -172,6 +173,33 @@
172/* SBTOPCI2 values. */ 173/* SBTOPCI2 values. */
173#define BCM43xx_SBTOPCI2_PREFETCH 0x4 174#define BCM43xx_SBTOPCI2_PREFETCH 0x4
174#define BCM43xx_SBTOPCI2_BURST 0x8 175#define BCM43xx_SBTOPCI2_BURST 0x8
176#define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20
177
178/* PCI-E core registers. */
179#define BCM43xx_PCIECORE_REG_ADDR 0x0130
180#define BCM43xx_PCIECORE_REG_DATA 0x0134
181#define BCM43xx_PCIECORE_MDIO_CTL 0x0128
182#define BCM43xx_PCIECORE_MDIO_DATA 0x012C
183
184/* PCI-E registers. */
185#define BCM43xx_PCIE_TLP_WORKAROUND 0x0004
186#define BCM43xx_PCIE_DLLP_LINKCTL 0x0100
187
188/* PCI-E MDIO bits. */
189#define BCM43xx_PCIE_MDIO_ST 0x40000000
190#define BCM43xx_PCIE_MDIO_WT 0x10000000
191#define BCM43xx_PCIE_MDIO_DEV 22
192#define BCM43xx_PCIE_MDIO_REG 18
193#define BCM43xx_PCIE_MDIO_TA 0x00020000
194#define BCM43xx_PCIE_MDIO_TC 0x0100
195
196/* MDIO devices. */
197#define BCM43xx_MDIO_SERDES_RX 0x1F
198
199/* SERDES RX registers. */
200#define BCM43xx_SERDES_RXTIMER 0x2
201#define BCM43xx_SERDES_CDR 0x6
202#define BCM43xx_SERDES_CDR_BW 0x7
175 203
176/* Chipcommon capabilities. */ 204/* Chipcommon capabilities. */
177#define BCM43xx_CAPABILITIES_PCTL 0x00040000 205#define BCM43xx_CAPABILITIES_PCTL 0x00040000
@@ -221,6 +249,7 @@
221#define BCM43xx_COREID_USB20_HOST 0x819 249#define BCM43xx_COREID_USB20_HOST 0x819
222#define BCM43xx_COREID_USB20_DEV 0x81a 250#define BCM43xx_COREID_USB20_DEV 0x81a
223#define BCM43xx_COREID_SDIO_HOST 0x81b 251#define BCM43xx_COREID_SDIO_HOST 0x81b
252#define BCM43xx_COREID_PCIE 0x820
224 253
225/* Core Information Registers */ 254/* Core Information Registers */
226#define BCM43xx_CIR_BASE 0xf00 255#define BCM43xx_CIR_BASE 0xf00
@@ -365,6 +394,9 @@
365#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 394#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
366#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 395#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
367 396
397/* FIXME: the next line is a guess as to what the maximum RSSI value might be */
398#define RX_RSSI_MAX 60
399
368/* Max size of a security key */ 400/* Max size of a security key */
369#define BCM43xx_SEC_KEYSIZE 16 401#define BCM43xx_SEC_KEYSIZE 16
370/* Security algorithms. */ 402/* Security algorithms. */
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_main.c b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
index 728a9b789fdf..2ec2e5afce67 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_main.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
@@ -130,6 +130,10 @@ MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4307 802.11b */ 131 /* Broadcom 4307 802.11b */
132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4311 802.11(a)/b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4312 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */ 137 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 138 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4319 802.11a/b/g */ 139 /* Broadcom 4319 802.11a/b/g */
@@ -2600,8 +2604,9 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2600 /* fetch sb_id_hi from core information registers */ 2604 /* fetch sb_id_hi from core information registers */
2601 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI); 2605 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2602 2606
2603 core_id = (sb_id_hi & 0xFFF0) >> 4; 2607 core_id = (sb_id_hi & 0x8FF0) >> 4;
2604 core_rev = (sb_id_hi & 0xF); 2608 core_rev = (sb_id_hi & 0x7000) >> 8;
2609 core_rev |= (sb_id_hi & 0xF);
2605 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16; 2610 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2606 2611
2607 /* if present, chipcommon is always core 0; read the chipid from it */ 2612 /* if present, chipcommon is always core 0; read the chipid from it */
@@ -2679,14 +2684,10 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2679 bcm->chip_id, bcm->chip_rev); 2684 bcm->chip_id, bcm->chip_rev);
2680 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count); 2685 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2681 if (bcm->core_chipcommon.available) { 2686 if (bcm->core_chipcommon.available) {
2682 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n", 2687 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2683 core_id, core_rev, core_vendor, 2688 core_id, core_rev, core_vendor);
2684 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2685 }
2686
2687 if (bcm->core_chipcommon.available)
2688 current_core = 1; 2689 current_core = 1;
2689 else 2690 } else
2690 current_core = 0; 2691 current_core = 0;
2691 for ( ; current_core < core_count; current_core++) { 2692 for ( ; current_core < core_count; current_core++) {
2692 struct bcm43xx_coreinfo *core; 2693 struct bcm43xx_coreinfo *core;
@@ -2704,13 +2705,13 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2704 core_rev = (sb_id_hi & 0xF); 2705 core_rev = (sb_id_hi & 0xF);
2705 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16; 2706 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2706 2707
2707 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n", 2708 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n",
2708 current_core, core_id, core_rev, core_vendor, 2709 current_core, core_id, core_rev, core_vendor);
2709 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2710 2710
2711 core = NULL; 2711 core = NULL;
2712 switch (core_id) { 2712 switch (core_id) {
2713 case BCM43xx_COREID_PCI: 2713 case BCM43xx_COREID_PCI:
2714 case BCM43xx_COREID_PCIE:
2714 core = &bcm->core_pci; 2715 core = &bcm->core_pci;
2715 if (core->available) { 2716 if (core->available) {
2716 printk(KERN_WARNING PFX "Multiple PCI cores found.\n"); 2717 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
@@ -2749,12 +2750,12 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2749 case 6: 2750 case 6:
2750 case 7: 2751 case 7:
2751 case 9: 2752 case 9:
2753 case 10:
2752 break; 2754 break;
2753 default: 2755 default:
2754 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n", 2756 printk(KERN_WARNING PFX
2757 "Unsupported 80211 core revision %u\n",
2755 core_rev); 2758 core_rev);
2756 err = -ENODEV;
2757 goto out;
2758 } 2759 }
2759 bcm->nr_80211_available++; 2760 bcm->nr_80211_available++;
2760 core->priv = ext_80211; 2761 core->priv = ext_80211;
@@ -2868,16 +2869,11 @@ static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2868 u32 sbimconfiglow; 2869 u32 sbimconfiglow;
2869 u8 limit; 2870 u8 limit;
2870 2871
2871 if (bcm->chip_rev < 5) { 2872 if (bcm->core_pci.rev <= 5 && bcm->core_pci.id != BCM43xx_COREID_PCIE) {
2872 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW); 2873 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2873 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK; 2874 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2874 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK; 2875 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2875 if (bcm->bustype == BCM43xx_BUSTYPE_PCI) 2876 sbimconfiglow |= 0x32;
2876 sbimconfiglow |= 0x32;
2877 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2878 sbimconfiglow |= 0x53;
2879 else
2880 assert(0);
2881 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow); 2877 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2882 } 2878 }
2883 2879
@@ -3004,22 +3000,64 @@ static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
3004 3000
3005static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm) 3001static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
3006{ 3002{
3007 int err; 3003 int err = 0;
3008 struct bcm43xx_coreinfo *old_core;
3009 3004
3010 old_core = bcm->current_core; 3005 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3011 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3012 if (err)
3013 goto out;
3014 3006
3015 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000); 3007 if (bcm->core_chipcommon.available) {
3008 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
3009 if (err)
3010 goto out;
3011
3012 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3013
3014 /* this function is always called when a PCI core is mapped */
3015 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3016 if (err)
3017 goto out;
3018 } else
3019 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
3020
3021 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3016 3022
3017 bcm43xx_switch_core(bcm, old_core);
3018 assert(err == 0);
3019out: 3023out:
3020 return err; 3024 return err;
3021} 3025}
3022 3026
3027static u32 bcm43xx_pcie_reg_read(struct bcm43xx_private *bcm, u32 address)
3028{
3029 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3030 return bcm43xx_read32(bcm, BCM43xx_PCIECORE_REG_DATA);
3031}
3032
3033static void bcm43xx_pcie_reg_write(struct bcm43xx_private *bcm, u32 address,
3034 u32 data)
3035{
3036 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
3037 bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_DATA, data);
3038}
3039
3040static void bcm43xx_pcie_mdio_write(struct bcm43xx_private *bcm, u8 dev, u8 reg,
3041 u16 data)
3042{
3043 int i;
3044
3045 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0x0082);
3046 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_DATA, BCM43xx_PCIE_MDIO_ST |
3047 BCM43xx_PCIE_MDIO_WT | (dev << BCM43xx_PCIE_MDIO_DEV) |
3048 (reg << BCM43xx_PCIE_MDIO_REG) | BCM43xx_PCIE_MDIO_TA |
3049 data);
3050 udelay(10);
3051
3052 for (i = 0; i < 10; i++) {
3053 if (bcm43xx_read32(bcm, BCM43xx_PCIECORE_MDIO_CTL) &
3054 BCM43xx_PCIE_MDIO_TC)
3055 break;
3056 msleep(1);
3057 }
3058 bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0);
3059}
3060
3023/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable. 3061/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3024 * To enable core 0, pass a core_mask of 1<<0 3062 * To enable core 0, pass a core_mask of 1<<0
3025 */ 3063 */
@@ -3039,7 +3077,8 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3039 if (err) 3077 if (err)
3040 goto out; 3078 goto out;
3041 3079
3042 if (bcm->core_pci.rev < 6) { 3080 if (bcm->current_core->rev < 6 ||
3081 bcm->current_core->id == BCM43xx_COREID_PCI) {
3043 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC); 3082 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3044 value |= (1 << backplane_flag_nr); 3083 value |= (1 << backplane_flag_nr);
3045 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value); 3084 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
@@ -3057,21 +3096,46 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3057 } 3096 }
3058 } 3097 }
3059 3098
3060 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2); 3099 if (bcm->current_core->id == BCM43xx_COREID_PCI) {
3061 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST; 3100 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3062 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value); 3101 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3063 3102 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3064 if (bcm->core_pci.rev < 5) { 3103
3065 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW); 3104 if (bcm->current_core->rev < 5) {
3066 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT) 3105 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3067 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK; 3106 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3068 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT) 3107 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3069 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK; 3108 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3070 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value); 3109 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3071 err = bcm43xx_pcicore_commit_settings(bcm); 3110 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3072 assert(err == 0); 3111 err = bcm43xx_pcicore_commit_settings(bcm);
3112 assert(err == 0);
3113 } else if (bcm->current_core->rev >= 11) {
3114 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3115 value |= BCM43xx_SBTOPCI2_MEMREAD_MULTI;
3116 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3117 }
3118 } else {
3119 if (bcm->current_core->rev == 0 || bcm->current_core->rev == 1) {
3120 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_TLP_WORKAROUND);
3121 value |= 0x8;
3122 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_TLP_WORKAROUND,
3123 value);
3124 }
3125 if (bcm->current_core->rev == 0) {
3126 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3127 BCM43xx_SERDES_RXTIMER, 0x8128);
3128 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3129 BCM43xx_SERDES_CDR, 0x0100);
3130 bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
3131 BCM43xx_SERDES_CDR_BW, 0x1466);
3132 } else if (bcm->current_core->rev == 1) {
3133 value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_DLLP_LINKCTL);
3134 value |= 0x40;
3135 bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_DLLP_LINKCTL,
3136 value);
3137 }
3073 } 3138 }
3074
3075out_switch_back: 3139out_switch_back:
3076 err = bcm43xx_switch_core(bcm, old_core); 3140 err = bcm43xx_switch_core(bcm, old_core);
3077out: 3141out:
@@ -3140,43 +3204,17 @@ static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3140 3204
3141static void do_periodic_work(struct bcm43xx_private *bcm) 3205static void do_periodic_work(struct bcm43xx_private *bcm)
3142{ 3206{
3143 unsigned int state; 3207 if (bcm->periodic_state % 8 == 0)
3144
3145 state = bcm->periodic_state;
3146 if (state % 8 == 0)
3147 bcm43xx_periodic_every120sec(bcm); 3208 bcm43xx_periodic_every120sec(bcm);
3148 if (state % 4 == 0) 3209 if (bcm->periodic_state % 4 == 0)
3149 bcm43xx_periodic_every60sec(bcm); 3210 bcm43xx_periodic_every60sec(bcm);
3150 if (state % 2 == 0) 3211 if (bcm->periodic_state % 2 == 0)
3151 bcm43xx_periodic_every30sec(bcm); 3212 bcm43xx_periodic_every30sec(bcm);
3152 if (state % 1 == 0) 3213 bcm43xx_periodic_every15sec(bcm);
3153 bcm43xx_periodic_every15sec(bcm);
3154 bcm->periodic_state = state + 1;
3155 3214
3156 schedule_delayed_work(&bcm->periodic_work, HZ * 15); 3215 schedule_delayed_work(&bcm->periodic_work, HZ * 15);
3157} 3216}
3158 3217
3159/* Estimate a "Badness" value based on the periodic work
3160 * state-machine state. "Badness" is worse (bigger), if the
3161 * periodic work will take longer.
3162 */
3163static int estimate_periodic_work_badness(unsigned int state)
3164{
3165 int badness = 0;
3166
3167 if (state % 8 == 0) /* every 120 sec */
3168 badness += 10;
3169 if (state % 4 == 0) /* every 60 sec */
3170 badness += 5;
3171 if (state % 2 == 0) /* every 30 sec */
3172 badness += 1;
3173 if (state % 1 == 0) /* every 15 sec */
3174 badness += 1;
3175
3176#define BADNESS_LIMIT 4
3177 return badness;
3178}
3179
3180static void bcm43xx_periodic_work_handler(struct work_struct *work) 3218static void bcm43xx_periodic_work_handler(struct work_struct *work)
3181{ 3219{
3182 struct bcm43xx_private *bcm = 3220 struct bcm43xx_private *bcm =
@@ -3184,12 +3222,10 @@ static void bcm43xx_periodic_work_handler(struct work_struct *work)
3184 struct net_device *net_dev = bcm->net_dev; 3222 struct net_device *net_dev = bcm->net_dev;
3185 unsigned long flags; 3223 unsigned long flags;
3186 u32 savedirqs = 0; 3224 u32 savedirqs = 0;
3187 int badness;
3188 unsigned long orig_trans_start = 0; 3225 unsigned long orig_trans_start = 0;
3189 3226
3190 mutex_lock(&bcm->mutex); 3227 mutex_lock(&bcm->mutex);
3191 badness = estimate_periodic_work_badness(bcm->periodic_state); 3228 if (unlikely(bcm->periodic_state % 4 == 0)) {
3192 if (badness > BADNESS_LIMIT) {
3193 /* Periodic work will take a long time, so we want it to 3229 /* Periodic work will take a long time, so we want it to
3194 * be preemtible. 3230 * be preemtible.
3195 */ 3231 */
@@ -3221,7 +3257,7 @@ static void bcm43xx_periodic_work_handler(struct work_struct *work)
3221 3257
3222 do_periodic_work(bcm); 3258 do_periodic_work(bcm);
3223 3259
3224 if (badness > BADNESS_LIMIT) { 3260 if (unlikely(bcm->periodic_state % 4 == 0)) {
3225 spin_lock_irqsave(&bcm->irq_lock, flags); 3261 spin_lock_irqsave(&bcm->irq_lock, flags);
3226 tasklet_enable(&bcm->isr_tasklet); 3262 tasklet_enable(&bcm->isr_tasklet);
3227 bcm43xx_interrupt_enable(bcm, savedirqs); 3263 bcm43xx_interrupt_enable(bcm, savedirqs);
@@ -3232,6 +3268,7 @@ static void bcm43xx_periodic_work_handler(struct work_struct *work)
3232 net_dev->trans_start = orig_trans_start; 3268 net_dev->trans_start = orig_trans_start;
3233 } 3269 }
3234 mmiowb(); 3270 mmiowb();
3271 bcm->periodic_state++;
3235 spin_unlock_irqrestore(&bcm->irq_lock, flags); 3272 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3236 mutex_unlock(&bcm->mutex); 3273 mutex_unlock(&bcm->mutex);
3237} 3274}
@@ -3677,7 +3714,7 @@ static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3677 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND; 3714 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3678 break; 3715 break;
3679 case BCM43xx_PHYTYPE_G: 3716 case BCM43xx_PHYTYPE_G:
3680 if (phy_rev > 7) 3717 if (phy_rev > 8)
3681 phy_rev_ok = 0; 3718 phy_rev_ok = 0;
3682 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION | 3719 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3683 IEEE80211_CCK_MODULATION; 3720 IEEE80211_CCK_MODULATION;
@@ -3689,6 +3726,8 @@ static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3689 phy_type); 3726 phy_type);
3690 return -ENODEV; 3727 return -ENODEV;
3691 }; 3728 };
3729 bcm->ieee->perfect_rssi = RX_RSSI_MAX;
3730 bcm->ieee->worst_rssi = 0;
3692 if (!phy_rev_ok) { 3731 if (!phy_rev_ok) {
3693 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n", 3732 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3694 phy_rev); 3733 phy_rev);
@@ -3975,11 +4014,6 @@ static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3975 return NETDEV_TX_OK; 4014 return NETDEV_TX_OK;
3976} 4015}
3977 4016
3978static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3979{
3980 return &(bcm43xx_priv(net_dev)->ieee->stats);
3981}
3982
3983static void bcm43xx_net_tx_timeout(struct net_device *net_dev) 4017static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3984{ 4018{
3985 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev); 4019 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
@@ -4093,7 +4127,6 @@ static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4093 4127
4094 net_dev->open = bcm43xx_net_open; 4128 net_dev->open = bcm43xx_net_open;
4095 net_dev->stop = bcm43xx_net_stop; 4129 net_dev->stop = bcm43xx_net_stop;
4096 net_dev->get_stats = bcm43xx_net_get_stats;
4097 net_dev->tx_timeout = bcm43xx_net_tx_timeout; 4130 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4098#ifdef CONFIG_NET_POLL_CONTROLLER 4131#ifdef CONFIG_NET_POLL_CONTROLLER
4099 net_dev->poll_controller = bcm43xx_net_poll_controller; 4132 net_dev->poll_controller = bcm43xx_net_poll_controller;
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_power.c b/drivers/net/wireless/bcm43xx/bcm43xx_power.c
index 6569da3a7a39..7e774f410953 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_power.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_power.c
@@ -153,8 +153,6 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
153 int err, maxfreq; 153 int err, maxfreq;
154 struct bcm43xx_coreinfo *old_core; 154 struct bcm43xx_coreinfo *old_core;
155 155
156 if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
157 return 0;
158 old_core = bcm->current_core; 156 old_core = bcm->current_core;
159 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon); 157 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
160 if (err == -ENODEV) 158 if (err == -ENODEV)
@@ -162,11 +160,27 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
162 if (err) 160 if (err)
163 goto out; 161 goto out;
164 162
165 maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1); 163 if (bcm->chip_id == 0x4321) {
166 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY, 164 if (bcm->chip_rev == 0)
167 (maxfreq * 150 + 999999) / 1000000); 165 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x03A4);
168 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY, 166 if (bcm->chip_rev == 1)
169 (maxfreq * 15 + 999999) / 1000000); 167 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x00A4);
168 }
169
170 if (bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL) {
171 if (bcm->current_core->rev >= 10) {
172 /* Set Idle Power clock rate to 1Mhz */
173 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL,
174 (bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL)
175 & 0x0000FFFF) | 0x40000);
176 } else {
177 maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
178 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
179 (maxfreq * 150 + 999999) / 1000000);
180 bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
181 (maxfreq * 15 + 999999) / 1000000);
182 }
183 }
170 184
171 err = bcm43xx_switch_core(bcm, old_core); 185 err = bcm43xx_switch_core(bcm, old_core);
172 assert(err == 0); 186 assert(err == 0);
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_wx.c b/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
index d27016f8c736..a659442b9c15 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_wx.c
@@ -47,9 +47,6 @@
47#define BCM43xx_WX_VERSION 18 47#define BCM43xx_WX_VERSION 18
48 48
49#define MAX_WX_STRING 80 49#define MAX_WX_STRING 80
50/* FIXME: the next line is a guess as to what the maximum RSSI value might be */
51#define RX_RSSI_MAX 60
52
53 50
54static int bcm43xx_wx_get_name(struct net_device *net_dev, 51static int bcm43xx_wx_get_name(struct net_device *net_dev,
55 struct iw_request_info *info, 52 struct iw_request_info *info,
@@ -693,6 +690,7 @@ static int bcm43xx_wx_set_swencryption(struct net_device *net_dev,
693 bcm->ieee->host_encrypt = !!on; 690 bcm->ieee->host_encrypt = !!on;
694 bcm->ieee->host_decrypt = !!on; 691 bcm->ieee->host_decrypt = !!on;
695 bcm->ieee->host_build_iv = !on; 692 bcm->ieee->host_build_iv = !on;
693 bcm->ieee->host_strip_iv_icv = !on;
696 spin_unlock_irqrestore(&bcm->irq_lock, flags); 694 spin_unlock_irqrestore(&bcm->irq_lock, flags);
697 mutex_unlock(&bcm->mutex); 695 mutex_unlock(&bcm->mutex);
698 696
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c b/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
index 0159e4e93201..3e2462671690 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_xmit.c
@@ -544,24 +544,6 @@ int bcm43xx_rx(struct bcm43xx_private *bcm,
544 } 544 }
545 545
546 frame_ctl = le16_to_cpu(wlhdr->frame_ctl); 546 frame_ctl = le16_to_cpu(wlhdr->frame_ctl);
547 if ((frame_ctl & IEEE80211_FCTL_PROTECTED) && !bcm->ieee->host_decrypt) {
548 frame_ctl &= ~IEEE80211_FCTL_PROTECTED;
549 wlhdr->frame_ctl = cpu_to_le16(frame_ctl);
550 /* trim IV and ICV */
551 /* FIXME: this must be done only for WEP encrypted packets */
552 if (skb->len < 32) {
553 dprintkl(KERN_ERR PFX "RX packet dropped (PROTECTED flag "
554 "set and length < 32)\n");
555 return -EINVAL;
556 } else {
557 memmove(skb->data + 4, skb->data, 24);
558 skb_pull(skb, 4);
559 skb_trim(skb, skb->len - 4);
560 stats.len -= 8;
561 }
562 wlhdr = (struct ieee80211_hdr_4addr *)(skb->data);
563 }
564
565 switch (WLAN_FC_GET_TYPE(frame_ctl)) { 547 switch (WLAN_FC_GET_TYPE(frame_ctl)) {
566 case IEEE80211_FTYPE_MGMT: 548 case IEEE80211_FTYPE_MGMT:
567 ieee80211_rx_mgt(bcm->ieee, wlhdr, &stats); 549 ieee80211_rx_mgt(bcm->ieee, wlhdr, &stats);