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authorStefano Brivio <stefano.brivio@polimi.it>2008-01-23 08:48:50 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-31 22:26:37 -0500
commite78c9d285709f535caae405f1da5b2936f51f0b5 (patch)
tree13840f98a004920dd8e93e8fe2c16d8b51b59e8f /drivers/net/wireless/b43legacy/phy.c
parent8712f2769dd66d8e7ff179d525b93e0a15a5b963 (diff)
b43legacy: fix MAC control and microcode init
This zeros out all microcode related memory before loading the microcode. This also fixes initialization of the MAC control register. The _only_ place where we overwrite the contents of the MAC control register is at the beginning of b43_chip_init(). All other places must do read() -> mask/set -> write() to not overwrite existing bits. This also adds a longer delay for waiting for the microcode to initialize itself. It seems that the current timeout is sufficient on all available devices, but there's no real reason why we shouldn't wait for up to one second. Slow embedded devices might exist. Better safe than sorry. While at it, fix naming of MACCTL values. This patch by Michael Buesch has been ported to b43legacy. Signed-off-by: Stefano Brivio <stefano.brivio@polimi.it> Acked-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wireless/b43legacy/phy.c')
-rw-r--r--drivers/net/wireless/b43legacy/phy.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/net/wireless/b43legacy/phy.c b/drivers/net/wireless/b43legacy/phy.c
index c16febbdbf5d..8e5c09b81871 100644
--- a/drivers/net/wireless/b43legacy/phy.c
+++ b/drivers/net/wireless/b43legacy/phy.c
@@ -140,7 +140,7 @@ void b43legacy_phy_calibrate(struct b43legacy_wldev *dev)
140{ 140{
141 struct b43legacy_phy *phy = &dev->phy; 141 struct b43legacy_phy *phy = &dev->phy;
142 142
143 b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD); /* Dummy read. */ 143 b43legacy_read32(dev, B43legacy_MMIO_MACCTL); /* Dummy read. */
144 if (phy->calibrated) 144 if (phy->calibrated)
145 return; 145 return;
146 if (phy->type == B43legacy_PHYTYPE_G && phy->rev == 1) { 146 if (phy->type == B43legacy_PHYTYPE_G && phy->rev == 1) {
@@ -2231,16 +2231,16 @@ bit26 = 1;
2231 * or the latest PS-Poll packet sent was successful, 2231 * or the latest PS-Poll packet sent was successful,
2232 * set bit26 */ 2232 * set bit26 */
2233 } 2233 }
2234 status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD); 2234 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2235 if (bit25) 2235 if (bit25)
2236 status |= B43legacy_SBF_PS1; 2236 status |= B43legacy_MACCTL_HWPS;
2237 else 2237 else
2238 status &= ~B43legacy_SBF_PS1; 2238 status &= ~B43legacy_MACCTL_HWPS;
2239 if (bit26) 2239 if (bit26)
2240 status |= B43legacy_SBF_PS2; 2240 status |= B43legacy_MACCTL_AWAKE;
2241 else 2241 else
2242 status &= ~B43legacy_SBF_PS2; 2242 status &= ~B43legacy_MACCTL_AWAKE;
2243 b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status); 2243 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
2244 if (bit26 && dev->dev->id.revision >= 5) { 2244 if (bit26 && dev->dev->id.revision >= 5) {
2245 for (i = 0; i < 100; i++) { 2245 for (i = 0; i < 100; i++) {
2246 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 2246 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED,