diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2011-09-21 15:44:13 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-09-27 14:34:01 -0400 |
commit | 7955d87f5ce94bb19554892b5dee963f276fd265 (patch) | |
tree | f38b4dfa9f79948769e0525f8c4d98a579d082bd /drivers/net/wireless/b43 | |
parent | b4c3f34afffcab01b6eb5155399a0b85b1123ada (diff) |
b43: add missing MMIO defines
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r-- | drivers/net/wireless/b43/b43.h | 40 | ||||
-rw-r--r-- | drivers/net/wireless/b43/main.c | 38 |
2 files changed, 60 insertions, 18 deletions
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h index f8615cdf1075..447a2307c9d9 100644 --- a/drivers/net/wireless/b43/b43.h +++ b/drivers/net/wireless/b43/b43.h | |||
@@ -107,6 +107,40 @@ | |||
107 | #define B43_MMIO_RADIO_HWENABLED_LO 0x49A | 107 | #define B43_MMIO_RADIO_HWENABLED_LO 0x49A |
108 | #define B43_MMIO_GPIO_CONTROL 0x49C | 108 | #define B43_MMIO_GPIO_CONTROL 0x49C |
109 | #define B43_MMIO_GPIO_MASK 0x49E | 109 | #define B43_MMIO_GPIO_MASK 0x49E |
110 | #define B43_MMIO_TXE0_CTL 0x500 | ||
111 | #define B43_MMIO_TXE0_AUX 0x502 | ||
112 | #define B43_MMIO_TXE0_TS_LOC 0x504 | ||
113 | #define B43_MMIO_TXE0_TIME_OUT 0x506 | ||
114 | #define B43_MMIO_TXE0_WM_0 0x508 | ||
115 | #define B43_MMIO_TXE0_WM_1 0x50A | ||
116 | #define B43_MMIO_TXE0_PHYCTL 0x50C | ||
117 | #define B43_MMIO_TXE0_STATUS 0x50E | ||
118 | #define B43_MMIO_TXE0_MMPLCP0 0x510 | ||
119 | #define B43_MMIO_TXE0_MMPLCP1 0x512 | ||
120 | #define B43_MMIO_TXE0_PHYCTL1 0x514 | ||
121 | #define B43_MMIO_XMTFIFODEF 0x520 | ||
122 | #define B43_MMIO_XMTFIFO_FRAME_CNT 0x522 /* core rev>= 16 only */ | ||
123 | #define B43_MMIO_XMTFIFO_BYTE_CNT 0x524 /* core rev>= 16 only */ | ||
124 | #define B43_MMIO_XMTFIFO_HEAD 0x526 /* core rev>= 16 only */ | ||
125 | #define B43_MMIO_XMTFIFO_RD_PTR 0x528 /* core rev>= 16 only */ | ||
126 | #define B43_MMIO_XMTFIFO_WR_PTR 0x52A /* core rev>= 16 only */ | ||
127 | #define B43_MMIO_XMTFIFODEF1 0x52C /* core rev>= 16 only */ | ||
128 | #define B43_MMIO_XMTFIFOCMD 0x540 | ||
129 | #define B43_MMIO_XMTFIFOFLUSH 0x542 | ||
130 | #define B43_MMIO_XMTFIFOTHRESH 0x544 | ||
131 | #define B43_MMIO_XMTFIFORDY 0x546 | ||
132 | #define B43_MMIO_XMTFIFOPRIRDY 0x548 | ||
133 | #define B43_MMIO_XMTFIFORQPRI 0x54A | ||
134 | #define B43_MMIO_XMTTPLATETXPTR 0x54C | ||
135 | #define B43_MMIO_XMTTPLATEPTR 0x550 | ||
136 | #define B43_MMIO_SMPL_CLCT_STRPTR 0x552 /* core rev>= 22 only */ | ||
137 | #define B43_MMIO_SMPL_CLCT_STPPTR 0x554 /* core rev>= 22 only */ | ||
138 | #define B43_MMIO_SMPL_CLCT_CURPTR 0x556 /* core rev>= 22 only */ | ||
139 | #define B43_MMIO_XMTTPLATEDATALO 0x560 | ||
140 | #define B43_MMIO_XMTTPLATEDATAHI 0x562 | ||
141 | #define B43_MMIO_XMTSEL 0x568 | ||
142 | #define B43_MMIO_XMTTXCNT 0x56A | ||
143 | #define B43_MMIO_XMTTXSHMADDR 0x56C | ||
110 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 | 144 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 |
111 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 | 145 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 |
112 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 | 146 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 |
@@ -118,12 +152,16 @@ | |||
118 | #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ | 152 | #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ |
119 | #define B43_MMIO_RNG 0x65A | 153 | #define B43_MMIO_RNG 0x65A |
120 | #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ | 154 | #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ |
121 | #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ | 155 | #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ |
156 | #define B43_MMIO_IFSSTAT 0x690 | ||
157 | #define B43_MMIO_IFSMEDBUSYCTL 0x692 | ||
158 | #define B43_MMIO_IFTXDUR 0x694 | ||
122 | #define B43_MMIO_IFSCTL_USE_EDCF 0x0004 | 159 | #define B43_MMIO_IFSCTL_USE_EDCF 0x0004 |
123 | #define B43_MMIO_POWERUP_DELAY 0x6A8 | 160 | #define B43_MMIO_POWERUP_DELAY 0x6A8 |
124 | #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */ | 161 | #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */ |
125 | #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */ | 162 | #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */ |
126 | #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */ | 163 | #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */ |
164 | #define B43_MMIO_WEPCTL 0x7C0 | ||
127 | 165 | ||
128 | /* SPROM boardflags_lo values */ | 166 | /* SPROM boardflags_lo values */ |
129 | #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ | 167 | #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ |
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c index 559bcd6688ec..fa27c3d97d8b 100644 --- a/drivers/net/wireless/b43/main.c +++ b/drivers/net/wireless/b43/main.c | |||
@@ -729,52 +729,56 @@ void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on) | |||
729 | for (i = 0; i < 5; i++) | 729 | for (i = 0; i < 5; i++) |
730 | b43_ram_write(dev, i * 4, buffer[i]); | 730 | b43_ram_write(dev, i * 4, buffer[i]); |
731 | 731 | ||
732 | b43_write16(dev, 0x0568, 0x0000); | 732 | b43_write16(dev, B43_MMIO_XMTSEL, 0x0000); |
733 | |||
733 | if (dev->dev->core_rev < 11) | 734 | if (dev->dev->core_rev < 11) |
734 | b43_write16(dev, 0x07C0, 0x0000); | 735 | b43_write16(dev, B43_MMIO_WEPCTL, 0x0000); |
735 | else | 736 | else |
736 | b43_write16(dev, 0x07C0, 0x0100); | 737 | b43_write16(dev, B43_MMIO_WEPCTL, 0x0100); |
738 | |||
737 | value = (ofdm ? 0x41 : 0x40); | 739 | value = (ofdm ? 0x41 : 0x40); |
738 | b43_write16(dev, 0x050C, value); | 740 | b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value); |
739 | if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) | 741 | if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP)) |
740 | b43_write16(dev, 0x0514, 0x1A02); | 742 | b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02); |
741 | b43_write16(dev, 0x0508, 0x0000); | 743 | |
742 | b43_write16(dev, 0x050A, 0x0000); | 744 | b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000); |
743 | b43_write16(dev, 0x054C, 0x0000); | 745 | b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000); |
744 | b43_write16(dev, 0x056A, 0x0014); | 746 | |
745 | b43_write16(dev, 0x0568, 0x0826); | 747 | b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000); |
746 | b43_write16(dev, 0x0500, 0x0000); | 748 | b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014); |
749 | b43_write16(dev, B43_MMIO_XMTSEL, 0x0826); | ||
750 | b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000); | ||
747 | if (!pa_on && (phy->type == B43_PHYTYPE_N)) { | 751 | if (!pa_on && (phy->type == B43_PHYTYPE_N)) { |
748 | //SPEC TODO | 752 | //SPEC TODO |
749 | } | 753 | } |
750 | 754 | ||
751 | switch (phy->type) { | 755 | switch (phy->type) { |
752 | case B43_PHYTYPE_N: | 756 | case B43_PHYTYPE_N: |
753 | b43_write16(dev, 0x0502, 0x00D0); | 757 | b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0); |
754 | break; | 758 | break; |
755 | case B43_PHYTYPE_LP: | 759 | case B43_PHYTYPE_LP: |
756 | b43_write16(dev, 0x0502, 0x0050); | 760 | b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050); |
757 | break; | 761 | break; |
758 | default: | 762 | default: |
759 | b43_write16(dev, 0x0502, 0x0030); | 763 | b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030); |
760 | } | 764 | } |
761 | 765 | ||
762 | if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) | 766 | if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) |
763 | b43_radio_write16(dev, 0x0051, 0x0017); | 767 | b43_radio_write16(dev, 0x0051, 0x0017); |
764 | for (i = 0x00; i < max_loop; i++) { | 768 | for (i = 0x00; i < max_loop; i++) { |
765 | value = b43_read16(dev, 0x050E); | 769 | value = b43_read16(dev, B43_MMIO_TXE0_STATUS); |
766 | if (value & 0x0080) | 770 | if (value & 0x0080) |
767 | break; | 771 | break; |
768 | udelay(10); | 772 | udelay(10); |
769 | } | 773 | } |
770 | for (i = 0x00; i < 0x0A; i++) { | 774 | for (i = 0x00; i < 0x0A; i++) { |
771 | value = b43_read16(dev, 0x050E); | 775 | value = b43_read16(dev, B43_MMIO_TXE0_STATUS); |
772 | if (value & 0x0400) | 776 | if (value & 0x0400) |
773 | break; | 777 | break; |
774 | udelay(10); | 778 | udelay(10); |
775 | } | 779 | } |
776 | for (i = 0x00; i < 0x19; i++) { | 780 | for (i = 0x00; i < 0x19; i++) { |
777 | value = b43_read16(dev, 0x0690); | 781 | value = b43_read16(dev, B43_MMIO_IFSSTAT); |
778 | if (!(value & 0x0100)) | 782 | if (!(value & 0x0100)) |
779 | break; | 783 | break; |
780 | udelay(10); | 784 | udelay(10); |