[B43]: add mac80211-based driver for modern BCM43xx devices

Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

25 files changed, 16688 insertions, 0 deletions

diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig
new file mode 100644
index 000000000000..4620119891f2
--- /dev/null
+++ b/drivers/net/wireless/b43/Kconfig
@@ -0,0 +1,119 @@
+config B43
+        tristate "Broadcom 43xx wireless support (mac80211 stack)"
+        depends on SSB_POSSIBLE && MAC80211 && WLAN_80211
+        select SSB
+        select FW_LOADER
+        select HW_RANDOM
+        ---help---
+          b43 is a driver for the Broadcom 43xx series wireless devices.
+
+          Check "lspci" for something like
+          "Broadcom Corporation BCM43XX 802.11 Wireless LAN Controller"
+          to determine whether you own such a device.
+
+          This driver supports the new BCM43xx IEEE 802.11G devices, but not
+          the old IEEE 802.11B devices. Old devices are supported by
+          the b43legacy driver.
+          Note that this has nothing to do with the standard that your AccessPoint
+          supports (A, B, G or a combination).
+          IEEE 802.11G devices can talk to IEEE 802.11B AccessPoints.
+
+          It is safe to include both b43 and b43legacy as the underlying glue
+          layer will automatically load the correct version for your device.
+
+          This driver uses V4 firmware, which must be installed separately using
+          b43-fwcutter.
+
+          This driver can be built as a module (recommended) that will be called "b43".
+          If unsure, say M.
+
+# Auto-select SSB PCI-HOST support, if possible
+config B43_PCI_AUTOSELECT
+        bool
+        depends on B43 && SSB_PCIHOST_POSSIBLE
+        select SSB_PCIHOST
+        default y
+
+# Auto-select SSB PCICORE driver, if possible
+config B43_PCICORE_AUTOSELECT
+        bool
+        depends on B43 && SSB_DRIVER_PCICORE_POSSIBLE
+        select SSB_DRIVER_PCICORE
+        default y
+
+config B43_PCMCIA
+        bool "Broadcom 43xx PCMCIA device support (EXPERIMENTAL)"
+        depends on B43 && SSB_PCMCIAHOST_POSSIBLE && EXPERIMENTAL
+        select SSB_PCMCIAHOST
+        ---help---
+          Broadcom 43xx PCMCIA device support.
+
+          Support for 16bit PCMCIA devices.
+          Please note that most PC-CARD devices are _NOT_ 16bit PCMCIA
+          devices, but 32bit CardBUS devices. CardBUS devices are supported
+          out of the box by b43.
+
+          With this config option you can drive b43 cards in
+          CompactFlash formfactor in a PCMCIA adaptor.
+          CF b43 cards can sometimes be found in handheld PCs.
+
+          It's safe to select Y here, even if you don't have a B43 PCMCIA device.
+
+          If unsure, say N.
+
+config B43_DEBUG
+        bool "Broadcom 43xx debugging"
+        depends on B43
+        ---help---
+          Broadcom 43xx debugging messages.
+
+          Say Y, if you want to find out why the driver does not
+          work for you.
+
+config B43_DMA
+        bool
+        depends on B43
+config B43_PIO
+        bool
+        depends on B43
+
+choice
+        prompt "Broadcom 43xx data transfer mode"
+        depends on B43
+        default B43_DMA_AND_PIO_MODE
+
+config B43_DMA_AND_PIO_MODE
+        bool "DMA + PIO"
+        select B43_DMA
+        select B43_PIO
+        ---help---
+          Include both, Direct Memory Access (DMA) and Programmed I/O (PIO)
+          data transfer modes.
+          The actually used mode is selectable through the module
+          parameter "pio". If the module parameter is pio=0, DMA is used.
+          Otherwise PIO is used. DMA is default.
+
+          If unsure, choose this option.
+
+config B43_DMA_MODE
+        bool "DMA (Direct Memory Access) only"
+        select B43_DMA
+        ---help---
+          Only include Direct Memory Access (DMA).
+          This reduces the size of the driver module, by omitting the PIO code.
+
+config B43_PIO_MODE
+        bool "PIO (Programmed I/O) only"
+        select B43_PIO
+        ---help---
+          Only include Programmed I/O (PIO).
+          This reduces the size of the driver module, by omitting the DMA code.
+          Please note that PIO transfers are slow (compared to DMA).
+
+          Also note that not all devices of the 43xx series support PIO.
+          The 4306 (Apple Airport Extreme and others) supports PIO, while
+          the 4318 is known to _not_ support PIO.
+
+          Only use PIO, if DMA does not work for you.
+
+endchoice
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
new file mode 100644
index 000000000000..370935b84c5e
--- /dev/null
+++ b/drivers/net/wireless/b43/Makefile
@@ -0,0 +1,17 @@
+# b43 core
+b43-y                           += main.o
+b43-y                           += tables.o
+b43-y                           += phy.o
+b43-y                           += sysfs.o
+b43-y                           += leds.o
+b43-y                           += xmit.o
+b43-y                           += lo.o
+# b43 PCMCIA support
+b43-$(CONFIG_B43_PCMCIA)        += pcmcia.o
+# b43 debugging
+b43-$(CONFIG_B43_DEBUG)         += debugfs.o
+# b43 DMA and PIO
+b43-$(CONFIG_B43_DMA)           += dma.o
+b43-$(CONFIG_B43_PIO)           += pio.o
+
+obj-$(CONFIG_B43)               += b43.o
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
new file mode 100644
index 000000000000..270a2112de2a
--- /dev/null
+++ b/drivers/net/wireless/b43/b43.h
@@ -0,0 +1,845 @@
+#ifndef B43_H_
+#define B43_H_
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/hw_random.h>
+#include <linux/ssb/ssb.h>
+#include <net/mac80211.h>
+
+#include "debugfs.h"
+#include "leds.h"
+#include "lo.h"
+#include "phy.h"
+
+#ifdef CONFIG_B43_DEBUG
+# define B43_DEBUG      1
+#else
+# define B43_DEBUG      0
+#endif
+
+#define B43_RX_MAX_SSI                  60
+
+/* MMIO offsets */
+#define B43_MMIO_DMA0_REASON            0x20
+#define B43_MMIO_DMA0_IRQ_MASK          0x24
+#define B43_MMIO_DMA1_REASON            0x28
+#define B43_MMIO_DMA1_IRQ_MASK          0x2C
+#define B43_MMIO_DMA2_REASON            0x30
+#define B43_MMIO_DMA2_IRQ_MASK          0x34
+#define B43_MMIO_DMA3_REASON            0x38
+#define B43_MMIO_DMA3_IRQ_MASK          0x3C
+#define B43_MMIO_DMA4_REASON            0x40
+#define B43_MMIO_DMA4_IRQ_MASK          0x44
+#define B43_MMIO_DMA5_REASON            0x48
+#define B43_MMIO_DMA5_IRQ_MASK          0x4C
+#define B43_MMIO_MACCTL                 0x120
+#define B43_MMIO_STATUS2_BITFIELD       0x124
+#define B43_MMIO_GEN_IRQ_REASON         0x128
+#define B43_MMIO_GEN_IRQ_MASK           0x12C
+#define B43_MMIO_RAM_CONTROL            0x130
+#define B43_MMIO_RAM_DATA               0x134
+#define B43_MMIO_PS_STATUS              0x140
+#define B43_MMIO_RADIO_HWENABLED_HI     0x158
+#define B43_MMIO_SHM_CONTROL            0x160
+#define B43_MMIO_SHM_DATA               0x164
+#define B43_MMIO_SHM_DATA_UNALIGNED     0x166
+#define B43_MMIO_XMITSTAT_0             0x170
+#define B43_MMIO_XMITSTAT_1             0x174
+#define B43_MMIO_REV3PLUS_TSF_LOW       0x180   /* core rev >= 3 only */
+#define B43_MMIO_REV3PLUS_TSF_HIGH      0x184   /* core rev >= 3 only */
+
+/* 32-bit DMA */
+#define B43_MMIO_DMA32_BASE0            0x200
+#define B43_MMIO_DMA32_BASE1            0x220
+#define B43_MMIO_DMA32_BASE2            0x240
+#define B43_MMIO_DMA32_BASE3            0x260
+#define B43_MMIO_DMA32_BASE4            0x280
+#define B43_MMIO_DMA32_BASE5            0x2A0
+/* 64-bit DMA */
+#define B43_MMIO_DMA64_BASE0            0x200
+#define B43_MMIO_DMA64_BASE1            0x240
+#define B43_MMIO_DMA64_BASE2            0x280
+#define B43_MMIO_DMA64_BASE3            0x2C0
+#define B43_MMIO_DMA64_BASE4            0x300
+#define B43_MMIO_DMA64_BASE5            0x340
+/* PIO */
+#define B43_MMIO_PIO1_BASE              0x300
+#define B43_MMIO_PIO2_BASE              0x310
+#define B43_MMIO_PIO3_BASE              0x320
+#define B43_MMIO_PIO4_BASE              0x330
+
+#define B43_MMIO_PHY_VER                0x3E0
+#define B43_MMIO_PHY_RADIO              0x3E2
+#define B43_MMIO_PHY0                   0x3E6
+#define B43_MMIO_ANTENNA                0x3E8
+#define B43_MMIO_CHANNEL                0x3F0
+#define B43_MMIO_CHANNEL_EXT            0x3F4
+#define B43_MMIO_RADIO_CONTROL          0x3F6
+#define B43_MMIO_RADIO_DATA_HIGH        0x3F8
+#define B43_MMIO_RADIO_DATA_LOW         0x3FA
+#define B43_MMIO_PHY_CONTROL            0x3FC
+#define B43_MMIO_PHY_DATA               0x3FE
+#define B43_MMIO_MACFILTER_CONTROL      0x420
+#define B43_MMIO_MACFILTER_DATA         0x422
+#define B43_MMIO_RCMTA_COUNT            0x43C
+#define B43_MMIO_RADIO_HWENABLED_LO     0x49A
+#define B43_MMIO_GPIO_CONTROL           0x49C
+#define B43_MMIO_GPIO_MASK              0x49E
+#define B43_MMIO_TSF_0                  0x632   /* core rev < 3 only */
+#define B43_MMIO_TSF_1                  0x634   /* core rev < 3 only */
+#define B43_MMIO_TSF_2                  0x636   /* core rev < 3 only */
+#define B43_MMIO_TSF_3                  0x638   /* core rev < 3 only */
+#define B43_MMIO_RNG                    0x65A
+#define B43_MMIO_POWERUP_DELAY          0x6A8
+
+/* SPROM boardflags_lo values */
+#define B43_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
+#define B43_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */
+#define B43_BFL_AIRLINEMODE             0x0004  /* implements GPIO 13 radio disable indication */
+#define B43_BFL_RSSI                    0x0008  /* software calculates nrssi slope. */
+#define B43_BFL_ENETSPI                 0x0010  /* has ephy roboswitch spi */
+#define B43_BFL_XTAL_NOSLOW             0x0020  /* no slow clock available */
+#define B43_BFL_CCKHIPWR                0x0040  /* can do high power CCK transmission */
+#define B43_BFL_ENETADM                 0x0080  /* has ADMtek switch */
+#define B43_BFL_ENETVLAN                0x0100  /* can do vlan */
+#define B43_BFL_AFTERBURNER             0x0200  /* supports Afterburner mode */
+#define B43_BFL_NOPCI                   0x0400  /* leaves PCI floating */
+#define B43_BFL_FEM                     0x0800  /* supports the Front End Module */
+#define B43_BFL_EXTLNA                  0x1000  /* has an external LNA */
+#define B43_BFL_HGPA                    0x2000  /* had high gain PA */
+#define B43_BFL_BTCMOD                  0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
+#define B43_BFL_ALTIQ                   0x8000  /* alternate I/Q settings */
+
+/* GPIO register offset, in both ChipCommon and PCI core. */
+#define B43_GPIO_CONTROL                0x6c
+
+/* SHM Routing */
+enum {
+        B43_SHM_UCODE,          /* Microcode memory */
+        B43_SHM_SHARED,         /* Shared memory */
+        B43_SHM_SCRATCH,        /* Scratch memory */
+        B43_SHM_HW,             /* Internal hardware register */
+        B43_SHM_RCMTA,          /* Receive match transmitter address (rev >= 5 only) */
+};
+/* SHM Routing modifiers */
+#define B43_SHM_AUTOINC_R               0x0200  /* Auto-increment address on read */
+#define B43_SHM_AUTOINC_W               0x0100  /* Auto-increment address on write */
+#define B43_SHM_AUTOINC_RW              (B43_SHM_AUTOINC_R | \
+                                         B43_SHM_AUTOINC_W)
+
+/* Misc SHM_SHARED offsets */
+#define B43_SHM_SH_WLCOREREV            0x0016  /* 802.11 core revision */
+#define B43_SHM_SH_PCTLWDPOS            0x0008
+#define B43_SHM_SH_RXPADOFF             0x0034  /* RX Padding data offset (PIO only) */
+#define B43_SHM_SH_PHYVER               0x0050  /* PHY version */
+#define B43_SHM_SH_PHYTYPE              0x0052  /* PHY type */
+#define B43_SHM_SH_ANTSWAP              0x005C  /* Antenna swap threshold */
+#define B43_SHM_SH_HOSTFLO              0x005E  /* Hostflags for ucode options (low) */
+#define B43_SHM_SH_HOSTFHI              0x0060  /* Hostflags for ucode options (high) */
+#define B43_SHM_SH_RFATT                0x0064  /* Current radio attenuation value */
+#define B43_SHM_SH_RADAR                0x0066  /* Radar register */
+#define B43_SHM_SH_PHYTXNOI             0x006E  /* PHY noise directly after TX (lower 8bit only) */
+#define B43_SHM_SH_RFRXSP1              0x0072  /* RF RX SP Register 1 */
+#define B43_SHM_SH_CHAN                 0x00A0  /* Current channel (low 8bit only) */
+#define  B43_SHM_SH_CHAN_5GHZ           0x0100  /* Bit set, if 5Ghz channel */
+#define B43_SHM_SH_BCMCFIFOID           0x0108  /* Last posted cookie to the bcast/mcast FIFO */
+/* SHM_SHARED TX FIFO variables */
+#define B43_SHM_SH_SIZE01               0x0098  /* TX FIFO size for FIFO 0 (low) and 1 (high) */
+#define B43_SHM_SH_SIZE23               0x009A  /* TX FIFO size for FIFO 2 and 3 */
+#define B43_SHM_SH_SIZE45               0x009C  /* TX FIFO size for FIFO 4 and 5 */
+#define B43_SHM_SH_SIZE67               0x009E  /* TX FIFO size for FIFO 6 and 7 */
+/* SHM_SHARED background noise */
+#define B43_SHM_SH_JSSI0                0x0088  /* Measure JSSI 0 */
+#define B43_SHM_SH_JSSI1                0x008A  /* Measure JSSI 1 */
+#define B43_SHM_SH_JSSIAUX              0x008C  /* Measure JSSI AUX */
+/* SHM_SHARED crypto engine */
+#define B43_SHM_SH_DEFAULTIV            0x003C  /* Default IV location */
+#define B43_SHM_SH_NRRXTRANS            0x003E  /* # of soft RX transmitter addresses (max 8) */
+#define B43_SHM_SH_KTP                  0x0056  /* Key table pointer */
+#define B43_SHM_SH_TKIPTSCTTAK          0x0318
+#define B43_SHM_SH_KEYIDXBLOCK          0x05D4  /* Key index/algorithm block (v4 firmware) */
+#define B43_SHM_SH_PSM                  0x05F4  /* PSM transmitter address match block (rev < 5) */
+/* SHM_SHARED WME variables */
+#define B43_SHM_SH_EDCFSTAT             0x000E  /* EDCF status */
+#define B43_SHM_SH_TXFCUR               0x0030  /* TXF current index */
+#define B43_SHM_SH_EDCFQ                0x0240  /* EDCF Q info */
+/* SHM_SHARED powersave mode related */
+#define B43_SHM_SH_SLOTT                0x0010  /* Slot time */
+#define B43_SHM_SH_DTIMPER              0x0012  /* DTIM period */
+#define B43_SHM_SH_NOSLPZNATDTIM        0x004C  /* NOSLPZNAT DTIM */
+/* SHM_SHARED beacon variables */
+#define B43_SHM_SH_BTL0                 0x0018  /* Beacon template length 0 */
+#define B43_SHM_SH_BTL1                 0x001A  /* Beacon template length 1 */
+#define B43_SHM_SH_BTSFOFF              0x001C  /* Beacon TSF offset */
+#define B43_SHM_SH_TIMBPOS              0x001E  /* TIM B position in beacon */
+#define B43_SHM_SH_SFFBLIM              0x0044  /* Short frame fallback retry limit */
+#define B43_SHM_SH_LFFBLIM              0x0046  /* Long frame fallback retry limit */
+#define B43_SHM_SH_BEACPHYCTL           0x0054  /* Beacon PHY TX control word (see PHY TX control) */
+/* SHM_SHARED ACK/CTS control */
+#define B43_SHM_SH_ACKCTSPHYCTL         0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
+/* SHM_SHARED probe response variables */
+#define B43_SHM_SH_PRSSID               0x0160  /* Probe Response SSID */
+#define B43_SHM_SH_PRSSIDLEN            0x0048  /* Probe Response SSID length */
+#define B43_SHM_SH_PRTLEN               0x004A  /* Probe Response template length */
+#define B43_SHM_SH_PRMAXTIME            0x0074  /* Probe Response max time */
+#define B43_SHM_SH_PRPHYCTL             0x0188  /* Probe Response PHY TX control word */
+/* SHM_SHARED rate tables */
+#define B43_SHM_SH_OFDMDIRECT           0x01C0  /* Pointer to OFDM direct map */
+#define B43_SHM_SH_OFDMBASIC            0x01E0  /* Pointer to OFDM basic rate map */
+#define B43_SHM_SH_CCKDIRECT            0x0200  /* Pointer to CCK direct map */
+#define B43_SHM_SH_CCKBASIC             0x0220  /* Pointer to CCK basic rate map */
+/* SHM_SHARED microcode soft registers */
+#define B43_SHM_SH_UCODEREV             0x0000  /* Microcode revision */
+#define B43_SHM_SH_UCODEPATCH           0x0002  /* Microcode patchlevel */
+#define B43_SHM_SH_UCODEDATE            0x0004  /* Microcode date */
+#define B43_SHM_SH_UCODETIME            0x0006  /* Microcode time */
+#define B43_SHM_SH_UCODESTAT            0x0040  /* Microcode debug status code */
+#define  B43_SHM_SH_UCODESTAT_INVALID   0
+#define  B43_SHM_SH_UCODESTAT_INIT      1
+#define  B43_SHM_SH_UCODESTAT_ACTIVE    2
+#define  B43_SHM_SH_UCODESTAT_SUSP      3       /* suspended */
+#define  B43_SHM_SH_UCODESTAT_SLEEP     4       /* asleep (PS) */
+#define B43_SHM_SH_MAXBFRAMES           0x0080  /* Maximum number of frames in a burst */
+#define B43_SHM_SH_SPUWKUP              0x0094  /* pre-wakeup for synth PU in us */
+#define B43_SHM_SH_PRETBTT              0x0096  /* pre-TBTT in us */
+
+/* SHM_SCRATCH offsets */
+#define B43_SHM_SC_MINCONT              0x0003  /* Minimum contention window */
+#define B43_SHM_SC_MAXCONT              0x0004  /* Maximum contention window */
+#define B43_SHM_SC_CURCONT              0x0005  /* Current contention window */
+#define B43_SHM_SC_SRLIMIT              0x0006  /* Short retry count limit */
+#define B43_SHM_SC_LRLIMIT              0x0007  /* Long retry count limit */
+#define B43_SHM_SC_DTIMC                0x0008  /* Current DTIM count */
+#define B43_SHM_SC_BTL0LEN              0x0015  /* Beacon 0 template length */
+#define B43_SHM_SC_BTL1LEN              0x0016  /* Beacon 1 template length */
+#define B43_SHM_SC_SCFB                 0x0017  /* Short frame transmit count threshold for rate fallback */
+#define B43_SHM_SC_LCFB                 0x0018  /* Long frame transmit count threshold for rate fallback */
+
+/* Hardware Radio Enable masks */
+#define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
+#define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
+
+/* HostFlags. See b43_hf_read/write() */
+#define B43_HF_ANTDIVHELP               0x00000001      /* ucode antenna div helper */
+#define B43_HF_SYMW                     0x00000002      /* G-PHY SYM workaround */
+#define B43_HF_RXPULLW                  0x00000004      /* RX pullup workaround */
+#define B43_HF_CCKBOOST                 0x00000008      /* 4dB CCK power boost (exclusive with OFDM boost) */
+#define B43_HF_BTCOEX                   0x00000010      /* Bluetooth coexistance */
+#define B43_HF_GDCW                     0x00000020      /* G-PHY DV canceller filter bw workaround */
+#define B43_HF_OFDMPABOOST              0x00000040      /* Enable PA gain boost for OFDM */
+#define B43_HF_ACPR                     0x00000080      /* Disable for Japan, channel 14 */
+#define B43_HF_EDCF                     0x00000100      /* on if WME and MAC suspended */
+#define B43_HF_TSSIRPSMW                0x00000200      /* TSSI reset PSM ucode workaround */
+#define B43_HF_DSCRQ                    0x00000400      /* Disable slow clock request in ucode */
+#define B43_HF_ACIW                     0x00000800      /* ACI workaround: shift bits by 2 on PHY CRS */
+#define B43_HF_2060W                    0x00001000      /* 2060 radio workaround */
+#define B43_HF_RADARW                   0x00002000      /* Radar workaround */
+#define B43_HF_USEDEFKEYS               0x00004000      /* Enable use of default keys */
+#define B43_HF_BT4PRIOCOEX              0x00010000      /* Bluetooth 2-priority coexistance */
+#define B43_HF_FWKUP                    0x00020000      /* Fast wake-up ucode */
+#define B43_HF_VCORECALC                0x00040000      /* Force VCO recalculation when powering up synthpu */
+#define B43_HF_PCISCW                   0x00080000      /* PCI slow clock workaround */
+#define B43_HF_4318TSSI                 0x00200000      /* 4318 TSSI */
+#define B43_HF_FBCMCFIFO                0x00400000      /* Flush bcast/mcast FIFO immediately */
+#define B43_HF_HWPCTL                   0x00800000      /* Enable hardwarre power control */
+#define B43_HF_BTCOEXALT                0x01000000      /* Bluetooth coexistance in alternate pins */
+#define B43_HF_TXBTCHECK                0x02000000      /* Bluetooth check during transmission */
+#define B43_HF_SKCFPUP                  0x04000000      /* Skip CFP update */
+
+/* MacFilter offsets. */
+#define B43_MACFILTER_SELF              0x0000
+#define B43_MACFILTER_BSSID             0x0003
+
+/* PowerControl */
+#define B43_PCTL_IN                     0xB0
+#define B43_PCTL_OUT                    0xB4
+#define B43_PCTL_OUTENABLE              0xB8
+#define B43_PCTL_XTAL_POWERUP           0x40
+#define B43_PCTL_PLL_POWERDOWN          0x80
+
+/* PowerControl Clock Modes */
+#define B43_PCTL_CLK_FAST               0x00
+#define B43_PCTL_CLK_SLOW               0x01
+#define B43_PCTL_CLK_DYNAMIC            0x02
+
+#define B43_PCTL_FORCE_SLOW             0x0800
+#define B43_PCTL_FORCE_PLL              0x1000
+#define B43_PCTL_DYN_XTAL               0x2000
+
+/* PHYVersioning */
+#define B43_PHYTYPE_A                   0x00
+#define B43_PHYTYPE_B                   0x01
+#define B43_PHYTYPE_G                   0x02
+
+/* PHYRegisters */
+#define B43_PHY_ILT_A_CTRL              0x0072
+#define B43_PHY_ILT_A_DATA1             0x0073
+#define B43_PHY_ILT_A_DATA2             0x0074
+#define B43_PHY_G_LO_CONTROL            0x0810
+#define B43_PHY_ILT_G_CTRL              0x0472
+#define B43_PHY_ILT_G_DATA1             0x0473
+#define B43_PHY_ILT_G_DATA2             0x0474
+#define B43_PHY_A_PCTL                  0x007B
+#define B43_PHY_G_PCTL                  0x0029
+#define B43_PHY_A_CRS                   0x0029
+#define B43_PHY_RADIO_BITFIELD          0x0401
+#define B43_PHY_G_CRS                   0x0429
+#define B43_PHY_NRSSILT_CTRL            0x0803
+#define B43_PHY_NRSSILT_DATA            0x0804
+
+/* RadioRegisters */
+#define B43_RADIOCTL_ID                 0x01
+
+/* MAC Control bitfield */
+#define B43_MACCTL_ENABLED              0x00000001      /* MAC Enabled */
+#define B43_MACCTL_PSM_RUN              0x00000002      /* Run Microcode */
+#define B43_MACCTL_PSM_JMP0             0x00000004      /* Microcode jump to 0 */
+#define B43_MACCTL_SHM_ENABLED          0x00000100      /* SHM Enabled */
+#define B43_MACCTL_SHM_UPPER            0x00000200      /* SHM Upper */
+#define B43_MACCTL_IHR_ENABLED          0x00000400      /* IHR Region Enabled */
+#define B43_MACCTL_PSM_DBG              0x00002000      /* Microcode debugging enabled */
+#define B43_MACCTL_GPOUTSMSK            0x0000C000      /* GPOUT Select Mask */
+#define B43_MACCTL_BE                   0x00010000      /* Big Endian mode */
+#define B43_MACCTL_INFRA                0x00020000      /* Infrastructure mode */
+#define B43_MACCTL_AP                   0x00040000      /* AccessPoint mode */
+#define B43_MACCTL_RADIOLOCK            0x00080000      /* Radio lock */
+#define B43_MACCTL_BEACPROMISC          0x00100000      /* Beacon Promiscuous */
+#define B43_MACCTL_KEEP_BADPLCP         0x00200000      /* Keep frames with bad PLCP */
+#define B43_MACCTL_KEEP_CTL             0x00400000      /* Keep control frames */
+#define B43_MACCTL_KEEP_BAD             0x00800000      /* Keep bad frames (FCS) */
+#define B43_MACCTL_PROMISC              0x01000000      /* Promiscuous mode */
+#define B43_MACCTL_HWPS                 0x02000000      /* Hardware Power Saving */
+#define B43_MACCTL_AWAKE                0x04000000      /* Device is awake */
+#define B43_MACCTL_CLOSEDNET            0x08000000      /* Closed net (no SSID bcast) */
+#define B43_MACCTL_TBTTHOLD             0x10000000      /* TBTT Hold */
+#define B43_MACCTL_DISCTXSTAT           0x20000000      /* Discard TX status */
+#define B43_MACCTL_DISCPMQ              0x40000000      /* Discard Power Management Queue */
+#define B43_MACCTL_GMODE                0x80000000      /* G Mode */
+
+/* 802.11 core specific TM State Low flags */
+#define B43_TMSLOW_GMODE                0x20000000      /* G Mode Enable */
+#define B43_TMSLOW_PLLREFSEL            0x00200000      /* PLL Frequency Reference Select */
+#define B43_TMSLOW_MACPHYCLKEN          0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
+#define B43_TMSLOW_PHYRESET             0x00080000      /* PHY Reset */
+#define B43_TMSLOW_PHYCLKEN             0x00040000      /* PHY Clock Enable */
+
+/* 802.11 core specific TM State High flags */
+#define B43_TMSHIGH_FCLOCK              0x00040000      /* Fast Clock Available (rev >= 5) */
+#define B43_TMSHIGH_APHY                0x00020000      /* A-PHY available (rev >= 5) */
+#define B43_TMSHIGH_GPHY                0x00010000      /* G-PHY available (rev >= 5) */
+
+/* Generic-Interrupt reasons. */
+#define B43_IRQ_MAC_SUSPENDED           0x00000001
+#define B43_IRQ_BEACON                  0x00000002
+#define B43_IRQ_TBTT_INDI               0x00000004
+#define B43_IRQ_BEACON_TX_OK            0x00000008
+#define B43_IRQ_BEACON_CANCEL           0x00000010
+#define B43_IRQ_ATIM_END                0x00000020
+#define B43_IRQ_PMQ                     0x00000040
+#define B43_IRQ_PIO_WORKAROUND          0x00000100
+#define B43_IRQ_MAC_TXERR               0x00000200
+#define B43_IRQ_PHY_TXERR               0x00000800
+#define B43_IRQ_PMEVENT                 0x00001000
+#define B43_IRQ_TIMER0                  0x00002000
+#define B43_IRQ_TIMER1                  0x00004000
+#define B43_IRQ_DMA                     0x00008000
+#define B43_IRQ_TXFIFO_FLUSH_OK         0x00010000
+#define B43_IRQ_CCA_MEASURE_OK          0x00020000
+#define B43_IRQ_NOISESAMPLE_OK          0x00040000
+#define B43_IRQ_UCODE_DEBUG             0x08000000
+#define B43_IRQ_RFKILL                  0x10000000
+#define B43_IRQ_TX_OK                   0x20000000
+#define B43_IRQ_PHY_G_CHANGED           0x40000000
+#define B43_IRQ_TIMEOUT                 0x80000000
+
+#define B43_IRQ_ALL                     0xFFFFFFFF
+#define B43_IRQ_MASKTEMPLATE            (B43_IRQ_MAC_SUSPENDED | \
+                                         B43_IRQ_BEACON | \
+                                         B43_IRQ_TBTT_INDI | \
+                                         B43_IRQ_ATIM_END | \
+                                         B43_IRQ_PMQ | \
+                                         B43_IRQ_MAC_TXERR | \
+                                         B43_IRQ_PHY_TXERR | \
+                                         B43_IRQ_DMA | \
+                                         B43_IRQ_TXFIFO_FLUSH_OK | \
+                                         B43_IRQ_NOISESAMPLE_OK | \
+                                         B43_IRQ_UCODE_DEBUG | \
+                                         B43_IRQ_RFKILL | \
+                                         B43_IRQ_TX_OK)
+
+/* Device specific rate values.
+ * The actual values defined here are (rate_in_mbps * 2).
+ * Some code depends on this. Don't change it. */
+#define B43_CCK_RATE_1MB                0x02
+#define B43_CCK_RATE_2MB                0x04
+#define B43_CCK_RATE_5MB                0x0B
+#define B43_CCK_RATE_11MB               0x16
+#define B43_OFDM_RATE_6MB               0x0C
+#define B43_OFDM_RATE_9MB               0x12
+#define B43_OFDM_RATE_12MB              0x18
+#define B43_OFDM_RATE_18MB              0x24
+#define B43_OFDM_RATE_24MB              0x30
+#define B43_OFDM_RATE_36MB              0x48
+#define B43_OFDM_RATE_48MB              0x60
+#define B43_OFDM_RATE_54MB              0x6C
+/* Convert a b43 rate value to a rate in 100kbps */
+#define B43_RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
+
+#define B43_DEFAULT_SHORT_RETRY_LIMIT   7
+#define B43_DEFAULT_LONG_RETRY_LIMIT    4
+
+/* Max size of a security key */
+#define B43_SEC_KEYSIZE                 16
+/* Security algorithms. */
+enum {
+        B43_SEC_ALGO_NONE = 0,  /* unencrypted, as of TX header. */
+        B43_SEC_ALGO_WEP40,
+        B43_SEC_ALGO_TKIP,
+        B43_SEC_ALGO_AES,
+        B43_SEC_ALGO_WEP104,
+        B43_SEC_ALGO_AES_LEGACY,
+};
+
+struct b43_dmaring;
+struct b43_pioqueue;
+
+/* The firmware file header */
+#define B43_FW_TYPE_UCODE       'u'
+#define B43_FW_TYPE_PCM         'p'
+#define B43_FW_TYPE_IV          'i'
+struct b43_fw_header {
+        /* File type */
+        u8 type;
+        /* File format version */
+        u8 ver;
+        u8 __padding[2];
+        /* Size of the data. For ucode and PCM this is in bytes.
+         * For IV this is number-of-ivs. */
+        __be32 size;
+} __attribute__((__packed__));
+
+/* Initial Value file format */
+#define B43_IV_OFFSET_MASK      0x7FFF
+#define B43_IV_32BIT            0x8000
+struct b43_iv {
+        __be16 offset_size;
+        union {
+                __be16 d16;
+                __be32 d32;
+        } data __attribute__((__packed__));
+} __attribute__((__packed__));
+
+
+#define B43_PHYMODE(phytype)            (1 << (phytype))
+#define B43_PHYMODE_A                   B43_PHYMODE(B43_PHYTYPE_A)
+#define B43_PHYMODE_B                   B43_PHYMODE(B43_PHYTYPE_B)
+#define B43_PHYMODE_G                   B43_PHYMODE(B43_PHYTYPE_G)
+
+struct b43_phy {
+        /* Possible PHYMODEs on this PHY */
+        u8 possible_phymodes;
+        /* GMODE bit enabled? */
+        bool gmode;
+        /* Possible ieee80211 subsystem hwmodes for this PHY.
+         * Which mode is selected, depends on thr GMODE enabled bit */
+#define B43_MAX_PHYHWMODES      2
+        struct ieee80211_hw_mode hwmodes[B43_MAX_PHYHWMODES];
+
+        /* Analog Type */
+        u8 analog;
+        /* B43_PHYTYPE_ */
+        u8 type;
+        /* PHY revision number. */
+        u8 rev;
+
+        /* Radio versioning */
+        u16 radio_manuf;        /* Radio manufacturer */
+        u16 radio_ver;          /* Radio version */
+        u8 radio_rev;           /* Radio revision */
+
+        bool radio_on;          /* Radio switched on/off */
+        bool locked;            /* Only used in b43_phy_{un}lock() */
+        bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
+
+        /* ACI (adjacent channel interference) flags. */
+        bool aci_enable;
+        bool aci_wlan_automatic;
+        bool aci_hw_rssi;
+
+        u16 minlowsig[2];
+        u16 minlowsigpos[2];
+
+        /* TSSI to dBm table in use */
+        const s8 *tssi2dbm;
+        /* Target idle TSSI */
+        int tgt_idle_tssi;
+        /* Current idle TSSI */
+        int cur_idle_tssi;
+
+        /* LocalOscillator control values. */
+        struct b43_txpower_lo_control *lo_control;
+        /* Values from b43_calc_loopback_gain() */
+        s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
+        s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
+        s16 lna_lod_gain;       /* LNA lod */
+        s16 lna_gain;           /* LNA */
+        s16 pga_gain;           /* PGA */
+
+        /* PHY lock for core.rev < 3
+         * This lock is only used by b43_phy_{un}lock()
+         */
+        spinlock_t lock;
+
+        /* Desired TX power level (in dBm).
+         * This is set by the user and adjusted in b43_phy_xmitpower(). */
+        u8 power_level;
+        /* A-PHY TX Power control value. */
+        u16 txpwr_offset;
+
+        /* Current TX power level attenuation control values */
+        struct b43_bbatt bbatt;
+        struct b43_rfatt rfatt;
+        u8 tx_control;          /* B43_TXCTL_XXX */
+#ifdef CONFIG_B43_DEBUG
+        bool manual_txpower_control;    /* Manual TX-power control enabled? */
+#endif
+        /* Hardware Power Control enabled? */
+        bool hardware_power_control;
+
+        /* Current Interference Mitigation mode */
+        int interfmode;
+        /* Stack of saved values from the Interference Mitigation code.
+         * Each value in the stack is layed out as follows:
+         * bit 0-11:  offset
+         * bit 12-15: register ID
+         * bit 16-32: value
+         * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
+         */
+#define B43_INTERFSTACK_SIZE    26
+        u32 interfstack[B43_INTERFSTACK_SIZE];  //FIXME: use a data structure
+
+        /* Saved values from the NRSSI Slope calculation */
+        s16 nrssi[2];
+        s32 nrssislope;
+        /* In memory nrssi lookup table. */
+        s8 nrssi_lt[64];
+
+        /* current channel */
+        u8 channel;
+
+        u16 lofcal;
+
+        u16 initval;            //FIXME rename?
+};
+
+/* Data structures for DMA transmission, per 80211 core. */
+struct b43_dma {
+        struct b43_dmaring *tx_ring0;
+        struct b43_dmaring *tx_ring1;
+        struct b43_dmaring *tx_ring2;
+        struct b43_dmaring *tx_ring3;
+        struct b43_dmaring *tx_ring4;
+        struct b43_dmaring *tx_ring5;
+
+        struct b43_dmaring *rx_ring0;
+        struct b43_dmaring *rx_ring3;   /* only available on core.rev < 5 */
+};
+
+/* Data structures for PIO transmission, per 80211 core. */
+struct b43_pio {
+        struct b43_pioqueue *queue0;
+        struct b43_pioqueue *queue1;
+        struct b43_pioqueue *queue2;
+        struct b43_pioqueue *queue3;
+};
+
+/* Context information for a noise calculation (Link Quality). */
+struct b43_noise_calculation {
+        u8 channel_at_start;
+        bool calculation_running;
+        u8 nr_samples;
+        s8 samples[8][4];
+};
+
+struct b43_stats {
+        u8 link_noise;
+        /* Store the last TX/RX times here for updating the leds. */
+        unsigned long last_tx;
+        unsigned long last_rx;
+};
+
+struct b43_key {
+        /* If keyconf is NULL, this key is disabled.
+         * keyconf is a cookie. Don't derefenrence it outside of the set_key
+         * path, because b43 doesn't own it. */
+        struct ieee80211_key_conf *keyconf;
+        u8 algorithm;
+};
+
+struct b43_wldev;
+
+/* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
+struct b43_wl {
+        /* Pointer to the active wireless device on this chip */
+        struct b43_wldev *current_dev;
+        /* Pointer to the ieee80211 hardware data structure */
+        struct ieee80211_hw *hw;
+
+        spinlock_t irq_lock;
+        struct mutex mutex;
+        spinlock_t leds_lock;
+
+        /* We can only have one operating interface (802.11 core)
+         * at a time. General information about this interface follows.
+         */
+
+        /* Opaque ID of the operating interface (!= monitor
+         * interface) from the ieee80211 subsystem.
+         * Do not modify.
+         */
+        int if_id;
+        /* The MAC address of the operating interface. */
+        u8 mac_addr[ETH_ALEN];
+        /* Current BSSID */
+        u8 bssid[ETH_ALEN];
+        /* Interface type. (IEEE80211_IF_TYPE_XXX) */
+        int if_type;
+        /* Counter of active monitor interfaces. */
+        int monitor;
+        /* Is the card operating in AP, STA or IBSS mode? */
+        bool operating;
+        /* Promisc mode active?
+         * Note that (monitor != 0) implies promisc.
+         */
+        bool promisc;
+        /* Stats about the wireless interface */
+        struct ieee80211_low_level_stats ieee_stats;
+
+        struct hwrng rng;
+        u8 rng_initialized;
+        char rng_name[30 + 1];
+
+        /* List of all wireless devices on this chip */
+        struct list_head devlist;
+        u8 nr_devs;
+};
+
+/* Pointers to the firmware data and meta information about it. */
+struct b43_firmware {
+        /* Microcode */
+        const struct firmware *ucode;
+        /* PCM code */
+        const struct firmware *pcm;
+        /* Initial MMIO values for the firmware */
+        const struct firmware *initvals;
+        /* Initial MMIO values for the firmware, band-specific */
+        const struct firmware *initvals_band;
+        /* Firmware revision */
+        u16 rev;
+        /* Firmware patchlevel */
+        u16 patch;
+};
+
+/* Device (802.11 core) initialization status. */
+enum {
+        B43_STAT_UNINIT = 0,    /* Uninitialized. */
+        B43_STAT_INITIALIZED = 1,       /* Initialized, but not started, yet. */
+        B43_STAT_STARTED = 2,   /* Up and running. */
+};
+#define b43_status(wldev)               atomic_read(&(wldev)->__init_status)
+#define b43_set_status(wldev, stat)     do {                    \
+                atomic_set(&(wldev)->__init_status, (stat));    \
+                smp_wmb();                                      \
+                                        } while (0)
+
+/* XXX---   HOW LOCKING WORKS IN B43   ---XXX
+ *
+ * You should always acquire both, wl->mutex and wl->irq_lock unless:
+ * - You don't need to acquire wl->irq_lock, if the interface is stopped.
+ * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
+ *   and packet TX path (and _ONLY_ there.)
+ */
+
+/* Data structure for one wireless device (802.11 core) */
+struct b43_wldev {
+        struct ssb_device *dev;
+        struct b43_wl *wl;
+
+        /* The device initialization status.
+         * Use b43_status() to query. */
+        atomic_t __init_status;
+        /* Saved init status for handling suspend. */
+        int suspend_init_status;
+
+        bool __using_pio;       /* Internal, use b43_using_pio(). */
+        bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */
+        bool reg124_set_0x4;    /* Some variable to keep track of IRQ stuff. */
+        bool short_preamble;    /* TRUE, if short preamble is enabled. */
+        bool short_slot;        /* TRUE, if short slot timing is enabled. */
+        bool radio_hw_enable;   /* saved state of radio hardware enabled state */
+
+        /* PHY/Radio device. */
+        struct b43_phy phy;
+        union {
+                /* DMA engines. */
+                struct b43_dma dma;
+                /* PIO engines. */
+                struct b43_pio pio;
+        };
+
+        /* Various statistics about the physical device. */
+        struct b43_stats stats;
+
+#define B43_NR_LEDS             4
+        struct b43_led leds[B43_NR_LEDS];
+
+        /* Reason code of the last interrupt. */
+        u32 irq_reason;
+        u32 dma_reason[6];
+        /* saved irq enable/disable state bitfield. */
+        u32 irq_savedstate;
+        /* Link Quality calculation context. */
+        struct b43_noise_calculation noisecalc;
+        /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
+        int mac_suspended;
+
+        /* Interrupt Service Routine tasklet (bottom-half) */
+        struct tasklet_struct isr_tasklet;
+
+        /* Periodic tasks */
+        struct delayed_work periodic_work;
+        unsigned int periodic_state;
+
+        struct work_struct restart_work;
+
+        /* encryption/decryption */
+        u16 ktp;                /* Key table pointer */
+        u8 max_nr_keys;
+        struct b43_key key[58];
+
+        /* Cached beacon template while uploading the template. */
+        struct sk_buff *cached_beacon;
+
+        /* Firmware data */
+        struct b43_firmware fw;
+
+        /* Devicelist in struct b43_wl (all 802.11 cores) */
+        struct list_head list;
+
+        /* Debugging stuff follows. */
+#ifdef CONFIG_B43_DEBUG
+        struct b43_dfsentry *dfsentry;
+#endif
+};
+
+static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
+{
+        return hw->priv;
+}
+
+/* Helper function, which returns a boolean.
+ * TRUE, if PIO is used; FALSE, if DMA is used.
+ */
+#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
+static inline int b43_using_pio(struct b43_wldev *dev)
+{
+        return dev->__using_pio;
+}
+#elif defined(CONFIG_B43_DMA)
+static inline int b43_using_pio(struct b43_wldev *dev)
+{
+        return 0;
+}
+#elif defined(CONFIG_B43_PIO)
+static inline int b43_using_pio(struct b43_wldev *dev)
+{
+        return 1;
+}
+#else
+# error "Using neither DMA nor PIO? Confused..."
+#endif
+
+static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
+{
+        struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
+        return ssb_get_drvdata(ssb_dev);
+}
+
+/* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
+static inline int b43_is_mode(struct b43_wl *wl, int type)
+{
+        if (type == IEEE80211_IF_TYPE_MNTR)
+                return !!(wl->monitor);
+        return (wl->operating && wl->if_type == type);
+}
+
+static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
+{
+        return ssb_read16(dev->dev, offset);
+}
+
+static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
+{
+        ssb_write16(dev->dev, offset, value);
+}
+
+static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
+{
+        return ssb_read32(dev->dev, offset);
+}
+
+static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
+{
+        ssb_write32(dev->dev, offset, value);
+}
+
+/* Message printing */
+void b43info(struct b43_wl *wl, const char *fmt, ...)
+    __attribute__ ((format(printf, 2, 3)));
+void b43err(struct b43_wl *wl, const char *fmt, ...)
+    __attribute__ ((format(printf, 2, 3)));
+void b43warn(struct b43_wl *wl, const char *fmt, ...)
+    __attribute__ ((format(printf, 2, 3)));
+#if B43_DEBUG
+void b43dbg(struct b43_wl *wl, const char *fmt, ...)
+    __attribute__ ((format(printf, 2, 3)));
+#else /* DEBUG */
+# define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
+#endif /* DEBUG */
+
+/* A WARN_ON variant that vanishes when b43 debugging is disabled.
+ * This _also_ evaluates the arg with debugging disabled. */
+#if B43_DEBUG
+# define B43_WARN_ON(x) WARN_ON(x)
+#else
+static inline bool __b43_warn_on_dummy(bool x) { return x; }
+# define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
+#endif
+
+/** Limit a value between two limits */
+#ifdef limit_value
+# undef limit_value
+#endif
+#define limit_value(value, min, max)  \
+        ({                                              \
+                typeof(value) __value = (value);        \
+                typeof(value) __min = (min);            \
+                typeof(value) __max = (max);            \
+                if (__value < __min)                    \
+                        __value = __min;                \
+                else if (__value > __max)               \
+                        __value = __max;                \
+                __value;                                \
+        })
+
+/* Convert an integer to a Q5.2 value */
+#define INT_TO_Q52(i)   ((i) << 2)
+/* Convert a Q5.2 value to an integer (precision loss!) */
+#define Q52_TO_INT(q52) ((q52) >> 2)
+/* Macros for printing a value in Q5.2 format */
+#define Q52_FMT         "%u.%u"
+#define Q52_ARG(q52)    Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
+
+#endif /* B43_H_ */
diff --git a/drivers/net/wireless/b43/debugfs.c b/drivers/net/wireless/b43/debugfs.c
new file mode 100644
index 000000000000..f82e3ef9bd73
--- /dev/null
+++ b/drivers/net/wireless/b43/debugfs.c
@@ -0,0 +1,654 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  debugfs driver debugging code
+
+  Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/fs.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+
+#include "b43.h"
+#include "main.h"
+#include "debugfs.h"
+#include "dma.h"
+#include "pio.h"
+#include "xmit.h"
+
+
+/* The root directory. */
+struct dentry *rootdir;
+
+struct b43_debugfs_fops {
+        ssize_t (*read)(struct b43_wldev *dev, char *buf, size_t bufsize);
+        int (*write)(struct b43_wldev *dev, const char *buf, size_t count);
+        struct file_operations fops;
+        /* Offset of struct b43_dfs_file in struct b43_dfsentry */
+        size_t file_struct_offset;
+        /* Take wl->irq_lock before calling read/write? */
+        bool take_irqlock;
+};
+
+static inline
+struct b43_dfs_file * fops_to_dfs_file(struct b43_wldev *dev,
+                                       const struct b43_debugfs_fops *dfops)
+{
+        void *p;
+
+        p = dev->dfsentry;
+        p += dfops->file_struct_offset;
+
+        return p;
+}
+
+
+#define fappend(fmt, x...)      \
+        do {                                                    \
+                if (bufsize - count)                            \
+                        count += snprintf(buf + count,          \
+                                          bufsize - count,      \
+                                          fmt , ##x);           \
+                else                                            \
+                        printk(KERN_ERR "b43: fappend overflow\n"); \
+        } while (0)
+
+
+/* wl->irq_lock is locked */
+ssize_t tsf_read_file(struct b43_wldev *dev, char *buf, size_t bufsize)
+{
+        ssize_t count = 0;
+        u64 tsf;
+
+        b43_tsf_read(dev, &tsf);
+        fappend("0x%08x%08x\n",
+                (unsigned int)((tsf & 0xFFFFFFFF00000000ULL) >> 32),
+                (unsigned int)(tsf & 0xFFFFFFFFULL));
+
+        return count;
+}
+
+/* wl->irq_lock is locked */
+int tsf_write_file(struct b43_wldev *dev, const char *buf, size_t count)
+{
+        u64 tsf;
+
+        if (sscanf(buf, "%llu", (unsigned long long *)(&tsf)) != 1)
+                return -EINVAL;
+        b43_tsf_write(dev, tsf);
+
+        return 0;
+}
+
+/* wl->irq_lock is locked */
+ssize_t ucode_regs_read_file(struct b43_wldev *dev, char *buf, size_t bufsize)
+{
+        ssize_t count = 0;
+        int i;
+
+        for (i = 0; i < 64; i++) {
+                fappend("r%d = 0x%04x\n", i,
+                        b43_shm_read16(dev, B43_SHM_SCRATCH, i));
+        }
+
+        return count;
+}
+
+/* wl->irq_lock is locked */
+ssize_t shm_read_file(struct b43_wldev *dev, char *buf, size_t bufsize)
+{
+        ssize_t count = 0;
+        int i;
+        u16 tmp;
+        __le16 *le16buf = (__le16 *)buf;
+
+        for (i = 0; i < 0x1000; i++) {
+                if (bufsize <= 0)
+                        break;
+                tmp = b43_shm_read16(dev, B43_SHM_SHARED, 2 * i);
+                le16buf[i] = cpu_to_le16(tmp);
+                count += sizeof(tmp);
+                bufsize -= sizeof(tmp);
+        }
+
+        return count;
+}
+
+ssize_t txstat_read_file(struct b43_wldev *dev, char *buf, size_t bufsize)
+{
+        struct b43_txstatus_log *log = &dev->dfsentry->txstatlog;
+        ssize_t count = 0;
+        unsigned long flags;
+        int i, idx;
+        struct b43_txstatus *stat;
+
+        spin_lock_irqsave(&log->lock, flags);
+        if (log->end < 0) {
+                fappend("Nothing transmitted, yet\n");
+                goto out_unlock;
+        }
+        fappend("b43 TX status reports:\n\n"
+                "index | cookie | seq | phy_stat | frame_count | "
+                "rts_count | supp_reason | pm_indicated | "
+                "intermediate | for_ampdu | acked\n" "---\n");
+        i = log->end + 1;
+        idx = 0;
+        while (1) {
+                if (i == B43_NR_LOGGED_TXSTATUS)
+                        i = 0;
+                stat = &(log->log[i]);
+                if (stat->cookie) {
+                        fappend("%03d | "
+                                "0x%04X | 0x%04X | 0x%02X | "
+                                "0x%X | 0x%X | "
+                                "%u | %u | "
+                                "%u | %u | %u\n",
+                                idx,
+                                stat->cookie, stat->seq, stat->phy_stat,
+                                stat->frame_count, stat->rts_count,
+                                stat->supp_reason, stat->pm_indicated,
+                                stat->intermediate, stat->for_ampdu,
+                                stat->acked);
+                        idx++;
+                }
+                if (i == log->end)
+                        break;
+                i++;
+        }
+out_unlock:
+        spin_unlock_irqrestore(&log->lock, flags);
+
+        return count;
+}
+
+ssize_t txpower_g_read_file(struct b43_wldev *dev, char *buf, size_t bufsize)
+{
+        ssize_t count = 0;
+
+        if (dev->phy.type != B43_PHYTYPE_G) {
+                fappend("Device is not a G-PHY\n");
+                goto out;
+        }
+        fappend("Control:               %s\n", dev->phy.manual_txpower_control ?
+                "MANUAL" : "AUTOMATIC");
+        fappend("Baseband attenuation:  %u\n", dev->phy.bbatt.att);
+        fappend("Radio attenuation:     %u\n", dev->phy.rfatt.att);
+        fappend("TX Mixer Gain:         %s\n",
+                (dev->phy.tx_control & B43_TXCTL_TXMIX) ? "ON" : "OFF");
+        fappend("PA Gain 2dB:           %s\n",
+                (dev->phy.tx_control & B43_TXCTL_PA2DB) ? "ON" : "OFF");
+        fappend("PA Gain 3dB:           %s\n",
+                (dev->phy.tx_control & B43_TXCTL_PA3DB) ? "ON" : "OFF");
+        fappend("\n\n");
+        fappend("You can write to this file:\n");
+        fappend("Writing \"auto\" enables automatic txpower control.\n");
+        fappend
+            ("Writing the attenuation values as \"bbatt rfatt txmix pa2db pa3db\" "
+             "enables manual txpower control.\n");
+        fappend("Example: 5 4 0 0 1\n");
+        fappend("Enables manual control with Baseband attenuation 5, "
+                "Radio attenuation 4, No TX Mixer Gain, "
+                "No PA Gain 2dB, With PA Gain 3dB.\n");
+out:
+        return count;
+}
+
+int txpower_g_write_file(struct b43_wldev *dev, const char *buf, size_t count)
+{
+        unsigned long flags;
+        unsigned long phy_flags;
+        int err = 0;
+
+        spin_lock_irqsave(&dev->wl->irq_lock, flags);
+        if (dev->phy.type != B43_PHYTYPE_G) {
+                err = -ENODEV;
+                goto out_unlock;
+        }
+        if ((count >= 4) && (memcmp(buf, "auto", 4) == 0)) {
+                /* Automatic control */
+                dev->phy.manual_txpower_control = 0;
+                b43_phy_xmitpower(dev);
+        } else {
+                int bbatt = 0, rfatt = 0, txmix = 0, pa2db = 0, pa3db = 0;
+                /* Manual control */
+                if (sscanf(buf, "%d %d %d %d %d", &bbatt, &rfatt,
+                           &txmix, &pa2db, &pa3db) != 5) {
+                        err = -EINVAL;
+                        goto out_unlock;
+                }
+                b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
+                dev->phy.manual_txpower_control = 1;
+                dev->phy.bbatt.att = bbatt;
+                dev->phy.rfatt.att = rfatt;
+                dev->phy.tx_control = 0;
+                if (txmix)
+                        dev->phy.tx_control |= B43_TXCTL_TXMIX;
+                if (pa2db)
+                        dev->phy.tx_control |= B43_TXCTL_PA2DB;
+                if (pa3db)
+                        dev->phy.tx_control |= B43_TXCTL_PA3DB;
+                b43_phy_lock(dev, phy_flags);
+                b43_radio_lock(dev);
+                b43_set_txpower_g(dev, &dev->phy.bbatt,
+                                  &dev->phy.rfatt, dev->phy.tx_control);
+                b43_radio_unlock(dev);
+                b43_phy_unlock(dev, phy_flags);
+        }
+out_unlock:
+        spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+
+        return err;
+}
+
+/* wl->irq_lock is locked */
+int restart_write_file(struct b43_wldev *dev, const char *buf, size_t count)
+{
+        int err = 0;
+
+        if (count > 0 && buf[0] == '1') {
+                b43_controller_restart(dev, "manually restarted");
+        } else
+                err = -EINVAL;
+
+        return err;
+}
+
+static ssize_t append_lo_table(ssize_t count, char *buf, const size_t bufsize,
+                               struct b43_loctl table[B43_NR_BB][B43_NR_RF])
+{
+        unsigned int i, j;
+        struct b43_loctl *ctl;
+
+        for (i = 0; i < B43_NR_BB; i++) {
+                for (j = 0; j < B43_NR_RF; j++) {
+                        ctl = &(table[i][j]);
+                        fappend("(bbatt %2u, rfatt %2u)  ->  "
+                                "(I %+3d, Q %+3d, Used: %d, Calibrated: %d)\n",
+                                i, j, ctl->i, ctl->q,
+                                ctl->used,
+                                b43_loctl_is_calibrated(ctl));
+                }
+        }
+
+        return count;
+}
+
+ssize_t loctls_read_file(struct b43_wldev *dev, char *buf, size_t bufsize)
+{
+        ssize_t count = 0;
+        struct b43_txpower_lo_control *lo;
+        int i, err = 0;
+
+        if (dev->phy.type != B43_PHYTYPE_G) {
+                fappend("Device is not a G-PHY\n");
+                err = -ENODEV;
+                goto out;
+        }
+        lo = dev->phy.lo_control;
+        fappend("-- Local Oscillator calibration data --\n\n");
+        fappend("Measured: %d,  Rebuild: %d,  HW-power-control: %d\n",
+                lo->lo_measured,
+                lo->rebuild,
+                dev->phy.hardware_power_control);
+        fappend("TX Bias: 0x%02X,  TX Magn: 0x%02X\n",
+                lo->tx_bias, lo->tx_magn);
+        fappend("Power Vector: 0x%08X%08X\n",
+                (unsigned int)((lo->power_vector & 0xFFFFFFFF00000000ULL) >> 32),
+                (unsigned int)(lo->power_vector & 0x00000000FFFFFFFFULL));
+        fappend("\nControl table WITH PADMIX:\n");
+        count = append_lo_table(count, buf, bufsize, lo->with_padmix);
+        fappend("\nControl table WITHOUT PADMIX:\n");
+        count = append_lo_table(count, buf, bufsize, lo->no_padmix);
+        fappend("\nUsed RF attenuation values:  Value(WithPadmix flag)\n");
+        for (i = 0; i < lo->rfatt_list.len; i++) {
+                fappend("%u(%d), ",
+                        lo->rfatt_list.list[i].att,
+                        lo->rfatt_list.list[i].with_padmix);
+        }
+        fappend("\n");
+        fappend("\nUsed Baseband attenuation values:\n");
+        for (i = 0; i < lo->bbatt_list.len; i++) {
+                fappend("%u, ",
+                        lo->bbatt_list.list[i].att);
+        }
+        fappend("\n");
+
+out:
+        return err ? err : count;
+}
+
+#undef fappend
+
+static int b43_debugfs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf,
+                                size_t count, loff_t *ppos)
+{
+        struct b43_wldev *dev;
+        struct b43_debugfs_fops *dfops;
+        struct b43_dfs_file *dfile;
+        ssize_t ret;
+        char *buf;
+        const size_t bufsize = 1024 * 128;
+        const size_t buforder = get_order(bufsize);
+        int err = 0;
+
+        if (!count)
+                return 0;
+        dev = file->private_data;
+        if (!dev)
+                return -ENODEV;
+
+        mutex_lock(&dev->wl->mutex);
+        if (b43_status(dev) < B43_STAT_INITIALIZED) {
+                err = -ENODEV;
+                goto out_unlock;
+        }
+
+        dfops = container_of(file->f_op, struct b43_debugfs_fops, fops);
+        if (!dfops->read) {
+                err = -ENOSYS;
+                goto out_unlock;
+        }
+        dfile = fops_to_dfs_file(dev, dfops);
+
+        if (!dfile->buffer) {
+                buf = (char *)__get_free_pages(GFP_KERNEL, buforder);
+                if (!buf) {
+                        err = -ENOMEM;
+                        goto out_unlock;
+                }
+                memset(buf, 0, bufsize);
+                if (dfops->take_irqlock) {
+                        spin_lock_irq(&dev->wl->irq_lock);
+                        ret = dfops->read(dev, buf, bufsize);
+                        spin_unlock_irq(&dev->wl->irq_lock);
+                } else
+                        ret = dfops->read(dev, buf, bufsize);
+                if (ret <= 0) {
+                        free_pages((unsigned long)buf, buforder);
+                        err = ret;
+                        goto out_unlock;
+                }
+                dfile->data_len = ret;
+                dfile->buffer = buf;
+        }
+
+        ret = simple_read_from_buffer(userbuf, count, ppos,
+                                      dfile->buffer,
+                                      dfile->data_len);
+        if (*ppos >= dfile->data_len) {
+                free_pages((unsigned long)dfile->buffer, buforder);
+                dfile->buffer = NULL;
+                dfile->data_len = 0;
+        }
+out_unlock:
+        mutex_unlock(&dev->wl->mutex);
+
+        return err ? err : ret;
+}
+
+static ssize_t b43_debugfs_write(struct file *file,
+                                 const char __user *userbuf,
+                                 size_t count, loff_t *ppos)
+{
+        struct b43_wldev *dev;
+        struct b43_debugfs_fops *dfops;
+        char *buf;
+        int err = 0;
+
+        if (!count)
+                return 0;
+        if (count > PAGE_SIZE)
+                return -E2BIG;
+        dev = file->private_data;
+        if (!dev)
+                return -ENODEV;
+
+        mutex_lock(&dev->wl->mutex);
+        if (b43_status(dev) < B43_STAT_INITIALIZED) {
+                err = -ENODEV;
+                goto out_unlock;
+        }
+
+        dfops = container_of(file->f_op, struct b43_debugfs_fops, fops);
+        if (!dfops->write) {
+                err = -ENOSYS;
+                goto out_unlock;
+        }
+
+        buf = (char *)get_zeroed_page(GFP_KERNEL);
+        if (!buf) {
+                err = -ENOMEM;
+                goto out_unlock;
+        }
+        if (copy_from_user(buf, userbuf, count)) {
+                err = -EFAULT;
+                goto out_freepage;
+        }
+        if (dfops->take_irqlock) {
+                spin_lock_irq(&dev->wl->irq_lock);
+                err = dfops->write(dev, buf, count);
+                spin_unlock_irq(&dev->wl->irq_lock);
+        } else
+                err = dfops->write(dev, buf, count);
+        if (err)
+                goto out_freepage;
+
+out_freepage:
+        free_page((unsigned long)buf);
+out_unlock:
+        mutex_unlock(&dev->wl->mutex);
+
+        return err ? err : count;
+}
+
+
+#define B43_DEBUGFS_FOPS(name, _read, _write, _take_irqlock)    \
+        static struct b43_debugfs_fops fops_##name = {          \
+                .read   = _read,                                \
+                .write  = _write,                               \
+                .fops   = {                                     \
+                        .open   = b43_debugfs_open,             \
+                        .read   = b43_debugfs_read,             \
+                        .write  = b43_debugfs_write,            \
+                },                                              \
+                .file_struct_offset = offsetof(struct b43_dfsentry, \
+                                               file_##name),    \
+                .take_irqlock   = _take_irqlock,                \
+        }
+
+B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1);
+B43_DEBUGFS_FOPS(ucode_regs, ucode_regs_read_file, NULL, 1);
+B43_DEBUGFS_FOPS(shm, shm_read_file, NULL, 1);
+B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0);
+B43_DEBUGFS_FOPS(txpower_g, txpower_g_read_file, txpower_g_write_file, 0);
+B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1);
+B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL, 0);
+
+
+int b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature)
+{
+        return !!(dev->dfsentry && dev->dfsentry->dyn_debug[feature]);
+}
+
+static void b43_remove_dynamic_debug(struct b43_wldev *dev)
+{
+        struct b43_dfsentry *e = dev->dfsentry;
+        int i;
+
+        for (i = 0; i < __B43_NR_DYNDBG; i++)
+                debugfs_remove(e->dyn_debug_dentries[i]);
+}
+
+static void b43_add_dynamic_debug(struct b43_wldev *dev)
+{
+        struct b43_dfsentry *e = dev->dfsentry;
+        struct dentry *d;
+
+#define add_dyn_dbg(name, id, initstate) do {           \
+        e->dyn_debug[id] = (initstate);                 \
+        d = debugfs_create_bool(name, 0600, e->subdir,  \
+                                &(e->dyn_debug[id]));   \
+        if (!IS_ERR(d))                                 \
+                e->dyn_debug_dentries[id] = d;          \
+                                } while (0)
+
+        add_dyn_dbg("debug_xmitpower", B43_DBG_XMITPOWER, 0);
+        add_dyn_dbg("debug_dmaoverflow", B43_DBG_DMAOVERFLOW, 0);
+        add_dyn_dbg("debug_dmaverbose", B43_DBG_DMAVERBOSE, 0);
+        add_dyn_dbg("debug_pwork_fast", B43_DBG_PWORK_FAST, 0);
+        add_dyn_dbg("debug_pwork_stop", B43_DBG_PWORK_STOP, 0);
+
+#undef add_dyn_dbg
+}
+
+void b43_debugfs_add_device(struct b43_wldev *dev)
+{
+        struct b43_dfsentry *e;
+        struct b43_txstatus_log *log;
+        char devdir[16];
+
+        B43_WARN_ON(!dev);
+        e = kzalloc(sizeof(*e), GFP_KERNEL);
+        if (!e) {
+                b43err(dev->wl, "debugfs: add device OOM\n");
+                return;
+        }
+        e->dev = dev;
+        log = &e->txstatlog;
+        log->log = kcalloc(B43_NR_LOGGED_TXSTATUS,
+                           sizeof(struct b43_txstatus), GFP_KERNEL);
+        if (!log->log) {
+                b43err(dev->wl, "debugfs: add device txstatus OOM\n");
+                kfree(e);
+                return;
+        }
+        log->end = -1;
+        spin_lock_init(&log->lock);
+
+        dev->dfsentry = e;
+
+        snprintf(devdir, sizeof(devdir), "%s", wiphy_name(dev->wl->hw->wiphy));
+        e->subdir = debugfs_create_dir(devdir, rootdir);
+        if (!e->subdir || IS_ERR(e->subdir)) {
+                if (e->subdir == ERR_PTR(-ENODEV)) {
+                        b43dbg(dev->wl, "DebugFS (CONFIG_DEBUG_FS) not "
+                               "enabled in kernel config\n");
+                } else {
+                        b43err(dev->wl, "debugfs: cannot create %s directory\n",
+                               devdir);
+                }
+                dev->dfsentry = NULL;
+                kfree(log->log);
+                kfree(e);
+                return;
+        }
+
+#define ADD_FILE(name, mode)    \
+        do {                                                    \
+                struct dentry *d;                               \
+                d = debugfs_create_file(__stringify(name),      \
+                                        mode, e->subdir, dev,   \
+                                        &fops_##name.fops);     \
+                e->file_##name.dentry = NULL;                   \
+                if (!IS_ERR(d))                                 \
+                        e->file_##name.dentry = d;              \
+        } while (0)
+
+
+        ADD_FILE(tsf, 0600);
+        ADD_FILE(ucode_regs, 0400);
+        ADD_FILE(shm, 0400);
+        ADD_FILE(txstat, 0400);
+        ADD_FILE(txpower_g, 0600);
+        ADD_FILE(restart, 0200);
+        ADD_FILE(loctls, 0400);
+
+#undef ADD_FILE
+
+        b43_add_dynamic_debug(dev);
+}
+
+void b43_debugfs_remove_device(struct b43_wldev *dev)
+{
+        struct b43_dfsentry *e;
+
+        if (!dev)
+                return;
+        e = dev->dfsentry;
+        if (!e)
+                return;
+        b43_remove_dynamic_debug(dev);
+
+        debugfs_remove(e->file_tsf.dentry);
+        debugfs_remove(e->file_ucode_regs.dentry);
+        debugfs_remove(e->file_shm.dentry);
+        debugfs_remove(e->file_txstat.dentry);
+        debugfs_remove(e->file_txpower_g.dentry);
+        debugfs_remove(e->file_restart.dentry);
+        debugfs_remove(e->file_loctls.dentry);
+
+        debugfs_remove(e->subdir);
+        kfree(e->txstatlog.log);
+        kfree(e);
+}
+
+void b43_debugfs_log_txstat(struct b43_wldev *dev,
+                            const struct b43_txstatus *status)
+{
+        struct b43_dfsentry *e = dev->dfsentry;
+        struct b43_txstatus_log *log;
+        struct b43_txstatus *cur;
+        int i;
+
+        if (!e)
+                return;
+        log = &e->txstatlog;
+        B43_WARN_ON(!irqs_disabled());
+        spin_lock(&log->lock);
+        i = log->end + 1;
+        if (i == B43_NR_LOGGED_TXSTATUS)
+                i = 0;
+        log->end = i;
+        cur = &(log->log[i]);
+        memcpy(cur, status, sizeof(*cur));
+        spin_unlock(&log->lock);
+}
+
+void b43_debugfs_init(void)
+{
+        rootdir = debugfs_create_dir(KBUILD_MODNAME, NULL);
+        if (IS_ERR(rootdir))
+                rootdir = NULL;
+}
+
+void b43_debugfs_exit(void)
+{
+        debugfs_remove(rootdir);
+}
diff --git a/drivers/net/wireless/b43/debugfs.h b/drivers/net/wireless/b43/debugfs.h
new file mode 100644
index 000000000000..6eebe858db5a
--- /dev/null
+++ b/drivers/net/wireless/b43/debugfs.h
@@ -0,0 +1,89 @@
+#ifndef B43_DEBUGFS_H_
+#define B43_DEBUGFS_H_
+
+struct b43_wldev;
+struct b43_txstatus;
+
+enum b43_dyndbg {               /* Dynamic debugging features */
+        B43_DBG_XMITPOWER,
+        B43_DBG_DMAOVERFLOW,
+        B43_DBG_DMAVERBOSE,
+        B43_DBG_PWORK_FAST,
+        B43_DBG_PWORK_STOP,
+        __B43_NR_DYNDBG,
+};
+
+#ifdef CONFIG_B43_DEBUG
+
+struct dentry;
+
+#define B43_NR_LOGGED_TXSTATUS  100
+
+struct b43_txstatus_log {
+        struct b43_txstatus *log;
+        int end;
+        spinlock_t lock;
+};
+
+struct b43_dfs_file {
+        struct dentry *dentry;
+        char *buffer;
+        size_t data_len;
+};
+
+struct b43_dfsentry {
+        struct b43_wldev *dev;
+        struct dentry *subdir;
+
+        struct b43_dfs_file file_tsf;
+        struct b43_dfs_file file_ucode_regs;
+        struct b43_dfs_file file_shm;
+        struct b43_dfs_file file_txstat;
+        struct b43_dfs_file file_txpower_g;
+        struct b43_dfs_file file_restart;
+        struct b43_dfs_file file_loctls;
+
+        struct b43_txstatus_log txstatlog;
+
+        /* Enabled/Disabled list for the dynamic debugging features. */
+        u32 dyn_debug[__B43_NR_DYNDBG];
+        /* Dentries for the dynamic debugging entries. */
+        struct dentry *dyn_debug_dentries[__B43_NR_DYNDBG];
+};
+
+int b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature);
+
+void b43_debugfs_init(void);
+void b43_debugfs_exit(void);
+void b43_debugfs_add_device(struct b43_wldev *dev);
+void b43_debugfs_remove_device(struct b43_wldev *dev);
+void b43_debugfs_log_txstat(struct b43_wldev *dev,
+                            const struct b43_txstatus *status);
+
+#else /* CONFIG_B43_DEBUG */
+
+static inline int b43_debug(struct b43_wldev *dev, enum b43_dyndbg feature)
+{
+        return 0;
+}
+
+static inline void b43_debugfs_init(void)
+{
+}
+static inline void b43_debugfs_exit(void)
+{
+}
+static inline void b43_debugfs_add_device(struct b43_wldev *dev)
+{
+}
+static inline void b43_debugfs_remove_device(struct b43_wldev *dev)
+{
+}
+static inline void b43_debugfs_log_txstat(struct b43_wldev *dev,
+                                          const struct b43_txstatus *status)
+{
+}
+
+#endif /* CONFIG_B43_DEBUG */
+
+#endif /* B43_DEBUGFS_H_ */
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
new file mode 100644
index 000000000000..5e8f8ac0f1dd
--- /dev/null
+++ b/drivers/net/wireless/b43/dma.c
@@ -0,0 +1,1494 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  DMA ringbuffer and descriptor allocation/management
+
+  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+
+  Some code in this file is derived from the b44.c driver
+  Copyright (C) 2002 David S. Miller
+  Copyright (C) Pekka Pietikainen
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "b43.h"
+#include "dma.h"
+#include "main.h"
+#include "debugfs.h"
+#include "xmit.h"
+
+#include <linux/dma-mapping.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/skbuff.h>
+
+/* 32bit DMA ops. */
+static
+struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
+                                          int slot,
+                                          struct b43_dmadesc_meta **meta)
+{
+        struct b43_dmadesc32 *desc;
+
+        *meta = &(ring->meta[slot]);
+        desc = ring->descbase;
+        desc = &(desc[slot]);
+
+        return (struct b43_dmadesc_generic *)desc;
+}
+
+static void op32_fill_descriptor(struct b43_dmaring *ring,
+                                 struct b43_dmadesc_generic *desc,
+                                 dma_addr_t dmaaddr, u16 bufsize,
+                                 int start, int end, int irq)
+{
+        struct b43_dmadesc32 *descbase = ring->descbase;
+        int slot;
+        u32 ctl;
+        u32 addr;
+        u32 addrext;
+
+        slot = (int)(&(desc->dma32) - descbase);
+        B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
+
+        addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
+        addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
+            >> SSB_DMA_TRANSLATION_SHIFT;
+        addr |= ssb_dma_translation(ring->dev->dev);
+        ctl = (bufsize - ring->frameoffset)
+            & B43_DMA32_DCTL_BYTECNT;
+        if (slot == ring->nr_slots - 1)
+                ctl |= B43_DMA32_DCTL_DTABLEEND;
+        if (start)
+                ctl |= B43_DMA32_DCTL_FRAMESTART;
+        if (end)
+                ctl |= B43_DMA32_DCTL_FRAMEEND;
+        if (irq)
+                ctl |= B43_DMA32_DCTL_IRQ;
+        ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
+            & B43_DMA32_DCTL_ADDREXT_MASK;
+
+        desc->dma32.control = cpu_to_le32(ctl);
+        desc->dma32.address = cpu_to_le32(addr);
+}
+
+static void op32_poke_tx(struct b43_dmaring *ring, int slot)
+{
+        b43_dma_write(ring, B43_DMA32_TXINDEX,
+                      (u32) (slot * sizeof(struct b43_dmadesc32)));
+}
+
+static void op32_tx_suspend(struct b43_dmaring *ring)
+{
+        b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
+                      | B43_DMA32_TXSUSPEND);
+}
+
+static void op32_tx_resume(struct b43_dmaring *ring)
+{
+        b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
+                      & ~B43_DMA32_TXSUSPEND);
+}
+
+static int op32_get_current_rxslot(struct b43_dmaring *ring)
+{
+        u32 val;
+
+        val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
+        val &= B43_DMA32_RXDPTR;
+
+        return (val / sizeof(struct b43_dmadesc32));
+}
+
+static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
+{
+        b43_dma_write(ring, B43_DMA32_RXINDEX,
+                      (u32) (slot * sizeof(struct b43_dmadesc32)));
+}
+
+static const struct b43_dma_ops dma32_ops = {
+        .idx2desc = op32_idx2desc,
+        .fill_descriptor = op32_fill_descriptor,
+        .poke_tx = op32_poke_tx,
+        .tx_suspend = op32_tx_suspend,
+        .tx_resume = op32_tx_resume,
+        .get_current_rxslot = op32_get_current_rxslot,
+        .set_current_rxslot = op32_set_current_rxslot,
+};
+
+/* 64bit DMA ops. */
+static
+struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
+                                          int slot,
+                                          struct b43_dmadesc_meta **meta)
+{
+        struct b43_dmadesc64 *desc;
+
+        *meta = &(ring->meta[slot]);
+        desc = ring->descbase;
+        desc = &(desc[slot]);
+
+        return (struct b43_dmadesc_generic *)desc;
+}
+
+static void op64_fill_descriptor(struct b43_dmaring *ring,
+                                 struct b43_dmadesc_generic *desc,
+                                 dma_addr_t dmaaddr, u16 bufsize,
+                                 int start, int end, int irq)
+{
+        struct b43_dmadesc64 *descbase = ring->descbase;
+        int slot;
+        u32 ctl0 = 0, ctl1 = 0;
+        u32 addrlo, addrhi;
+        u32 addrext;
+
+        slot = (int)(&(desc->dma64) - descbase);
+        B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
+
+        addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
+        addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
+        addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
+            >> SSB_DMA_TRANSLATION_SHIFT;
+        addrhi |= ssb_dma_translation(ring->dev->dev);
+        if (slot == ring->nr_slots - 1)
+                ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
+        if (start)
+                ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
+        if (end)
+                ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
+        if (irq)
+                ctl0 |= B43_DMA64_DCTL0_IRQ;
+        ctl1 |= (bufsize - ring->frameoffset)
+            & B43_DMA64_DCTL1_BYTECNT;
+        ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
+            & B43_DMA64_DCTL1_ADDREXT_MASK;
+
+        desc->dma64.control0 = cpu_to_le32(ctl0);
+        desc->dma64.control1 = cpu_to_le32(ctl1);
+        desc->dma64.address_low = cpu_to_le32(addrlo);
+        desc->dma64.address_high = cpu_to_le32(addrhi);
+}
+
+static void op64_poke_tx(struct b43_dmaring *ring, int slot)
+{
+        b43_dma_write(ring, B43_DMA64_TXINDEX,
+                      (u32) (slot * sizeof(struct b43_dmadesc64)));
+}
+
+static void op64_tx_suspend(struct b43_dmaring *ring)
+{
+        b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
+                      | B43_DMA64_TXSUSPEND);
+}
+
+static void op64_tx_resume(struct b43_dmaring *ring)
+{
+        b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
+                      & ~B43_DMA64_TXSUSPEND);
+}
+
+static int op64_get_current_rxslot(struct b43_dmaring *ring)
+{
+        u32 val;
+
+        val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
+        val &= B43_DMA64_RXSTATDPTR;
+
+        return (val / sizeof(struct b43_dmadesc64));
+}
+
+static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
+{
+        b43_dma_write(ring, B43_DMA64_RXINDEX,
+                      (u32) (slot * sizeof(struct b43_dmadesc64)));
+}
+
+static const struct b43_dma_ops dma64_ops = {
+        .idx2desc = op64_idx2desc,
+        .fill_descriptor = op64_fill_descriptor,
+        .poke_tx = op64_poke_tx,
+        .tx_suspend = op64_tx_suspend,
+        .tx_resume = op64_tx_resume,
+        .get_current_rxslot = op64_get_current_rxslot,
+        .set_current_rxslot = op64_set_current_rxslot,
+};
+
+static inline int free_slots(struct b43_dmaring *ring)
+{
+        return (ring->nr_slots - ring->used_slots);
+}
+
+static inline int next_slot(struct b43_dmaring *ring, int slot)
+{
+        B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
+        if (slot == ring->nr_slots - 1)
+                return 0;
+        return slot + 1;
+}
+
+static inline int prev_slot(struct b43_dmaring *ring, int slot)
+{
+        B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
+        if (slot == 0)
+                return ring->nr_slots - 1;
+        return slot - 1;
+}
+
+#ifdef CONFIG_B43_DEBUG
+static void update_max_used_slots(struct b43_dmaring *ring,
+                                  int current_used_slots)
+{
+        if (current_used_slots <= ring->max_used_slots)
+                return;
+        ring->max_used_slots = current_used_slots;
+        if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
+                b43dbg(ring->dev->wl,
+                       "max_used_slots increased to %d on %s ring %d\n",
+                       ring->max_used_slots,
+                       ring->tx ? "TX" : "RX", ring->index);
+        }
+}
+#else
+static inline
+    void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
+{
+}
+#endif /* DEBUG */
+
+/* Request a slot for usage. */
+static inline int request_slot(struct b43_dmaring *ring)
+{
+        int slot;
+
+        B43_WARN_ON(!ring->tx);
+        B43_WARN_ON(ring->stopped);
+        B43_WARN_ON(free_slots(ring) == 0);
+
+        slot = next_slot(ring, ring->current_slot);
+        ring->current_slot = slot;
+        ring->used_slots++;
+
+        update_max_used_slots(ring, ring->used_slots);
+
+        return slot;
+}
+
+/* Mac80211-queue to b43-ring mapping */
+static struct b43_dmaring *priority_to_txring(struct b43_wldev *dev,
+                                              int queue_priority)
+{
+        struct b43_dmaring *ring;
+
+/*FIXME: For now we always run on TX-ring-1 */
+        return dev->dma.tx_ring1;
+
+        /* 0 = highest priority */
+        switch (queue_priority) {
+        default:
+                B43_WARN_ON(1);
+                /* fallthrough */
+        case 0:
+                ring = dev->dma.tx_ring3;
+                break;
+        case 1:
+                ring = dev->dma.tx_ring2;
+                break;
+        case 2:
+                ring = dev->dma.tx_ring1;
+                break;
+        case 3:
+                ring = dev->dma.tx_ring0;
+                break;
+        case 4:
+                ring = dev->dma.tx_ring4;
+                break;
+        case 5:
+                ring = dev->dma.tx_ring5;
+                break;
+        }
+
+        return ring;
+}
+
+/* Bcm43xx-ring to mac80211-queue mapping */
+static inline int txring_to_priority(struct b43_dmaring *ring)
+{
+        static const u8 idx_to_prio[] = { 3, 2, 1, 0, 4, 5, };
+
+/*FIXME: have only one queue, for now */
+        return 0;
+
+        return idx_to_prio[ring->index];
+}
+
+u16 b43_dmacontroller_base(int dma64bit, int controller_idx)
+{
+        static const u16 map64[] = {
+                B43_MMIO_DMA64_BASE0,
+                B43_MMIO_DMA64_BASE1,
+                B43_MMIO_DMA64_BASE2,
+                B43_MMIO_DMA64_BASE3,
+                B43_MMIO_DMA64_BASE4,
+                B43_MMIO_DMA64_BASE5,
+        };
+        static const u16 map32[] = {
+                B43_MMIO_DMA32_BASE0,
+                B43_MMIO_DMA32_BASE1,
+                B43_MMIO_DMA32_BASE2,
+                B43_MMIO_DMA32_BASE3,
+                B43_MMIO_DMA32_BASE4,
+                B43_MMIO_DMA32_BASE5,
+        };
+
+        if (dma64bit) {
+                B43_WARN_ON(!(controller_idx >= 0 &&
+                              controller_idx < ARRAY_SIZE(map64)));
+                return map64[controller_idx];
+        }
+        B43_WARN_ON(!(controller_idx >= 0 &&
+                      controller_idx < ARRAY_SIZE(map32)));
+        return map32[controller_idx];
+}
+
+static inline
+    dma_addr_t map_descbuffer(struct b43_dmaring *ring,
+                              unsigned char *buf, size_t len, int tx)
+{
+        dma_addr_t dmaaddr;
+
+        if (tx) {
+                dmaaddr = dma_map_single(ring->dev->dev->dev,
+                                         buf, len, DMA_TO_DEVICE);
+        } else {
+                dmaaddr = dma_map_single(ring->dev->dev->dev,
+                                         buf, len, DMA_FROM_DEVICE);
+        }
+
+        return dmaaddr;
+}
+
+static inline
+    void unmap_descbuffer(struct b43_dmaring *ring,
+                          dma_addr_t addr, size_t len, int tx)
+{
+        if (tx) {
+                dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE);
+        } else {
+                dma_unmap_single(ring->dev->dev->dev,
+                                 addr, len, DMA_FROM_DEVICE);
+        }
+}
+
+static inline
+    void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
+                                 dma_addr_t addr, size_t len)
+{
+        B43_WARN_ON(ring->tx);
+        dma_sync_single_for_cpu(ring->dev->dev->dev,
+                                addr, len, DMA_FROM_DEVICE);
+}
+
+static inline
+    void sync_descbuffer_for_device(struct b43_dmaring *ring,
+                                    dma_addr_t addr, size_t len)
+{
+        B43_WARN_ON(ring->tx);
+        dma_sync_single_for_device(ring->dev->dev->dev,
+                                   addr, len, DMA_FROM_DEVICE);
+}
+
+static inline
+    void free_descriptor_buffer(struct b43_dmaring *ring,
+                                struct b43_dmadesc_meta *meta)
+{
+        if (meta->skb) {
+                dev_kfree_skb_any(meta->skb);
+                meta->skb = NULL;
+        }
+}
+
+static int alloc_ringmemory(struct b43_dmaring *ring)
+{
+        struct device *dev = ring->dev->dev->dev;
+
+        ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
+                                            &(ring->dmabase), GFP_KERNEL);
+        if (!ring->descbase) {
+                b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
+                return -ENOMEM;
+        }
+        memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
+
+        return 0;
+}
+
+static void free_ringmemory(struct b43_dmaring *ring)
+{
+        struct device *dev = ring->dev->dev->dev;
+
+        dma_free_coherent(dev, B43_DMA_RINGMEMSIZE,
+                          ring->descbase, ring->dmabase);
+}
+
+/* Reset the RX DMA channel */
+int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
+{
+        int i;
+        u32 value;
+        u16 offset;
+
+        might_sleep();
+
+        offset = dma64 ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
+        b43_write32(dev, mmio_base + offset, 0);
+        for (i = 0; i < 10; i++) {
+                offset = dma64 ? B43_DMA64_RXSTATUS : B43_DMA32_RXSTATUS;
+                value = b43_read32(dev, mmio_base + offset);
+                if (dma64) {
+                        value &= B43_DMA64_RXSTAT;
+                        if (value == B43_DMA64_RXSTAT_DISABLED) {
+                                i = -1;
+                                break;
+                        }
+                } else {
+                        value &= B43_DMA32_RXSTATE;
+                        if (value == B43_DMA32_RXSTAT_DISABLED) {
+                                i = -1;
+                                break;
+                        }
+                }
+                msleep(1);
+        }
+        if (i != -1) {
+                b43err(dev->wl, "DMA RX reset timed out\n");
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+/* Reset the RX DMA channel */
+int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, int dma64)
+{
+        int i;
+        u32 value;
+        u16 offset;
+
+        might_sleep();
+
+        for (i = 0; i < 10; i++) {
+                offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
+                value = b43_read32(dev, mmio_base + offset);
+                if (dma64) {
+                        value &= B43_DMA64_TXSTAT;
+                        if (value == B43_DMA64_TXSTAT_DISABLED ||
+                            value == B43_DMA64_TXSTAT_IDLEWAIT ||
+                            value == B43_DMA64_TXSTAT_STOPPED)
+                                break;
+                } else {
+                        value &= B43_DMA32_TXSTATE;
+                        if (value == B43_DMA32_TXSTAT_DISABLED ||
+                            value == B43_DMA32_TXSTAT_IDLEWAIT ||
+                            value == B43_DMA32_TXSTAT_STOPPED)
+                                break;
+                }
+                msleep(1);
+        }
+        offset = dma64 ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
+        b43_write32(dev, mmio_base + offset, 0);
+        for (i = 0; i < 10; i++) {
+                offset = dma64 ? B43_DMA64_TXSTATUS : B43_DMA32_TXSTATUS;
+                value = b43_read32(dev, mmio_base + offset);
+                if (dma64) {
+                        value &= B43_DMA64_TXSTAT;
+                        if (value == B43_DMA64_TXSTAT_DISABLED) {
+                                i = -1;
+                                break;
+                        }
+                } else {
+                        value &= B43_DMA32_TXSTATE;
+                        if (value == B43_DMA32_TXSTAT_DISABLED) {
+                                i = -1;
+                                break;
+                        }
+                }
+                msleep(1);
+        }
+        if (i != -1) {
+                b43err(dev->wl, "DMA TX reset timed out\n");
+                return -ENODEV;
+        }
+        /* ensure the reset is completed. */
+        msleep(1);
+
+        return 0;
+}
+
+static int setup_rx_descbuffer(struct b43_dmaring *ring,
+                               struct b43_dmadesc_generic *desc,
+                               struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
+{
+        struct b43_rxhdr_fw4 *rxhdr;
+        struct b43_hwtxstatus *txstat;
+        dma_addr_t dmaaddr;
+        struct sk_buff *skb;
+
+        B43_WARN_ON(ring->tx);
+
+        skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
+        if (unlikely(!skb))
+                return -ENOMEM;
+        dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
+        if (dma_mapping_error(dmaaddr)) {
+                /* ugh. try to realloc in zone_dma */
+                gfp_flags |= GFP_DMA;
+
+                dev_kfree_skb_any(skb);
+
+                skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
+                if (unlikely(!skb))
+                        return -ENOMEM;
+                dmaaddr = map_descbuffer(ring, skb->data,
+                                         ring->rx_buffersize, 0);
+        }
+
+        if (dma_mapping_error(dmaaddr)) {
+                dev_kfree_skb_any(skb);
+                return -EIO;
+        }
+
+        meta->skb = skb;
+        meta->dmaaddr = dmaaddr;
+        ring->ops->fill_descriptor(ring, desc, dmaaddr,
+                                   ring->rx_buffersize, 0, 0, 0);
+
+        rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
+        rxhdr->frame_len = 0;
+        txstat = (struct b43_hwtxstatus *)(skb->data);
+        txstat->cookie = 0;
+
+        return 0;
+}
+
+/* Allocate the initial descbuffers.
+ * This is used for an RX ring only.
+ */
+static int alloc_initial_descbuffers(struct b43_dmaring *ring)
+{
+        int i, err = -ENOMEM;
+        struct b43_dmadesc_generic *desc;
+        struct b43_dmadesc_meta *meta;
+
+        for (i = 0; i < ring->nr_slots; i++) {
+                desc = ring->ops->idx2desc(ring, i, &meta);
+
+                err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
+                if (err) {
+                        b43err(ring->dev->wl,
+                               "Failed to allocate initial descbuffers\n");
+                        goto err_unwind;
+                }
+        }
+        mb();
+        ring->used_slots = ring->nr_slots;
+        err = 0;
+      out:
+        return err;
+
+      err_unwind:
+        for (i--; i >= 0; i--) {
+                desc = ring->ops->idx2desc(ring, i, &meta);
+
+                unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
+                dev_kfree_skb(meta->skb);
+        }
+        goto out;
+}
+
+/* Do initial setup of the DMA controller.
+ * Reset the controller, write the ring busaddress
+ * and switch the "enable" bit on.
+ */
+static int dmacontroller_setup(struct b43_dmaring *ring)
+{
+        int err = 0;
+        u32 value;
+        u32 addrext;
+        u32 trans = ssb_dma_translation(ring->dev->dev);
+
+        if (ring->tx) {
+                if (ring->dma64) {
+                        u64 ringbase = (u64) (ring->dmabase);
+
+                        addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
+                            >> SSB_DMA_TRANSLATION_SHIFT;
+                        value = B43_DMA64_TXENABLE;
+                        value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
+                            & B43_DMA64_TXADDREXT_MASK;
+                        b43_dma_write(ring, B43_DMA64_TXCTL, value);
+                        b43_dma_write(ring, B43_DMA64_TXRINGLO,
+                                      (ringbase & 0xFFFFFFFF));
+                        b43_dma_write(ring, B43_DMA64_TXRINGHI,
+                                      ((ringbase >> 32) &
+                                       ~SSB_DMA_TRANSLATION_MASK)
+                                      | trans);
+                } else {
+                        u32 ringbase = (u32) (ring->dmabase);
+
+                        addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
+                            >> SSB_DMA_TRANSLATION_SHIFT;
+                        value = B43_DMA32_TXENABLE;
+                        value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
+                            & B43_DMA32_TXADDREXT_MASK;
+                        b43_dma_write(ring, B43_DMA32_TXCTL, value);
+                        b43_dma_write(ring, B43_DMA32_TXRING,
+                                      (ringbase & ~SSB_DMA_TRANSLATION_MASK)
+                                      | trans);
+                }
+        } else {
+                err = alloc_initial_descbuffers(ring);
+                if (err)
+                        goto out;
+                if (ring->dma64) {
+                        u64 ringbase = (u64) (ring->dmabase);
+
+                        addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
+                            >> SSB_DMA_TRANSLATION_SHIFT;
+                        value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
+                        value |= B43_DMA64_RXENABLE;
+                        value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
+                            & B43_DMA64_RXADDREXT_MASK;
+                        b43_dma_write(ring, B43_DMA64_RXCTL, value);
+                        b43_dma_write(ring, B43_DMA64_RXRINGLO,
+                                      (ringbase & 0xFFFFFFFF));
+                        b43_dma_write(ring, B43_DMA64_RXRINGHI,
+                                      ((ringbase >> 32) &
+                                       ~SSB_DMA_TRANSLATION_MASK)
+                                      | trans);
+                        b43_dma_write(ring, B43_DMA64_RXINDEX, 200);
+                } else {
+                        u32 ringbase = (u32) (ring->dmabase);
+
+                        addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
+                            >> SSB_DMA_TRANSLATION_SHIFT;
+                        value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
+                        value |= B43_DMA32_RXENABLE;
+                        value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
+                            & B43_DMA32_RXADDREXT_MASK;
+                        b43_dma_write(ring, B43_DMA32_RXCTL, value);
+                        b43_dma_write(ring, B43_DMA32_RXRING,
+                                      (ringbase & ~SSB_DMA_TRANSLATION_MASK)
+                                      | trans);
+                        b43_dma_write(ring, B43_DMA32_RXINDEX, 200);
+                }
+        }
+
+      out:
+        return err;
+}
+
+/* Shutdown the DMA controller. */
+static void dmacontroller_cleanup(struct b43_dmaring *ring)
+{
+        if (ring->tx) {
+                b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
+                                           ring->dma64);
+                if (ring->dma64) {
+                        b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
+                        b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
+                } else
+                        b43_dma_write(ring, B43_DMA32_TXRING, 0);
+        } else {
+                b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
+                                           ring->dma64);
+                if (ring->dma64) {
+                        b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
+                        b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
+                } else
+                        b43_dma_write(ring, B43_DMA32_RXRING, 0);
+        }
+}
+
+static void free_all_descbuffers(struct b43_dmaring *ring)
+{
+        struct b43_dmadesc_generic *desc;
+        struct b43_dmadesc_meta *meta;
+        int i;
+
+        if (!ring->used_slots)
+                return;
+        for (i = 0; i < ring->nr_slots; i++) {
+                desc = ring->ops->idx2desc(ring, i, &meta);
+
+                if (!meta->skb) {
+                        B43_WARN_ON(!ring->tx);
+                        continue;
+                }
+                if (ring->tx) {
+                        unmap_descbuffer(ring, meta->dmaaddr,
+                                         meta->skb->len, 1);
+                } else {
+                        unmap_descbuffer(ring, meta->dmaaddr,
+                                         ring->rx_buffersize, 0);
+                }
+                free_descriptor_buffer(ring, meta);
+        }
+}
+
+static u64 supported_dma_mask(struct b43_wldev *dev)
+{
+        u32 tmp;
+        u16 mmio_base;
+
+        tmp = b43_read32(dev, SSB_TMSHIGH);
+        if (tmp & SSB_TMSHIGH_DMA64)
+                return DMA_64BIT_MASK;
+        mmio_base = b43_dmacontroller_base(0, 0);
+        b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
+        tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
+        if (tmp & B43_DMA32_TXADDREXT_MASK)
+                return DMA_32BIT_MASK;
+
+        return DMA_30BIT_MASK;
+}
+
+/* Main initialization function. */
+static
+struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
+                                      int controller_index,
+                                      int for_tx, int dma64)
+{
+        struct b43_dmaring *ring;
+        int err;
+        int nr_slots;
+        dma_addr_t dma_test;
+
+        ring = kzalloc(sizeof(*ring), GFP_KERNEL);
+        if (!ring)
+                goto out;
+
+        nr_slots = B43_RXRING_SLOTS;
+        if (for_tx)
+                nr_slots = B43_TXRING_SLOTS;
+
+        ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
+                             GFP_KERNEL);
+        if (!ring->meta)
+                goto err_kfree_ring;
+        if (for_tx) {
+                ring->txhdr_cache = kcalloc(nr_slots,
+                                            sizeof(struct b43_txhdr_fw4),
+                                            GFP_KERNEL);
+                if (!ring->txhdr_cache)
+                        goto err_kfree_meta;
+
+                /* test for ability to dma to txhdr_cache */
+                dma_test = dma_map_single(dev->dev->dev,
+                                          ring->txhdr_cache,
+                                          sizeof(struct b43_txhdr_fw4),
+                                          DMA_TO_DEVICE);
+
+                if (dma_mapping_error(dma_test)) {
+                        /* ugh realloc */
+                        kfree(ring->txhdr_cache);
+                        ring->txhdr_cache = kcalloc(nr_slots,
+                                                    sizeof(struct
+                                                           b43_txhdr_fw4),
+                                                    GFP_KERNEL | GFP_DMA);
+                        if (!ring->txhdr_cache)
+                                goto err_kfree_meta;
+
+                        dma_test = dma_map_single(dev->dev->dev,
+                                                  ring->txhdr_cache,
+                                                  sizeof(struct b43_txhdr_fw4),
+                                                  DMA_TO_DEVICE);
+
+                        if (dma_mapping_error(dma_test))
+                                goto err_kfree_txhdr_cache;
+                }
+
+                dma_unmap_single(dev->dev->dev,
+                                 dma_test, sizeof(struct b43_txhdr_fw4),
+                                 DMA_TO_DEVICE);
+        }
+
+        ring->dev = dev;
+        ring->nr_slots = nr_slots;
+        ring->mmio_base = b43_dmacontroller_base(dma64, controller_index);
+        ring->index = controller_index;
+        ring->dma64 = !!dma64;
+        if (dma64)
+                ring->ops = &dma64_ops;
+        else
+                ring->ops = &dma32_ops;
+        if (for_tx) {
+                ring->tx = 1;
+                ring->current_slot = -1;
+        } else {
+                if (ring->index == 0) {
+                        ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
+                        ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
+                } else if (ring->index == 3) {
+                        ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
+                        ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
+                } else
+                        B43_WARN_ON(1);
+        }
+        spin_lock_init(&ring->lock);
+#ifdef CONFIG_B43_DEBUG
+        ring->last_injected_overflow = jiffies;
+#endif
+
+        err = alloc_ringmemory(ring);
+        if (err)
+                goto err_kfree_txhdr_cache;
+        err = dmacontroller_setup(ring);
+        if (err)
+                goto err_free_ringmemory;
+
+      out:
+        return ring;
+
+      err_free_ringmemory:
+        free_ringmemory(ring);
+      err_kfree_txhdr_cache:
+        kfree(ring->txhdr_cache);
+      err_kfree_meta:
+        kfree(ring->meta);
+      err_kfree_ring:
+        kfree(ring);
+        ring = NULL;
+        goto out;
+}
+
+/* Main cleanup function. */
+static void b43_destroy_dmaring(struct b43_dmaring *ring)
+{
+        if (!ring)
+                return;
+
+        b43dbg(ring->dev->wl, "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
+               (ring->dma64) ? "64" : "32",
+               ring->mmio_base,
+               (ring->tx) ? "TX" : "RX", ring->max_used_slots, ring->nr_slots);
+        /* Device IRQs are disabled prior entering this function,
+         * so no need to take care of concurrency with rx handler stuff.
+         */
+        dmacontroller_cleanup(ring);
+        free_all_descbuffers(ring);
+        free_ringmemory(ring);
+
+        kfree(ring->txhdr_cache);
+        kfree(ring->meta);
+        kfree(ring);
+}
+
+void b43_dma_free(struct b43_wldev *dev)
+{
+        struct b43_dma *dma;
+
+        if (b43_using_pio(dev))
+                return;
+        dma = &dev->dma;
+
+        b43_destroy_dmaring(dma->rx_ring3);
+        dma->rx_ring3 = NULL;
+        b43_destroy_dmaring(dma->rx_ring0);
+        dma->rx_ring0 = NULL;
+
+        b43_destroy_dmaring(dma->tx_ring5);
+        dma->tx_ring5 = NULL;
+        b43_destroy_dmaring(dma->tx_ring4);
+        dma->tx_ring4 = NULL;
+        b43_destroy_dmaring(dma->tx_ring3);
+        dma->tx_ring3 = NULL;
+        b43_destroy_dmaring(dma->tx_ring2);
+        dma->tx_ring2 = NULL;
+        b43_destroy_dmaring(dma->tx_ring1);
+        dma->tx_ring1 = NULL;
+        b43_destroy_dmaring(dma->tx_ring0);
+        dma->tx_ring0 = NULL;
+}
+
+int b43_dma_init(struct b43_wldev *dev)
+{
+        struct b43_dma *dma = &dev->dma;
+        struct b43_dmaring *ring;
+        int err;
+        u64 dmamask;
+        int dma64 = 0;
+
+        dmamask = supported_dma_mask(dev);
+        if (dmamask == DMA_64BIT_MASK)
+                dma64 = 1;
+
+        err = ssb_dma_set_mask(dev->dev, dmamask);
+        if (err) {
+#ifdef B43_PIO
+                b43warn(dev->wl, "DMA for this device not supported. "
+                        "Falling back to PIO\n");
+                dev->__using_pio = 1;
+                return -EAGAIN;
+#else
+                b43err(dev->wl, "DMA for this device not supported and "
+                       "no PIO support compiled in\n");
+                return -EOPNOTSUPP;
+#endif
+        }
+
+        err = -ENOMEM;
+        /* setup TX DMA channels. */
+        ring = b43_setup_dmaring(dev, 0, 1, dma64);
+        if (!ring)
+                goto out;
+        dma->tx_ring0 = ring;
+
+        ring = b43_setup_dmaring(dev, 1, 1, dma64);
+        if (!ring)
+                goto err_destroy_tx0;
+        dma->tx_ring1 = ring;
+
+        ring = b43_setup_dmaring(dev, 2, 1, dma64);
+        if (!ring)
+                goto err_destroy_tx1;
+        dma->tx_ring2 = ring;
+
+        ring = b43_setup_dmaring(dev, 3, 1, dma64);
+        if (!ring)
+                goto err_destroy_tx2;
+        dma->tx_ring3 = ring;
+
+        ring = b43_setup_dmaring(dev, 4, 1, dma64);
+        if (!ring)
+                goto err_destroy_tx3;
+        dma->tx_ring4 = ring;
+
+        ring = b43_setup_dmaring(dev, 5, 1, dma64);
+        if (!ring)
+                goto err_destroy_tx4;
+        dma->tx_ring5 = ring;
+
+        /* setup RX DMA channels. */
+        ring = b43_setup_dmaring(dev, 0, 0, dma64);
+        if (!ring)
+                goto err_destroy_tx5;
+        dma->rx_ring0 = ring;
+
+        if (dev->dev->id.revision < 5) {
+                ring = b43_setup_dmaring(dev, 3, 0, dma64);
+                if (!ring)
+                        goto err_destroy_rx0;
+                dma->rx_ring3 = ring;
+        }
+
+        b43dbg(dev->wl, "%d-bit DMA initialized\n",
+               (dmamask == DMA_64BIT_MASK) ? 64 :
+               (dmamask == DMA_32BIT_MASK) ? 32 : 30);
+        err = 0;
+      out:
+        return err;
+
+      err_destroy_rx0:
+        b43_destroy_dmaring(dma->rx_ring0);
+        dma->rx_ring0 = NULL;
+      err_destroy_tx5:
+        b43_destroy_dmaring(dma->tx_ring5);
+        dma->tx_ring5 = NULL;
+      err_destroy_tx4:
+        b43_destroy_dmaring(dma->tx_ring4);
+        dma->tx_ring4 = NULL;
+      err_destroy_tx3:
+        b43_destroy_dmaring(dma->tx_ring3);
+        dma->tx_ring3 = NULL;
+      err_destroy_tx2:
+        b43_destroy_dmaring(dma->tx_ring2);
+        dma->tx_ring2 = NULL;
+      err_destroy_tx1:
+        b43_destroy_dmaring(dma->tx_ring1);
+        dma->tx_ring1 = NULL;
+      err_destroy_tx0:
+        b43_destroy_dmaring(dma->tx_ring0);
+        dma->tx_ring0 = NULL;
+        goto out;
+}
+
+/* Generate a cookie for the TX header. */
+static u16 generate_cookie(struct b43_dmaring *ring, int slot)
+{
+        u16 cookie = 0x1000;
+
+        /* Use the upper 4 bits of the cookie as
+         * DMA controller ID and store the slot number
+         * in the lower 12 bits.
+         * Note that the cookie must never be 0, as this
+         * is a special value used in RX path.
+         */
+        switch (ring->index) {
+        case 0:
+                cookie = 0xA000;
+                break;
+        case 1:
+                cookie = 0xB000;
+                break;
+        case 2:
+                cookie = 0xC000;
+                break;
+        case 3:
+                cookie = 0xD000;
+                break;
+        case 4:
+                cookie = 0xE000;
+                break;
+        case 5:
+                cookie = 0xF000;
+                break;
+        }
+        B43_WARN_ON(slot & ~0x0FFF);
+        cookie |= (u16) slot;
+
+        return cookie;
+}
+
+/* Inspect a cookie and find out to which controller/slot it belongs. */
+static
+struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
+{
+        struct b43_dma *dma = &dev->dma;
+        struct b43_dmaring *ring = NULL;
+
+        switch (cookie & 0xF000) {
+        case 0xA000:
+                ring = dma->tx_ring0;
+                break;
+        case 0xB000:
+                ring = dma->tx_ring1;
+                break;
+        case 0xC000:
+                ring = dma->tx_ring2;
+                break;
+        case 0xD000:
+                ring = dma->tx_ring3;
+                break;
+        case 0xE000:
+                ring = dma->tx_ring4;
+                break;
+        case 0xF000:
+                ring = dma->tx_ring5;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        *slot = (cookie & 0x0FFF);
+        B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
+
+        return ring;
+}
+
+static int dma_tx_fragment(struct b43_dmaring *ring,
+                           struct sk_buff *skb,
+                           struct ieee80211_tx_control *ctl)
+{
+        const struct b43_dma_ops *ops = ring->ops;
+        u8 *header;
+        int slot;
+        int err;
+        struct b43_dmadesc_generic *desc;
+        struct b43_dmadesc_meta *meta;
+        struct b43_dmadesc_meta *meta_hdr;
+        struct sk_buff *bounce_skb;
+
+#define SLOTS_PER_PACKET  2
+        B43_WARN_ON(skb_shinfo(skb)->nr_frags);
+
+        /* Get a slot for the header. */
+        slot = request_slot(ring);
+        desc = ops->idx2desc(ring, slot, &meta_hdr);
+        memset(meta_hdr, 0, sizeof(*meta_hdr));
+
+        header = &(ring->txhdr_cache[slot * sizeof(struct b43_txhdr_fw4)]);
+        b43_generate_txhdr(ring->dev, header,
+                           skb->data, skb->len, ctl,
+                           generate_cookie(ring, slot));
+
+        meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
+                                           sizeof(struct b43_txhdr_fw4), 1);
+        if (dma_mapping_error(meta_hdr->dmaaddr))
+                return -EIO;
+        ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
+                             sizeof(struct b43_txhdr_fw4), 1, 0, 0);
+
+        /* Get a slot for the payload. */
+        slot = request_slot(ring);
+        desc = ops->idx2desc(ring, slot, &meta);
+        memset(meta, 0, sizeof(*meta));
+
+        memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
+        meta->skb = skb;
+        meta->is_last_fragment = 1;
+
+        meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
+        /* create a bounce buffer in zone_dma on mapping failure. */
+        if (dma_mapping_error(meta->dmaaddr)) {
+                bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
+                if (!bounce_skb) {
+                        err = -ENOMEM;
+                        goto out_unmap_hdr;
+                }
+
+                memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
+                dev_kfree_skb_any(skb);
+                skb = bounce_skb;
+                meta->skb = skb;
+                meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
+                if (dma_mapping_error(meta->dmaaddr)) {
+                        err = -EIO;
+                        goto out_free_bounce;
+                }
+        }
+
+        ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
+
+        /* Now transfer the whole frame. */
+        wmb();
+        ops->poke_tx(ring, next_slot(ring, slot));
+        return 0;
+
+      out_free_bounce:
+        dev_kfree_skb_any(skb);
+      out_unmap_hdr:
+        unmap_descbuffer(ring, meta_hdr->dmaaddr,
+                         sizeof(struct b43_txhdr_fw4), 1);
+        return err;
+}
+
+static inline int should_inject_overflow(struct b43_dmaring *ring)
+{
+#ifdef CONFIG_B43_DEBUG
+        if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
+                /* Check if we should inject another ringbuffer overflow
+                 * to test handling of this situation in the stack. */
+                unsigned long next_overflow;
+
+                next_overflow = ring->last_injected_overflow + HZ;
+                if (time_after(jiffies, next_overflow)) {
+                        ring->last_injected_overflow = jiffies;
+                        b43dbg(ring->dev->wl,
+                               "Injecting TX ring overflow on "
+                               "DMA controller %d\n", ring->index);
+                        return 1;
+                }
+        }
+#endif /* CONFIG_B43_DEBUG */
+        return 0;
+}
+
+int b43_dma_tx(struct b43_wldev *dev,
+               struct sk_buff *skb, struct ieee80211_tx_control *ctl)
+{
+        struct b43_dmaring *ring;
+        int err = 0;
+        unsigned long flags;
+
+        ring = priority_to_txring(dev, ctl->queue);
+        spin_lock_irqsave(&ring->lock, flags);
+        B43_WARN_ON(!ring->tx);
+        if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
+                b43warn(dev->wl, "DMA queue overflow\n");
+                err = -ENOSPC;
+                goto out_unlock;
+        }
+        /* Check if the queue was stopped in mac80211,
+         * but we got called nevertheless.
+         * That would be a mac80211 bug. */
+        B43_WARN_ON(ring->stopped);
+
+        err = dma_tx_fragment(ring, skb, ctl);
+        if (unlikely(err)) {
+                b43err(dev->wl, "DMA tx mapping failure\n");
+                goto out_unlock;
+        }
+        ring->nr_tx_packets++;
+        if ((free_slots(ring) < SLOTS_PER_PACKET) ||
+            should_inject_overflow(ring)) {
+                /* This TX ring is full. */
+                ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
+                ring->stopped = 1;
+                if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
+                        b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
+                }
+        }
+      out_unlock:
+        spin_unlock_irqrestore(&ring->lock, flags);
+
+        return err;
+}
+
+void b43_dma_handle_txstatus(struct b43_wldev *dev,
+                             const struct b43_txstatus *status)
+{
+        const struct b43_dma_ops *ops;
+        struct b43_dmaring *ring;
+        struct b43_dmadesc_generic *desc;
+        struct b43_dmadesc_meta *meta;
+        int slot;
+
+        ring = parse_cookie(dev, status->cookie, &slot);
+        if (unlikely(!ring))
+                return;
+        B43_WARN_ON(!irqs_disabled());
+        spin_lock(&ring->lock);
+
+        B43_WARN_ON(!ring->tx);
+        ops = ring->ops;
+        while (1) {
+                B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
+                desc = ops->idx2desc(ring, slot, &meta);
+
+                if (meta->skb)
+                        unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
+                                         1);
+                else
+                        unmap_descbuffer(ring, meta->dmaaddr,
+                                         sizeof(struct b43_txhdr_fw4), 1);
+
+                if (meta->is_last_fragment) {
+                        B43_WARN_ON(!meta->skb);
+                        /* Call back to inform the ieee80211 subsystem about the
+                         * status of the transmission.
+                         * Some fields of txstat are already filled in dma_tx().
+                         */
+                        if (status->acked) {
+                                meta->txstat.flags |= IEEE80211_TX_STATUS_ACK;
+                        } else {
+                                if (!(meta->txstat.control.flags
+                                      & IEEE80211_TXCTL_NO_ACK))
+                                        meta->txstat.excessive_retries = 1;
+                        }
+                        if (status->frame_count == 0) {
+                                /* The frame was not transmitted at all. */
+                                meta->txstat.retry_count = 0;
+                        } else
+                                meta->txstat.retry_count = status->frame_count - 1;
+                        ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
+                                                    &(meta->txstat));
+                        /* skb is freed by ieee80211_tx_status_irqsafe() */
+                        meta->skb = NULL;
+                } else {
+                        /* No need to call free_descriptor_buffer here, as
+                         * this is only the txhdr, which is not allocated.
+                         */
+                        B43_WARN_ON(meta->skb);
+                }
+
+                /* Everything unmapped and free'd. So it's not used anymore. */
+                ring->used_slots--;
+
+                if (meta->is_last_fragment)
+                        break;
+                slot = next_slot(ring, slot);
+        }
+        dev->stats.last_tx = jiffies;
+        if (ring->stopped) {
+                B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
+                ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
+                ring->stopped = 0;
+                if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
+                        b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
+                }
+        }
+
+        spin_unlock(&ring->lock);
+}
+
+void b43_dma_get_tx_stats(struct b43_wldev *dev,
+                          struct ieee80211_tx_queue_stats *stats)
+{
+        const int nr_queues = dev->wl->hw->queues;
+        struct b43_dmaring *ring;
+        struct ieee80211_tx_queue_stats_data *data;
+        unsigned long flags;
+        int i;
+
+        for (i = 0; i < nr_queues; i++) {
+                data = &(stats->data[i]);
+                ring = priority_to_txring(dev, i);
+
+                spin_lock_irqsave(&ring->lock, flags);
+                data->len = ring->used_slots / SLOTS_PER_PACKET;
+                data->limit = ring->nr_slots / SLOTS_PER_PACKET;
+                data->count = ring->nr_tx_packets;
+                spin_unlock_irqrestore(&ring->lock, flags);
+        }
+}
+
+static void dma_rx(struct b43_dmaring *ring, int *slot)
+{
+        const struct b43_dma_ops *ops = ring->ops;
+        struct b43_dmadesc_generic *desc;
+        struct b43_dmadesc_meta *meta;
+        struct b43_rxhdr_fw4 *rxhdr;
+        struct sk_buff *skb;
+        u16 len;
+        int err;
+        dma_addr_t dmaaddr;
+
+        desc = ops->idx2desc(ring, *slot, &meta);
+
+        sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
+        skb = meta->skb;
+
+        if (ring->index == 3) {
+                /* We received an xmit status. */
+                struct b43_hwtxstatus *hw = (struct b43_hwtxstatus *)skb->data;
+                int i = 0;
+
+                while (hw->cookie == 0) {
+                        if (i > 100)
+                                break;
+                        i++;
+                        udelay(2);
+                        barrier();
+                }
+                b43_handle_hwtxstatus(ring->dev, hw);
+                /* recycle the descriptor buffer. */
+                sync_descbuffer_for_device(ring, meta->dmaaddr,
+                                           ring->rx_buffersize);
+
+                return;
+        }
+        rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
+        len = le16_to_cpu(rxhdr->frame_len);
+        if (len == 0) {
+                int i = 0;
+
+                do {
+                        udelay(2);
+                        barrier();
+                        len = le16_to_cpu(rxhdr->frame_len);
+                } while (len == 0 && i++ < 5);
+                if (unlikely(len == 0)) {
+                        /* recycle the descriptor buffer. */
+                        sync_descbuffer_for_device(ring, meta->dmaaddr,
+                                                   ring->rx_buffersize);
+                        goto drop;
+                }
+        }
+        if (unlikely(len > ring->rx_buffersize)) {
+                /* The data did not fit into one descriptor buffer
+                 * and is split over multiple buffers.
+                 * This should never happen, as we try to allocate buffers
+                 * big enough. So simply ignore this packet.
+                 */
+                int cnt = 0;
+                s32 tmp = len;
+
+                while (1) {
+                        desc = ops->idx2desc(ring, *slot, &meta);
+                        /* recycle the descriptor buffer. */
+                        sync_descbuffer_for_device(ring, meta->dmaaddr,
+                                                   ring->rx_buffersize);
+                        *slot = next_slot(ring, *slot);
+                        cnt++;
+                        tmp -= ring->rx_buffersize;
+                        if (tmp <= 0)
+                                break;
+                }
+                b43err(ring->dev->wl, "DMA RX buffer too small "
+                       "(len: %u, buffer: %u, nr-dropped: %d)\n",
+                       len, ring->rx_buffersize, cnt);
+                goto drop;
+        }
+
+        dmaaddr = meta->dmaaddr;
+        err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
+        if (unlikely(err)) {
+                b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
+                sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
+                goto drop;
+        }
+
+        unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
+        skb_put(skb, len + ring->frameoffset);
+        skb_pull(skb, ring->frameoffset);
+
+        b43_rx(ring->dev, skb, rxhdr);
+      drop:
+        return;
+}
+
+void b43_dma_rx(struct b43_dmaring *ring)
+{
+        const struct b43_dma_ops *ops = ring->ops;
+        int slot, current_slot;
+        int used_slots = 0;
+
+        B43_WARN_ON(ring->tx);
+        current_slot = ops->get_current_rxslot(ring);
+        B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
+
+        slot = ring->current_slot;
+        for (; slot != current_slot; slot = next_slot(ring, slot)) {
+                dma_rx(ring, &slot);
+                update_max_used_slots(ring, ++used_slots);
+        }
+        ops->set_current_rxslot(ring, slot);
+        ring->current_slot = slot;
+}
+
+static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ring->lock, flags);
+        B43_WARN_ON(!ring->tx);
+        ring->ops->tx_suspend(ring);
+        spin_unlock_irqrestore(&ring->lock, flags);
+}
+
+static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ring->lock, flags);
+        B43_WARN_ON(!ring->tx);
+        ring->ops->tx_resume(ring);
+        spin_unlock_irqrestore(&ring->lock, flags);
+}
+
+void b43_dma_tx_suspend(struct b43_wldev *dev)
+{
+        b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
+        b43_dma_tx_suspend_ring(dev->dma.tx_ring0);
+        b43_dma_tx_suspend_ring(dev->dma.tx_ring1);
+        b43_dma_tx_suspend_ring(dev->dma.tx_ring2);
+        b43_dma_tx_suspend_ring(dev->dma.tx_ring3);
+        b43_dma_tx_suspend_ring(dev->dma.tx_ring4);
+        b43_dma_tx_suspend_ring(dev->dma.tx_ring5);
+}
+
+void b43_dma_tx_resume(struct b43_wldev *dev)
+{
+        b43_dma_tx_resume_ring(dev->dma.tx_ring5);
+        b43_dma_tx_resume_ring(dev->dma.tx_ring4);
+        b43_dma_tx_resume_ring(dev->dma.tx_ring3);
+        b43_dma_tx_resume_ring(dev->dma.tx_ring2);
+        b43_dma_tx_resume_ring(dev->dma.tx_ring1);
+        b43_dma_tx_resume_ring(dev->dma.tx_ring0);
+        b43_power_saving_ctl_bits(dev, 0);
+}
diff --git a/drivers/net/wireless/b43/dma.h b/drivers/net/wireless/b43/dma.h
new file mode 100644
index 000000000000..3eed185be725
--- /dev/null
+++ b/drivers/net/wireless/b43/dma.h
@@ -0,0 +1,337 @@
+#ifndef B43_DMA_H_
+#define B43_DMA_H_
+
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/linkage.h>
+#include <asm/atomic.h>
+
+#include "b43.h"
+
+/* DMA-Interrupt reasons. */
+#define B43_DMAIRQ_FATALMASK    ((1 << 10) | (1 << 11) | (1 << 12) \
+                                         | (1 << 14) | (1 << 15))
+#define B43_DMAIRQ_NONFATALMASK (1 << 13)
+#define B43_DMAIRQ_RX_DONE              (1 << 16)
+
+/*** 32-bit DMA Engine. ***/
+
+/* 32-bit DMA controller registers. */
+#define B43_DMA32_TXCTL                         0x00
+#define         B43_DMA32_TXENABLE                      0x00000001
+#define         B43_DMA32_TXSUSPEND                     0x00000002
+#define         B43_DMA32_TXLOOPBACK            0x00000004
+#define         B43_DMA32_TXFLUSH                       0x00000010
+#define         B43_DMA32_TXADDREXT_MASK                0x00030000
+#define         B43_DMA32_TXADDREXT_SHIFT               16
+#define B43_DMA32_TXRING                                0x04
+#define B43_DMA32_TXINDEX                               0x08
+#define B43_DMA32_TXSTATUS                              0x0C
+#define         B43_DMA32_TXDPTR                        0x00000FFF
+#define         B43_DMA32_TXSTATE                       0x0000F000
+#define                 B43_DMA32_TXSTAT_DISABLED       0x00000000
+#define                 B43_DMA32_TXSTAT_ACTIVE 0x00001000
+#define                 B43_DMA32_TXSTAT_IDLEWAIT       0x00002000
+#define                 B43_DMA32_TXSTAT_STOPPED        0x00003000
+#define                 B43_DMA32_TXSTAT_SUSP   0x00004000
+#define         B43_DMA32_TXERROR                       0x000F0000
+#define                 B43_DMA32_TXERR_NOERR   0x00000000
+#define                 B43_DMA32_TXERR_PROT    0x00010000
+#define                 B43_DMA32_TXERR_UNDERRUN        0x00020000
+#define                 B43_DMA32_TXERR_BUFREAD 0x00030000
+#define                 B43_DMA32_TXERR_DESCREAD        0x00040000
+#define         B43_DMA32_TXACTIVE                      0xFFF00000
+#define B43_DMA32_RXCTL                         0x10
+#define         B43_DMA32_RXENABLE                      0x00000001
+#define         B43_DMA32_RXFROFF_MASK          0x000000FE
+#define         B43_DMA32_RXFROFF_SHIFT         1
+#define         B43_DMA32_RXDIRECTFIFO          0x00000100
+#define         B43_DMA32_RXADDREXT_MASK                0x00030000
+#define         B43_DMA32_RXADDREXT_SHIFT               16
+#define B43_DMA32_RXRING                                0x14
+#define B43_DMA32_RXINDEX                               0x18
+#define B43_DMA32_RXSTATUS                              0x1C
+#define         B43_DMA32_RXDPTR                        0x00000FFF
+#define         B43_DMA32_RXSTATE                       0x0000F000
+#define                 B43_DMA32_RXSTAT_DISABLED       0x00000000
+#define                 B43_DMA32_RXSTAT_ACTIVE 0x00001000
+#define                 B43_DMA32_RXSTAT_IDLEWAIT       0x00002000
+#define                 B43_DMA32_RXSTAT_STOPPED        0x00003000
+#define         B43_DMA32_RXERROR                       0x000F0000
+#define                 B43_DMA32_RXERR_NOERR   0x00000000
+#define                 B43_DMA32_RXERR_PROT    0x00010000
+#define                 B43_DMA32_RXERR_OVERFLOW        0x00020000
+#define                 B43_DMA32_RXERR_BUFWRITE        0x00030000
+#define                 B43_DMA32_RXERR_DESCREAD        0x00040000
+#define         B43_DMA32_RXACTIVE                      0xFFF00000
+
+/* 32-bit DMA descriptor. */
+struct b43_dmadesc32 {
+        __le32 control;
+        __le32 address;
+} __attribute__ ((__packed__));
+#define B43_DMA32_DCTL_BYTECNT          0x00001FFF
+#define B43_DMA32_DCTL_ADDREXT_MASK             0x00030000
+#define B43_DMA32_DCTL_ADDREXT_SHIFT    16
+#define B43_DMA32_DCTL_DTABLEEND                0x10000000
+#define B43_DMA32_DCTL_IRQ                      0x20000000
+#define B43_DMA32_DCTL_FRAMEEND         0x40000000
+#define B43_DMA32_DCTL_FRAMESTART               0x80000000
+
+/*** 64-bit DMA Engine. ***/
+
+/* 64-bit DMA controller registers. */
+#define B43_DMA64_TXCTL                         0x00
+#define         B43_DMA64_TXENABLE                      0x00000001
+#define         B43_DMA64_TXSUSPEND                     0x00000002
+#define         B43_DMA64_TXLOOPBACK            0x00000004
+#define         B43_DMA64_TXFLUSH                       0x00000010
+#define         B43_DMA64_TXADDREXT_MASK                0x00030000
+#define         B43_DMA64_TXADDREXT_SHIFT               16
+#define B43_DMA64_TXINDEX                               0x04
+#define B43_DMA64_TXRINGLO                              0x08
+#define B43_DMA64_TXRINGHI                              0x0C
+#define B43_DMA64_TXSTATUS                              0x10
+#define         B43_DMA64_TXSTATDPTR            0x00001FFF
+#define         B43_DMA64_TXSTAT                        0xF0000000
+#define                 B43_DMA64_TXSTAT_DISABLED       0x00000000
+#define                 B43_DMA64_TXSTAT_ACTIVE 0x10000000
+#define                 B43_DMA64_TXSTAT_IDLEWAIT       0x20000000
+#define                 B43_DMA64_TXSTAT_STOPPED        0x30000000
+#define                 B43_DMA64_TXSTAT_SUSP   0x40000000
+#define B43_DMA64_TXERROR                               0x14
+#define         B43_DMA64_TXERRDPTR                     0x0001FFFF
+#define         B43_DMA64_TXERR                 0xF0000000
+#define                 B43_DMA64_TXERR_NOERR   0x00000000
+#define                 B43_DMA64_TXERR_PROT    0x10000000
+#define                 B43_DMA64_TXERR_UNDERRUN        0x20000000
+#define                 B43_DMA64_TXERR_TRANSFER        0x30000000
+#define                 B43_DMA64_TXERR_DESCREAD        0x40000000
+#define                 B43_DMA64_TXERR_CORE    0x50000000
+#define B43_DMA64_RXCTL                         0x20
+#define         B43_DMA64_RXENABLE                      0x00000001
+#define         B43_DMA64_RXFROFF_MASK          0x000000FE
+#define         B43_DMA64_RXFROFF_SHIFT         1
+#define         B43_DMA64_RXDIRECTFIFO          0x00000100
+#define         B43_DMA64_RXADDREXT_MASK                0x00030000
+#define         B43_DMA64_RXADDREXT_SHIFT               16
+#define B43_DMA64_RXINDEX                               0x24
+#define B43_DMA64_RXRINGLO                              0x28
+#define B43_DMA64_RXRINGHI                              0x2C
+#define B43_DMA64_RXSTATUS                              0x30
+#define         B43_DMA64_RXSTATDPTR            0x00001FFF
+#define         B43_DMA64_RXSTAT                        0xF0000000
+#define                 B43_DMA64_RXSTAT_DISABLED       0x00000000
+#define                 B43_DMA64_RXSTAT_ACTIVE 0x10000000
+#define                 B43_DMA64_RXSTAT_IDLEWAIT       0x20000000
+#define                 B43_DMA64_RXSTAT_STOPPED        0x30000000
+#define                 B43_DMA64_RXSTAT_SUSP   0x40000000
+#define B43_DMA64_RXERROR                               0x34
+#define         B43_DMA64_RXERRDPTR                     0x0001FFFF
+#define         B43_DMA64_RXERR                 0xF0000000
+#define                 B43_DMA64_RXERR_NOERR   0x00000000
+#define                 B43_DMA64_RXERR_PROT    0x10000000
+#define                 B43_DMA64_RXERR_UNDERRUN        0x20000000
+#define                 B43_DMA64_RXERR_TRANSFER        0x30000000
+#define                 B43_DMA64_RXERR_DESCREAD        0x40000000
+#define                 B43_DMA64_RXERR_CORE    0x50000000
+
+/* 64-bit DMA descriptor. */
+struct b43_dmadesc64 {
+        __le32 control0;
+        __le32 control1;
+        __le32 address_low;
+        __le32 address_high;
+} __attribute__ ((__packed__));
+#define B43_DMA64_DCTL0_DTABLEEND               0x10000000
+#define B43_DMA64_DCTL0_IRQ                     0x20000000
+#define B43_DMA64_DCTL0_FRAMEEND                0x40000000
+#define B43_DMA64_DCTL0_FRAMESTART              0x80000000
+#define B43_DMA64_DCTL1_BYTECNT         0x00001FFF
+#define B43_DMA64_DCTL1_ADDREXT_MASK    0x00030000
+#define B43_DMA64_DCTL1_ADDREXT_SHIFT   16
+
+struct b43_dmadesc_generic {
+        union {
+                struct b43_dmadesc32 dma32;
+                struct b43_dmadesc64 dma64;
+        } __attribute__ ((__packed__));
+} __attribute__ ((__packed__));
+
+/* Misc DMA constants */
+#define B43_DMA_RINGMEMSIZE             PAGE_SIZE
+#define B43_DMA0_RX_FRAMEOFFSET 30
+#define B43_DMA3_RX_FRAMEOFFSET 0
+
+/* DMA engine tuning knobs */
+#define B43_TXRING_SLOTS                128
+#define B43_RXRING_SLOTS                64
+#define B43_DMA0_RX_BUFFERSIZE  (2304 + 100)
+#define B43_DMA3_RX_BUFFERSIZE  16
+
+#ifdef CONFIG_B43_DMA
+
+struct sk_buff;
+struct b43_private;
+struct b43_txstatus;
+
+struct b43_dmadesc_meta {
+        /* The kernel DMA-able buffer. */
+        struct sk_buff *skb;
+        /* DMA base bus-address of the descriptor buffer. */
+        dma_addr_t dmaaddr;
+        /* ieee80211 TX status. Only used once per 802.11 frag. */
+        bool is_last_fragment;
+        struct ieee80211_tx_status txstat;
+};
+
+struct b43_dmaring;
+
+/* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
+struct b43_dma_ops {
+        struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
+                                                 int slot,
+                                                 struct b43_dmadesc_meta **
+                                                 meta);
+        void (*fill_descriptor) (struct b43_dmaring * ring,
+                                 struct b43_dmadesc_generic * desc,
+                                 dma_addr_t dmaaddr, u16 bufsize, int start,
+                                 int end, int irq);
+        void (*poke_tx) (struct b43_dmaring * ring, int slot);
+        void (*tx_suspend) (struct b43_dmaring * ring);
+        void (*tx_resume) (struct b43_dmaring * ring);
+        int (*get_current_rxslot) (struct b43_dmaring * ring);
+        void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
+};
+
+struct b43_dmaring {
+        /* Lowlevel DMA ops. */
+        const struct b43_dma_ops *ops;
+        /* Kernel virtual base address of the ring memory. */
+        void *descbase;
+        /* Meta data about all descriptors. */
+        struct b43_dmadesc_meta *meta;
+        /* Cache of TX headers for each slot.
+         * This is to avoid an allocation on each TX.
+         * This is NULL for an RX ring.
+         */
+        u8 *txhdr_cache;
+        /* (Unadjusted) DMA base bus-address of the ring memory. */
+        dma_addr_t dmabase;
+        /* Number of descriptor slots in the ring. */
+        int nr_slots;
+        /* Number of used descriptor slots. */
+        int used_slots;
+        /* Currently used slot in the ring. */
+        int current_slot;
+        /* Total number of packets sent. Statistics only. */
+        unsigned int nr_tx_packets;
+        /* Frameoffset in octets. */
+        u32 frameoffset;
+        /* Descriptor buffer size. */
+        u16 rx_buffersize;
+        /* The MMIO base register of the DMA controller. */
+        u16 mmio_base;
+        /* DMA controller index number (0-5). */
+        int index;
+        /* Boolean. Is this a TX ring? */
+        bool tx;
+        /* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
+        bool dma64;
+        /* Boolean. Is this ring stopped at ieee80211 level? */
+        bool stopped;
+        /* Lock, only used for TX. */
+        spinlock_t lock;
+        struct b43_wldev *dev;
+#ifdef CONFIG_B43_DEBUG
+        /* Maximum number of used slots. */
+        int max_used_slots;
+        /* Last time we injected a ring overflow. */
+        unsigned long last_injected_overflow;
+#endif                          /* CONFIG_B43_DEBUG */
+};
+
+static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
+{
+        return b43_read32(ring->dev, ring->mmio_base + offset);
+}
+
+static inline
+    void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
+{
+        b43_write32(ring->dev, ring->mmio_base + offset, value);
+}
+
+int b43_dma_init(struct b43_wldev *dev);
+void b43_dma_free(struct b43_wldev *dev);
+
+int b43_dmacontroller_rx_reset(struct b43_wldev *dev,
+                               u16 dmacontroller_mmio_base, int dma64);
+int b43_dmacontroller_tx_reset(struct b43_wldev *dev,
+                               u16 dmacontroller_mmio_base, int dma64);
+
+u16 b43_dmacontroller_base(int dma64bit, int dmacontroller_idx);
+
+void b43_dma_tx_suspend(struct b43_wldev *dev);
+void b43_dma_tx_resume(struct b43_wldev *dev);
+
+void b43_dma_get_tx_stats(struct b43_wldev *dev,
+                          struct ieee80211_tx_queue_stats *stats);
+
+int b43_dma_tx(struct b43_wldev *dev,
+               struct sk_buff *skb, struct ieee80211_tx_control *ctl);
+void b43_dma_handle_txstatus(struct b43_wldev *dev,
+                             const struct b43_txstatus *status);
+
+void b43_dma_rx(struct b43_dmaring *ring);
+
+#else /* CONFIG_B43_DMA */
+
+static inline int b43_dma_init(struct b43_wldev *dev)
+{
+        return 0;
+}
+static inline void b43_dma_free(struct b43_wldev *dev)
+{
+}
+static inline
+    int b43_dmacontroller_rx_reset(struct b43_wldev *dev,
+                                   u16 dmacontroller_mmio_base, int dma64)
+{
+        return 0;
+}
+static inline
+    int b43_dmacontroller_tx_reset(struct b43_wldev *dev,
+                                   u16 dmacontroller_mmio_base, int dma64)
+{
+        return 0;
+}
+static inline
+    void b43_dma_get_tx_stats(struct b43_wldev *dev,
+                              struct ieee80211_tx_queue_stats *stats)
+{
+}
+static inline
+    int b43_dma_tx(struct b43_wldev *dev,
+                   struct sk_buff *skb, struct ieee80211_tx_control *ctl)
+{
+        return 0;
+}
+static inline
+    void b43_dma_handle_txstatus(struct b43_wldev *dev,
+                                 const struct b43_txstatus *status)
+{
+}
+static inline void b43_dma_rx(struct b43_dmaring *ring)
+{
+}
+static inline void b43_dma_tx_suspend(struct b43_wldev *dev)
+{
+}
+static inline void b43_dma_tx_resume(struct b43_wldev *dev)
+{
+}
+
+#endif /* CONFIG_B43_DMA */
+#endif /* B43_DMA_H_ */
diff --git a/drivers/net/wireless/b43/leds.c b/drivers/net/wireless/b43/leds.c
new file mode 100644
index 000000000000..535f960412d7
--- /dev/null
+++ b/drivers/net/wireless/b43/leds.c
@@ -0,0 +1,299 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+                     Stefano Brivio <st3@riseup.net>
+                     Michael Buesch <mb@bu3sch.de>
+                     Danny van Dyk <kugelfang@gentoo.org>
+                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "b43.h"
+#include "leds.h"
+#include "main.h"
+
+static void b43_led_changestate(struct b43_led *led)
+{
+        struct b43_wldev *dev = led->dev;
+        const int index = b43_led_index(led);
+        const u16 mask = (1 << index);
+        u16 ledctl;
+
+        B43_WARN_ON(!(index >= 0 && index < B43_NR_LEDS));
+        B43_WARN_ON(!led->blink_interval);
+        ledctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL);
+        ledctl = (ledctl & mask) ? (ledctl & ~mask) : (ledctl | mask);
+        b43_write16(dev, B43_MMIO_GPIO_CONTROL, ledctl);
+}
+
+static void b43_led_blink(unsigned long d)
+{
+        struct b43_led *led = (struct b43_led *)d;
+        struct b43_wldev *dev = led->dev;
+        unsigned long flags;
+
+        spin_lock_irqsave(&dev->wl->leds_lock, flags);
+        if (led->blink_interval) {
+                b43_led_changestate(led);
+                mod_timer(&led->blink_timer, jiffies + led->blink_interval);
+        }
+        spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
+
+static void b43_led_blink_start(struct b43_led *led, unsigned long interval)
+{
+        if (led->blink_interval)
+                return;
+        led->blink_interval = interval;
+        b43_led_changestate(led);
+        led->blink_timer.expires = jiffies + interval;
+        add_timer(&led->blink_timer);
+}
+
+static void b43_led_blink_stop(struct b43_led *led, int sync)
+{
+        struct b43_wldev *dev = led->dev;
+        const int index = b43_led_index(led);
+        u16 ledctl;
+
+        if (!led->blink_interval)
+                return;
+        if (unlikely(sync))
+                del_timer_sync(&led->blink_timer);
+        else
+                del_timer(&led->blink_timer);
+        led->blink_interval = 0;
+
+        /* Make sure the LED is turned off. */
+        B43_WARN_ON(!(index >= 0 && index < B43_NR_LEDS));
+        ledctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL);
+        if (led->activelow)
+                ledctl |= (1 << index);
+        else
+                ledctl &= ~(1 << index);
+        b43_write16(dev, B43_MMIO_GPIO_CONTROL, ledctl);
+}
+
+static void b43_led_init_hardcoded(struct b43_wldev *dev,
+                                   struct b43_led *led, int led_index)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+
+        /* This function is called, if the behaviour (and activelow)
+         * information for a LED is missing in the SPROM.
+         * We hardcode the behaviour values for various devices here.
+         * Note that the B43_LED_TEST_XXX behaviour values can
+         * be used to figure out which led is mapped to which index.
+         */
+
+        switch (led_index) {
+        case 0:
+                led->behaviour = B43_LED_ACTIVITY;
+                led->activelow = 1;
+                if (bus->boardinfo.vendor == PCI_VENDOR_ID_COMPAQ)
+                        led->behaviour = B43_LED_RADIO_ALL;
+                break;
+        case 1:
+                led->behaviour = B43_LED_RADIO_B;
+                if (bus->boardinfo.vendor == PCI_VENDOR_ID_ASUSTEK)
+                        led->behaviour = B43_LED_ASSOC;
+                break;
+        case 2:
+                led->behaviour = B43_LED_RADIO_A;
+                break;
+        case 3:
+                led->behaviour = B43_LED_OFF;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+int b43_leds_init(struct b43_wldev *dev)
+{
+        struct b43_led *led;
+        u8 sprom[4];
+        int i;
+
+        sprom[0] = dev->dev->bus->sprom.r1.gpio0;
+        sprom[1] = dev->dev->bus->sprom.r1.gpio1;
+        sprom[2] = dev->dev->bus->sprom.r1.gpio2;
+        sprom[3] = dev->dev->bus->sprom.r1.gpio3;
+
+        for (i = 0; i < B43_NR_LEDS; i++) {
+                led = &(dev->leds[i]);
+                led->dev = dev;
+                setup_timer(&led->blink_timer,
+                            b43_led_blink, (unsigned long)led);
+
+                if (sprom[i] == 0xFF) {
+                        b43_led_init_hardcoded(dev, led, i);
+                } else {
+                        led->behaviour = sprom[i] & B43_LED_BEHAVIOUR;
+                        led->activelow = !!(sprom[i] & B43_LED_ACTIVELOW);
+                }
+        }
+
+        return 0;
+}
+
+void b43_leds_exit(struct b43_wldev *dev)
+{
+        struct b43_led *led;
+        int i;
+
+        for (i = 0; i < B43_NR_LEDS; i++) {
+                led = &(dev->leds[i]);
+                b43_led_blink_stop(led, 1);
+        }
+        b43_leds_switch_all(dev, 0);
+}
+
+void b43_leds_update(struct b43_wldev *dev, int activity)
+{
+        struct b43_led *led;
+        struct b43_phy *phy = &dev->phy;
+        const int transferring =
+            (jiffies - dev->stats.last_tx) < B43_LED_XFER_THRES;
+        int i, turn_on;
+        unsigned long interval = 0;
+        u16 ledctl;
+        unsigned long flags;
+
+        spin_lock_irqsave(&dev->wl->leds_lock, flags);
+        ledctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL);
+        for (i = 0; i < B43_NR_LEDS; i++) {
+                led = &(dev->leds[i]);
+
+                turn_on = 0;
+                switch (led->behaviour) {
+                case B43_LED_INACTIVE:
+                        continue;
+                case B43_LED_OFF:
+                        break;
+                case B43_LED_ON:
+                        turn_on = 1;
+                        break;
+                case B43_LED_ACTIVITY:
+                        turn_on = activity;
+                        break;
+                case B43_LED_RADIO_ALL:
+                        turn_on = phy->radio_on && b43_is_hw_radio_enabled(dev);
+                        break;
+                case B43_LED_RADIO_A:
+                        turn_on = (phy->radio_on && b43_is_hw_radio_enabled(dev)
+                                   && phy->type == B43_PHYTYPE_A);
+                        break;
+                case B43_LED_RADIO_B:
+                        turn_on = (phy->radio_on && b43_is_hw_radio_enabled(dev)
+                                   && (phy->type == B43_PHYTYPE_B
+                                       || phy->type == B43_PHYTYPE_G));
+                        break;
+                case B43_LED_MODE_BG:
+                        if (phy->type == B43_PHYTYPE_G
+                            && b43_is_hw_radio_enabled(dev)
+                            && 1 /*FIXME: using G rates. */ )
+                                turn_on = 1;
+                        break;
+                case B43_LED_TRANSFER:
+                        if (transferring)
+                                b43_led_blink_start(led, B43_LEDBLINK_MEDIUM);
+                        else
+                                b43_led_blink_stop(led, 0);
+                        continue;
+                case B43_LED_APTRANSFER:
+                        if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
+                                if (transferring) {
+                                        interval = B43_LEDBLINK_FAST;
+                                        turn_on = 1;
+                                }
+                        } else {
+                                turn_on = 1;
+                                if (0 /*TODO: not assoc */ )
+                                        interval = B43_LEDBLINK_SLOW;
+                                else if (transferring)
+                                        interval = B43_LEDBLINK_FAST;
+                                else
+                                        turn_on = 0;
+                        }
+                        if (turn_on)
+                                b43_led_blink_start(led, interval);
+                        else
+                                b43_led_blink_stop(led, 0);
+                        continue;
+                case B43_LED_WEIRD:
+                        //TODO
+                        break;
+                case B43_LED_ASSOC:
+                        if (1 /*dev->softmac->associated */ )
+                                turn_on = 1;
+                        break;
+#ifdef CONFIG_B43_DEBUG
+                case B43_LED_TEST_BLINKSLOW:
+                        b43_led_blink_start(led, B43_LEDBLINK_SLOW);
+                        continue;
+                case B43_LED_TEST_BLINKMEDIUM:
+                        b43_led_blink_start(led, B43_LEDBLINK_MEDIUM);
+                        continue;
+                case B43_LED_TEST_BLINKFAST:
+                        b43_led_blink_start(led, B43_LEDBLINK_FAST);
+                        continue;
+#endif /* CONFIG_B43_DEBUG */
+                default:
+                        B43_WARN_ON(1);
+                };
+
+                if (led->activelow)
+                        turn_on = !turn_on;
+                if (turn_on)
+                        ledctl |= (1 << i);
+                else
+                        ledctl &= ~(1 << i);
+        }
+        b43_write16(dev, B43_MMIO_GPIO_CONTROL, ledctl);
+        spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
+
+void b43_leds_switch_all(struct b43_wldev *dev, int on)
+{
+        struct b43_led *led;
+        u16 ledctl;
+        int i;
+        int bit_on;
+        unsigned long flags;
+
+        spin_lock_irqsave(&dev->wl->leds_lock, flags);
+        ledctl = b43_read16(dev, B43_MMIO_GPIO_CONTROL);
+        for (i = 0; i < B43_NR_LEDS; i++) {
+                led = &(dev->leds[i]);
+                if (led->behaviour == B43_LED_INACTIVE)
+                        continue;
+                if (on)
+                        bit_on = led->activelow ? 0 : 1;
+                else
+                        bit_on = led->activelow ? 1 : 0;
+                if (bit_on)
+                        ledctl |= (1 << i);
+                else
+                        ledctl &= ~(1 << i);
+        }
+        b43_write16(dev, B43_MMIO_GPIO_CONTROL, ledctl);
+        spin_unlock_irqrestore(&dev->wl->leds_lock, flags);
+}
diff --git a/drivers/net/wireless/b43/leds.h b/drivers/net/wireless/b43/leds.h
new file mode 100644
index 000000000000..36b46cfda220
--- /dev/null
+++ b/drivers/net/wireless/b43/leds.h
@@ -0,0 +1,55 @@
+#ifndef B43_LEDS_H_
+#define B43_LEDS_H_
+
+#include <linux/types.h>
+#include <linux/timer.h>
+
+struct b43_led {
+        u8 behaviour:7;
+        u8 activelow:1;
+
+        struct b43_wldev *dev;
+        struct timer_list blink_timer;
+        unsigned long blink_interval;
+};
+#define b43_led_index(led)      ((int)((led) - (led)->dev->leds))
+
+/* Delay between state changes when blinking in jiffies */
+#define B43_LEDBLINK_SLOW               (HZ / 1)
+#define B43_LEDBLINK_MEDIUM             (HZ / 4)
+#define B43_LEDBLINK_FAST               (HZ / 8)
+
+#define B43_LED_XFER_THRES              (HZ / 100)
+
+#define B43_LED_BEHAVIOUR               0x7F
+#define B43_LED_ACTIVELOW               0x80
+enum {                          /* LED behaviour values */
+        B43_LED_OFF,
+        B43_LED_ON,
+        B43_LED_ACTIVITY,
+        B43_LED_RADIO_ALL,
+        B43_LED_RADIO_A,
+        B43_LED_RADIO_B,
+        B43_LED_MODE_BG,
+        B43_LED_TRANSFER,
+        B43_LED_APTRANSFER,
+        B43_LED_WEIRD,          //FIXME
+        B43_LED_ASSOC,
+        B43_LED_INACTIVE,
+
+        /* Behaviour values for testing.
+         * With these values it is easier to figure out
+         * the real behaviour of leds, in case the SPROM
+         * is missing information.
+         */
+        B43_LED_TEST_BLINKSLOW,
+        B43_LED_TEST_BLINKMEDIUM,
+        B43_LED_TEST_BLINKFAST,
+};
+
+int b43_leds_init(struct b43_wldev *dev);
+void b43_leds_exit(struct b43_wldev *dev);
+void b43_leds_update(struct b43_wldev *dev, int activity);
+void b43_leds_switch_all(struct b43_wldev *dev, int on);
+
+#endif /* B43_LEDS_H_ */
diff --git a/drivers/net/wireless/b43/lo.c b/drivers/net/wireless/b43/lo.c
new file mode 100644
index 000000000000..b14a1753a0d7
--- /dev/null
+++ b/drivers/net/wireless/b43/lo.c
@@ -0,0 +1,1261 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  G PHY LO (LocalOscillator) Measuring and Control routines
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+  Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
+  Copyright (c) 2005-2007 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "b43.h"
+#include "lo.h"
+#include "phy.h"
+#include "main.h"
+
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+
+/* Define to 1 to always calibrate all possible LO control pairs.
+ * This is a workaround until we fix the partial LO calibration optimization. */
+#define B43_CALIB_ALL_LOCTLS    1
+
+
+/* Write the LocalOscillator Control (adjust) value-pair. */
+static void b43_lo_write(struct b43_wldev *dev, struct b43_loctl *control)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 value;
+        u16 reg;
+
+        if (B43_DEBUG) {
+                if (unlikely(abs(control->i) > 16 || abs(control->q) > 16)) {
+                        b43dbg(dev->wl, "Invalid LO control pair "
+                               "(I: %d, Q: %d)\n", control->i, control->q);
+                        dump_stack();
+                        return;
+                }
+        }
+
+        value = (u8) (control->q);
+        value |= ((u8) (control->i)) << 8;
+
+        reg = (phy->type == B43_PHYTYPE_B) ? 0x002F : B43_PHY_LO_CTL;
+        b43_phy_write(dev, reg, value);
+}
+
+static int assert_rfatt_and_bbatt(const struct b43_rfatt *rfatt,
+                                  const struct b43_bbatt *bbatt,
+                                  struct b43_wldev *dev)
+{
+        int err = 0;
+
+        /* Check the attenuation values against the LO control array sizes. */
+        if (unlikely(rfatt->att >= B43_NR_RF)) {
+                b43err(dev->wl, "rfatt(%u) >= size of LO array\n", rfatt->att);
+                err = -EINVAL;
+        }
+        if (unlikely(bbatt->att >= B43_NR_BB)) {
+                b43err(dev->wl, "bbatt(%u) >= size of LO array\n", bbatt->att);
+                err = -EINVAL;
+        }
+
+        return err;
+}
+
+#if !B43_CALIB_ALL_LOCTLS
+static
+struct b43_loctl *b43_get_lo_g_ctl_nopadmix(struct b43_wldev *dev,
+                                            const struct b43_rfatt *rfatt,
+                                            const struct b43_bbatt *bbatt)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+
+        if (assert_rfatt_and_bbatt(rfatt, bbatt, dev))
+                return &(lo->no_padmix[0][0]);  /* Just prevent a crash */
+        return &(lo->no_padmix[bbatt->att][rfatt->att]);
+}
+#endif /* !B43_CALIB_ALL_LOCTLS */
+
+struct b43_loctl *b43_get_lo_g_ctl(struct b43_wldev *dev,
+                                   const struct b43_rfatt *rfatt,
+                                   const struct b43_bbatt *bbatt)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+
+        if (assert_rfatt_and_bbatt(rfatt, bbatt, dev))
+                return &(lo->no_padmix[0][0]);  /* Just prevent a crash */
+        if (rfatt->with_padmix)
+                return &(lo->with_padmix[bbatt->att][rfatt->att]);
+        return &(lo->no_padmix[bbatt->att][rfatt->att]);
+}
+
+/* Call a function for every possible LO control value-pair. */
+static void b43_call_for_each_loctl(struct b43_wldev *dev,
+                                    void (*func) (struct b43_wldev *,
+                                                  struct b43_loctl *))
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *ctl = phy->lo_control;
+        int i, j;
+
+        for (i = 0; i < B43_NR_BB; i++) {
+                for (j = 0; j < B43_NR_RF; j++)
+                        func(dev, &(ctl->with_padmix[i][j]));
+        }
+        for (i = 0; i < B43_NR_BB; i++) {
+                for (j = 0; j < B43_NR_RF; j++)
+                        func(dev, &(ctl->no_padmix[i][j]));
+        }
+}
+
+static u16 lo_b_r15_loop(struct b43_wldev *dev)
+{
+        int i;
+        u16 ret = 0;
+
+        for (i = 0; i < 10; i++) {
+                b43_phy_write(dev, 0x0015, 0xAFA0);
+                udelay(1);
+                b43_phy_write(dev, 0x0015, 0xEFA0);
+                udelay(10);
+                b43_phy_write(dev, 0x0015, 0xFFA0);
+                udelay(40);
+                ret += b43_phy_read(dev, 0x002C);
+        }
+
+        return ret;
+}
+
+void b43_lo_b_measure(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 regstack[12] = { 0 };
+        u16 mls;
+        u16 fval;
+        int i, j;
+
+        regstack[0] = b43_phy_read(dev, 0x0015);
+        regstack[1] = b43_radio_read16(dev, 0x0052) & 0xFFF0;
+
+        if (phy->radio_ver == 0x2053) {
+                regstack[2] = b43_phy_read(dev, 0x000A);
+                regstack[3] = b43_phy_read(dev, 0x002A);
+                regstack[4] = b43_phy_read(dev, 0x0035);
+                regstack[5] = b43_phy_read(dev, 0x0003);
+                regstack[6] = b43_phy_read(dev, 0x0001);
+                regstack[7] = b43_phy_read(dev, 0x0030);
+
+                regstack[8] = b43_radio_read16(dev, 0x0043);
+                regstack[9] = b43_radio_read16(dev, 0x007A);
+                regstack[10] = b43_read16(dev, 0x03EC);
+                regstack[11] = b43_radio_read16(dev, 0x0052) & 0x00F0;
+
+                b43_phy_write(dev, 0x0030, 0x00FF);
+                b43_write16(dev, 0x03EC, 0x3F3F);
+                b43_phy_write(dev, 0x0035, regstack[4] & 0xFF7F);
+                b43_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0);
+        }
+        b43_phy_write(dev, 0x0015, 0xB000);
+        b43_phy_write(dev, 0x002B, 0x0004);
+
+        if (phy->radio_ver == 0x2053) {
+                b43_phy_write(dev, 0x002B, 0x0203);
+                b43_phy_write(dev, 0x002A, 0x08A3);
+        }
+
+        phy->minlowsig[0] = 0xFFFF;
+
+        for (i = 0; i < 4; i++) {
+                b43_radio_write16(dev, 0x0052, regstack[1] | i);
+                lo_b_r15_loop(dev);
+        }
+        for (i = 0; i < 10; i++) {
+                b43_radio_write16(dev, 0x0052, regstack[1] | i);
+                mls = lo_b_r15_loop(dev) / 10;
+                if (mls < phy->minlowsig[0]) {
+                        phy->minlowsig[0] = mls;
+                        phy->minlowsigpos[0] = i;
+                }
+        }
+        b43_radio_write16(dev, 0x0052, regstack[1] | phy->minlowsigpos[0]);
+
+        phy->minlowsig[1] = 0xFFFF;
+
+        for (i = -4; i < 5; i += 2) {
+                for (j = -4; j < 5; j += 2) {
+                        if (j < 0)
+                                fval = (0x0100 * i) + j + 0x0100;
+                        else
+                                fval = (0x0100 * i) + j;
+                        b43_phy_write(dev, 0x002F, fval);
+                        mls = lo_b_r15_loop(dev) / 10;
+                        if (mls < phy->minlowsig[1]) {
+                                phy->minlowsig[1] = mls;
+                                phy->minlowsigpos[1] = fval;
+                        }
+                }
+        }
+        phy->minlowsigpos[1] += 0x0101;
+
+        b43_phy_write(dev, 0x002F, phy->minlowsigpos[1]);
+        if (phy->radio_ver == 0x2053) {
+                b43_phy_write(dev, 0x000A, regstack[2]);
+                b43_phy_write(dev, 0x002A, regstack[3]);
+                b43_phy_write(dev, 0x0035, regstack[4]);
+                b43_phy_write(dev, 0x0003, regstack[5]);
+                b43_phy_write(dev, 0x0001, regstack[6]);
+                b43_phy_write(dev, 0x0030, regstack[7]);
+
+                b43_radio_write16(dev, 0x0043, regstack[8]);
+                b43_radio_write16(dev, 0x007A, regstack[9]);
+
+                b43_radio_write16(dev, 0x0052,
+                                  (b43_radio_read16(dev, 0x0052) & 0x000F)
+                                  | regstack[11]);
+
+                b43_write16(dev, 0x03EC, regstack[10]);
+        }
+        b43_phy_write(dev, 0x0015, regstack[0]);
+}
+
+static u16 lo_measure_feedthrough(struct b43_wldev *dev,
+                                  u16 lna, u16 pga, u16 trsw_rx)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 rfover;
+        u16 feedthrough;
+
+        if (phy->gmode) {
+                lna <<= B43_PHY_RFOVERVAL_LNA_SHIFT;
+                pga <<= B43_PHY_RFOVERVAL_PGA_SHIFT;
+
+                B43_WARN_ON(lna & ~B43_PHY_RFOVERVAL_LNA);
+                B43_WARN_ON(pga & ~B43_PHY_RFOVERVAL_PGA);
+/*FIXME This assertion fails            B43_WARN_ON(trsw_rx & ~(B43_PHY_RFOVERVAL_TRSWRX |
+                                    B43_PHY_RFOVERVAL_BW));
+*/
+                trsw_rx &= (B43_PHY_RFOVERVAL_TRSWRX | B43_PHY_RFOVERVAL_BW);
+
+                /* Construct the RF Override Value */
+                rfover = B43_PHY_RFOVERVAL_UNK;
+                rfover |= pga;
+                rfover |= lna;
+                rfover |= trsw_rx;
+                if ((dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) &&
+                    phy->rev > 6)
+                        rfover |= B43_PHY_RFOVERVAL_EXTLNA;
+
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
+                udelay(10);
+                rfover |= B43_PHY_RFOVERVAL_BW_LBW;
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
+                udelay(10);
+                rfover |= B43_PHY_RFOVERVAL_BW_LPF;
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, rfover);
+                udelay(10);
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xF300);
+        } else {
+                pga |= B43_PHY_PGACTL_UNKNOWN;
+                b43_phy_write(dev, B43_PHY_PGACTL, pga);
+                udelay(10);
+                pga |= B43_PHY_PGACTL_LOWBANDW;
+                b43_phy_write(dev, B43_PHY_PGACTL, pga);
+                udelay(10);
+                pga |= B43_PHY_PGACTL_LPF;
+                b43_phy_write(dev, B43_PHY_PGACTL, pga);
+        }
+        udelay(21);
+        feedthrough = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
+
+        /* This is a good place to check if we need to relax a bit,
+         * as this is the main function called regularly
+         * in the LO calibration. */
+        cond_resched();
+
+        return feedthrough;
+}
+
+/* TXCTL Register and Value Table.
+ * Returns the "TXCTL Register".
+ * "value" is the "TXCTL Value".
+ * "pad_mix_gain" is the PAD Mixer Gain.
+ */
+static u16 lo_txctl_register_table(struct b43_wldev *dev,
+                                   u16 * value, u16 * pad_mix_gain)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 reg, v, padmix;
+
+        if (phy->type == B43_PHYTYPE_B) {
+                v = 0x30;
+                if (phy->radio_rev <= 5) {
+                        reg = 0x43;
+                        padmix = 0;
+                } else {
+                        reg = 0x52;
+                        padmix = 5;
+                }
+        } else {
+                if (phy->rev >= 2 && phy->radio_rev == 8) {
+                        reg = 0x43;
+                        v = 0x10;
+                        padmix = 2;
+                } else {
+                        reg = 0x52;
+                        v = 0x30;
+                        padmix = 5;
+                }
+        }
+        if (value)
+                *value = v;
+        if (pad_mix_gain)
+                *pad_mix_gain = padmix;
+
+        return reg;
+}
+
+static void lo_measure_txctl_values(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        u16 reg, mask;
+        u16 trsw_rx, pga;
+        u16 radio_pctl_reg;
+
+        static const u8 tx_bias_values[] = {
+                0x09, 0x08, 0x0A, 0x01, 0x00,
+                0x02, 0x05, 0x04, 0x06,
+        };
+        static const u8 tx_magn_values[] = {
+                0x70, 0x40,
+        };
+
+        if (!has_loopback_gain(phy)) {
+                radio_pctl_reg = 6;
+                trsw_rx = 2;
+                pga = 0;
+        } else {
+                int lb_gain;    /* Loopback gain (in dB) */
+
+                trsw_rx = 0;
+                lb_gain = phy->max_lb_gain / 2;
+                if (lb_gain > 10) {
+                        radio_pctl_reg = 0;
+                        pga = abs(10 - lb_gain) / 6;
+                        pga = limit_value(pga, 0, 15);
+                } else {
+                        int cmp_val;
+                        int tmp;
+
+                        pga = 0;
+                        cmp_val = 0x24;
+                        if ((phy->rev >= 2) &&
+                            (phy->radio_ver == 0x2050) && (phy->radio_rev == 8))
+                                cmp_val = 0x3C;
+                        tmp = lb_gain;
+                        if ((10 - lb_gain) < cmp_val)
+                                tmp = (10 - lb_gain);
+                        if (tmp < 0)
+                                tmp += 6;
+                        else
+                                tmp += 3;
+                        cmp_val /= 4;
+                        tmp /= 4;
+                        if (tmp >= cmp_val)
+                                radio_pctl_reg = cmp_val;
+                        else
+                                radio_pctl_reg = tmp;
+                }
+        }
+        b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
+                                      & 0xFFF0) | radio_pctl_reg);
+        b43_phy_set_baseband_attenuation(dev, 2);
+
+        reg = lo_txctl_register_table(dev, &mask, NULL);
+        mask = ~mask;
+        b43_radio_write16(dev, reg, b43_radio_read16(dev, reg)
+                          & mask);
+
+        if (has_tx_magnification(phy)) {
+                int i, j;
+                int feedthrough;
+                int min_feedth = 0xFFFF;
+                u8 tx_magn, tx_bias;
+
+                for (i = 0; i < ARRAY_SIZE(tx_magn_values); i++) {
+                        tx_magn = tx_magn_values[i];
+                        b43_radio_write16(dev, 0x52,
+                                          (b43_radio_read16(dev, 0x52)
+                                           & 0xFF0F) | tx_magn);
+                        for (j = 0; j < ARRAY_SIZE(tx_bias_values); j++) {
+                                tx_bias = tx_bias_values[j];
+                                b43_radio_write16(dev, 0x52,
+                                                  (b43_radio_read16(dev, 0x52)
+                                                   & 0xFFF0) | tx_bias);
+                                feedthrough =
+                                    lo_measure_feedthrough(dev, 0, pga,
+                                                           trsw_rx);
+                                if (feedthrough < min_feedth) {
+                                        lo->tx_bias = tx_bias;
+                                        lo->tx_magn = tx_magn;
+                                        min_feedth = feedthrough;
+                                }
+                                if (lo->tx_bias == 0)
+                                        break;
+                        }
+                        b43_radio_write16(dev, 0x52,
+                                          (b43_radio_read16(dev, 0x52)
+                                           & 0xFF00) | lo->tx_bias | lo->
+                                          tx_magn);
+                }
+        } else {
+                lo->tx_magn = 0;
+                lo->tx_bias = 0;
+                b43_radio_write16(dev, 0x52, b43_radio_read16(dev, 0x52)
+                                  & 0xFFF0);    /* TX bias == 0 */
+        }
+}
+
+static void lo_read_power_vector(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        u16 i;
+        u64 tmp;
+        u64 power_vector = 0;
+        int rf_offset, bb_offset;
+        struct b43_loctl *loctl;
+
+        for (i = 0; i < 8; i += 2) {
+                tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x310 + i);
+                /* Clear the top byte. We get holes in the bitmap... */
+                tmp &= 0xFF;
+                power_vector |= (tmp << (i * 8));
+                /* Clear the vector on the device. */
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x310 + i, 0);
+        }
+
+        if (power_vector)
+                lo->power_vector = power_vector;
+        power_vector = lo->power_vector;
+
+        for (i = 0; i < 64; i++) {
+                if (power_vector & ((u64) 1ULL << i)) {
+                        /* Now figure out which b43_loctl corresponds
+                         * to this bit.
+                         */
+                        rf_offset = i / lo->rfatt_list.len;
+                        bb_offset = i % lo->rfatt_list.len;     //FIXME?
+                        loctl =
+                            b43_get_lo_g_ctl(dev,
+                                             &lo->rfatt_list.list[rf_offset],
+                                             &lo->bbatt_list.list[bb_offset]);
+                        /* And mark it as "used", as the device told us
+                         * through the bitmap it is using it.
+                         */
+                        loctl->used = 1;
+                }
+        }
+}
+
+/* 802.11/LO/GPHY/MeasuringGains */
+static void lo_measure_gain_values(struct b43_wldev *dev,
+                                   s16 max_rx_gain, int use_trsw_rx)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 tmp;
+
+        if (max_rx_gain < 0)
+                max_rx_gain = 0;
+
+        if (has_loopback_gain(phy)) {
+                int trsw_rx = 0;
+                int trsw_rx_gain;
+
+                if (use_trsw_rx) {
+                        trsw_rx_gain = phy->trsw_rx_gain / 2;
+                        if (max_rx_gain >= trsw_rx_gain) {
+                                trsw_rx_gain = max_rx_gain - trsw_rx_gain;
+                                trsw_rx = 0x20;
+                        }
+                } else
+                        trsw_rx_gain = max_rx_gain;
+                if (trsw_rx_gain < 9) {
+                        phy->lna_lod_gain = 0;
+                } else {
+                        phy->lna_lod_gain = 1;
+                        trsw_rx_gain -= 8;
+                }
+                trsw_rx_gain = limit_value(trsw_rx_gain, 0, 0x2D);
+                phy->pga_gain = trsw_rx_gain / 3;
+                if (phy->pga_gain >= 5) {
+                        phy->pga_gain -= 5;
+                        phy->lna_gain = 2;
+                } else
+                        phy->lna_gain = 0;
+        } else {
+                phy->lna_gain = 0;
+                phy->trsw_rx_gain = 0x20;
+                if (max_rx_gain >= 0x14) {
+                        phy->lna_lod_gain = 1;
+                        phy->pga_gain = 2;
+                } else if (max_rx_gain >= 0x12) {
+                        phy->lna_lod_gain = 1;
+                        phy->pga_gain = 1;
+                } else if (max_rx_gain >= 0xF) {
+                        phy->lna_lod_gain = 1;
+                        phy->pga_gain = 0;
+                } else {
+                        phy->lna_lod_gain = 0;
+                        phy->pga_gain = 0;
+                }
+        }
+
+        tmp = b43_radio_read16(dev, 0x7A);
+        if (phy->lna_lod_gain == 0)
+                tmp &= ~0x0008;
+        else
+                tmp |= 0x0008;
+        b43_radio_write16(dev, 0x7A, tmp);
+}
+
+struct lo_g_saved_values {
+        u8 old_channel;
+
+        /* Core registers */
+        u16 reg_3F4;
+        u16 reg_3E2;
+
+        /* PHY registers */
+        u16 phy_lo_mask;
+        u16 phy_extg_01;
+        u16 phy_dacctl_hwpctl;
+        u16 phy_dacctl;
+        u16 phy_base_14;
+        u16 phy_hpwr_tssictl;
+        u16 phy_analogover;
+        u16 phy_analogoverval;
+        u16 phy_rfover;
+        u16 phy_rfoverval;
+        u16 phy_classctl;
+        u16 phy_base_3E;
+        u16 phy_crs0;
+        u16 phy_pgactl;
+        u16 phy_base_2A;
+        u16 phy_syncctl;
+        u16 phy_base_30;
+        u16 phy_base_06;
+
+        /* Radio registers */
+        u16 radio_43;
+        u16 radio_7A;
+        u16 radio_52;
+};
+
+static void lo_measure_setup(struct b43_wldev *dev,
+                             struct lo_g_saved_values *sav)
+{
+        struct ssb_sprom *sprom = &dev->dev->bus->sprom;
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        u16 tmp;
+
+        if (b43_has_hardware_pctl(phy)) {
+                sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
+                sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01));
+                sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL);
+                sav->phy_base_14 = b43_phy_read(dev, B43_PHY_BASE(0x14));
+                sav->phy_hpwr_tssictl = b43_phy_read(dev, B43_PHY_HPWR_TSSICTL);
+
+                b43_phy_write(dev, B43_PHY_HPWR_TSSICTL,
+                              b43_phy_read(dev, B43_PHY_HPWR_TSSICTL)
+                              | 0x100);
+                b43_phy_write(dev, B43_PHY_EXTG(0x01),
+                              b43_phy_read(dev, B43_PHY_EXTG(0x01))
+                              | 0x40);
+                b43_phy_write(dev, B43_PHY_DACCTL,
+                              b43_phy_read(dev, B43_PHY_DACCTL)
+                              | 0x40);
+                b43_phy_write(dev, B43_PHY_BASE(0x14),
+                              b43_phy_read(dev, B43_PHY_BASE(0x14))
+                              | 0x200);
+        }
+        if (phy->type == B43_PHYTYPE_B &&
+            phy->radio_ver == 0x2050 && phy->radio_rev < 6) {
+                b43_phy_write(dev, B43_PHY_BASE(0x16), 0x410);
+                b43_phy_write(dev, B43_PHY_BASE(0x17), 0x820);
+        }
+        if (!lo->rebuild && b43_has_hardware_pctl(phy))
+                lo_read_power_vector(dev);
+        if (phy->rev >= 2) {
+                sav->phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
+                sav->phy_analogoverval =
+                    b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
+                sav->phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
+                sav->phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
+                sav->phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
+                sav->phy_base_3E = b43_phy_read(dev, B43_PHY_BASE(0x3E));
+                sav->phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
+
+                b43_phy_write(dev, B43_PHY_CLASSCTL,
+                              b43_phy_read(dev, B43_PHY_CLASSCTL)
+                              & 0xFFFC);
+                b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
+                              & 0x7FFF);
+                b43_phy_write(dev, B43_PHY_ANALOGOVER,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVER)
+                              | 0x0003);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
+                              & 0xFFFC);
+                if (phy->type == B43_PHYTYPE_G) {
+                        if ((phy->rev >= 7) &&
+                            (sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
+                                b43_phy_write(dev, B43_PHY_RFOVER, 0x933);
+                        } else {
+                                b43_phy_write(dev, B43_PHY_RFOVER, 0x133);
+                        }
+                } else {
+                        b43_phy_write(dev, B43_PHY_RFOVER, 0);
+                }
+                b43_phy_write(dev, B43_PHY_BASE(0x3E), 0);
+        }
+        sav->reg_3F4 = b43_read16(dev, 0x3F4);
+        sav->reg_3E2 = b43_read16(dev, 0x3E2);
+        sav->radio_43 = b43_radio_read16(dev, 0x43);
+        sav->radio_7A = b43_radio_read16(dev, 0x7A);
+        sav->phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
+        sav->phy_base_2A = b43_phy_read(dev, B43_PHY_BASE(0x2A));
+        sav->phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
+        sav->phy_dacctl = b43_phy_read(dev, B43_PHY_DACCTL);
+
+        if (!has_tx_magnification(phy)) {
+                sav->radio_52 = b43_radio_read16(dev, 0x52);
+                sav->radio_52 &= 0x00F0;
+        }
+        if (phy->type == B43_PHYTYPE_B) {
+                sav->phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
+                sav->phy_base_06 = b43_phy_read(dev, B43_PHY_BASE(0x06));
+                b43_phy_write(dev, B43_PHY_BASE(0x30), 0x00FF);
+                b43_phy_write(dev, B43_PHY_BASE(0x06), 0x3F3F);
+        } else {
+                b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2)
+                            | 0x8000);
+        }
+        b43_write16(dev, 0x3F4, b43_read16(dev, 0x3F4)
+                    & 0xF000);
+
+        tmp =
+            (phy->type == B43_PHYTYPE_G) ? B43_PHY_LO_MASK : B43_PHY_BASE(0x2E);
+        b43_phy_write(dev, tmp, 0x007F);
+
+        tmp = sav->phy_syncctl;
+        b43_phy_write(dev, B43_PHY_SYNCCTL, tmp & 0xFF7F);
+        tmp = sav->radio_7A;
+        b43_radio_write16(dev, 0x007A, tmp & 0xFFF0);
+
+        b43_phy_write(dev, B43_PHY_BASE(0x2A), 0x8A3);
+        if (phy->type == B43_PHYTYPE_G ||
+            (phy->type == B43_PHYTYPE_B &&
+             phy->radio_ver == 0x2050 && phy->radio_rev >= 6)) {
+                b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1003);
+        } else
+                b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x0802);
+        if (phy->rev >= 2)
+                b43_dummy_transmission(dev);
+        b43_radio_selectchannel(dev, 6, 0);
+        b43_radio_read16(dev, 0x51);    /* dummy read */
+        if (phy->type == B43_PHYTYPE_G)
+                b43_phy_write(dev, B43_PHY_BASE(0x2F), 0);
+        if (lo->rebuild)
+                lo_measure_txctl_values(dev);
+        if (phy->type == B43_PHYTYPE_G && phy->rev >= 3) {
+                b43_phy_write(dev, B43_PHY_LO_MASK, 0xC078);
+        } else {
+                if (phy->type == B43_PHYTYPE_B)
+                        b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8078);
+                else
+                        b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
+        }
+}
+
+static void lo_measure_restore(struct b43_wldev *dev,
+                               struct lo_g_saved_values *sav)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        u16 tmp;
+
+        if (phy->rev >= 2) {
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
+                tmp = (phy->pga_gain << 8);
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA0);
+                udelay(5);
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA2);
+                udelay(2);
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA3);
+        } else {
+                tmp = (phy->pga_gain | 0xEFA0);
+                b43_phy_write(dev, B43_PHY_PGACTL, tmp);
+        }
+        if (b43_has_hardware_pctl(phy)) {
+                b43_gphy_dc_lt_init(dev);
+        } else {
+                if (lo->rebuild)
+                        b43_lo_g_adjust_to(dev, 3, 2, 0);
+                else
+                        b43_lo_g_adjust(dev);
+        }
+        if (phy->type == B43_PHYTYPE_G) {
+                if (phy->rev >= 3)
+                        b43_phy_write(dev, B43_PHY_BASE(0x2E), 0xC078);
+                else
+                        b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8078);
+                if (phy->rev >= 2)
+                        b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x0202);
+                else
+                        b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x0101);
+        }
+        b43_write16(dev, 0x3F4, sav->reg_3F4);
+        b43_phy_write(dev, B43_PHY_PGACTL, sav->phy_pgactl);
+        b43_phy_write(dev, B43_PHY_BASE(0x2A), sav->phy_base_2A);
+        b43_phy_write(dev, B43_PHY_SYNCCTL, sav->phy_syncctl);
+        b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl);
+        b43_radio_write16(dev, 0x43, sav->radio_43);
+        b43_radio_write16(dev, 0x7A, sav->radio_7A);
+        if (!has_tx_magnification(phy)) {
+                tmp = sav->radio_52;
+                b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
+                                              & 0xFF0F) | tmp);
+        }
+        b43_write16(dev, 0x3E2, sav->reg_3E2);
+        if (phy->type == B43_PHYTYPE_B &&
+            phy->radio_ver == 0x2050 && phy->radio_rev <= 5) {
+                b43_phy_write(dev, B43_PHY_BASE(0x30), sav->phy_base_30);
+                b43_phy_write(dev, B43_PHY_BASE(0x06), sav->phy_base_06);
+        }
+        if (phy->rev >= 2) {
+                b43_phy_write(dev, B43_PHY_ANALOGOVER, sav->phy_analogover);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              sav->phy_analogoverval);
+                b43_phy_write(dev, B43_PHY_CLASSCTL, sav->phy_classctl);
+                b43_phy_write(dev, B43_PHY_RFOVER, sav->phy_rfover);
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, sav->phy_rfoverval);
+                b43_phy_write(dev, B43_PHY_BASE(0x3E), sav->phy_base_3E);
+                b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
+        }
+        if (b43_has_hardware_pctl(phy)) {
+                tmp = (sav->phy_lo_mask & 0xBFFF);
+                b43_phy_write(dev, B43_PHY_LO_MASK, tmp);
+                b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01);
+                b43_phy_write(dev, B43_PHY_DACCTL, sav->phy_dacctl_hwpctl);
+                b43_phy_write(dev, B43_PHY_BASE(0x14), sav->phy_base_14);
+                b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
+        }
+        b43_radio_selectchannel(dev, sav->old_channel, 1);
+}
+
+struct b43_lo_g_statemachine {
+        int current_state;
+        int nr_measured;
+        int state_val_multiplier;
+        u16 lowest_feedth;
+        struct b43_loctl min_loctl;
+};
+
+/* Loop over each possible value in this state. */
+static int lo_probe_possible_loctls(struct b43_wldev *dev,
+                                    struct b43_loctl *probe_loctl,
+                                    struct b43_lo_g_statemachine *d)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        struct b43_loctl test_loctl;
+        struct b43_loctl orig_loctl;
+        struct b43_loctl prev_loctl = {
+                .i = -100,
+                .q = -100,
+        };
+        int i;
+        int begin, end;
+        int found_lower = 0;
+        u16 feedth;
+
+        static const struct b43_loctl modifiers[] = {
+                {.i = 1,.q = 1,},
+                {.i = 1,.q = 0,},
+                {.i = 1,.q = -1,},
+                {.i = 0,.q = -1,},
+                {.i = -1,.q = -1,},
+                {.i = -1,.q = 0,},
+                {.i = -1,.q = 1,},
+                {.i = 0,.q = 1,},
+        };
+
+        if (d->current_state == 0) {
+                begin = 1;
+                end = 8;
+        } else if (d->current_state % 2 == 0) {
+                begin = d->current_state - 1;
+                end = d->current_state + 1;
+        } else {
+                begin = d->current_state - 2;
+                end = d->current_state + 2;
+        }
+        if (begin < 1)
+                begin += 8;
+        if (end > 8)
+                end -= 8;
+
+        memcpy(&orig_loctl, probe_loctl, sizeof(struct b43_loctl));
+        i = begin;
+        d->current_state = i;
+        while (1) {
+                B43_WARN_ON(!(i >= 1 && i <= 8));
+                memcpy(&test_loctl, &orig_loctl, sizeof(struct b43_loctl));
+                test_loctl.i += modifiers[i - 1].i * d->state_val_multiplier;
+                test_loctl.q += modifiers[i - 1].q * d->state_val_multiplier;
+                if ((test_loctl.i != prev_loctl.i ||
+                     test_loctl.q != prev_loctl.q) &&
+                    (abs(test_loctl.i) <= 16 && abs(test_loctl.q) <= 16)) {
+                        b43_lo_write(dev, &test_loctl);
+                        feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+                                                        phy->pga_gain,
+                                                        phy->trsw_rx_gain);
+                        if (feedth < d->lowest_feedth) {
+                                memcpy(probe_loctl, &test_loctl,
+                                       sizeof(struct b43_loctl));
+                                found_lower = 1;
+                                d->lowest_feedth = feedth;
+                                if ((d->nr_measured < 2) &&
+                                    (!has_loopback_gain(phy) || lo->rebuild))
+                                        break;
+                        }
+                }
+                memcpy(&prev_loctl, &test_loctl, sizeof(prev_loctl));
+                if (i == end)
+                        break;
+                if (i == 8)
+                        i = 1;
+                else
+                        i++;
+                d->current_state = i;
+        }
+
+        return found_lower;
+}
+
+static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
+                                         struct b43_loctl *loctl,
+                                         int *max_rx_gain)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        struct b43_lo_g_statemachine d;
+        u16 feedth;
+        int found_lower;
+        struct b43_loctl probe_loctl;
+        int max_repeat = 1, repeat_cnt = 0;
+
+        d.nr_measured = 0;
+        d.state_val_multiplier = 1;
+        if (has_loopback_gain(phy) && !lo->rebuild)
+                d.state_val_multiplier = 3;
+
+        memcpy(&d.min_loctl, loctl, sizeof(struct b43_loctl));
+        if (has_loopback_gain(phy) && lo->rebuild)
+                max_repeat = 4;
+        do {
+                b43_lo_write(dev, &d.min_loctl);
+                feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+                                                phy->pga_gain,
+                                                phy->trsw_rx_gain);
+                if (!lo->rebuild && feedth < 0x258) {
+                        if (feedth >= 0x12C)
+                                *max_rx_gain += 6;
+                        else
+                                *max_rx_gain += 3;
+                        feedth = lo_measure_feedthrough(dev, phy->lna_gain,
+                                                        phy->pga_gain,
+                                                        phy->trsw_rx_gain);
+                }
+                d.lowest_feedth = feedth;
+
+                d.current_state = 0;
+                do {
+                        B43_WARN_ON(!
+                                    (d.current_state >= 0
+                                     && d.current_state <= 8));
+                        memcpy(&probe_loctl, &d.min_loctl,
+                               sizeof(struct b43_loctl));
+                        found_lower =
+                            lo_probe_possible_loctls(dev, &probe_loctl, &d);
+                        if (!found_lower)
+                                break;
+                        if ((probe_loctl.i == d.min_loctl.i) &&
+                            (probe_loctl.q == d.min_loctl.q))
+                                break;
+                        memcpy(&d.min_loctl, &probe_loctl,
+                               sizeof(struct b43_loctl));
+                        d.nr_measured++;
+                } while (d.nr_measured < 24);
+                memcpy(loctl, &d.min_loctl, sizeof(struct b43_loctl));
+
+                if (has_loopback_gain(phy)) {
+                        if (d.lowest_feedth > 0x1194)
+                                *max_rx_gain -= 6;
+                        else if (d.lowest_feedth < 0x5DC)
+                                *max_rx_gain += 3;
+                        if (repeat_cnt == 0) {
+                                if (d.lowest_feedth <= 0x5DC) {
+                                        d.state_val_multiplier = 1;
+                                        repeat_cnt++;
+                                } else
+                                        d.state_val_multiplier = 2;
+                        } else if (repeat_cnt == 2)
+                                d.state_val_multiplier = 1;
+                }
+                lo_measure_gain_values(dev, *max_rx_gain,
+                                       has_loopback_gain(phy));
+        } while (++repeat_cnt < max_repeat);
+}
+
+#if B43_CALIB_ALL_LOCTLS
+static const struct b43_rfatt b43_full_rfatt_list_items[] = {
+        { .att = 0, .with_padmix = 0, },
+        { .att = 1, .with_padmix = 0, },
+        { .att = 2, .with_padmix = 0, },
+        { .att = 3, .with_padmix = 0, },
+        { .att = 4, .with_padmix = 0, },
+        { .att = 5, .with_padmix = 0, },
+        { .att = 6, .with_padmix = 0, },
+        { .att = 7, .with_padmix = 0, },
+        { .att = 8, .with_padmix = 0, },
+        { .att = 9, .with_padmix = 0, },
+        { .att = 10, .with_padmix = 0, },
+        { .att = 11, .with_padmix = 0, },
+        { .att = 12, .with_padmix = 0, },
+        { .att = 13, .with_padmix = 0, },
+        { .att = 14, .with_padmix = 0, },
+        { .att = 15, .with_padmix = 0, },
+        { .att = 0, .with_padmix = 1, },
+        { .att = 1, .with_padmix = 1, },
+        { .att = 2, .with_padmix = 1, },
+        { .att = 3, .with_padmix = 1, },
+        { .att = 4, .with_padmix = 1, },
+        { .att = 5, .with_padmix = 1, },
+        { .att = 6, .with_padmix = 1, },
+        { .att = 7, .with_padmix = 1, },
+        { .att = 8, .with_padmix = 1, },
+        { .att = 9, .with_padmix = 1, },
+        { .att = 10, .with_padmix = 1, },
+        { .att = 11, .with_padmix = 1, },
+        { .att = 12, .with_padmix = 1, },
+        { .att = 13, .with_padmix = 1, },
+        { .att = 14, .with_padmix = 1, },
+        { .att = 15, .with_padmix = 1, },
+};
+static const struct b43_rfatt_list b43_full_rfatt_list = {
+        .list           = b43_full_rfatt_list_items,
+        .len            = ARRAY_SIZE(b43_full_rfatt_list_items),
+};
+
+static const struct b43_bbatt b43_full_bbatt_list_items[] = {
+        { .att = 0, },
+        { .att = 1, },
+        { .att = 2, },
+        { .att = 3, },
+        { .att = 4, },
+        { .att = 5, },
+        { .att = 6, },
+        { .att = 7, },
+        { .att = 8, },
+        { .att = 9, },
+        { .att = 10, },
+        { .att = 11, },
+};
+static const struct b43_bbatt_list b43_full_bbatt_list = {
+        .list           = b43_full_bbatt_list_items,
+        .len            = ARRAY_SIZE(b43_full_bbatt_list_items),
+};
+#endif /* B43_CALIB_ALL_LOCTLS */
+
+static void lo_measure(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        struct b43_loctl loctl = {
+                .i = 0,
+                .q = 0,
+        };
+        struct b43_loctl *ploctl;
+        int max_rx_gain;
+        int rfidx, bbidx;
+        const struct b43_bbatt_list *bbatt_list;
+        const struct b43_rfatt_list *rfatt_list;
+
+        /* Values from the "TXCTL Register and Value Table" */
+        u16 txctl_reg;
+        u16 txctl_value;
+        u16 pad_mix_gain;
+
+        bbatt_list = &lo->bbatt_list;
+        rfatt_list = &lo->rfatt_list;
+#if B43_CALIB_ALL_LOCTLS
+        bbatt_list = &b43_full_bbatt_list;
+        rfatt_list = &b43_full_rfatt_list;
+#endif
+
+        txctl_reg = lo_txctl_register_table(dev, &txctl_value, &pad_mix_gain);
+
+        for (rfidx = 0; rfidx < rfatt_list->len; rfidx++) {
+
+                b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
+                                              & 0xFFF0) |
+                                  rfatt_list->list[rfidx].att);
+                b43_radio_write16(dev, txctl_reg,
+                                  (b43_radio_read16(dev, txctl_reg)
+                                   & ~txctl_value)
+                                  | (rfatt_list->list[rfidx].with_padmix ?
+                                     txctl_value : 0));
+
+                for (bbidx = 0; bbidx < bbatt_list->len; bbidx++) {
+                        if (lo->rebuild) {
+#if B43_CALIB_ALL_LOCTLS
+                                ploctl = b43_get_lo_g_ctl(dev,
+                                                          &rfatt_list->list[rfidx],
+                                                          &bbatt_list->list[bbidx]);
+#else
+                                ploctl = b43_get_lo_g_ctl_nopadmix(dev,
+                                                                   &rfatt_list->
+                                                                   list[rfidx],
+                                                                   &bbatt_list->
+                                                                   list[bbidx]);
+#endif
+                        } else {
+                                ploctl = b43_get_lo_g_ctl(dev,
+                                                          &rfatt_list->list[rfidx],
+                                                          &bbatt_list->list[bbidx]);
+                                if (!ploctl->used)
+                                        continue;
+                        }
+                        memcpy(&loctl, ploctl, sizeof(loctl));
+                        loctl.i = 0;
+                        loctl.q = 0;
+
+                        max_rx_gain = rfatt_list->list[rfidx].att * 2;
+                        max_rx_gain += bbatt_list->list[bbidx].att / 2;
+                        if (rfatt_list->list[rfidx].with_padmix)
+                                max_rx_gain -= pad_mix_gain;
+                        if (has_loopback_gain(phy))
+                                max_rx_gain += phy->max_lb_gain;
+                        lo_measure_gain_values(dev, max_rx_gain,
+                                               has_loopback_gain(phy));
+
+                        b43_phy_set_baseband_attenuation(dev,
+                                                         bbatt_list->list[bbidx].att);
+                        lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
+                        if (phy->type == B43_PHYTYPE_B) {
+                                loctl.i++;
+                                loctl.q++;
+                        }
+                        b43_loctl_set_calibrated(&loctl, 1);
+                        memcpy(ploctl, &loctl, sizeof(loctl));
+                }
+        }
+}
+
+#if B43_DEBUG
+static void do_validate_loctl(struct b43_wldev *dev, struct b43_loctl *control)
+{
+        const int is_initializing = (b43_status(dev) == B43_STAT_UNINIT);
+        int i = control->i;
+        int q = control->q;
+
+        if (b43_loctl_is_calibrated(control)) {
+                if ((abs(i) > 16) || (abs(q) > 16))
+                        goto error;
+        } else {
+                if (control->used)
+                        goto error;
+                if (dev->phy.lo_control->rebuild) {
+                        control->i = 0;
+                        control->q = 0;
+                        if ((i != B43_LOCTL_POISON) ||
+                            (q != B43_LOCTL_POISON))
+                                goto error;
+                }
+        }
+        if (is_initializing && control->used)
+                goto error;
+
+        return;
+error:
+        b43err(dev->wl, "LO control pair validation failed "
+               "(I: %d, Q: %d, used %u, calib: %u, initing: %d)\n",
+               i, q, control->used,
+               b43_loctl_is_calibrated(control),
+               is_initializing);
+}
+
+static void validate_all_loctls(struct b43_wldev *dev)
+{
+        b43_call_for_each_loctl(dev, do_validate_loctl);
+}
+
+static void do_reset_calib(struct b43_wldev *dev, struct b43_loctl *control)
+{
+        if (dev->phy.lo_control->rebuild ||
+            control->used) {
+                b43_loctl_set_calibrated(control, 0);
+                control->i = B43_LOCTL_POISON;
+                control->q = B43_LOCTL_POISON;
+        }
+}
+
+static void reset_all_loctl_calibration_states(struct b43_wldev *dev)
+{
+        b43_call_for_each_loctl(dev, do_reset_calib);
+}
+
+#else /* B43_DEBUG */
+static inline void validate_all_loctls(struct b43_wldev *dev) { }
+static inline void reset_all_loctl_calibration_states(struct b43_wldev *dev) { }
+#endif /* B43_DEBUG */
+
+void b43_lo_g_measure(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct lo_g_saved_values uninitialized_var(sav);
+
+        B43_WARN_ON((phy->type != B43_PHYTYPE_B) &&
+                    (phy->type != B43_PHYTYPE_G));
+
+        sav.old_channel = phy->channel;
+        lo_measure_setup(dev, &sav);
+        reset_all_loctl_calibration_states(dev);
+        lo_measure(dev);
+        lo_measure_restore(dev, &sav);
+
+        validate_all_loctls(dev);
+
+        phy->lo_control->lo_measured = 1;
+        phy->lo_control->rebuild = 0;
+}
+
+#if B43_DEBUG
+static void validate_loctl_calibration(struct b43_wldev *dev,
+                                       struct b43_loctl *loctl,
+                                       struct b43_rfatt *rfatt,
+                                       struct b43_bbatt *bbatt)
+{
+        if (b43_loctl_is_calibrated(loctl))
+                return;
+        if (!dev->phy.lo_control->lo_measured) {
+                /* On init we set the attenuation values before we
+                 * calibrated the LO. I guess that's OK. */
+                return;
+        }
+        b43err(dev->wl, "Adjusting Local Oscillator to an uncalibrated "
+               "control pair: rfatt=%u,%spadmix bbatt=%u\n",
+               rfatt->att,
+               (rfatt->with_padmix) ? "" : "no-",
+               bbatt->att);
+}
+#else
+static inline void validate_loctl_calibration(struct b43_wldev *dev,
+                                              struct b43_loctl *loctl,
+                                              struct b43_rfatt *rfatt,
+                                              struct b43_bbatt *bbatt)
+{
+}
+#endif
+
+static inline void fixup_rfatt_for_txcontrol(struct b43_rfatt *rf,
+                                             u8 tx_control)
+{
+        if (tx_control & B43_TXCTL_TXMIX) {
+                if (rf->att < 5)
+                        rf->att = 4;
+        }
+}
+
+void b43_lo_g_adjust(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_rfatt rf;
+        struct b43_loctl *loctl;
+
+        memcpy(&rf, &phy->rfatt, sizeof(rf));
+        fixup_rfatt_for_txcontrol(&rf, phy->tx_control);
+
+        loctl = b43_get_lo_g_ctl(dev, &rf, &phy->bbatt);
+        validate_loctl_calibration(dev, loctl, &rf, &phy->bbatt);
+        b43_lo_write(dev, loctl);
+}
+
+void b43_lo_g_adjust_to(struct b43_wldev *dev,
+                        u16 rfatt, u16 bbatt, u16 tx_control)
+{
+        struct b43_rfatt rf;
+        struct b43_bbatt bb;
+        struct b43_loctl *loctl;
+
+        memset(&rf, 0, sizeof(rf));
+        memset(&bb, 0, sizeof(bb));
+        rf.att = rfatt;
+        bb.att = bbatt;
+        fixup_rfatt_for_txcontrol(&rf, tx_control);
+        loctl = b43_get_lo_g_ctl(dev, &rf, &bb);
+        validate_loctl_calibration(dev, loctl, &rf, &bb);
+        b43_lo_write(dev, loctl);
+}
+
+static void do_mark_unused(struct b43_wldev *dev, struct b43_loctl *control)
+{
+        control->used = 0;
+}
+
+void b43_lo_g_ctl_mark_all_unused(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+
+        b43_call_for_each_loctl(dev, do_mark_unused);
+        lo->rebuild = 1;
+}
+
+void b43_lo_g_ctl_mark_cur_used(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_rfatt rf;
+
+        memcpy(&rf, &phy->rfatt, sizeof(rf));
+        fixup_rfatt_for_txcontrol(&rf, phy->tx_control);
+
+        b43_get_lo_g_ctl(dev, &rf, &phy->bbatt)->used = 1;
+}
diff --git a/drivers/net/wireless/b43/lo.h b/drivers/net/wireless/b43/lo.h
new file mode 100644
index 000000000000..455615d1f8c6
--- /dev/null
+++ b/drivers/net/wireless/b43/lo.h
@@ -0,0 +1,112 @@
+#ifndef B43_LO_H_
+#define B43_LO_H_
+
+#include "phy.h"
+
+struct b43_wldev;
+
+/* Local Oscillator control value-pair. */
+struct b43_loctl {
+        /* Control values. */
+        s8 i;
+        s8 q;
+        /* "Used by hardware" flag. */
+        bool used;
+#ifdef CONFIG_B43_DEBUG
+        /* Is this lo-control-array entry calibrated? */
+        bool calibrated;
+#endif
+};
+
+/* Debugging: Poison value for i and q values. */
+#define B43_LOCTL_POISON        111
+
+/* loctl->calibrated debugging mechanism */
+#ifdef CONFIG_B43_DEBUG
+static inline void b43_loctl_set_calibrated(struct b43_loctl *loctl,
+                                            bool calibrated)
+{
+        loctl->calibrated = calibrated;
+}
+static inline bool b43_loctl_is_calibrated(struct b43_loctl *loctl)
+{
+        return loctl->calibrated;
+}
+#else
+static inline void b43_loctl_set_calibrated(struct b43_loctl *loctl,
+                                            bool calibrated)
+{
+}
+static inline bool b43_loctl_is_calibrated(struct b43_loctl *loctl)
+{
+        return 1;
+}
+#endif
+
+/* TX Power LO Control Array.
+ * Value-pairs to adjust the LocalOscillator are stored
+ * in this structure.
+ * There are two different set of values. One for "Flag is Set"
+ * and one for "Flag is Unset".
+ * By "Flag" the flag in struct b43_rfatt is meant.
+ * The Value arrays are two-dimensional. The first index
+ * is the baseband attenuation and the second index
+ * is the radio attenuation.
+ * Use b43_get_lo_g_ctl() to retrieve a value from the lists.
+ */
+struct b43_txpower_lo_control {
+#define B43_NR_BB       12
+#define B43_NR_RF       16
+        /* LO Control values, with PAD Mixer */
+        struct b43_loctl with_padmix[B43_NR_BB][B43_NR_RF];
+        /* LO Control values, without PAD Mixer */
+        struct b43_loctl no_padmix[B43_NR_BB][B43_NR_RF];
+
+        /* Flag to indicate a complete rebuild of the two tables above
+         * to the LO measuring code. */
+        bool rebuild;
+
+        /* Lists of valid RF and BB attenuation values for this device. */
+        struct b43_rfatt_list rfatt_list;
+        struct b43_bbatt_list bbatt_list;
+
+        /* Current TX Bias value */
+        u8 tx_bias;
+        /* Current TX Magnification Value (if used by the device) */
+        u8 tx_magn;
+
+        /* GPHY LO is measured. */
+        bool lo_measured;
+
+        /* Saved device PowerVector */
+        u64 power_vector;
+};
+
+/* Measure the BPHY Local Oscillator. */
+void b43_lo_b_measure(struct b43_wldev *dev);
+/* Measure the BPHY/GPHY Local Oscillator. */
+void b43_lo_g_measure(struct b43_wldev *dev);
+
+/* Adjust the Local Oscillator to the saved attenuation
+ * and txctl values.
+ */
+void b43_lo_g_adjust(struct b43_wldev *dev);
+/* Adjust to specific values. */
+void b43_lo_g_adjust_to(struct b43_wldev *dev,
+                        u16 rfatt, u16 bbatt, u16 tx_control);
+
+/* Mark all possible b43_lo_g_ctl as "unused" */
+void b43_lo_g_ctl_mark_all_unused(struct b43_wldev *dev);
+/* Mark the b43_lo_g_ctl corresponding to the current
+ * attenuation values as used.
+ */
+void b43_lo_g_ctl_mark_cur_used(struct b43_wldev *dev);
+
+/* Get a reference to a LO Control value pair in the
+ * TX Power LO Control Array.
+ */
+struct b43_loctl *b43_get_lo_g_ctl(struct b43_wldev *dev,
+                                   const struct b43_rfatt *rfatt,
+                                   const struct b43_bbatt *bbatt);
+
+#endif /* B43_LO_H_ */
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
new file mode 100644
index 000000000000..184ebe3ed738
--- /dev/null
+++ b/drivers/net/wireless/b43/main.c
@@ -0,0 +1,4091 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
+  Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
+  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  Some parts of the code in this file are derived from the ipw2200
+  driver  Copyright(c) 2003 - 2004 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/moduleparam.h>
+#include <linux/if_arp.h>
+#include <linux/etherdevice.h>
+#include <linux/version.h>
+#include <linux/firmware.h>
+#include <linux/wireless.h>
+#include <linux/workqueue.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <asm/unaligned.h>
+
+#include "b43.h"
+#include "main.h"
+#include "debugfs.h"
+#include "phy.h"
+#include "dma.h"
+#include "pio.h"
+#include "sysfs.h"
+#include "xmit.h"
+#include "sysfs.h"
+#include "lo.h"
+#include "pcmcia.h"
+
+MODULE_DESCRIPTION("Broadcom B43 wireless driver");
+MODULE_AUTHOR("Martin Langer");
+MODULE_AUTHOR("Stefano Brivio");
+MODULE_AUTHOR("Michael Buesch");
+MODULE_LICENSE("GPL");
+
+extern char *nvram_get(char *name);
+
+#if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
+static int modparam_pio;
+module_param_named(pio, modparam_pio, int, 0444);
+MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
+#elif defined(CONFIG_B43_DMA)
+# define modparam_pio   0
+#elif defined(CONFIG_B43_PIO)
+# define modparam_pio   1
+#endif
+
+static int modparam_bad_frames_preempt;
+module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
+MODULE_PARM_DESC(bad_frames_preempt,
+                 "enable(1) / disable(0) Bad Frames Preemption");
+
+static int modparam_short_retry = B43_DEFAULT_SHORT_RETRY_LIMIT;
+module_param_named(short_retry, modparam_short_retry, int, 0444);
+MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
+
+static int modparam_long_retry = B43_DEFAULT_LONG_RETRY_LIMIT;
+module_param_named(long_retry, modparam_long_retry, int, 0444);
+MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
+
+static int modparam_noleds;
+module_param_named(noleds, modparam_noleds, int, 0444);
+MODULE_PARM_DESC(noleds, "Turn off all LED activity");
+
+static char modparam_fwpostfix[16];
+module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
+MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
+
+static int modparam_mon_keep_bad;
+module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444);
+MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode");
+
+static int modparam_mon_keep_badplcp;
+module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444);
+MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode");
+
+static int modparam_hwpctl;
+module_param_named(hwpctl, modparam_hwpctl, int, 0444);
+MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
+
+static int modparam_nohwcrypt;
+module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
+MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
+
+static const struct ssb_device_id b43_ssb_tbl[] = {
+        SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
+        SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
+        SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
+        SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
+        SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
+        SSB_DEVTABLE_END
+};
+
+MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
+
+/* Channel and ratetables are shared for all devices.
+ * They can't be const, because ieee80211 puts some precalculated
+ * data in there. This data is the same for all devices, so we don't
+ * get concurrency issues */
+#define RATETAB_ENT(_rateid, _flags) \
+        {                                                       \
+                .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
+                .val    = (_rateid),                            \
+                .val2   = (_rateid),                            \
+                .flags  = (_flags),                             \
+        }
+static struct ieee80211_rate __b43_ratetable[] = {
+        RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
+        RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
+        RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
+        RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
+        RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
+        RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
+};
+
+#define b43_a_ratetable         (__b43_ratetable + 4)
+#define b43_a_ratetable_size    8
+#define b43_b_ratetable         (__b43_ratetable + 0)
+#define b43_b_ratetable_size    4
+#define b43_g_ratetable         (__b43_ratetable + 0)
+#define b43_g_ratetable_size    12
+
+#define CHANTAB_ENT(_chanid, _freq) \
+        {                                                       \
+                .chan   = (_chanid),                            \
+                .freq   = (_freq),                              \
+                .val    = (_chanid),                            \
+                .flag   = IEEE80211_CHAN_W_SCAN |               \
+                          IEEE80211_CHAN_W_ACTIVE_SCAN |        \
+                          IEEE80211_CHAN_W_IBSS,                \
+                .power_level    = 0xFF,                         \
+                .antenna_max    = 0xFF,                         \
+        }
+static struct ieee80211_channel b43_bg_chantable[] = {
+        CHANTAB_ENT(1, 2412),
+        CHANTAB_ENT(2, 2417),
+        CHANTAB_ENT(3, 2422),
+        CHANTAB_ENT(4, 2427),
+        CHANTAB_ENT(5, 2432),
+        CHANTAB_ENT(6, 2437),
+        CHANTAB_ENT(7, 2442),
+        CHANTAB_ENT(8, 2447),
+        CHANTAB_ENT(9, 2452),
+        CHANTAB_ENT(10, 2457),
+        CHANTAB_ENT(11, 2462),
+        CHANTAB_ENT(12, 2467),
+        CHANTAB_ENT(13, 2472),
+        CHANTAB_ENT(14, 2484),
+};
+
+#define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
+static struct ieee80211_channel b43_a_chantable[] = {
+        CHANTAB_ENT(36, 5180),
+        CHANTAB_ENT(40, 5200),
+        CHANTAB_ENT(44, 5220),
+        CHANTAB_ENT(48, 5240),
+        CHANTAB_ENT(52, 5260),
+        CHANTAB_ENT(56, 5280),
+        CHANTAB_ENT(60, 5300),
+        CHANTAB_ENT(64, 5320),
+        CHANTAB_ENT(149, 5745),
+        CHANTAB_ENT(153, 5765),
+        CHANTAB_ENT(157, 5785),
+        CHANTAB_ENT(161, 5805),
+        CHANTAB_ENT(165, 5825),
+};
+
+#define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
+
+static void b43_wireless_core_exit(struct b43_wldev *dev);
+static int b43_wireless_core_init(struct b43_wldev *dev);
+static void b43_wireless_core_stop(struct b43_wldev *dev);
+static int b43_wireless_core_start(struct b43_wldev *dev);
+
+static int b43_ratelimit(struct b43_wl *wl)
+{
+        if (!wl || !wl->current_dev)
+                return 1;
+        if (b43_status(wl->current_dev) < B43_STAT_STARTED)
+                return 1;
+        /* We are up and running.
+         * Ratelimit the messages to avoid DoS over the net. */
+        return net_ratelimit();
+}
+
+void b43info(struct b43_wl *wl, const char *fmt, ...)
+{
+        va_list args;
+
+        if (!b43_ratelimit(wl))
+                return;
+        va_start(args, fmt);
+        printk(KERN_INFO "b43-%s: ",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
+        vprintk(fmt, args);
+        va_end(args);
+}
+
+void b43err(struct b43_wl *wl, const char *fmt, ...)
+{
+        va_list args;
+
+        if (!b43_ratelimit(wl))
+                return;
+        va_start(args, fmt);
+        printk(KERN_ERR "b43-%s ERROR: ",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
+        vprintk(fmt, args);
+        va_end(args);
+}
+
+void b43warn(struct b43_wl *wl, const char *fmt, ...)
+{
+        va_list args;
+
+        if (!b43_ratelimit(wl))
+                return;
+        va_start(args, fmt);
+        printk(KERN_WARNING "b43-%s warning: ",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
+        vprintk(fmt, args);
+        va_end(args);
+}
+
+#if B43_DEBUG
+void b43dbg(struct b43_wl *wl, const char *fmt, ...)
+{
+        va_list args;
+
+        va_start(args, fmt);
+        printk(KERN_DEBUG "b43-%s debug: ",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
+        vprintk(fmt, args);
+        va_end(args);
+}
+#endif /* DEBUG */
+
+static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
+{
+        u32 macctl;
+
+        B43_WARN_ON(offset % 4 != 0);
+
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        if (macctl & B43_MACCTL_BE)
+                val = swab32(val);
+
+        b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
+        mmiowb();
+        b43_write32(dev, B43_MMIO_RAM_DATA, val);
+}
+
+static inline
+    void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
+{
+        u32 control;
+
+        /* "offset" is the WORD offset. */
+
+        control = routing;
+        control <<= 16;
+        control |= offset;
+        b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
+}
+
+u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
+{
+        u32 ret;
+
+        if (routing == B43_SHM_SHARED) {
+                B43_WARN_ON(offset & 0x0001);
+                if (offset & 0x0003) {
+                        /* Unaligned access */
+                        b43_shm_control_word(dev, routing, offset >> 2);
+                        ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
+                        ret <<= 16;
+                        b43_shm_control_word(dev, routing, (offset >> 2) + 1);
+                        ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
+
+                        return ret;
+                }
+                offset >>= 2;
+        }
+        b43_shm_control_word(dev, routing, offset);
+        ret = b43_read32(dev, B43_MMIO_SHM_DATA);
+
+        return ret;
+}
+
+u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
+{
+        u16 ret;
+
+        if (routing == B43_SHM_SHARED) {
+                B43_WARN_ON(offset & 0x0001);
+                if (offset & 0x0003) {
+                        /* Unaligned access */
+                        b43_shm_control_word(dev, routing, offset >> 2);
+                        ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
+
+                        return ret;
+                }
+                offset >>= 2;
+        }
+        b43_shm_control_word(dev, routing, offset);
+        ret = b43_read16(dev, B43_MMIO_SHM_DATA);
+
+        return ret;
+}
+
+void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
+{
+        if (routing == B43_SHM_SHARED) {
+                B43_WARN_ON(offset & 0x0001);
+                if (offset & 0x0003) {
+                        /* Unaligned access */
+                        b43_shm_control_word(dev, routing, offset >> 2);
+                        mmiowb();
+                        b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
+                                    (value >> 16) & 0xffff);
+                        mmiowb();
+                        b43_shm_control_word(dev, routing, (offset >> 2) + 1);
+                        mmiowb();
+                        b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
+                        return;
+                }
+                offset >>= 2;
+        }
+        b43_shm_control_word(dev, routing, offset);
+        mmiowb();
+        b43_write32(dev, B43_MMIO_SHM_DATA, value);
+}
+
+void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
+{
+        if (routing == B43_SHM_SHARED) {
+                B43_WARN_ON(offset & 0x0001);
+                if (offset & 0x0003) {
+                        /* Unaligned access */
+                        b43_shm_control_word(dev, routing, offset >> 2);
+                        mmiowb();
+                        b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
+                        return;
+                }
+                offset >>= 2;
+        }
+        b43_shm_control_word(dev, routing, offset);
+        mmiowb();
+        b43_write16(dev, B43_MMIO_SHM_DATA, value);
+}
+
+/* Read HostFlags */
+u32 b43_hf_read(struct b43_wldev * dev)
+{
+        u32 ret;
+
+        ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
+        ret <<= 16;
+        ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
+
+        return ret;
+}
+
+/* Write HostFlags */
+void b43_hf_write(struct b43_wldev *dev, u32 value)
+{
+        b43_shm_write16(dev, B43_SHM_SHARED,
+                        B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
+        b43_shm_write16(dev, B43_SHM_SHARED,
+                        B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
+}
+
+void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
+{
+        /* We need to be careful. As we read the TSF from multiple
+         * registers, we should take care of register overflows.
+         * In theory, the whole tsf read process should be atomic.
+         * We try to be atomic here, by restaring the read process,
+         * if any of the high registers changed (overflew).
+         */
+        if (dev->dev->id.revision >= 3) {
+                u32 low, high, high2;
+
+                do {
+                        high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
+                        low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
+                        high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
+                } while (unlikely(high != high2));
+
+                *tsf = high;
+                *tsf <<= 32;
+                *tsf |= low;
+        } else {
+                u64 tmp;
+                u16 v0, v1, v2, v3;
+                u16 test1, test2, test3;
+
+                do {
+                        v3 = b43_read16(dev, B43_MMIO_TSF_3);
+                        v2 = b43_read16(dev, B43_MMIO_TSF_2);
+                        v1 = b43_read16(dev, B43_MMIO_TSF_1);
+                        v0 = b43_read16(dev, B43_MMIO_TSF_0);
+
+                        test3 = b43_read16(dev, B43_MMIO_TSF_3);
+                        test2 = b43_read16(dev, B43_MMIO_TSF_2);
+                        test1 = b43_read16(dev, B43_MMIO_TSF_1);
+                } while (v3 != test3 || v2 != test2 || v1 != test1);
+
+                *tsf = v3;
+                *tsf <<= 48;
+                tmp = v2;
+                tmp <<= 32;
+                *tsf |= tmp;
+                tmp = v1;
+                tmp <<= 16;
+                *tsf |= tmp;
+                *tsf |= v0;
+        }
+}
+
+static void b43_time_lock(struct b43_wldev *dev)
+{
+        u32 macctl;
+
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        macctl |= B43_MACCTL_TBTTHOLD;
+        b43_write32(dev, B43_MMIO_MACCTL, macctl);
+        /* Commit the write */
+        b43_read32(dev, B43_MMIO_MACCTL);
+}
+
+static void b43_time_unlock(struct b43_wldev *dev)
+{
+        u32 macctl;
+
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        macctl &= ~B43_MACCTL_TBTTHOLD;
+        b43_write32(dev, B43_MMIO_MACCTL, macctl);
+        /* Commit the write */
+        b43_read32(dev, B43_MMIO_MACCTL);
+}
+
+static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
+{
+        /* Be careful with the in-progress timer.
+         * First zero out the low register, so we have a full
+         * register-overflow duration to complete the operation.
+         */
+        if (dev->dev->id.revision >= 3) {
+                u32 lo = (tsf & 0x00000000FFFFFFFFULL);
+                u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
+
+                b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
+                mmiowb();
+                b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
+                mmiowb();
+                b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
+        } else {
+                u16 v0 = (tsf & 0x000000000000FFFFULL);
+                u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
+                u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
+                u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
+
+                b43_write16(dev, B43_MMIO_TSF_0, 0);
+                mmiowb();
+                b43_write16(dev, B43_MMIO_TSF_3, v3);
+                mmiowb();
+                b43_write16(dev, B43_MMIO_TSF_2, v2);
+                mmiowb();
+                b43_write16(dev, B43_MMIO_TSF_1, v1);
+                mmiowb();
+                b43_write16(dev, B43_MMIO_TSF_0, v0);
+        }
+}
+
+void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
+{
+        b43_time_lock(dev);
+        b43_tsf_write_locked(dev, tsf);
+        b43_time_unlock(dev);
+}
+
+static
+void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
+{
+        static const u8 zero_addr[ETH_ALEN] = { 0 };
+        u16 data;
+
+        if (!mac)
+                mac = zero_addr;
+
+        offset |= 0x0020;
+        b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
+
+        data = mac[0];
+        data |= mac[1] << 8;
+        b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
+        data = mac[2];
+        data |= mac[3] << 8;
+        b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
+        data = mac[4];
+        data |= mac[5] << 8;
+        b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
+}
+
+static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
+{
+        const u8 *mac;
+        const u8 *bssid;
+        u8 mac_bssid[ETH_ALEN * 2];
+        int i;
+        u32 tmp;
+
+        bssid = dev->wl->bssid;
+        mac = dev->wl->mac_addr;
+
+        b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
+
+        memcpy(mac_bssid, mac, ETH_ALEN);
+        memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
+
+        /* Write our MAC address and BSSID to template ram */
+        for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
+                tmp = (u32) (mac_bssid[i + 0]);
+                tmp |= (u32) (mac_bssid[i + 1]) << 8;
+                tmp |= (u32) (mac_bssid[i + 2]) << 16;
+                tmp |= (u32) (mac_bssid[i + 3]) << 24;
+                b43_ram_write(dev, 0x20 + i, tmp);
+        }
+}
+
+static void b43_upload_card_macaddress(struct b43_wldev *dev,
+                                       const u8 * mac_addr)
+{
+        if (mac_addr)
+                memcpy(dev->wl->mac_addr, mac_addr, ETH_ALEN);
+        else
+                memset(dev->wl->mac_addr, 0, ETH_ALEN);
+        b43_write_mac_bssid_templates(dev);
+        b43_macfilter_set(dev, B43_MACFILTER_SELF, mac_addr);
+}
+
+static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
+{
+        /* slot_time is in usec. */
+        if (dev->phy.type != B43_PHYTYPE_G)
+                return;
+        b43_write16(dev, 0x684, 510 + slot_time);
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
+}
+
+static void b43_short_slot_timing_enable(struct b43_wldev *dev)
+{
+        b43_set_slot_time(dev, 9);
+        dev->short_slot = 1;
+}
+
+static void b43_short_slot_timing_disable(struct b43_wldev *dev)
+{
+        b43_set_slot_time(dev, 20);
+        dev->short_slot = 0;
+}
+
+/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
+ * Returns the _previously_ enabled IRQ mask.
+ */
+static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
+{
+        u32 old_mask;
+
+        old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
+        b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
+
+        return old_mask;
+}
+
+/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
+ * Returns the _previously_ enabled IRQ mask.
+ */
+static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
+{
+        u32 old_mask;
+
+        old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
+        b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
+
+        return old_mask;
+}
+
+/* Synchronize IRQ top- and bottom-half.
+ * IRQs must be masked before calling this.
+ * This must not be called with the irq_lock held.
+ */
+static void b43_synchronize_irq(struct b43_wldev *dev)
+{
+        synchronize_irq(dev->dev->irq);
+        tasklet_kill(&dev->isr_tasklet);
+}
+
+/* DummyTransmission function, as documented on
+ * http://bcm-specs.sipsolutions.net/DummyTransmission
+ */
+void b43_dummy_transmission(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        unsigned int i, max_loop;
+        u16 value;
+        u32 buffer[5] = {
+                0x00000000,
+                0x00D40000,
+                0x00000000,
+                0x01000000,
+                0x00000000,
+        };
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                max_loop = 0x1E;
+                buffer[0] = 0x000201CC;
+                break;
+        case B43_PHYTYPE_B:
+        case B43_PHYTYPE_G:
+                max_loop = 0xFA;
+                buffer[0] = 0x000B846E;
+                break;
+        default:
+                B43_WARN_ON(1);
+                return;
+        }
+
+        for (i = 0; i < 5; i++)
+                b43_ram_write(dev, i * 4, buffer[i]);
+
+        /* Commit writes */
+        b43_read32(dev, B43_MMIO_MACCTL);
+
+        b43_write16(dev, 0x0568, 0x0000);
+        b43_write16(dev, 0x07C0, 0x0000);
+        value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
+        b43_write16(dev, 0x050C, value);
+        b43_write16(dev, 0x0508, 0x0000);
+        b43_write16(dev, 0x050A, 0x0000);
+        b43_write16(dev, 0x054C, 0x0000);
+        b43_write16(dev, 0x056A, 0x0014);
+        b43_write16(dev, 0x0568, 0x0826);
+        b43_write16(dev, 0x0500, 0x0000);
+        b43_write16(dev, 0x0502, 0x0030);
+
+        if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
+                b43_radio_write16(dev, 0x0051, 0x0017);
+        for (i = 0x00; i < max_loop; i++) {
+                value = b43_read16(dev, 0x050E);
+                if (value & 0x0080)
+                        break;
+                udelay(10);
+        }
+        for (i = 0x00; i < 0x0A; i++) {
+                value = b43_read16(dev, 0x050E);
+                if (value & 0x0400)
+                        break;
+                udelay(10);
+        }
+        for (i = 0x00; i < 0x0A; i++) {
+                value = b43_read16(dev, 0x0690);
+                if (!(value & 0x0100))
+                        break;
+                udelay(10);
+        }
+        if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
+                b43_radio_write16(dev, 0x0051, 0x0037);
+}
+
+static void key_write(struct b43_wldev *dev,
+                      u8 index, u8 algorithm, const u8 * key)
+{
+        unsigned int i;
+        u32 offset;
+        u16 value;
+        u16 kidx;
+
+        /* Key index/algo block */
+        kidx = b43_kidx_to_fw(dev, index);
+        value = ((kidx << 4) | algorithm);
+        b43_shm_write16(dev, B43_SHM_SHARED,
+                        B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
+
+        /* Write the key to the Key Table Pointer offset */
+        offset = dev->ktp + (index * B43_SEC_KEYSIZE);
+        for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
+                value = key[i];
+                value |= (u16) (key[i + 1]) << 8;
+                b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
+        }
+}
+
+static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
+{
+        u32 addrtmp[2] = { 0, 0, };
+        u8 per_sta_keys_start = 8;
+
+        if (b43_new_kidx_api(dev))
+                per_sta_keys_start = 4;
+
+        B43_WARN_ON(index < per_sta_keys_start);
+        /* We have two default TX keys and possibly two default RX keys.
+         * Physical mac 0 is mapped to physical key 4 or 8, depending
+         * on the firmware version.
+         * So we must adjust the index here.
+         */
+        index -= per_sta_keys_start;
+
+        if (addr) {
+                addrtmp[0] = addr[0];
+                addrtmp[0] |= ((u32) (addr[1]) << 8);
+                addrtmp[0] |= ((u32) (addr[2]) << 16);
+                addrtmp[0] |= ((u32) (addr[3]) << 24);
+                addrtmp[1] = addr[4];
+                addrtmp[1] |= ((u32) (addr[5]) << 8);
+        }
+
+        if (dev->dev->id.revision >= 5) {
+                /* Receive match transmitter address mechanism */
+                b43_shm_write32(dev, B43_SHM_RCMTA,
+                                (index * 2) + 0, addrtmp[0]);
+                b43_shm_write16(dev, B43_SHM_RCMTA,
+                                (index * 2) + 1, addrtmp[1]);
+        } else {
+                /* RXE (Receive Engine) and
+                 * PSM (Programmable State Machine) mechanism
+                 */
+                if (index < 8) {
+                        /* TODO write to RCM 16, 19, 22 and 25 */
+                } else {
+                        b43_shm_write32(dev, B43_SHM_SHARED,
+                                        B43_SHM_SH_PSM + (index * 6) + 0,
+                                        addrtmp[0]);
+                        b43_shm_write16(dev, B43_SHM_SHARED,
+                                        B43_SHM_SH_PSM + (index * 6) + 4,
+                                        addrtmp[1]);
+                }
+        }
+}
+
+static void do_key_write(struct b43_wldev *dev,
+                         u8 index, u8 algorithm,
+                         const u8 * key, size_t key_len, const u8 * mac_addr)
+{
+        u8 buf[B43_SEC_KEYSIZE] = { 0, };
+        u8 per_sta_keys_start = 8;
+
+        if (b43_new_kidx_api(dev))
+                per_sta_keys_start = 4;
+
+        B43_WARN_ON(index >= dev->max_nr_keys);
+        B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
+
+        if (index >= per_sta_keys_start)
+                keymac_write(dev, index, NULL); /* First zero out mac. */
+        if (key)
+                memcpy(buf, key, key_len);
+        key_write(dev, index, algorithm, buf);
+        if (index >= per_sta_keys_start)
+                keymac_write(dev, index, mac_addr);
+
+        dev->key[index].algorithm = algorithm;
+}
+
+static int b43_key_write(struct b43_wldev *dev,
+                         int index, u8 algorithm,
+                         const u8 * key, size_t key_len,
+                         const u8 * mac_addr,
+                         struct ieee80211_key_conf *keyconf)
+{
+        int i;
+        int sta_keys_start;
+
+        if (key_len > B43_SEC_KEYSIZE)
+                return -EINVAL;
+        for (i = 0; i < dev->max_nr_keys; i++) {
+                /* Check that we don't already have this key. */
+                B43_WARN_ON(dev->key[i].keyconf == keyconf);
+        }
+        if (index < 0) {
+                /* Either pairwise key or address is 00:00:00:00:00:00
+                 * for transmit-only keys. Search the index. */
+                if (b43_new_kidx_api(dev))
+                        sta_keys_start = 4;
+                else
+                        sta_keys_start = 8;
+                for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
+                        if (!dev->key[i].keyconf) {
+                                /* found empty */
+                                index = i;
+                                break;
+                        }
+                }
+                if (index < 0) {
+                        b43err(dev->wl, "Out of hardware key memory\n");
+                        return -ENOSPC;
+                }
+        } else
+                B43_WARN_ON(index > 3);
+
+        do_key_write(dev, index, algorithm, key, key_len, mac_addr);
+        if ((index <= 3) && !b43_new_kidx_api(dev)) {
+                /* Default RX key */
+                B43_WARN_ON(mac_addr);
+                do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
+        }
+        keyconf->hw_key_idx = index;
+        dev->key[index].keyconf = keyconf;
+
+        return 0;
+}
+
+static int b43_key_clear(struct b43_wldev *dev, int index)
+{
+        if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
+                return -EINVAL;
+        do_key_write(dev, index, B43_SEC_ALGO_NONE,
+                     NULL, B43_SEC_KEYSIZE, NULL);
+        if ((index <= 3) && !b43_new_kidx_api(dev)) {
+                do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
+                             NULL, B43_SEC_KEYSIZE, NULL);
+        }
+        dev->key[index].keyconf = NULL;
+
+        return 0;
+}
+
+static void b43_clear_keys(struct b43_wldev *dev)
+{
+        int i;
+
+        for (i = 0; i < dev->max_nr_keys; i++)
+                b43_key_clear(dev, i);
+}
+
+void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
+{
+        u32 macctl;
+        u16 ucstat;
+        bool hwps;
+        bool awake;
+        int i;
+
+        B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
+                    (ps_flags & B43_PS_DISABLED));
+        B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
+
+        if (ps_flags & B43_PS_ENABLED) {
+                hwps = 1;
+        } else if (ps_flags & B43_PS_DISABLED) {
+                hwps = 0;
+        } else {
+                //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
+                //      and thus is not an AP and we are associated, set bit 25
+        }
+        if (ps_flags & B43_PS_AWAKE) {
+                awake = 1;
+        } else if (ps_flags & B43_PS_ASLEEP) {
+                awake = 0;
+        } else {
+                //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
+                //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
+                //      successful, set bit26
+        }
+
+/* FIXME: For now we force awake-on and hwps-off */
+        hwps = 0;
+        awake = 1;
+
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        if (hwps)
+                macctl |= B43_MACCTL_HWPS;
+        else
+                macctl &= ~B43_MACCTL_HWPS;
+        if (awake)
+                macctl |= B43_MACCTL_AWAKE;
+        else
+                macctl &= ~B43_MACCTL_AWAKE;
+        b43_write32(dev, B43_MMIO_MACCTL, macctl);
+        /* Commit write */
+        b43_read32(dev, B43_MMIO_MACCTL);
+        if (awake && dev->dev->id.revision >= 5) {
+                /* Wait for the microcode to wake up. */
+                for (i = 0; i < 100; i++) {
+                        ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
+                                                B43_SHM_SH_UCODESTAT);
+                        if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
+                                break;
+                        udelay(10);
+                }
+        }
+}
+
+/* Turn the Analog ON/OFF */
+static void b43_switch_analog(struct b43_wldev *dev, int on)
+{
+        b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
+}
+
+void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
+{
+        u32 tmslow;
+        u32 macctl;
+
+        flags |= B43_TMSLOW_PHYCLKEN;
+        flags |= B43_TMSLOW_PHYRESET;
+        ssb_device_enable(dev->dev, flags);
+        msleep(2);              /* Wait for the PLL to turn on. */
+
+        /* Now take the PHY out of Reset again */
+        tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
+        tmslow |= SSB_TMSLOW_FGC;
+        tmslow &= ~B43_TMSLOW_PHYRESET;
+        ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+        ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
+        msleep(1);
+        tmslow &= ~SSB_TMSLOW_FGC;
+        ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
+        ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
+        msleep(1);
+
+        /* Turn Analog ON */
+        b43_switch_analog(dev, 1);
+
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        macctl &= ~B43_MACCTL_GMODE;
+        if (flags & B43_TMSLOW_GMODE)
+                macctl |= B43_MACCTL_GMODE;
+        macctl |= B43_MACCTL_IHR_ENABLED;
+        b43_write32(dev, B43_MMIO_MACCTL, macctl);
+}
+
+static void handle_irq_transmit_status(struct b43_wldev *dev)
+{
+        u32 v0, v1;
+        u16 tmp;
+        struct b43_txstatus stat;
+
+        while (1) {
+                v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
+                if (!(v0 & 0x00000001))
+                        break;
+                v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
+
+                stat.cookie = (v0 >> 16);
+                stat.seq = (v1 & 0x0000FFFF);
+                stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
+                tmp = (v0 & 0x0000FFFF);
+                stat.frame_count = ((tmp & 0xF000) >> 12);
+                stat.rts_count = ((tmp & 0x0F00) >> 8);
+                stat.supp_reason = ((tmp & 0x001C) >> 2);
+                stat.pm_indicated = !!(tmp & 0x0080);
+                stat.intermediate = !!(tmp & 0x0040);
+                stat.for_ampdu = !!(tmp & 0x0020);
+                stat.acked = !!(tmp & 0x0002);
+
+                b43_handle_txstatus(dev, &stat);
+        }
+}
+
+static void drain_txstatus_queue(struct b43_wldev *dev)
+{
+        u32 dummy;
+
+        if (dev->dev->id.revision < 5)
+                return;
+        /* Read all entries from the microcode TXstatus FIFO
+         * and throw them away.
+         */
+        while (1) {
+                dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
+                if (!(dummy & 0x00000001))
+                        break;
+                dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
+        }
+}
+
+static u32 b43_jssi_read(struct b43_wldev *dev)
+{
+        u32 val = 0;
+
+        val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
+        val <<= 16;
+        val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
+
+        return val;
+}
+
+static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
+{
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
+}
+
+static void b43_generate_noise_sample(struct b43_wldev *dev)
+{
+        b43_jssi_write(dev, 0x7F7F7F7F);
+        b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
+                    b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
+                    | (1 << 4));
+        B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
+}
+
+static void b43_calculate_link_quality(struct b43_wldev *dev)
+{
+        /* Top half of Link Quality calculation. */
+
+        if (dev->noisecalc.calculation_running)
+                return;
+        dev->noisecalc.channel_at_start = dev->phy.channel;
+        dev->noisecalc.calculation_running = 1;
+        dev->noisecalc.nr_samples = 0;
+
+        b43_generate_noise_sample(dev);
+}
+
+static void handle_irq_noise(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 tmp;
+        u8 noise[4];
+        u8 i, j;
+        s32 average;
+
+        /* Bottom half of Link Quality calculation. */
+
+        B43_WARN_ON(!dev->noisecalc.calculation_running);
+        if (dev->noisecalc.channel_at_start != phy->channel)
+                goto drop_calculation;
+        *((u32 *) noise) = cpu_to_le32(b43_jssi_read(dev));
+        if (noise[0] == 0x7F || noise[1] == 0x7F ||
+            noise[2] == 0x7F || noise[3] == 0x7F)
+                goto generate_new;
+
+        /* Get the noise samples. */
+        B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
+        i = dev->noisecalc.nr_samples;
+        noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+        noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+        noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+        noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
+        dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
+        dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
+        dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
+        dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
+        dev->noisecalc.nr_samples++;
+        if (dev->noisecalc.nr_samples == 8) {
+                /* Calculate the Link Quality by the noise samples. */
+                average = 0;
+                for (i = 0; i < 8; i++) {
+                        for (j = 0; j < 4; j++)
+                                average += dev->noisecalc.samples[i][j];
+                }
+                average /= (8 * 4);
+                average *= 125;
+                average += 64;
+                average /= 128;
+                tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
+                tmp = (tmp / 128) & 0x1F;
+                if (tmp >= 8)
+                        average += 2;
+                else
+                        average -= 25;
+                if (tmp == 8)
+                        average -= 72;
+                else
+                        average -= 48;
+
+                dev->stats.link_noise = average;
+              drop_calculation:
+                dev->noisecalc.calculation_running = 0;
+                return;
+        }
+      generate_new:
+        b43_generate_noise_sample(dev);
+}
+
+static void handle_irq_tbtt_indication(struct b43_wldev *dev)
+{
+        if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
+                ///TODO: PS TBTT
+        } else {
+                if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
+                        b43_power_saving_ctl_bits(dev, 0);
+        }
+        dev->reg124_set_0x4 = 0;
+        if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
+                dev->reg124_set_0x4 = 1;
+}
+
+static void handle_irq_atim_end(struct b43_wldev *dev)
+{
+        if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
+                return;
+        b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
+                    b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
+                    | 0x4);
+}
+
+static void handle_irq_pmq(struct b43_wldev *dev)
+{
+        u32 tmp;
+
+        //TODO: AP mode.
+
+        while (1) {
+                tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
+                if (!(tmp & 0x00000008))
+                        break;
+        }
+        /* 16bit write is odd, but correct. */
+        b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
+}
+
+static void b43_write_template_common(struct b43_wldev *dev,
+                                      const u8 * data, u16 size,
+                                      u16 ram_offset,
+                                      u16 shm_size_offset, u8 rate)
+{
+        u32 i, tmp;
+        struct b43_plcp_hdr4 plcp;
+
+        plcp.data = 0;
+        b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
+        b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
+        ram_offset += sizeof(u32);
+        /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
+         * So leave the first two bytes of the next write blank.
+         */
+        tmp = (u32) (data[0]) << 16;
+        tmp |= (u32) (data[1]) << 24;
+        b43_ram_write(dev, ram_offset, tmp);
+        ram_offset += sizeof(u32);
+        for (i = 2; i < size; i += sizeof(u32)) {
+                tmp = (u32) (data[i + 0]);
+                if (i + 1 < size)
+                        tmp |= (u32) (data[i + 1]) << 8;
+                if (i + 2 < size)
+                        tmp |= (u32) (data[i + 2]) << 16;
+                if (i + 3 < size)
+                        tmp |= (u32) (data[i + 3]) << 24;
+                b43_ram_write(dev, ram_offset + i - 2, tmp);
+        }
+        b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
+                        size + sizeof(struct b43_plcp_hdr6));
+}
+
+static void b43_write_beacon_template(struct b43_wldev *dev,
+                                      u16 ram_offset,
+                                      u16 shm_size_offset, u8 rate)
+{
+        int len;
+        const u8 *data;
+
+        B43_WARN_ON(!dev->cached_beacon);
+        len = min((size_t) dev->cached_beacon->len,
+                  0x200 - sizeof(struct b43_plcp_hdr6));
+        data = (const u8 *)(dev->cached_beacon->data);
+        b43_write_template_common(dev, data,
+                                  len, ram_offset, shm_size_offset, rate);
+}
+
+static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
+                                      u16 shm_offset, u16 size, u8 rate)
+{
+        struct b43_plcp_hdr4 plcp;
+        u32 tmp;
+        __le16 dur;
+
+        plcp.data = 0;
+        b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
+        dur = ieee80211_generic_frame_duration(dev->wl->hw,
+                                               dev->wl->if_id, size,
+                                               B43_RATE_TO_BASE100KBPS(rate));
+        /* Write PLCP in two parts and timing for packet transfer */
+        tmp = le32_to_cpu(plcp.data);
+        b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
+        b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
+        b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
+}
+
+/* Instead of using custom probe response template, this function
+ * just patches custom beacon template by:
+ * 1) Changing packet type
+ * 2) Patching duration field
+ * 3) Stripping TIM
+ */
+static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
+                                   u16 * dest_size, u8 rate)
+{
+        const u8 *src_data;
+        u8 *dest_data;
+        u16 src_size, elem_size, src_pos, dest_pos;
+        __le16 dur;
+        struct ieee80211_hdr *hdr;
+
+        B43_WARN_ON(!dev->cached_beacon);
+        src_size = dev->cached_beacon->len;
+        src_data = (const u8 *)dev->cached_beacon->data;
+
+        if (unlikely(src_size < 0x24)) {
+                b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
+                return NULL;
+        }
+
+        dest_data = kmalloc(src_size, GFP_ATOMIC);
+        if (unlikely(!dest_data))
+                return NULL;
+
+        /* 0x24 is offset of first variable-len Information-Element
+         * in beacon frame.
+         */
+        memcpy(dest_data, src_data, 0x24);
+        src_pos = dest_pos = 0x24;
+        for (; src_pos < src_size - 2; src_pos += elem_size) {
+                elem_size = src_data[src_pos + 1] + 2;
+                if (src_data[src_pos] != 0x05) {        /* TIM */
+                        memcpy(dest_data + dest_pos, src_data + src_pos,
+                               elem_size);
+                        dest_pos += elem_size;
+                }
+        }
+        *dest_size = dest_pos;
+        hdr = (struct ieee80211_hdr *)dest_data;
+
+        /* Set the frame control. */
+        hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
+                                         IEEE80211_STYPE_PROBE_RESP);
+        dur = ieee80211_generic_frame_duration(dev->wl->hw,
+                                               dev->wl->if_id, *dest_size,
+                                               B43_RATE_TO_BASE100KBPS(rate));
+        hdr->duration_id = dur;
+
+        return dest_data;
+}
+
+static void b43_write_probe_resp_template(struct b43_wldev *dev,
+                                          u16 ram_offset,
+                                          u16 shm_size_offset, u8 rate)
+{
+        u8 *probe_resp_data;
+        u16 size;
+
+        B43_WARN_ON(!dev->cached_beacon);
+        size = dev->cached_beacon->len;
+        probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
+        if (unlikely(!probe_resp_data))
+                return;
+
+        /* Looks like PLCP headers plus packet timings are stored for
+         * all possible basic rates
+         */
+        b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
+        b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
+        b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
+        b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
+
+        size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
+        b43_write_template_common(dev, probe_resp_data,
+                                  size, ram_offset, shm_size_offset, rate);
+        kfree(probe_resp_data);
+}
+
+static int b43_refresh_cached_beacon(struct b43_wldev *dev,
+                                     struct sk_buff *beacon)
+{
+        if (dev->cached_beacon)
+                kfree_skb(dev->cached_beacon);
+        dev->cached_beacon = beacon;
+
+        return 0;
+}
+
+static void b43_update_templates(struct b43_wldev *dev)
+{
+        u32 status;
+
+        B43_WARN_ON(!dev->cached_beacon);
+
+        b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
+        b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
+        b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
+
+        status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
+        status |= 0x03;
+        b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
+}
+
+static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
+{
+        int err;
+
+        err = b43_refresh_cached_beacon(dev, beacon);
+        if (unlikely(err))
+                return;
+        b43_update_templates(dev);
+}
+
+static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
+{
+        u32 tmp;
+        u16 i, len;
+
+        len = min((u16) ssid_len, (u16) 0x100);
+        for (i = 0; i < len; i += sizeof(u32)) {
+                tmp = (u32) (ssid[i + 0]);
+                if (i + 1 < len)
+                        tmp |= (u32) (ssid[i + 1]) << 8;
+                if (i + 2 < len)
+                        tmp |= (u32) (ssid[i + 2]) << 16;
+                if (i + 3 < len)
+                        tmp |= (u32) (ssid[i + 3]) << 24;
+                b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
+        }
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
+}
+
+static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
+{
+        b43_time_lock(dev);
+        if (dev->dev->id.revision >= 3) {
+                b43_write32(dev, 0x188, (beacon_int << 16));
+        } else {
+                b43_write16(dev, 0x606, (beacon_int >> 6));
+                b43_write16(dev, 0x610, beacon_int);
+        }
+        b43_time_unlock(dev);
+}
+
+static void handle_irq_beacon(struct b43_wldev *dev)
+{
+        u32 status;
+
+        if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+                return;
+
+        dev->irq_savedstate &= ~B43_IRQ_BEACON;
+        status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
+
+        if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
+                /* ACK beacon IRQ. */
+                b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
+                dev->irq_savedstate |= B43_IRQ_BEACON;
+                if (dev->cached_beacon)
+                        kfree_skb(dev->cached_beacon);
+                dev->cached_beacon = NULL;
+                return;
+        }
+        if (!(status & 0x1)) {
+                b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
+                status |= 0x1;
+                b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
+        }
+        if (!(status & 0x2)) {
+                b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
+                status |= 0x2;
+                b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
+        }
+}
+
+static void handle_irq_ucode_debug(struct b43_wldev *dev)
+{
+        //TODO
+}
+
+/* Interrupt handler bottom-half */
+static void b43_interrupt_tasklet(struct b43_wldev *dev)
+{
+        u32 reason;
+        u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
+        u32 merged_dma_reason = 0;
+        int i, activity = 0;
+        unsigned long flags;
+
+        spin_lock_irqsave(&dev->wl->irq_lock, flags);
+
+        B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
+
+        reason = dev->irq_reason;
+        for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
+                dma_reason[i] = dev->dma_reason[i];
+                merged_dma_reason |= dma_reason[i];
+        }
+
+        if (unlikely(reason & B43_IRQ_MAC_TXERR))
+                b43err(dev->wl, "MAC transmission error\n");
+
+        if (unlikely(reason & B43_IRQ_PHY_TXERR))
+                b43err(dev->wl, "PHY transmission error\n");
+
+        if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
+                                          B43_DMAIRQ_NONFATALMASK))) {
+                if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
+                        b43err(dev->wl, "Fatal DMA error: "
+                               "0x%08X, 0x%08X, 0x%08X, "
+                               "0x%08X, 0x%08X, 0x%08X\n",
+                               dma_reason[0], dma_reason[1],
+                               dma_reason[2], dma_reason[3],
+                               dma_reason[4], dma_reason[5]);
+                        b43_controller_restart(dev, "DMA error");
+                        mmiowb();
+                        spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+                        return;
+                }
+                if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
+                        b43err(dev->wl, "DMA error: "
+                               "0x%08X, 0x%08X, 0x%08X, "
+                               "0x%08X, 0x%08X, 0x%08X\n",
+                               dma_reason[0], dma_reason[1],
+                               dma_reason[2], dma_reason[3],
+                               dma_reason[4], dma_reason[5]);
+                }
+        }
+
+        if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
+                handle_irq_ucode_debug(dev);
+        if (reason & B43_IRQ_TBTT_INDI)
+                handle_irq_tbtt_indication(dev);
+        if (reason & B43_IRQ_ATIM_END)
+                handle_irq_atim_end(dev);
+        if (reason & B43_IRQ_BEACON)
+                handle_irq_beacon(dev);
+        if (reason & B43_IRQ_PMQ)
+                handle_irq_pmq(dev);
+        if (reason & B43_IRQ_TXFIFO_FLUSH_OK) ;
+        /*TODO*/ if (reason & B43_IRQ_NOISESAMPLE_OK)
+                handle_irq_noise(dev);
+
+        /* Check the DMA reason registers for received data. */
+        if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
+                if (b43_using_pio(dev))
+                        b43_pio_rx(dev->pio.queue0);
+                else
+                        b43_dma_rx(dev->dma.rx_ring0);
+                /* We intentionally don't set "activity" to 1, here. */
+        }
+        B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
+        B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
+        if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
+                if (b43_using_pio(dev))
+                        b43_pio_rx(dev->pio.queue3);
+                else
+                        b43_dma_rx(dev->dma.rx_ring3);
+                activity = 1;
+        }
+        B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
+        B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
+
+        if (reason & B43_IRQ_TX_OK) {
+                handle_irq_transmit_status(dev);
+                activity = 1;
+                //TODO: In AP mode, this also causes sending of powersave responses.
+        }
+
+        if (!modparam_noleds)
+                b43_leds_update(dev, activity);
+        b43_interrupt_enable(dev, dev->irq_savedstate);
+        mmiowb();
+        spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+}
+
+static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
+{
+        u16 rxctl;
+
+        rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
+        if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
+                dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
+        else
+                dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
+}
+
+static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
+{
+        if (b43_using_pio(dev) &&
+            (dev->dev->id.revision < 3) &&
+            (!(reason & B43_IRQ_PIO_WORKAROUND))) {
+                /* Apply a PIO specific workaround to the dma_reasons */
+                pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
+                pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
+                pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
+                pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
+        }
+
+        b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
+
+        b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
+        b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
+        b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
+        b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
+        b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
+        b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
+}
+
+/* Interrupt handler top-half */
+static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
+{
+        irqreturn_t ret = IRQ_NONE;
+        struct b43_wldev *dev = dev_id;
+        u32 reason;
+
+        if (!dev)
+                return IRQ_NONE;
+
+        spin_lock(&dev->wl->irq_lock);
+
+        if (b43_status(dev) < B43_STAT_STARTED)
+                goto out;
+        reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
+        if (reason == 0xffffffff)       /* shared IRQ */
+                goto out;
+        ret = IRQ_HANDLED;
+        reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
+        if (!reason)
+                goto out;
+
+        dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
+            & 0x0001DC00;
+        dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
+            & 0x0000DC00;
+        dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
+            & 0x0000DC00;
+        dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
+            & 0x0001DC00;
+        dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
+            & 0x0000DC00;
+        dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
+            & 0x0000DC00;
+
+        b43_interrupt_ack(dev, reason);
+        /* disable all IRQs. They are enabled again in the bottom half. */
+        dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
+        /* save the reason code and call our bottom half. */
+        dev->irq_reason = reason;
+        tasklet_schedule(&dev->isr_tasklet);
+      out:
+        mmiowb();
+        spin_unlock(&dev->wl->irq_lock);
+
+        return ret;
+}
+
+static void b43_release_firmware(struct b43_wldev *dev)
+{
+        release_firmware(dev->fw.ucode);
+        dev->fw.ucode = NULL;
+        release_firmware(dev->fw.pcm);
+        dev->fw.pcm = NULL;
+        release_firmware(dev->fw.initvals);
+        dev->fw.initvals = NULL;
+        release_firmware(dev->fw.initvals_band);
+        dev->fw.initvals_band = NULL;
+}
+
+static void b43_print_fw_helptext(struct b43_wl *wl)
+{
+        b43err(wl, "You must go to "
+               "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
+               "and download the correct firmware (version 4).\n");
+}
+
+static int do_request_fw(struct b43_wldev *dev,
+                         const char *name,
+                         const struct firmware **fw)
+{
+        const size_t plen = sizeof(modparam_fwpostfix) + 32;
+        char path[plen];
+        struct b43_fw_header *hdr;
+        u32 size;
+        int err;
+
+        if (!name)
+                return 0;
+
+        snprintf(path, ARRAY_SIZE(path),
+                 "b43%s/%s.fw",
+                 modparam_fwpostfix, name);
+        err = request_firmware(fw, path, dev->dev->dev);
+        if (err) {
+                b43err(dev->wl, "Firmware file \"%s\" not found "
+                       "or load failed.\n", path);
+                return err;
+        }
+        if ((*fw)->size < sizeof(struct b43_fw_header))
+                goto err_format;
+        hdr = (struct b43_fw_header *)((*fw)->data);
+        switch (hdr->type) {
+        case B43_FW_TYPE_UCODE:
+        case B43_FW_TYPE_PCM:
+                size = be32_to_cpu(hdr->size);
+                if (size != (*fw)->size - sizeof(struct b43_fw_header))
+                        goto err_format;
+                /* fallthrough */
+        case B43_FW_TYPE_IV:
+                if (hdr->ver != 1)
+                        goto err_format;
+                break;
+        default:
+                goto err_format;
+        }
+
+        return err;
+
+err_format:
+        b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
+        return -EPROTO;
+}
+
+static int b43_request_firmware(struct b43_wldev *dev)
+{
+        struct b43_firmware *fw = &dev->fw;
+        const u8 rev = dev->dev->id.revision;
+        const char *filename;
+        u32 tmshigh;
+        int err;
+
+        tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
+        if (!fw->ucode) {
+                if ((rev >= 5) && (rev <= 10))
+                        filename = "ucode5";
+                else if ((rev >= 11) && (rev <= 12))
+                        filename = "ucode11";
+                else if (rev >= 13)
+                        filename = "ucode13";
+                else
+                        goto err_no_ucode;
+                err = do_request_fw(dev, filename, &fw->ucode);
+                if (err)
+                        goto err_load;
+        }
+        if (!fw->pcm) {
+                if ((rev >= 5) && (rev <= 10))
+                        filename = "pcm5";
+                else if (rev >= 11)
+                        filename = NULL;
+                else
+                        goto err_no_pcm;
+                err = do_request_fw(dev, filename, &fw->pcm);
+                if (err)
+                        goto err_load;
+        }
+        if (!fw->initvals) {
+                switch (dev->phy.type) {
+                case B43_PHYTYPE_A:
+                        if ((rev >= 5) && (rev <= 10)) {
+                                if (tmshigh & B43_TMSHIGH_GPHY)
+                                        filename = "a0g1initvals5";
+                                else
+                                        filename = "a0g0initvals5";
+                        } else
+                                goto err_no_initvals;
+                        break;
+                case B43_PHYTYPE_G:
+                        if ((rev >= 5) && (rev <= 10))
+                                filename = "b0g0initvals5";
+                        else if (rev >= 13)
+                                filename = "lp0initvals13";
+                        else
+                                goto err_no_initvals;
+                        break;
+                default:
+                        goto err_no_initvals;
+                }
+                err = do_request_fw(dev, filename, &fw->initvals);
+                if (err)
+                        goto err_load;
+        }
+        if (!fw->initvals_band) {
+                switch (dev->phy.type) {
+                case B43_PHYTYPE_A:
+                        if ((rev >= 5) && (rev <= 10)) {
+                                if (tmshigh & B43_TMSHIGH_GPHY)
+                                        filename = "a0g1bsinitvals5";
+                                else
+                                        filename = "a0g0bsinitvals5";
+                        } else if (rev >= 11)
+                                filename = NULL;
+                        else
+                                goto err_no_initvals;
+                        break;
+                case B43_PHYTYPE_G:
+                        if ((rev >= 5) && (rev <= 10))
+                                filename = "b0g0bsinitvals5";
+                        else if (rev >= 11)
+                                filename = NULL;
+                        else
+                                goto err_no_initvals;
+                        break;
+                default:
+                        goto err_no_initvals;
+                }
+                err = do_request_fw(dev, filename, &fw->initvals_band);
+                if (err)
+                        goto err_load;
+        }
+
+        return 0;
+
+err_load:
+        b43_print_fw_helptext(dev->wl);
+        goto error;
+
+err_no_ucode:
+        err = -ENODEV;
+        b43err(dev->wl, "No microcode available for core rev %u\n", rev);
+        goto error;
+
+err_no_pcm:
+        err = -ENODEV;
+        b43err(dev->wl, "No PCM available for core rev %u\n", rev);
+        goto error;
+
+err_no_initvals:
+        err = -ENODEV;
+        b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
+               "core rev %u\n", dev->phy.type, rev);
+        goto error;
+
+error:
+        b43_release_firmware(dev);
+        return err;
+}
+
+static int b43_upload_microcode(struct b43_wldev *dev)
+{
+        const size_t hdr_len = sizeof(struct b43_fw_header);
+        const __be32 *data;
+        unsigned int i, len;
+        u16 fwrev, fwpatch, fwdate, fwtime;
+        u32 tmp;
+        int err = 0;
+
+        /* Upload Microcode. */
+        data = (__be32 *) (dev->fw.ucode->data + hdr_len);
+        len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
+        b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
+        for (i = 0; i < len; i++) {
+                b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
+                udelay(10);
+        }
+
+        if (dev->fw.pcm) {
+                /* Upload PCM data. */
+                data = (__be32 *) (dev->fw.pcm->data + hdr_len);
+                len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
+                b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
+                b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
+                /* No need for autoinc bit in SHM_HW */
+                b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
+                for (i = 0; i < len; i++) {
+                        b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
+                        udelay(10);
+                }
+        }
+
+        b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
+        b43_write32(dev, B43_MMIO_MACCTL,
+                    B43_MACCTL_PSM_RUN |
+                    B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
+
+        /* Wait for the microcode to load and respond */
+        i = 0;
+        while (1) {
+                tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
+                if (tmp == B43_IRQ_MAC_SUSPENDED)
+                        break;
+                i++;
+                if (i >= 50) {
+                        b43err(dev->wl, "Microcode not responding\n");
+                        b43_print_fw_helptext(dev->wl);
+                        err = -ENODEV;
+                        goto out;
+                }
+                udelay(10);
+        }
+        b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
+
+        /* Get and check the revisions. */
+        fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
+        fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
+        fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
+        fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
+
+        if (fwrev <= 0x128) {
+                b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
+                       "binary drivers older than version 4.x is unsupported. "
+                       "You must upgrade your firmware files.\n");
+                b43_print_fw_helptext(dev->wl);
+                b43_write32(dev, B43_MMIO_MACCTL, 0);
+                err = -EOPNOTSUPP;
+                goto out;
+        }
+        b43dbg(dev->wl, "Loading firmware version %u.%u "
+               "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
+               fwrev, fwpatch,
+               (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
+               (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
+
+        dev->fw.rev = fwrev;
+        dev->fw.patch = fwpatch;
+
+      out:
+        return err;
+}
+
+static int b43_write_initvals(struct b43_wldev *dev,
+                              const struct b43_iv *ivals,
+                              size_t count,
+                              size_t array_size)
+{
+        const struct b43_iv *iv;
+        u16 offset;
+        size_t i;
+        bool bit32;
+
+        BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
+        iv = ivals;
+        for (i = 0; i < count; i++) {
+                if (array_size < sizeof(iv->offset_size))
+                        goto err_format;
+                array_size -= sizeof(iv->offset_size);
+                offset = be16_to_cpu(iv->offset_size);
+                bit32 = !!(offset & B43_IV_32BIT);
+                offset &= B43_IV_OFFSET_MASK;
+                if (offset >= 0x1000)
+                        goto err_format;
+                if (bit32) {
+                        u32 value;
+
+                        if (array_size < sizeof(iv->data.d32))
+                                goto err_format;
+                        array_size -= sizeof(iv->data.d32);
+
+                        value = be32_to_cpu(get_unaligned(&iv->data.d32));
+                        b43_write32(dev, offset, value);
+
+                        iv = (const struct b43_iv *)((const uint8_t *)iv +
+                                                        sizeof(__be16) +
+                                                        sizeof(__be32));
+                } else {
+                        u16 value;
+
+                        if (array_size < sizeof(iv->data.d16))
+                                goto err_format;
+                        array_size -= sizeof(iv->data.d16);
+
+                        value = be16_to_cpu(iv->data.d16);
+                        b43_write16(dev, offset, value);
+
+                        iv = (const struct b43_iv *)((const uint8_t *)iv +
+                                                        sizeof(__be16) +
+                                                        sizeof(__be16));
+                }
+        }
+        if (array_size)
+                goto err_format;
+
+        return 0;
+
+err_format:
+        b43err(dev->wl, "Initial Values Firmware file-format error.\n");
+        b43_print_fw_helptext(dev->wl);
+
+        return -EPROTO;
+}
+
+static int b43_upload_initvals(struct b43_wldev *dev)
+{
+        const size_t hdr_len = sizeof(struct b43_fw_header);
+        const struct b43_fw_header *hdr;
+        struct b43_firmware *fw = &dev->fw;
+        const struct b43_iv *ivals;
+        size_t count;
+        int err;
+
+        hdr = (const struct b43_fw_header *)(fw->initvals->data);
+        ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
+        count = be32_to_cpu(hdr->size);
+        err = b43_write_initvals(dev, ivals, count,
+                                 fw->initvals->size - hdr_len);
+        if (err)
+                goto out;
+        if (fw->initvals_band) {
+                hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
+                ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
+                count = be32_to_cpu(hdr->size);
+                err = b43_write_initvals(dev, ivals, count,
+                                         fw->initvals_band->size - hdr_len);
+                if (err)
+                        goto out;
+        }
+out:
+
+        return err;
+}
+
+/* Initialize the GPIOs
+ * http://bcm-specs.sipsolutions.net/GPIO
+ */
+static int b43_gpio_init(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct ssb_device *gpiodev, *pcidev = NULL;
+        u32 mask, set;
+
+        b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
+                    & ~B43_MACCTL_GPOUTSMSK);
+
+        b43_leds_switch_all(dev, 0);
+        b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
+                    | 0x000F);
+
+        mask = 0x0000001F;
+        set = 0x0000000F;
+        if (dev->dev->bus->chip_id == 0x4301) {
+                mask |= 0x0060;
+                set |= 0x0060;
+        }
+        if (0 /* FIXME: conditional unknown */ ) {
+                b43_write16(dev, B43_MMIO_GPIO_MASK,
+                            b43_read16(dev, B43_MMIO_GPIO_MASK)
+                            | 0x0100);
+                mask |= 0x0180;
+                set |= 0x0180;
+        }
+        if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL) {
+                b43_write16(dev, B43_MMIO_GPIO_MASK,
+                            b43_read16(dev, B43_MMIO_GPIO_MASK)
+                            | 0x0200);
+                mask |= 0x0200;
+                set |= 0x0200;
+        }
+        if (dev->dev->id.revision >= 2)
+                mask |= 0x0010; /* FIXME: This is redundant. */
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        pcidev = bus->pcicore.dev;
+#endif
+        gpiodev = bus->chipco.dev ? : pcidev;
+        if (!gpiodev)
+                return 0;
+        ssb_write32(gpiodev, B43_GPIO_CONTROL,
+                    (ssb_read32(gpiodev, B43_GPIO_CONTROL)
+                     & mask) | set);
+
+        return 0;
+}
+
+/* Turn off all GPIO stuff. Call this on module unload, for example. */
+static void b43_gpio_cleanup(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct ssb_device *gpiodev, *pcidev = NULL;
+
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        pcidev = bus->pcicore.dev;
+#endif
+        gpiodev = bus->chipco.dev ? : pcidev;
+        if (!gpiodev)
+                return;
+        ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
+}
+
+/* http://bcm-specs.sipsolutions.net/EnableMac */
+void b43_mac_enable(struct b43_wldev *dev)
+{
+        dev->mac_suspended--;
+        B43_WARN_ON(dev->mac_suspended < 0);
+        if (dev->mac_suspended == 0) {
+                b43_write32(dev, B43_MMIO_MACCTL,
+                            b43_read32(dev, B43_MMIO_MACCTL)
+                            | B43_MACCTL_ENABLED);
+                b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
+                            B43_IRQ_MAC_SUSPENDED);
+                /* Commit writes */
+                b43_read32(dev, B43_MMIO_MACCTL);
+                b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
+                b43_power_saving_ctl_bits(dev, 0);
+        }
+}
+
+/* http://bcm-specs.sipsolutions.net/SuspendMAC */
+void b43_mac_suspend(struct b43_wldev *dev)
+{
+        int i;
+        u32 tmp;
+
+        B43_WARN_ON(dev->mac_suspended < 0);
+        if (dev->mac_suspended == 0) {
+                b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
+                b43_write32(dev, B43_MMIO_MACCTL,
+                            b43_read32(dev, B43_MMIO_MACCTL)
+                            & ~B43_MACCTL_ENABLED);
+                /* force pci to flush the write */
+                b43_read32(dev, B43_MMIO_MACCTL);
+                for (i = 10000; i; i--) {
+                        tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
+                        if (tmp & B43_IRQ_MAC_SUSPENDED)
+                                goto out;
+                        udelay(1);
+                }
+                b43err(dev->wl, "MAC suspend failed\n");
+        }
+      out:
+        dev->mac_suspended++;
+}
+
+static void b43_adjust_opmode(struct b43_wldev *dev)
+{
+        struct b43_wl *wl = dev->wl;
+        u32 ctl;
+        u16 cfp_pretbtt;
+
+        ctl = b43_read32(dev, B43_MMIO_MACCTL);
+        /* Reset status to STA infrastructure mode. */
+        ctl &= ~B43_MACCTL_AP;
+        ctl &= ~B43_MACCTL_KEEP_CTL;
+        ctl &= ~B43_MACCTL_KEEP_BADPLCP;
+        ctl &= ~B43_MACCTL_KEEP_BAD;
+        ctl &= ~B43_MACCTL_PROMISC;
+        ctl |= B43_MACCTL_INFRA;
+
+        if (wl->operating) {
+                switch (wl->if_type) {
+                case IEEE80211_IF_TYPE_AP:
+                        ctl |= B43_MACCTL_AP;
+                        break;
+                case IEEE80211_IF_TYPE_IBSS:
+                        ctl &= ~B43_MACCTL_INFRA;
+                        break;
+                case IEEE80211_IF_TYPE_STA:
+                case IEEE80211_IF_TYPE_MNTR:
+                case IEEE80211_IF_TYPE_WDS:
+                        break;
+                default:
+                        B43_WARN_ON(1);
+                }
+        }
+        if (wl->monitor) {
+                ctl |= B43_MACCTL_KEEP_CTL;
+                if (modparam_mon_keep_bad)
+                        ctl |= B43_MACCTL_KEEP_BAD;
+                if (modparam_mon_keep_badplcp)
+                        ctl |= B43_MACCTL_KEEP_BADPLCP;
+        }
+        if (wl->promisc)
+                ctl |= B43_MACCTL_PROMISC;
+        /* Workaround: On old hardware the HW-MAC-address-filter
+         * doesn't work properly, so always run promisc in filter
+         * it in software. */
+        if (dev->dev->id.revision <= 4)
+                ctl |= B43_MACCTL_PROMISC;
+
+        b43_write32(dev, B43_MMIO_MACCTL, ctl);
+
+        cfp_pretbtt = 2;
+        if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
+                if (dev->dev->bus->chip_id == 0x4306 &&
+                    dev->dev->bus->chip_rev == 3)
+                        cfp_pretbtt = 100;
+                else
+                        cfp_pretbtt = 50;
+        }
+        b43_write16(dev, 0x612, cfp_pretbtt);
+}
+
+static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
+{
+        u16 offset;
+
+        if (is_ofdm) {
+                offset = 0x480;
+                offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
+        } else {
+                offset = 0x4C0;
+                offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
+        }
+        b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
+                        b43_shm_read16(dev, B43_SHM_SHARED, offset));
+}
+
+static void b43_rate_memory_init(struct b43_wldev *dev)
+{
+        switch (dev->phy.type) {
+        case B43_PHYTYPE_A:
+        case B43_PHYTYPE_G:
+                b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
+                b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
+                b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
+                b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
+                b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
+                b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
+                b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
+                if (dev->phy.type == B43_PHYTYPE_A)
+                        break;
+                /* fallthrough */
+        case B43_PHYTYPE_B:
+                b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
+                b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
+                b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
+                b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+/* Set the TX-Antenna for management frames sent by firmware. */
+static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
+{
+        u16 ant = 0;
+        u16 tmp;
+
+        switch (antenna) {
+        case B43_ANTENNA0:
+                ant |= B43_TX4_PHY_ANT0;
+                break;
+        case B43_ANTENNA1:
+                ant |= B43_TX4_PHY_ANT1;
+                break;
+        case B43_ANTENNA_AUTO:
+                ant |= B43_TX4_PHY_ANTLAST;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+
+        /* FIXME We also need to set the other flags of the PHY control field somewhere. */
+
+        /* For Beacons */
+        tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
+        tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
+        /* For ACK/CTS */
+        tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
+        tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
+        /* For Probe Resposes */
+        tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
+        tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
+}
+
+/* This is the opposite of b43_chip_init() */
+static void b43_chip_exit(struct b43_wldev *dev)
+{
+        b43_radio_turn_off(dev);
+        if (!modparam_noleds)
+                b43_leds_exit(dev);
+        b43_gpio_cleanup(dev);
+        /* firmware is released later */
+}
+
+/* Initialize the chip
+ * http://bcm-specs.sipsolutions.net/ChipInit
+ */
+static int b43_chip_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        int err, tmp;
+        u32 value32;
+        u16 value16;
+
+        b43_write32(dev, B43_MMIO_MACCTL,
+                    B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
+
+        err = b43_request_firmware(dev);
+        if (err)
+                goto out;
+        err = b43_upload_microcode(dev);
+        if (err)
+                goto out;       /* firmware is released later */
+
+        err = b43_gpio_init(dev);
+        if (err)
+                goto out;       /* firmware is released later */
+        err = b43_upload_initvals(dev);
+        if (err)
+                goto err_gpio_cleanup;
+        b43_radio_turn_on(dev);
+        dev->radio_hw_enable = b43_is_hw_radio_enabled(dev);
+        b43dbg(dev->wl, "Radio %s by hardware\n",
+               (dev->radio_hw_enable == 0) ? "disabled" : "enabled");
+
+        b43_write16(dev, 0x03E6, 0x0000);
+        err = b43_phy_init(dev);
+        if (err)
+                goto err_radio_off;
+
+        /* Select initial Interference Mitigation. */
+        tmp = phy->interfmode;
+        phy->interfmode = B43_INTERFMODE_NONE;
+        b43_radio_set_interference_mitigation(dev, tmp);
+
+        b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
+        b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
+
+        if (phy->type == B43_PHYTYPE_B) {
+                value16 = b43_read16(dev, 0x005E);
+                value16 |= 0x0004;
+                b43_write16(dev, 0x005E, value16);
+        }
+        b43_write32(dev, 0x0100, 0x01000000);
+        if (dev->dev->id.revision < 5)
+                b43_write32(dev, 0x010C, 0x01000000);
+
+        b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
+                    & ~B43_MACCTL_INFRA);
+        b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
+                    | B43_MACCTL_INFRA);
+        /* Let beacons come through */
+        b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
+                    | B43_MACCTL_BEACPROMISC);
+
+        if (b43_using_pio(dev)) {
+                b43_write32(dev, 0x0210, 0x00000100);
+                b43_write32(dev, 0x0230, 0x00000100);
+                b43_write32(dev, 0x0250, 0x00000100);
+                b43_write32(dev, 0x0270, 0x00000100);
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
+        }
+
+        /* Probe Response Timeout value */
+        /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
+
+        /* Initially set the wireless operation mode. */
+        b43_adjust_opmode(dev);
+
+        if (dev->dev->id.revision < 3) {
+                b43_write16(dev, 0x060E, 0x0000);
+                b43_write16(dev, 0x0610, 0x8000);
+                b43_write16(dev, 0x0604, 0x0000);
+                b43_write16(dev, 0x0606, 0x0200);
+        } else {
+                b43_write32(dev, 0x0188, 0x80000000);
+                b43_write32(dev, 0x018C, 0x02000000);
+        }
+        b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
+        b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
+        b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
+        b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
+        b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
+        b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
+        b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
+
+        value32 = ssb_read32(dev->dev, SSB_TMSLOW);
+        value32 |= 0x00100000;
+        ssb_write32(dev->dev, SSB_TMSLOW, value32);
+
+        b43_write16(dev, B43_MMIO_POWERUP_DELAY,
+                    dev->dev->bus->chipco.fast_pwrup_delay);
+
+        err = 0;
+        b43dbg(dev->wl, "Chip initialized\n");
+      out:
+        return err;
+
+      err_radio_off:
+        b43_radio_turn_off(dev);
+      err_gpio_cleanup:
+        b43_gpio_cleanup(dev);
+        goto out;
+}
+
+static void b43_periodic_every120sec(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
+                return;
+
+        b43_mac_suspend(dev);
+        b43_lo_g_measure(dev);
+        b43_mac_enable(dev);
+        if (b43_has_hardware_pctl(phy))
+                b43_lo_g_ctl_mark_all_unused(dev);
+}
+
+static void b43_periodic_every60sec(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (!b43_has_hardware_pctl(phy))
+                b43_lo_g_ctl_mark_all_unused(dev);
+        if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
+                b43_mac_suspend(dev);
+                b43_calc_nrssi_slope(dev);
+                if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
+                        u8 old_chan = phy->channel;
+
+                        /* VCO Calibration */
+                        if (old_chan >= 8)
+                                b43_radio_selectchannel(dev, 1, 0);
+                        else
+                                b43_radio_selectchannel(dev, 13, 0);
+                        b43_radio_selectchannel(dev, old_chan, 0);
+                }
+                b43_mac_enable(dev);
+        }
+}
+
+static void b43_periodic_every30sec(struct b43_wldev *dev)
+{
+        /* Update device statistics. */
+        b43_calculate_link_quality(dev);
+}
+
+static void b43_periodic_every15sec(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->type == B43_PHYTYPE_G) {
+                //TODO: update_aci_moving_average
+                if (phy->aci_enable && phy->aci_wlan_automatic) {
+                        b43_mac_suspend(dev);
+                        if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
+                                if (0 /*TODO: bunch of conditions */ ) {
+                                        b43_radio_set_interference_mitigation
+                                            (dev, B43_INTERFMODE_MANUALWLAN);
+                                }
+                        } else if (1 /*TODO*/) {
+                                /*
+                                   if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
+                                   b43_radio_set_interference_mitigation(dev,
+                                   B43_INTERFMODE_NONE);
+                                   }
+                                 */
+                        }
+                        b43_mac_enable(dev);
+                } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
+                           phy->rev == 1) {
+                        //TODO: implement rev1 workaround
+                }
+        }
+        b43_phy_xmitpower(dev); //FIXME: unless scanning?
+        //TODO for APHY (temperature?)
+}
+
+static void b43_periodic_every1sec(struct b43_wldev *dev)
+{
+        int radio_hw_enable;
+
+        /* check if radio hardware enabled status changed */
+        radio_hw_enable = b43_is_hw_radio_enabled(dev);
+        if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
+                dev->radio_hw_enable = radio_hw_enable;
+                b43dbg(dev->wl, "Radio hardware status changed to %s\n",
+                       (radio_hw_enable == 0) ? "disabled" : "enabled");
+                b43_leds_update(dev, 0);
+        }
+}
+
+static void do_periodic_work(struct b43_wldev *dev)
+{
+        unsigned int state;
+
+        state = dev->periodic_state;
+        if (state % 120 == 0)
+                b43_periodic_every120sec(dev);
+        if (state % 60 == 0)
+                b43_periodic_every60sec(dev);
+        if (state % 30 == 0)
+                b43_periodic_every30sec(dev);
+        if (state % 15 == 0)
+                b43_periodic_every15sec(dev);
+        b43_periodic_every1sec(dev);
+}
+
+/* Estimate a "Badness" value based on the periodic work
+ * state-machine state. "Badness" is worse (bigger), if the
+ * periodic work will take longer.
+ */
+static int estimate_periodic_work_badness(unsigned int state)
+{
+        int badness = 0;
+
+        if (state % 120 == 0)   /* every 120 sec */
+                badness += 10;
+        if (state % 60 == 0)    /* every 60 sec */
+                badness += 5;
+        if (state % 30 == 0)    /* every 30 sec */
+                badness += 1;
+        if (state % 15 == 0)    /* every 15 sec */
+                badness += 1;
+
+#define BADNESS_LIMIT   4
+        return badness;
+}
+
+static void b43_periodic_work_handler(struct work_struct *work)
+{
+        struct b43_wldev *dev =
+            container_of(work, struct b43_wldev, periodic_work.work);
+        unsigned long flags, delay;
+        u32 savedirqs = 0;
+        int badness;
+
+        mutex_lock(&dev->wl->mutex);
+
+        if (unlikely(b43_status(dev) != B43_STAT_STARTED))
+                goto out;
+        if (b43_debug(dev, B43_DBG_PWORK_STOP))
+                goto out_requeue;
+
+        badness = estimate_periodic_work_badness(dev->periodic_state);
+        if (badness > BADNESS_LIMIT) {
+                spin_lock_irqsave(&dev->wl->irq_lock, flags);
+                /* Suspend TX as we don't want to transmit packets while
+                 * we recalibrate the hardware. */
+                b43_tx_suspend(dev);
+                savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
+                /* Periodic work will take a long time, so we want it to
+                 * be preemtible and release the spinlock. */
+                spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+                b43_synchronize_irq(dev);
+
+                do_periodic_work(dev);
+
+                spin_lock_irqsave(&dev->wl->irq_lock, flags);
+                b43_interrupt_enable(dev, savedirqs);
+                b43_tx_resume(dev);
+                mmiowb();
+                spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+        } else {
+                /* Take the global driver lock. This will lock any operation. */
+                spin_lock_irqsave(&dev->wl->irq_lock, flags);
+
+                do_periodic_work(dev);
+
+                mmiowb();
+                spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+        }
+        dev->periodic_state++;
+      out_requeue:
+        if (b43_debug(dev, B43_DBG_PWORK_FAST))
+                delay = msecs_to_jiffies(50);
+        else
+                delay = round_jiffies(HZ);
+        queue_delayed_work(dev->wl->hw->workqueue, &dev->periodic_work, delay);
+      out:
+        mutex_unlock(&dev->wl->mutex);
+}
+
+static void b43_periodic_tasks_setup(struct b43_wldev *dev)
+{
+        struct delayed_work *work = &dev->periodic_work;
+
+        dev->periodic_state = 0;
+        INIT_DELAYED_WORK(work, b43_periodic_work_handler);
+        queue_delayed_work(dev->wl->hw->workqueue, work, 0);
+}
+
+/* Validate access to the chip (SHM) */
+static int b43_validate_chipaccess(struct b43_wldev *dev)
+{
+        u32 value;
+        u32 shm_backup;
+
+        shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
+        b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
+        if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
+                goto error;
+        b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
+        if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
+                goto error;
+        b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
+
+        value = b43_read32(dev, B43_MMIO_MACCTL);
+        if ((value | B43_MACCTL_GMODE) !=
+            (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
+                goto error;
+
+        value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
+        if (value)
+                goto error;
+
+        return 0;
+      error:
+        b43err(dev->wl, "Failed to validate the chipaccess\n");
+        return -ENODEV;
+}
+
+static void b43_security_init(struct b43_wldev *dev)
+{
+        dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
+        B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
+        dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
+        /* KTP is a word address, but we address SHM bytewise.
+         * So multiply by two.
+         */
+        dev->ktp *= 2;
+        if (dev->dev->id.revision >= 5) {
+                /* Number of RCMTA address slots */
+                b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
+        }
+        b43_clear_keys(dev);
+}
+
+static int b43_rng_read(struct hwrng *rng, u32 * data)
+{
+        struct b43_wl *wl = (struct b43_wl *)rng->priv;
+        unsigned long flags;
+
+        /* Don't take wl->mutex here, as it could deadlock with
+         * hwrng internal locking. It's not needed to take
+         * wl->mutex here, anyway. */
+
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+        return (sizeof(u16));
+}
+
+static void b43_rng_exit(struct b43_wl *wl)
+{
+        if (wl->rng_initialized)
+                hwrng_unregister(&wl->rng);
+}
+
+static int b43_rng_init(struct b43_wl *wl)
+{
+        int err;
+
+        snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
+                 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
+        wl->rng.name = wl->rng_name;
+        wl->rng.data_read = b43_rng_read;
+        wl->rng.priv = (unsigned long)wl;
+        wl->rng_initialized = 1;
+        err = hwrng_register(&wl->rng);
+        if (err) {
+                wl->rng_initialized = 0;
+                b43err(wl, "Failed to register the random "
+                       "number generator (%d)\n", err);
+        }
+
+        return err;
+}
+
+static int b43_tx(struct ieee80211_hw *hw,
+                  struct sk_buff *skb, struct ieee80211_tx_control *ctl)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev = wl->current_dev;
+        int err = -ENODEV;
+        unsigned long flags;
+
+        if (unlikely(!dev))
+                goto out;
+        if (unlikely(b43_status(dev) < B43_STAT_STARTED))
+                goto out;
+        /* DMA-TX is done without a global lock. */
+        if (b43_using_pio(dev)) {
+                spin_lock_irqsave(&wl->irq_lock, flags);
+                err = b43_pio_tx(dev, skb, ctl);
+                spin_unlock_irqrestore(&wl->irq_lock, flags);
+        } else
+                err = b43_dma_tx(dev, skb, ctl);
+      out:
+        if (unlikely(err))
+                return NETDEV_TX_BUSY;
+        return NETDEV_TX_OK;
+}
+
+static int b43_conf_tx(struct ieee80211_hw *hw,
+                       int queue,
+                       const struct ieee80211_tx_queue_params *params)
+{
+        return 0;
+}
+
+static int b43_get_tx_stats(struct ieee80211_hw *hw,
+                            struct ieee80211_tx_queue_stats *stats)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev = wl->current_dev;
+        unsigned long flags;
+        int err = -ENODEV;
+
+        if (!dev)
+                goto out;
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
+                if (b43_using_pio(dev))
+                        b43_pio_get_tx_stats(dev, stats);
+                else
+                        b43_dma_get_tx_stats(dev, stats);
+                err = 0;
+        }
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+      out:
+        return err;
+}
+
+static int b43_get_stats(struct ieee80211_hw *hw,
+                         struct ieee80211_low_level_stats *stats)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        unsigned long flags;
+
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        memcpy(stats, &wl->ieee_stats, sizeof(*stats));
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+        return 0;
+}
+
+static const char *phymode_to_string(unsigned int phymode)
+{
+        switch (phymode) {
+        case B43_PHYMODE_A:
+                return "A";
+        case B43_PHYMODE_B:
+                return "B";
+        case B43_PHYMODE_G:
+                return "G";
+        default:
+                B43_WARN_ON(1);
+        }
+        return "";
+}
+
+static int find_wldev_for_phymode(struct b43_wl *wl,
+                                  unsigned int phymode,
+                                  struct b43_wldev **dev, bool * gmode)
+{
+        struct b43_wldev *d;
+
+        list_for_each_entry(d, &wl->devlist, list) {
+                if (d->phy.possible_phymodes & phymode) {
+                        /* Ok, this device supports the PHY-mode.
+                         * Now figure out how the gmode bit has to be
+                         * set to support it. */
+                        if (phymode == B43_PHYMODE_A)
+                                *gmode = 0;
+                        else
+                                *gmode = 1;
+                        *dev = d;
+
+                        return 0;
+                }
+        }
+
+        return -ESRCH;
+}
+
+static void b43_put_phy_into_reset(struct b43_wldev *dev)
+{
+        struct ssb_device *sdev = dev->dev;
+        u32 tmslow;
+
+        tmslow = ssb_read32(sdev, SSB_TMSLOW);
+        tmslow &= ~B43_TMSLOW_GMODE;
+        tmslow |= B43_TMSLOW_PHYRESET;
+        tmslow |= SSB_TMSLOW_FGC;
+        ssb_write32(sdev, SSB_TMSLOW, tmslow);
+        msleep(1);
+
+        tmslow = ssb_read32(sdev, SSB_TMSLOW);
+        tmslow &= ~SSB_TMSLOW_FGC;
+        tmslow |= B43_TMSLOW_PHYRESET;
+        ssb_write32(sdev, SSB_TMSLOW, tmslow);
+        msleep(1);
+}
+
+/* Expects wl->mutex locked */
+static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
+{
+        struct b43_wldev *up_dev;
+        struct b43_wldev *down_dev;
+        int err;
+        bool gmode = 0;
+        int prev_status;
+
+        err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
+        if (err) {
+                b43err(wl, "Could not find a device for %s-PHY mode\n",
+                       phymode_to_string(new_mode));
+                return err;
+        }
+        if ((up_dev == wl->current_dev) &&
+            (!!wl->current_dev->phy.gmode == !!gmode)) {
+                /* This device is already running. */
+                return 0;
+        }
+        b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
+               phymode_to_string(new_mode));
+        down_dev = wl->current_dev;
+
+        prev_status = b43_status(down_dev);
+        /* Shutdown the currently running core. */
+        if (prev_status >= B43_STAT_STARTED)
+                b43_wireless_core_stop(down_dev);
+        if (prev_status >= B43_STAT_INITIALIZED)
+                b43_wireless_core_exit(down_dev);
+
+        if (down_dev != up_dev) {
+                /* We switch to a different core, so we put PHY into
+                 * RESET on the old core. */
+                b43_put_phy_into_reset(down_dev);
+        }
+
+        /* Now start the new core. */
+        up_dev->phy.gmode = gmode;
+        if (prev_status >= B43_STAT_INITIALIZED) {
+                err = b43_wireless_core_init(up_dev);
+                if (err) {
+                        b43err(wl, "Fatal: Could not initialize device for "
+                               "newly selected %s-PHY mode\n",
+                               phymode_to_string(new_mode));
+                        goto init_failure;
+                }
+        }
+        if (prev_status >= B43_STAT_STARTED) {
+                err = b43_wireless_core_start(up_dev);
+                if (err) {
+                        b43err(wl, "Fatal: Coult not start device for "
+                               "newly selected %s-PHY mode\n",
+                               phymode_to_string(new_mode));
+                        b43_wireless_core_exit(up_dev);
+                        goto init_failure;
+                }
+        }
+        B43_WARN_ON(b43_status(up_dev) != prev_status);
+
+        wl->current_dev = up_dev;
+
+        return 0;
+      init_failure:
+        /* Whoops, failed to init the new core. No core is operating now. */
+        wl->current_dev = NULL;
+        return err;
+}
+
+static int b43_antenna_from_ieee80211(u8 antenna)
+{
+        switch (antenna) {
+        case 0:         /* default/diversity */
+                return B43_ANTENNA_DEFAULT;
+        case 1:         /* Antenna 0 */
+                return B43_ANTENNA0;
+        case 2:         /* Antenna 1 */
+                return B43_ANTENNA1;
+        default:
+                return B43_ANTENNA_DEFAULT;
+        }
+}
+
+static int b43_dev_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev;
+        struct b43_phy *phy;
+        unsigned long flags;
+        unsigned int new_phymode = 0xFFFF;
+        int antenna_tx;
+        int antenna_rx;
+        int err = 0;
+        u32 savedirqs;
+
+        antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
+        antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
+
+        mutex_lock(&wl->mutex);
+
+        /* Switch the PHY mode (if necessary). */
+        switch (conf->phymode) {
+        case MODE_IEEE80211A:
+                new_phymode = B43_PHYMODE_A;
+                break;
+        case MODE_IEEE80211B:
+                new_phymode = B43_PHYMODE_B;
+                break;
+        case MODE_IEEE80211G:
+                new_phymode = B43_PHYMODE_G;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        err = b43_switch_phymode(wl, new_phymode);
+        if (err)
+                goto out_unlock_mutex;
+        dev = wl->current_dev;
+        phy = &dev->phy;
+
+        /* Disable IRQs while reconfiguring the device.
+         * This makes it possible to drop the spinlock throughout
+         * the reconfiguration process. */
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        if (b43_status(dev) < B43_STAT_STARTED) {
+                spin_unlock_irqrestore(&wl->irq_lock, flags);
+                goto out_unlock_mutex;
+        }
+        savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+        b43_synchronize_irq(dev);
+
+        /* Switch to the requested channel.
+         * The firmware takes care of races with the TX handler. */
+        if (conf->channel_val != phy->channel)
+                b43_radio_selectchannel(dev, conf->channel_val, 0);
+
+        /* Enable/Disable ShortSlot timing. */
+        if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
+            dev->short_slot) {
+                B43_WARN_ON(phy->type != B43_PHYTYPE_G);
+                if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
+                        b43_short_slot_timing_enable(dev);
+                else
+                        b43_short_slot_timing_disable(dev);
+        }
+
+        /* Adjust the desired TX power level. */
+        if (conf->power_level != 0) {
+                if (conf->power_level != phy->power_level) {
+                        phy->power_level = conf->power_level;
+                        b43_phy_xmitpower(dev);
+                }
+        }
+
+        /* Antennas for RX and management frame TX. */
+        b43_mgmtframe_txantenna(dev, antenna_tx);
+        b43_set_rx_antenna(dev, antenna_rx);
+
+        /* Update templates for AP mode. */
+        if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
+                b43_set_beacon_int(dev, conf->beacon_int);
+
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        b43_interrupt_enable(dev, savedirqs);
+        mmiowb();
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+      out_unlock_mutex:
+        mutex_unlock(&wl->mutex);
+
+        return err;
+}
+
+static int b43_dev_set_key(struct ieee80211_hw *hw,
+                           set_key_cmd cmd, const u8 *local_addr,
+                           const u8 *addr, struct ieee80211_key_conf *key)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev = wl->current_dev;
+        unsigned long flags;
+        u8 algorithm;
+        u8 index;
+        int err = -EINVAL;
+
+        if (modparam_nohwcrypt)
+                return -ENOSPC; /* User disabled HW-crypto */
+
+        if (!dev)
+                return -ENODEV;
+        switch (key->alg) {
+        case ALG_NONE:
+                algorithm = B43_SEC_ALGO_NONE;
+                break;
+        case ALG_WEP:
+                if (key->keylen == 5)
+                        algorithm = B43_SEC_ALGO_WEP40;
+                else
+                        algorithm = B43_SEC_ALGO_WEP104;
+                break;
+        case ALG_TKIP:
+                algorithm = B43_SEC_ALGO_TKIP;
+                break;
+        case ALG_CCMP:
+                algorithm = B43_SEC_ALGO_AES;
+                break;
+        default:
+                B43_WARN_ON(1);
+                goto out;
+        }
+
+        index = (u8) (key->keyidx);
+        if (index > 3)
+                goto out;
+
+        mutex_lock(&wl->mutex);
+        spin_lock_irqsave(&wl->irq_lock, flags);
+
+        if (b43_status(dev) < B43_STAT_INITIALIZED) {
+                err = -ENODEV;
+                goto out_unlock;
+        }
+
+        switch (cmd) {
+        case SET_KEY:
+                if (algorithm == B43_SEC_ALGO_TKIP) {
+                        /* FIXME: No TKIP hardware encryption for now. */
+                        err = -EOPNOTSUPP;
+                        goto out_unlock;
+                }
+
+                if (is_broadcast_ether_addr(addr)) {
+                        /* addr is FF:FF:FF:FF:FF:FF for default keys */
+                        err = b43_key_write(dev, index, algorithm,
+                                            key->key, key->keylen, NULL, key);
+                } else {
+                        /*
+                         * either pairwise key or address is 00:00:00:00:00:00
+                         * for transmit-only keys
+                         */
+                        err = b43_key_write(dev, -1, algorithm,
+                                            key->key, key->keylen, addr, key);
+                }
+                if (err)
+                        goto out_unlock;
+
+                if (algorithm == B43_SEC_ALGO_WEP40 ||
+                    algorithm == B43_SEC_ALGO_WEP104) {
+                        b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
+                } else {
+                        b43_hf_write(dev,
+                                     b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
+                }
+                key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
+                break;
+        case DISABLE_KEY: {
+                err = b43_key_clear(dev, key->hw_key_idx);
+                if (err)
+                        goto out_unlock;
+                break;
+        }
+        default:
+                B43_WARN_ON(1);
+        }
+out_unlock:
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+        mutex_unlock(&wl->mutex);
+out:
+        if (!err) {
+                b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
+                       "mac: " MAC_FMT "\n",
+                       cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
+                       MAC_ARG(addr));
+        }
+        return err;
+}
+
+static void b43_set_multicast_list(struct ieee80211_hw *hw,
+                                   unsigned short netflags, int mc_count)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev = wl->current_dev;
+        unsigned long flags;
+
+        if (!dev)
+                return;
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        if (wl->promisc != !!(netflags & IFF_PROMISC)) {
+                wl->promisc = !!(netflags & IFF_PROMISC);
+                if (b43_status(dev) >= B43_STAT_INITIALIZED)
+                        b43_adjust_opmode(dev);
+        }
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+}
+
+static int b43_config_interface(struct ieee80211_hw *hw,
+                                int if_id, struct ieee80211_if_conf *conf)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev = wl->current_dev;
+        unsigned long flags;
+
+        if (!dev)
+                return -ENODEV;
+        mutex_lock(&wl->mutex);
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        if (conf->type != IEEE80211_IF_TYPE_MNTR) {
+                B43_WARN_ON(wl->if_id != if_id);
+                if (conf->bssid)
+                        memcpy(wl->bssid, conf->bssid, ETH_ALEN);
+                else
+                        memset(wl->bssid, 0, ETH_ALEN);
+                if (b43_status(dev) >= B43_STAT_INITIALIZED) {
+                        if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
+                                B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
+                                b43_set_ssid(dev, conf->ssid, conf->ssid_len);
+                                if (conf->beacon)
+                                        b43_refresh_templates(dev, conf->beacon);
+                        }
+                        b43_write_mac_bssid_templates(dev);
+                }
+        }
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+        mutex_unlock(&wl->mutex);
+
+        return 0;
+}
+
+/* Locking: wl->mutex */
+static void b43_wireless_core_stop(struct b43_wldev *dev)
+{
+        struct b43_wl *wl = dev->wl;
+        unsigned long flags;
+
+        if (b43_status(dev) < B43_STAT_STARTED)
+                return;
+        b43_set_status(dev, B43_STAT_INITIALIZED);
+
+        mutex_unlock(&wl->mutex);
+        /* Must unlock as it would otherwise deadlock. No races here.
+         * Cancel the possibly running self-rearming periodic work. */
+        cancel_delayed_work_sync(&dev->periodic_work);
+        mutex_lock(&wl->mutex);
+
+        ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
+
+        /* Disable and sync interrupts. */
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
+        b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+        b43_synchronize_irq(dev);
+
+        b43_mac_suspend(dev);
+        free_irq(dev->dev->irq, dev);
+        b43dbg(wl, "Wireless interface stopped\n");
+}
+
+/* Locking: wl->mutex */
+static int b43_wireless_core_start(struct b43_wldev *dev)
+{
+        int err;
+
+        B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
+
+        drain_txstatus_queue(dev);
+        err = request_irq(dev->dev->irq, b43_interrupt_handler,
+                          IRQF_SHARED, KBUILD_MODNAME, dev);
+        if (err) {
+                b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
+                goto out;
+        }
+
+        /* We are ready to run. */
+        b43_set_status(dev, B43_STAT_STARTED);
+
+        /* Start data flow (TX/RX). */
+        b43_mac_enable(dev);
+        b43_interrupt_enable(dev, dev->irq_savedstate);
+        ieee80211_start_queues(dev->wl->hw);
+
+        /* Start maintainance work */
+        b43_periodic_tasks_setup(dev);
+
+        b43dbg(dev->wl, "Wireless interface started\n");
+      out:
+        return err;
+}
+
+/* Get PHY and RADIO versioning numbers */
+static int b43_phy_versioning(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u32 tmp;
+        u8 analog_type;
+        u8 phy_type;
+        u8 phy_rev;
+        u16 radio_manuf;
+        u16 radio_ver;
+        u16 radio_rev;
+        int unsupported = 0;
+
+        /* Get PHY versioning */
+        tmp = b43_read16(dev, B43_MMIO_PHY_VER);
+        analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
+        phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
+        phy_rev = (tmp & B43_PHYVER_VERSION);
+        switch (phy_type) {
+        case B43_PHYTYPE_A:
+                if (phy_rev >= 4)
+                        unsupported = 1;
+                break;
+        case B43_PHYTYPE_B:
+                if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
+                    && phy_rev != 7)
+                        unsupported = 1;
+                break;
+        case B43_PHYTYPE_G:
+                if (phy_rev > 8)
+                        unsupported = 1;
+                break;
+        default:
+                unsupported = 1;
+        };
+        if (unsupported) {
+                b43err(dev->wl, "FOUND UNSUPPORTED PHY "
+                       "(Analog %u, Type %u, Revision %u)\n",
+                       analog_type, phy_type, phy_rev);
+                return -EOPNOTSUPP;
+        }
+        b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
+               analog_type, phy_type, phy_rev);
+
+        /* Get RADIO versioning */
+        if (dev->dev->bus->chip_id == 0x4317) {
+                if (dev->dev->bus->chip_rev == 0)
+                        tmp = 0x3205017F;
+                else if (dev->dev->bus->chip_rev == 1)
+                        tmp = 0x4205017F;
+                else
+                        tmp = 0x5205017F;
+        } else {
+                b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
+                tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
+                tmp <<= 16;
+                b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
+                tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
+        }
+        radio_manuf = (tmp & 0x00000FFF);
+        radio_ver = (tmp & 0x0FFFF000) >> 12;
+        radio_rev = (tmp & 0xF0000000) >> 28;
+        switch (phy_type) {
+        case B43_PHYTYPE_A:
+                if (radio_ver != 0x2060)
+                        unsupported = 1;
+                if (radio_rev != 1)
+                        unsupported = 1;
+                if (radio_manuf != 0x17F)
+                        unsupported = 1;
+                break;
+        case B43_PHYTYPE_B:
+                if ((radio_ver & 0xFFF0) != 0x2050)
+                        unsupported = 1;
+                break;
+        case B43_PHYTYPE_G:
+                if (radio_ver != 0x2050)
+                        unsupported = 1;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        if (unsupported) {
+                b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
+                       "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
+                       radio_manuf, radio_ver, radio_rev);
+                return -EOPNOTSUPP;
+        }
+        b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
+               radio_manuf, radio_ver, radio_rev);
+
+        phy->radio_manuf = radio_manuf;
+        phy->radio_ver = radio_ver;
+        phy->radio_rev = radio_rev;
+
+        phy->analog = analog_type;
+        phy->type = phy_type;
+        phy->rev = phy_rev;
+
+        return 0;
+}
+
+static void setup_struct_phy_for_init(struct b43_wldev *dev,
+                                      struct b43_phy *phy)
+{
+        struct b43_txpower_lo_control *lo;
+        int i;
+
+        memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
+        memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
+
+        /* Flags */
+        phy->locked = 0;
+
+        phy->aci_enable = 0;
+        phy->aci_wlan_automatic = 0;
+        phy->aci_hw_rssi = 0;
+
+        lo = phy->lo_control;
+        if (lo) {
+                memset(lo, 0, sizeof(*(phy->lo_control)));
+                lo->rebuild = 1;
+                lo->tx_bias = 0xFF;
+        }
+        phy->max_lb_gain = 0;
+        phy->trsw_rx_gain = 0;
+        phy->txpwr_offset = 0;
+
+        /* NRSSI */
+        phy->nrssislope = 0;
+        for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
+                phy->nrssi[i] = -1000;
+        for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
+                phy->nrssi_lt[i] = i;
+
+        phy->lofcal = 0xFFFF;
+        phy->initval = 0xFFFF;
+
+        spin_lock_init(&phy->lock);
+        phy->interfmode = B43_INTERFMODE_NONE;
+        phy->channel = 0xFF;
+
+        phy->hardware_power_control = !!modparam_hwpctl;
+}
+
+static void setup_struct_wldev_for_init(struct b43_wldev *dev)
+{
+        /* Flags */
+        dev->reg124_set_0x4 = 0;
+
+        /* Stats */
+        memset(&dev->stats, 0, sizeof(dev->stats));
+
+        setup_struct_phy_for_init(dev, &dev->phy);
+
+        /* IRQ related flags */
+        dev->irq_reason = 0;
+        memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
+        dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
+
+        dev->mac_suspended = 1;
+
+        /* Noise calculation context */
+        memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
+}
+
+static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
+{
+        struct ssb_sprom *sprom = &dev->dev->bus->sprom;
+        u32 hf;
+
+        if (!(sprom->r1.boardflags_lo & B43_BFL_BTCOEXIST))
+                return;
+        if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
+                return;
+
+        hf = b43_hf_read(dev);
+        if (sprom->r1.boardflags_lo & B43_BFL_BTCMOD)
+                hf |= B43_HF_BTCOEXALT;
+        else
+                hf |= B43_HF_BTCOEX;
+        b43_hf_write(dev, hf);
+        //TODO
+}
+
+static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
+{                               //TODO
+}
+
+static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
+{
+#ifdef CONFIG_SSB_DRIVER_PCICORE
+        struct ssb_bus *bus = dev->dev->bus;
+        u32 tmp;
+
+        if (bus->pcicore.dev &&
+            bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
+            bus->pcicore.dev->id.revision <= 5) {
+                /* IMCFGLO timeouts workaround. */
+                tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
+                tmp &= ~SSB_IMCFGLO_REQTO;
+                tmp &= ~SSB_IMCFGLO_SERTO;
+                switch (bus->bustype) {
+                case SSB_BUSTYPE_PCI:
+                case SSB_BUSTYPE_PCMCIA:
+                        tmp |= 0x32;
+                        break;
+                case SSB_BUSTYPE_SSB:
+                        tmp |= 0x53;
+                        break;
+                }
+                ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
+        }
+#endif /* CONFIG_SSB_DRIVER_PCICORE */
+}
+
+/* Shutdown a wireless core */
+/* Locking: wl->mutex */
+static void b43_wireless_core_exit(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
+        if (b43_status(dev) != B43_STAT_INITIALIZED)
+                return;
+        b43_set_status(dev, B43_STAT_UNINIT);
+
+        b43_rng_exit(dev->wl);
+        b43_pio_free(dev);
+        b43_dma_free(dev);
+        b43_chip_exit(dev);
+        b43_radio_turn_off(dev);
+        b43_switch_analog(dev, 0);
+        if (phy->dyn_tssi_tbl)
+                kfree(phy->tssi2dbm);
+        kfree(phy->lo_control);
+        phy->lo_control = NULL;
+        ssb_device_disable(dev->dev, 0);
+        ssb_bus_may_powerdown(dev->dev->bus);
+}
+
+/* Initialize a wireless core */
+static int b43_wireless_core_init(struct b43_wldev *dev)
+{
+        struct b43_wl *wl = dev->wl;
+        struct ssb_bus *bus = dev->dev->bus;
+        struct ssb_sprom *sprom = &bus->sprom;
+        struct b43_phy *phy = &dev->phy;
+        int err;
+        u32 hf, tmp;
+
+        B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
+
+        err = ssb_bus_powerup(bus, 0);
+        if (err)
+                goto out;
+        if (!ssb_device_is_enabled(dev->dev)) {
+                tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
+                b43_wireless_core_reset(dev, tmp);
+        }
+
+        if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
+                phy->lo_control =
+                    kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
+                if (!phy->lo_control) {
+                        err = -ENOMEM;
+                        goto err_busdown;
+                }
+        }
+        setup_struct_wldev_for_init(dev);
+
+        err = b43_phy_init_tssi2dbm_table(dev);
+        if (err)
+                goto err_kfree_lo_control;
+
+        /* Enable IRQ routing to this device. */
+        ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
+
+        b43_imcfglo_timeouts_workaround(dev);
+        b43_bluetooth_coext_disable(dev);
+        b43_phy_early_init(dev);
+        err = b43_chip_init(dev);
+        if (err)
+                goto err_kfree_tssitbl;
+        b43_shm_write16(dev, B43_SHM_SHARED,
+                        B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
+        hf = b43_hf_read(dev);
+        if (phy->type == B43_PHYTYPE_G) {
+                hf |= B43_HF_SYMW;
+                if (phy->rev == 1)
+                        hf |= B43_HF_GDCW;
+                if (sprom->r1.boardflags_lo & B43_BFL_PACTRL)
+                        hf |= B43_HF_OFDMPABOOST;
+        } else if (phy->type == B43_PHYTYPE_B) {
+                hf |= B43_HF_SYMW;
+                if (phy->rev >= 2 && phy->radio_ver == 0x2050)
+                        hf &= ~B43_HF_GDCW;
+        }
+        b43_hf_write(dev, hf);
+
+        /* Short/Long Retry Limit.
+         * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
+         * the chip-internal counter.
+         */
+        tmp = limit_value(modparam_short_retry, 0, 0xF);
+        b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, tmp);
+        tmp = limit_value(modparam_long_retry, 0, 0xF);
+        b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, tmp);
+
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
+
+        /* Disable sending probe responses from firmware.
+         * Setting the MaxTime to one usec will always trigger
+         * a timeout, so we never send any probe resp.
+         * A timeout of zero is infinite. */
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
+
+        b43_rate_memory_init(dev);
+
+        /* Minimum Contention Window */
+        if (phy->type == B43_PHYTYPE_B) {
+                b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
+        } else {
+                b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
+        }
+        /* Maximum Contention Window */
+        b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
+
+        do {
+                if (b43_using_pio(dev)) {
+                        err = b43_pio_init(dev);
+                } else {
+                        err = b43_dma_init(dev);
+                        if (!err)
+                                b43_qos_init(dev);
+                }
+        } while (err == -EAGAIN);
+        if (err)
+                goto err_chip_exit;
+
+//FIXME
+#if 1
+        b43_write16(dev, 0x0612, 0x0050);
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
+        b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
+#endif
+
+        b43_bluetooth_coext_enable(dev);
+
+        ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
+        memset(wl->bssid, 0, ETH_ALEN);
+        b43_upload_card_macaddress(dev, NULL);
+        b43_security_init(dev);
+        b43_rng_init(wl);
+
+        b43_set_status(dev, B43_STAT_INITIALIZED);
+
+      out:
+        return err;
+
+      err_chip_exit:
+        b43_chip_exit(dev);
+      err_kfree_tssitbl:
+        if (phy->dyn_tssi_tbl)
+                kfree(phy->tssi2dbm);
+      err_kfree_lo_control:
+        kfree(phy->lo_control);
+        phy->lo_control = NULL;
+      err_busdown:
+        ssb_bus_may_powerdown(bus);
+        B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
+        return err;
+}
+
+static int b43_add_interface(struct ieee80211_hw *hw,
+                             struct ieee80211_if_init_conf *conf)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev;
+        unsigned long flags;
+        int err = -EOPNOTSUPP;
+        int did_init = 0;
+
+        mutex_lock(&wl->mutex);
+        if ((conf->type != IEEE80211_IF_TYPE_MNTR) && wl->operating)
+                goto out_mutex_unlock;
+
+        b43dbg(wl, "Adding Interface type %d\n", conf->type);
+
+        dev = wl->current_dev;
+        if (b43_status(dev) < B43_STAT_INITIALIZED) {
+                err = b43_wireless_core_init(dev);
+                if (err)
+                        goto out_mutex_unlock;
+                did_init = 1;
+        }
+        if (b43_status(dev) < B43_STAT_STARTED) {
+                err = b43_wireless_core_start(dev);
+                if (err) {
+                        if (did_init)
+                                b43_wireless_core_exit(dev);
+                        goto out_mutex_unlock;
+                }
+        }
+
+        spin_lock_irqsave(&wl->irq_lock, flags);
+        switch (conf->type) {
+        case IEEE80211_IF_TYPE_MNTR:
+                wl->monitor++;
+                break;
+        default:
+                wl->operating = 1;
+                wl->if_id = conf->if_id;
+                wl->if_type = conf->type;
+                b43_upload_card_macaddress(dev, conf->mac_addr);
+        }
+        b43_adjust_opmode(dev);
+        spin_unlock_irqrestore(&wl->irq_lock, flags);
+
+        err = 0;
+      out_mutex_unlock:
+        mutex_unlock(&wl->mutex);
+
+        return err;
+}
+
+static void b43_remove_interface(struct ieee80211_hw *hw,
+                                 struct ieee80211_if_init_conf *conf)
+{
+        struct b43_wl *wl = hw_to_b43_wl(hw);
+        struct b43_wldev *dev;
+        unsigned long flags;
+
+        b43dbg(wl, "Removing Interface type %d\n", conf->type);
+
+        mutex_lock(&wl->mutex);
+        if (conf->type == IEEE80211_IF_TYPE_MNTR) {
+                wl->monitor--;
+                B43_WARN_ON(wl->monitor < 0);
+        } else {
+                B43_WARN_ON(!wl->operating);
+                wl->operating = 0;
+        }
+
+        dev = wl->current_dev;
+        if (!wl->operating && wl->monitor == 0) {
+                /* No interface left. */
+                if (b43_status(dev) >= B43_STAT_STARTED)
+                        b43_wireless_core_stop(dev);
+                b43_wireless_core_exit(dev);
+        } else {
+                /* Just monitor interfaces left. */
+                spin_lock_irqsave(&wl->irq_lock, flags);
+                b43_adjust_opmode(dev);
+                if (!wl->operating)
+                        b43_upload_card_macaddress(dev, NULL);
+                spin_unlock_irqrestore(&wl->irq_lock, flags);
+        }
+        mutex_unlock(&wl->mutex);
+}
+
+static const struct ieee80211_ops b43_hw_ops = {
+        .tx = b43_tx,
+        .conf_tx = b43_conf_tx,
+        .add_interface = b43_add_interface,
+        .remove_interface = b43_remove_interface,
+        .config = b43_dev_config,
+        .config_interface = b43_config_interface,
+        .set_multicast_list = b43_set_multicast_list,
+        .set_key = b43_dev_set_key,
+        .get_stats = b43_get_stats,
+        .get_tx_stats = b43_get_tx_stats,
+};
+
+/* Hard-reset the chip. Do not call this directly.
+ * Use b43_controller_restart()
+ */
+static void b43_chip_reset(struct work_struct *work)
+{
+        struct b43_wldev *dev =
+            container_of(work, struct b43_wldev, restart_work);
+        struct b43_wl *wl = dev->wl;
+        int err = 0;
+        int prev_status;
+
+        mutex_lock(&wl->mutex);
+
+        prev_status = b43_status(dev);
+        /* Bring the device down... */
+        if (prev_status >= B43_STAT_STARTED)
+                b43_wireless_core_stop(dev);
+        if (prev_status >= B43_STAT_INITIALIZED)
+                b43_wireless_core_exit(dev);
+
+        /* ...and up again. */
+        if (prev_status >= B43_STAT_INITIALIZED) {
+                err = b43_wireless_core_init(dev);
+                if (err)
+                        goto out;
+        }
+        if (prev_status >= B43_STAT_STARTED) {
+                err = b43_wireless_core_start(dev);
+                if (err) {
+                        b43_wireless_core_exit(dev);
+                        goto out;
+                }
+        }
+      out:
+        mutex_unlock(&wl->mutex);
+        if (err)
+                b43err(wl, "Controller restart FAILED\n");
+        else
+                b43info(wl, "Controller restarted\n");
+}
+
+static int b43_setup_modes(struct b43_wldev *dev,
+                           int have_aphy, int have_bphy, int have_gphy)
+{
+        struct ieee80211_hw *hw = dev->wl->hw;
+        struct ieee80211_hw_mode *mode;
+        struct b43_phy *phy = &dev->phy;
+        int cnt = 0;
+        int err;
+
+/*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
+        have_aphy = 0;
+
+        phy->possible_phymodes = 0;
+        for (; 1; cnt++) {
+                if (have_aphy) {
+                        B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
+                        mode = &phy->hwmodes[cnt];
+
+                        mode->mode = MODE_IEEE80211A;
+                        mode->num_channels = b43_a_chantable_size;
+                        mode->channels = b43_a_chantable;
+                        mode->num_rates = b43_a_ratetable_size;
+                        mode->rates = b43_a_ratetable;
+                        err = ieee80211_register_hwmode(hw, mode);
+                        if (err)
+                                return err;
+
+                        phy->possible_phymodes |= B43_PHYMODE_A;
+                        have_aphy = 0;
+                        continue;
+                }
+                if (have_bphy) {
+                        B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
+                        mode = &phy->hwmodes[cnt];
+
+                        mode->mode = MODE_IEEE80211B;
+                        mode->num_channels = b43_bg_chantable_size;
+                        mode->channels = b43_bg_chantable;
+                        mode->num_rates = b43_b_ratetable_size;
+                        mode->rates = b43_b_ratetable;
+                        err = ieee80211_register_hwmode(hw, mode);
+                        if (err)
+                                return err;
+
+                        phy->possible_phymodes |= B43_PHYMODE_B;
+                        have_bphy = 0;
+                        continue;
+                }
+                if (have_gphy) {
+                        B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
+                        mode = &phy->hwmodes[cnt];
+
+                        mode->mode = MODE_IEEE80211G;
+                        mode->num_channels = b43_bg_chantable_size;
+                        mode->channels = b43_bg_chantable;
+                        mode->num_rates = b43_g_ratetable_size;
+                        mode->rates = b43_g_ratetable;
+                        err = ieee80211_register_hwmode(hw, mode);
+                        if (err)
+                                return err;
+
+                        phy->possible_phymodes |= B43_PHYMODE_G;
+                        have_gphy = 0;
+                        continue;
+                }
+                break;
+        }
+
+        return 0;
+}
+
+static void b43_wireless_core_detach(struct b43_wldev *dev)
+{
+        /* We release firmware that late to not be required to re-request
+         * is all the time when we reinit the core. */
+        b43_release_firmware(dev);
+}
+
+static int b43_wireless_core_attach(struct b43_wldev *dev)
+{
+        struct b43_wl *wl = dev->wl;
+        struct ssb_bus *bus = dev->dev->bus;
+        struct pci_dev *pdev = bus->host_pci;
+        int err;
+        int have_aphy = 0, have_bphy = 0, have_gphy = 0;
+        u32 tmp;
+
+        /* Do NOT do any device initialization here.
+         * Do it in wireless_core_init() instead.
+         * This function is for gathering basic information about the HW, only.
+         * Also some structs may be set up here. But most likely you want to have
+         * that in core_init(), too.
+         */
+
+        err = ssb_bus_powerup(bus, 0);
+        if (err) {
+                b43err(wl, "Bus powerup failed\n");
+                goto out;
+        }
+        /* Get the PHY type. */
+        if (dev->dev->id.revision >= 5) {
+                u32 tmshigh;
+
+                tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
+                have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
+                have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
+                if (!have_aphy && !have_gphy)
+                        have_bphy = 1;
+        } else if (dev->dev->id.revision == 4) {
+                have_gphy = 1;
+                have_aphy = 1;
+        } else
+                have_bphy = 1;
+
+        /* Initialize LEDs structs. */
+        err = b43_leds_init(dev);
+        if (err)
+                goto err_powerdown;
+
+        dev->phy.gmode = (have_gphy || have_bphy);
+        tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
+        b43_wireless_core_reset(dev, tmp);
+
+        err = b43_phy_versioning(dev);
+        if (err)
+                goto err_leds_exit;
+        /* Check if this device supports multiband. */
+        if (!pdev ||
+            (pdev->device != 0x4312 &&
+             pdev->device != 0x4319 && pdev->device != 0x4324)) {
+                /* No multiband support. */
+                have_aphy = 0;
+                have_bphy = 0;
+                have_gphy = 0;
+                switch (dev->phy.type) {
+                case B43_PHYTYPE_A:
+                        have_aphy = 1;
+                        break;
+                case B43_PHYTYPE_B:
+                        have_bphy = 1;
+                        break;
+                case B43_PHYTYPE_G:
+                        have_gphy = 1;
+                        break;
+                default:
+                        B43_WARN_ON(1);
+                }
+        }
+        dev->phy.gmode = (have_gphy || have_bphy);
+        tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
+        b43_wireless_core_reset(dev, tmp);
+
+        err = b43_validate_chipaccess(dev);
+        if (err)
+                goto err_leds_exit;
+        err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
+        if (err)
+                goto err_leds_exit;
+
+        /* Now set some default "current_dev" */
+        if (!wl->current_dev)
+                wl->current_dev = dev;
+        INIT_WORK(&dev->restart_work, b43_chip_reset);
+
+        b43_radio_turn_off(dev);
+        b43_switch_analog(dev, 0);
+        ssb_device_disable(dev->dev, 0);
+        ssb_bus_may_powerdown(bus);
+
+out:
+        return err;
+
+err_leds_exit:
+        b43_leds_exit(dev);
+err_powerdown:
+        ssb_bus_may_powerdown(bus);
+        return err;
+}
+
+static void b43_one_core_detach(struct ssb_device *dev)
+{
+        struct b43_wldev *wldev;
+        struct b43_wl *wl;
+
+        wldev = ssb_get_drvdata(dev);
+        wl = wldev->wl;
+        cancel_work_sync(&wldev->restart_work);
+        b43_debugfs_remove_device(wldev);
+        b43_wireless_core_detach(wldev);
+        list_del(&wldev->list);
+        wl->nr_devs--;
+        ssb_set_drvdata(dev, NULL);
+        kfree(wldev);
+}
+
+static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
+{
+        struct b43_wldev *wldev;
+        struct pci_dev *pdev;
+        int err = -ENOMEM;
+
+        if (!list_empty(&wl->devlist)) {
+                /* We are not the first core on this chip. */
+                pdev = dev->bus->host_pci;
+                /* Only special chips support more than one wireless
+                 * core, although some of the other chips have more than
+                 * one wireless core as well. Check for this and
+                 * bail out early.
+                 */
+                if (!pdev ||
+                    ((pdev->device != 0x4321) &&
+                     (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
+                        b43dbg(wl, "Ignoring unconnected 802.11 core\n");
+                        return -ENODEV;
+                }
+        }
+
+        wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
+        if (!wldev)
+                goto out;
+
+        wldev->dev = dev;
+        wldev->wl = wl;
+        b43_set_status(wldev, B43_STAT_UNINIT);
+        wldev->bad_frames_preempt = modparam_bad_frames_preempt;
+        tasklet_init(&wldev->isr_tasklet,
+                     (void (*)(unsigned long))b43_interrupt_tasklet,
+                     (unsigned long)wldev);
+        if (modparam_pio)
+                wldev->__using_pio = 1;
+        INIT_LIST_HEAD(&wldev->list);
+
+        err = b43_wireless_core_attach(wldev);
+        if (err)
+                goto err_kfree_wldev;
+
+        list_add(&wldev->list, &wl->devlist);
+        wl->nr_devs++;
+        ssb_set_drvdata(dev, wldev);
+        b43_debugfs_add_device(wldev);
+
+      out:
+        return err;
+
+      err_kfree_wldev:
+        kfree(wldev);
+        return err;
+}
+
+static void b43_sprom_fixup(struct ssb_bus *bus)
+{
+        /* boardflags workarounds */
+        if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
+            bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
+                bus->sprom.r1.boardflags_lo |= B43_BFL_BTCOEXIST;
+        if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
+            bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
+                bus->sprom.r1.boardflags_lo |= B43_BFL_PACTRL;
+
+        /* Handle case when gain is not set in sprom */
+        if (bus->sprom.r1.antenna_gain_a == 0xFF)
+                bus->sprom.r1.antenna_gain_a = 2;
+        if (bus->sprom.r1.antenna_gain_bg == 0xFF)
+                bus->sprom.r1.antenna_gain_bg = 2;
+
+        /* Convert Antennagain values to Q5.2 */
+        bus->sprom.r1.antenna_gain_a <<= 2;
+        bus->sprom.r1.antenna_gain_bg <<= 2;
+}
+
+static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
+{
+        struct ieee80211_hw *hw = wl->hw;
+
+        ssb_set_devtypedata(dev, NULL);
+        ieee80211_free_hw(hw);
+}
+
+static int b43_wireless_init(struct ssb_device *dev)
+{
+        struct ssb_sprom *sprom = &dev->bus->sprom;
+        struct ieee80211_hw *hw;
+        struct b43_wl *wl;
+        int err = -ENOMEM;
+
+        b43_sprom_fixup(dev->bus);
+
+        hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
+        if (!hw) {
+                b43err(NULL, "Could not allocate ieee80211 device\n");
+                goto out;
+        }
+
+        /* fill hw info */
+        hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
+            IEEE80211_HW_MONITOR_DURING_OPER;
+        hw->max_signal = 100;
+        hw->max_rssi = -110;
+        hw->max_noise = -110;
+        hw->queues = 1;         /* FIXME: hardware has more queues */
+        SET_IEEE80211_DEV(hw, dev->dev);
+        if (is_valid_ether_addr(sprom->r1.et1mac))
+                SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
+        else
+                SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
+
+        /* Get and initialize struct b43_wl */
+        wl = hw_to_b43_wl(hw);
+        memset(wl, 0, sizeof(*wl));
+        wl->hw = hw;
+        spin_lock_init(&wl->irq_lock);
+        spin_lock_init(&wl->leds_lock);
+        mutex_init(&wl->mutex);
+        INIT_LIST_HEAD(&wl->devlist);
+
+        ssb_set_devtypedata(dev, wl);
+        b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
+        err = 0;
+      out:
+        return err;
+}
+
+static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
+{
+        struct b43_wl *wl;
+        int err;
+        int first = 0;
+
+        wl = ssb_get_devtypedata(dev);
+        if (!wl) {
+                /* Probing the first core. Must setup common struct b43_wl */
+                first = 1;
+                err = b43_wireless_init(dev);
+                if (err)
+                        goto out;
+                wl = ssb_get_devtypedata(dev);
+                B43_WARN_ON(!wl);
+        }
+        err = b43_one_core_attach(dev, wl);
+        if (err)
+                goto err_wireless_exit;
+
+        if (first) {
+                err = ieee80211_register_hw(wl->hw);
+                if (err)
+                        goto err_one_core_detach;
+        }
+
+      out:
+        return err;
+
+      err_one_core_detach:
+        b43_one_core_detach(dev);
+      err_wireless_exit:
+        if (first)
+                b43_wireless_exit(dev, wl);
+        return err;
+}
+
+static void b43_remove(struct ssb_device *dev)
+{
+        struct b43_wl *wl = ssb_get_devtypedata(dev);
+        struct b43_wldev *wldev = ssb_get_drvdata(dev);
+
+        B43_WARN_ON(!wl);
+        if (wl->current_dev == wldev)
+                ieee80211_unregister_hw(wl->hw);
+
+        b43_one_core_detach(dev);
+
+        if (list_empty(&wl->devlist)) {
+                /* Last core on the chip unregistered.
+                 * We can destroy common struct b43_wl.
+                 */
+                b43_wireless_exit(dev, wl);
+        }
+}
+
+/* Perform a hardware reset. This can be called from any context. */
+void b43_controller_restart(struct b43_wldev *dev, const char *reason)
+{
+        /* Must avoid requeueing, if we are in shutdown. */
+        if (b43_status(dev) < B43_STAT_INITIALIZED)
+                return;
+        b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
+        queue_work(dev->wl->hw->workqueue, &dev->restart_work);
+}
+
+#ifdef CONFIG_PM
+
+static int b43_suspend(struct ssb_device *dev, pm_message_t state)
+{
+        struct b43_wldev *wldev = ssb_get_drvdata(dev);
+        struct b43_wl *wl = wldev->wl;
+
+        b43dbg(wl, "Suspending...\n");
+
+        mutex_lock(&wl->mutex);
+        wldev->suspend_init_status = b43_status(wldev);
+        if (wldev->suspend_init_status >= B43_STAT_STARTED)
+                b43_wireless_core_stop(wldev);
+        if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
+                b43_wireless_core_exit(wldev);
+        mutex_unlock(&wl->mutex);
+
+        b43dbg(wl, "Device suspended.\n");
+
+        return 0;
+}
+
+static int b43_resume(struct ssb_device *dev)
+{
+        struct b43_wldev *wldev = ssb_get_drvdata(dev);
+        struct b43_wl *wl = wldev->wl;
+        int err = 0;
+
+        b43dbg(wl, "Resuming...\n");
+
+        mutex_lock(&wl->mutex);
+        if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
+                err = b43_wireless_core_init(wldev);
+                if (err) {
+                        b43err(wl, "Resume failed at core init\n");
+                        goto out;
+                }
+        }
+        if (wldev->suspend_init_status >= B43_STAT_STARTED) {
+                err = b43_wireless_core_start(wldev);
+                if (err) {
+                        b43_wireless_core_exit(wldev);
+                        b43err(wl, "Resume failed at core start\n");
+                        goto out;
+                }
+        }
+        mutex_unlock(&wl->mutex);
+
+        b43dbg(wl, "Device resumed.\n");
+      out:
+        return err;
+}
+
+#else /* CONFIG_PM */
+# define b43_suspend    NULL
+# define b43_resume     NULL
+#endif /* CONFIG_PM */
+
+static struct ssb_driver b43_ssb_driver = {
+        .name           = KBUILD_MODNAME,
+        .id_table       = b43_ssb_tbl,
+        .probe          = b43_probe,
+        .remove         = b43_remove,
+        .suspend        = b43_suspend,
+        .resume         = b43_resume,
+};
+
+static int __init b43_init(void)
+{
+        int err;
+
+        b43_debugfs_init();
+        err = b43_pcmcia_init();
+        if (err)
+                goto err_dfs_exit;
+        err = ssb_driver_register(&b43_ssb_driver);
+        if (err)
+                goto err_pcmcia_exit;
+
+        return err;
+
+err_pcmcia_exit:
+        b43_pcmcia_exit();
+err_dfs_exit:
+        b43_debugfs_exit();
+        return err;
+}
+
+static void __exit b43_exit(void)
+{
+        ssb_driver_unregister(&b43_ssb_driver);
+        b43_pcmcia_exit();
+        b43_debugfs_exit();
+}
+
+module_init(b43_init)
+module_exit(b43_exit)
diff --git a/drivers/net/wireless/b43/main.h b/drivers/net/wireless/b43/main.h
new file mode 100644
index 000000000000..bd8fcf72dc5d
--- /dev/null
+++ b/drivers/net/wireless/b43/main.h
@@ -0,0 +1,142 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+                     Stefano Brivio <st3@riseup.net>
+                     Michael Buesch <mb@bu3sch.de>
+                     Danny van Dyk <kugelfang@gentoo.org>
+                     Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  Some parts of the code in this file are derived from the ipw2200
+  driver  Copyright(c) 2003 - 2004 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef B43_MAIN_H_
+#define B43_MAIN_H_
+
+#include "b43.h"
+
+#define P4D_BYT3S(magic, nr_bytes)      u8 __p4dding##magic[nr_bytes]
+#define P4D_BYTES(line, nr_bytes)       P4D_BYT3S(line, nr_bytes)
+/* Magic helper macro to pad structures. Ignore those above. It's magic. */
+#define PAD_BYTES(nr_bytes)             P4D_BYTES( __LINE__ , (nr_bytes))
+
+/* Lightweight function to convert a frequency (in Mhz) to a channel number. */
+static inline u8 b43_freq_to_channel_a(int freq)
+{
+        return ((freq - 5000) / 5);
+}
+static inline u8 b43_freq_to_channel_bg(int freq)
+{
+        u8 channel;
+
+        if (freq == 2484)
+                channel = 14;
+        else
+                channel = (freq - 2407) / 5;
+
+        return channel;
+}
+static inline u8 b43_freq_to_channel(struct b43_wldev *dev, int freq)
+{
+        if (dev->phy.type == B43_PHYTYPE_A)
+                return b43_freq_to_channel_a(freq);
+        return b43_freq_to_channel_bg(freq);
+}
+
+/* Lightweight function to convert a channel number to a frequency (in Mhz). */
+static inline int b43_channel_to_freq_a(u8 channel)
+{
+        return (5000 + (5 * channel));
+}
+static inline int b43_channel_to_freq_bg(u8 channel)
+{
+        int freq;
+
+        if (channel == 14)
+                freq = 2484;
+        else
+                freq = 2407 + (5 * channel);
+
+        return freq;
+}
+static inline int b43_channel_to_freq(struct b43_wldev *dev, u8 channel)
+{
+        if (dev->phy.type == B43_PHYTYPE_A)
+                return b43_channel_to_freq_a(channel);
+        return b43_channel_to_freq_bg(channel);
+}
+
+static inline int b43_is_cck_rate(int rate)
+{
+        return (rate == B43_CCK_RATE_1MB ||
+                rate == B43_CCK_RATE_2MB ||
+                rate == B43_CCK_RATE_5MB || rate == B43_CCK_RATE_11MB);
+}
+
+static inline int b43_is_ofdm_rate(int rate)
+{
+        return !b43_is_cck_rate(rate);
+}
+
+static inline int b43_is_hw_radio_enabled(struct b43_wldev *dev)
+{
+        /* function to return state of hardware enable of radio
+         * returns 0 if radio disabled, 1 if radio enabled
+         */
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->rev >= 3)
+                return ((b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI)
+                         & B43_MMIO_RADIO_HWENABLED_HI_MASK)
+                        == 0) ? 1 : 0;
+        else
+                return ((b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO)
+                         & B43_MMIO_RADIO_HWENABLED_LO_MASK)
+                        == 0) ? 0 : 1;
+}
+
+void b43_tsf_read(struct b43_wldev *dev, u64 * tsf);
+void b43_tsf_write(struct b43_wldev *dev, u64 tsf);
+
+u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset);
+u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset);
+void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value);
+void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value);
+
+u32 b43_hf_read(struct b43_wldev *dev);
+void b43_hf_write(struct b43_wldev *dev, u32 value);
+
+void b43_dummy_transmission(struct b43_wldev *dev);
+
+void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags);
+
+void b43_mac_suspend(struct b43_wldev *dev);
+void b43_mac_enable(struct b43_wldev *dev);
+
+void b43_controller_restart(struct b43_wldev *dev, const char *reason);
+
+#define B43_PS_ENABLED  (1 << 0)        /* Force enable hardware power saving */
+#define B43_PS_DISABLED (1 << 1)        /* Force disable hardware power saving */
+#define B43_PS_AWAKE    (1 << 2)        /* Force device awake */
+#define B43_PS_ASLEEP   (1 << 3)        /* Force device asleep */
+void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags);
+
+#endif /* B43_MAIN_H_ */
diff --git a/drivers/net/wireless/b43/pcmcia.c b/drivers/net/wireless/b43/pcmcia.c
new file mode 100644
index 000000000000..3e75a8a12c96
--- /dev/null
+++ b/drivers/net/wireless/b43/pcmcia.c
@@ -0,0 +1,157 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Copyright (c) 2007 Michael Buesch <mb@bu3sch.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/ssb/ssb.h>
+
+#include <pcmcia/cs_types.h>
+#include <pcmcia/cs.h>
+#include <pcmcia/cistpl.h>
+#include <pcmcia/ciscode.h>
+#include <pcmcia/ds.h>
+#include <pcmcia/cisreg.h>
+
+static /*const */ struct pcmcia_device_id b43_pcmcia_tbl[] = {
+        PCMCIA_DEVICE_MANF_CARD(0x2D0, 0x448),
+        PCMCIA_DEVICE_NULL,
+};
+
+MODULE_DEVICE_TABLE(pcmcia, b43_pcmcia_tbl);
+
+#ifdef CONFIG_PM
+static int b43_pcmcia_suspend(struct pcmcia_device *dev)
+{
+        //TODO
+        return 0;
+}
+
+static int b43_pcmcia_resume(struct pcmcia_device *dev)
+{
+        //TODO
+        return 0;
+}
+#else /* CONFIG_PM */
+# define b43_pcmcia_suspend             NULL
+# define b43_pcmcia_resume              NULL
+#endif /* CONFIG_PM */
+
+static int __devinit b43_pcmcia_probe(struct pcmcia_device *dev)
+{
+        struct ssb_bus *ssb;
+        win_req_t win;
+        memreq_t mem;
+        tuple_t tuple;
+        cisparse_t parse;
+        int err = -ENOMEM;
+        int res;
+        unsigned char buf[64];
+
+        ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
+        if (!ssb)
+                goto out;
+
+        err = -ENODEV;
+        tuple.DesiredTuple = CISTPL_CONFIG;
+        tuple.Attributes = 0;
+        tuple.TupleData = buf;
+        tuple.TupleDataMax = sizeof(buf);
+        tuple.TupleOffset = 0;
+
+        res = pcmcia_get_first_tuple(dev, &tuple);
+        if (res != CS_SUCCESS)
+                goto err_kfree_ssb;
+        res = pcmcia_get_tuple_data(dev, &tuple);
+        if (res != CS_SUCCESS)
+                goto err_kfree_ssb;
+        res = pcmcia_parse_tuple(dev, &tuple, &parse);
+        if (res != CS_SUCCESS)
+                goto err_kfree_ssb;
+
+        dev->conf.ConfigBase = parse.config.base;
+        dev->conf.Present = parse.config.rmask[0];
+
+        dev->io.BasePort2 = 0;
+        dev->io.NumPorts2 = 0;
+        dev->io.Attributes2 = 0;
+
+        win.Attributes = WIN_MEMORY_TYPE_CM | WIN_ENABLE | WIN_USE_WAIT;
+        win.Base = 0;
+        win.Size = SSB_CORE_SIZE;
+        win.AccessSpeed = 1000;
+        res = pcmcia_request_window(&dev, &win, &dev->win);
+        if (res != CS_SUCCESS)
+                goto err_kfree_ssb;
+
+        mem.CardOffset = 0;
+        mem.Page = 0;
+        res = pcmcia_map_mem_page(dev->win, &mem);
+        if (res != CS_SUCCESS)
+                goto err_kfree_ssb;
+
+        res = pcmcia_request_configuration(dev, &dev->conf);
+        if (res != CS_SUCCESS)
+                goto err_disable;
+
+        err = ssb_bus_pcmciabus_register(ssb, dev, win.Base);
+        dev->priv = ssb;
+
+      out:
+        return err;
+      err_disable:
+        pcmcia_disable_device(dev);
+      err_kfree_ssb:
+        kfree(ssb);
+        return err;
+}
+
+static void __devexit b43_pcmcia_remove(struct pcmcia_device *dev)
+{
+        struct ssb_bus *ssb = dev->priv;
+
+        ssb_bus_unregister(ssb);
+        pcmcia_release_window(dev->win);
+        pcmcia_disable_device(dev);
+        kfree(ssb);
+        dev->priv = NULL;
+}
+
+static struct pcmcia_driver b43_pcmcia_driver = {
+        .owner = THIS_MODULE,
+        .drv = {
+                .name = "b43-pcmcia",
+                },
+        .id_table = b43_pcmcia_tbl,
+        .probe = b43_pcmcia_probe,
+        .remove = b43_pcmcia_remove,
+        .suspend = b43_pcmcia_suspend,
+        .resume = b43_pcmcia_resume,
+};
+
+int b43_pcmcia_init(void)
+{
+        return pcmcia_register_driver(&b43_pcmcia_driver);
+}
+
+void b43_pcmcia_exit(void)
+{
+        pcmcia_unregister_driver(&b43_pcmcia_driver);
+}
diff --git a/drivers/net/wireless/b43/pcmcia.h b/drivers/net/wireless/b43/pcmcia.h
new file mode 100644
index 000000000000..85f120a67cbe
--- /dev/null
+++ b/drivers/net/wireless/b43/pcmcia.h
@@ -0,0 +1,20 @@
+#ifndef B43_PCMCIA_H_
+#define B43_PCMCIA_H_
+
+#ifdef CONFIG_B43_PCMCIA
+
+int b43_pcmcia_init(void);
+void b43_pcmcia_exit(void);
+
+#else /* CONFIG_B43_PCMCIA */
+
+static inline int b43_pcmcia_init(void)
+{
+        return 0;
+}
+static inline void b43_pcmcia_exit(void)
+{
+}
+
+#endif /* CONFIG_B43_PCMCIA */
+#endif /* B43_PCMCIA_H_ */
diff --git a/drivers/net/wireless/b43/phy.c b/drivers/net/wireless/b43/phy.c
new file mode 100644
index 000000000000..3282893021b0
--- /dev/null
+++ b/drivers/net/wireless/b43/phy.c
@@ -0,0 +1,4351 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+  Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
+  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include <linux/delay.h>
+#include <linux/types.h>
+
+#include "b43.h"
+#include "phy.h"
+#include "main.h"
+#include "tables.h"
+#include "lo.h"
+
+static const s8 b43_tssi2dbm_b_table[] = {
+        0x4D, 0x4C, 0x4B, 0x4A,
+        0x4A, 0x49, 0x48, 0x47,
+        0x47, 0x46, 0x45, 0x45,
+        0x44, 0x43, 0x42, 0x42,
+        0x41, 0x40, 0x3F, 0x3E,
+        0x3D, 0x3C, 0x3B, 0x3A,
+        0x39, 0x38, 0x37, 0x36,
+        0x35, 0x34, 0x32, 0x31,
+        0x30, 0x2F, 0x2D, 0x2C,
+        0x2B, 0x29, 0x28, 0x26,
+        0x25, 0x23, 0x21, 0x1F,
+        0x1D, 0x1A, 0x17, 0x14,
+        0x10, 0x0C, 0x06, 0x00,
+        -7, -7, -7, -7,
+        -7, -7, -7, -7,
+        -7, -7, -7, -7,
+};
+
+static const s8 b43_tssi2dbm_g_table[] = {
+        77, 77, 77, 76,
+        76, 76, 75, 75,
+        74, 74, 73, 73,
+        73, 72, 72, 71,
+        71, 70, 70, 69,
+        68, 68, 67, 67,
+        66, 65, 65, 64,
+        63, 63, 62, 61,
+        60, 59, 58, 57,
+        56, 55, 54, 53,
+        52, 50, 49, 47,
+        45, 43, 40, 37,
+        33, 28, 22, 14,
+        5, -7, -20, -20,
+        -20, -20, -20, -20,
+        -20, -20, -20, -20,
+};
+
+const u8 b43_radio_channel_codes_bg[] = {
+        12, 17, 22, 27,
+        32, 37, 42, 47,
+        52, 57, 62, 67,
+        72, 84,
+};
+
+static void b43_phy_initg(struct b43_wldev *dev);
+
+/* Reverse the bits of a 4bit value.
+ * Example:  1101 is flipped 1011
+ */
+static u16 flip_4bit(u16 value)
+{
+        u16 flipped = 0x0000;
+
+        B43_WARN_ON(value & ~0x000F);
+
+        flipped |= (value & 0x0001) << 3;
+        flipped |= (value & 0x0002) << 1;
+        flipped |= (value & 0x0004) >> 1;
+        flipped |= (value & 0x0008) >> 3;
+
+        return flipped;
+}
+
+static void generate_rfatt_list(struct b43_wldev *dev,
+                                struct b43_rfatt_list *list)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        /* APHY.rev < 5 || GPHY.rev < 6 */
+        static const struct b43_rfatt rfatt_0[] = {
+                {.att = 3,.with_padmix = 0,},
+                {.att = 1,.with_padmix = 0,},
+                {.att = 5,.with_padmix = 0,},
+                {.att = 7,.with_padmix = 0,},
+                {.att = 9,.with_padmix = 0,},
+                {.att = 2,.with_padmix = 0,},
+                {.att = 0,.with_padmix = 0,},
+                {.att = 4,.with_padmix = 0,},
+                {.att = 6,.with_padmix = 0,},
+                {.att = 8,.with_padmix = 0,},
+                {.att = 1,.with_padmix = 1,},
+                {.att = 2,.with_padmix = 1,},
+                {.att = 3,.with_padmix = 1,},
+                {.att = 4,.with_padmix = 1,},
+        };
+        /* Radio.rev == 8 && Radio.version == 0x2050 */
+        static const struct b43_rfatt rfatt_1[] = {
+                {.att = 2,.with_padmix = 1,},
+                {.att = 4,.with_padmix = 1,},
+                {.att = 6,.with_padmix = 1,},
+                {.att = 8,.with_padmix = 1,},
+                {.att = 10,.with_padmix = 1,},
+                {.att = 12,.with_padmix = 1,},
+                {.att = 14,.with_padmix = 1,},
+        };
+        /* Otherwise */
+        static const struct b43_rfatt rfatt_2[] = {
+                {.att = 0,.with_padmix = 1,},
+                {.att = 2,.with_padmix = 1,},
+                {.att = 4,.with_padmix = 1,},
+                {.att = 6,.with_padmix = 1,},
+                {.att = 8,.with_padmix = 1,},
+                {.att = 9,.with_padmix = 1,},
+                {.att = 9,.with_padmix = 1,},
+        };
+
+        if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
+            (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
+                /* Software pctl */
+                list->list = rfatt_0;
+                list->len = ARRAY_SIZE(rfatt_0);
+                list->min_val = 0;
+                list->max_val = 9;
+                return;
+        }
+        if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
+                /* Hardware pctl */
+                list->list = rfatt_1;
+                list->len = ARRAY_SIZE(rfatt_1);
+                list->min_val = 2;
+                list->max_val = 14;
+                return;
+        }
+        /* Hardware pctl */
+        list->list = rfatt_2;
+        list->len = ARRAY_SIZE(rfatt_2);
+        list->min_val = 0;
+        list->max_val = 9;
+}
+
+static void generate_bbatt_list(struct b43_wldev *dev,
+                                struct b43_bbatt_list *list)
+{
+        static const struct b43_bbatt bbatt_0[] = {
+                {.att = 0,},
+                {.att = 1,},
+                {.att = 2,},
+                {.att = 3,},
+                {.att = 4,},
+                {.att = 5,},
+                {.att = 6,},
+                {.att = 7,},
+                {.att = 8,},
+        };
+
+        list->list = bbatt_0;
+        list->len = ARRAY_SIZE(bbatt_0);
+        list->min_val = 0;
+        list->max_val = 8;
+}
+
+bool b43_has_hardware_pctl(struct b43_phy *phy)
+{
+        if (!phy->hardware_power_control)
+                return 0;
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                if (phy->rev >= 5)
+                        return 1;
+                break;
+        case B43_PHYTYPE_G:
+                if (phy->rev >= 6)
+                        return 1;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        return 0;
+}
+
+static void b43_shm_clear_tssi(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
+                break;
+        case B43_PHYTYPE_B:
+        case B43_PHYTYPE_G:
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
+                b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
+                break;
+        }
+}
+
+void b43_raw_phy_lock(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        B43_WARN_ON(!irqs_disabled());
+
+        /* We had a check for MACCTL==0 here, but I think that doesn't
+         * make sense, as MACCTL is never 0 when this is called.
+         *      --mb */
+        B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
+
+        if (dev->dev->id.revision < 3) {
+                b43_mac_suspend(dev);
+                spin_lock(&phy->lock);
+        } else {
+                if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+                        b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
+        }
+        phy->locked = 1;
+}
+
+void b43_raw_phy_unlock(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        B43_WARN_ON(!irqs_disabled());
+        if (dev->dev->id.revision < 3) {
+                if (phy->locked) {
+                        spin_unlock(&phy->lock);
+                        b43_mac_enable(dev);
+                }
+        } else {
+                if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
+                        b43_power_saving_ctl_bits(dev, 0);
+        }
+        phy->locked = 0;
+}
+
+/* Different PHYs require different register routing flags.
+ * This adjusts (and does sanity checks on) the routing flags.
+ */
+static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
+                                            u16 offset, struct b43_wldev *dev)
+{
+        if (phy->type == B43_PHYTYPE_A) {
+                /* OFDM registers are base-registers for the A-PHY. */
+                offset &= ~B43_PHYROUTE_OFDM_GPHY;
+        }
+        if (offset & B43_PHYROUTE_EXT_GPHY) {
+                /* Ext-G registers are only available on G-PHYs */
+                if (phy->type != B43_PHYTYPE_G) {
+                        b43dbg(dev->wl, "EXT-G PHY access at "
+                               "0x%04X on %u type PHY\n", offset, phy->type);
+                }
+        }
+
+        return offset;
+}
+
+u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        offset = adjust_phyreg_for_phytype(phy, offset, dev);
+        b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
+        return b43_read16(dev, B43_MMIO_PHY_DATA);
+}
+
+void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        offset = adjust_phyreg_for_phytype(phy, offset, dev);
+        b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
+        mmiowb();
+        b43_write16(dev, B43_MMIO_PHY_DATA, val);
+}
+
+static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower);
+
+/* Adjust the transmission power output (G-PHY) */
+void b43_set_txpower_g(struct b43_wldev *dev,
+                       const struct b43_bbatt *bbatt,
+                       const struct b43_rfatt *rfatt, u8 tx_control)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        u16 bb, rf;
+        u16 tx_bias, tx_magn;
+
+        bb = bbatt->att;
+        rf = rfatt->att;
+        tx_bias = lo->tx_bias;
+        tx_magn = lo->tx_magn;
+        if (unlikely(tx_bias == 0xFF))
+                tx_bias = 0;
+
+        /* Save the values for later */
+        phy->tx_control = tx_control;
+        memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
+        memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
+
+        if (b43_debug(dev, B43_DBG_XMITPOWER)) {
+                b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
+                       "rfatt(%u), tx_control(0x%02X), "
+                       "tx_bias(0x%02X), tx_magn(0x%02X)\n",
+                       bb, rf, tx_control, tx_bias, tx_magn);
+        }
+
+        b43_phy_set_baseband_attenuation(dev, bb);
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
+        if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
+                b43_radio_write16(dev, 0x43,
+                                  (rf & 0x000F) | (tx_control & 0x0070));
+        } else {
+                b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
+                                              & 0xFFF0) | (rf & 0x000F));
+                b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
+                                              & ~0x0070) | (tx_control &
+                                                            0x0070));
+        }
+        if (has_tx_magnification(phy)) {
+                b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
+        } else {
+                b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
+                                              & 0xFFF0) | (tx_bias & 0x000F));
+        }
+        if (phy->type == B43_PHYTYPE_G)
+                b43_lo_g_adjust(dev);
+}
+
+static void default_baseband_attenuation(struct b43_wldev *dev,
+                                         struct b43_bbatt *bb)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
+                bb->att = 0;
+        else
+                bb->att = 2;
+}
+
+static void default_radio_attenuation(struct b43_wldev *dev,
+                                      struct b43_rfatt *rf)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct b43_phy *phy = &dev->phy;
+
+        rf->with_padmix = 0;
+
+        if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
+            bus->boardinfo.type == SSB_BOARD_BCM4309G) {
+                if (bus->boardinfo.rev < 0x43) {
+                        rf->att = 2;
+                        return;
+                } else if (bus->boardinfo.rev < 0x51) {
+                        rf->att = 3;
+                        return;
+                }
+        }
+
+        if (phy->type == B43_PHYTYPE_A) {
+                rf->att = 0x60;
+                return;
+        }
+
+        switch (phy->radio_ver) {
+        case 0x2053:
+                switch (phy->radio_rev) {
+                case 1:
+                        rf->att = 6;
+                        return;
+                }
+                break;
+        case 0x2050:
+                switch (phy->radio_rev) {
+                case 0:
+                        rf->att = 5;
+                        return;
+                case 1:
+                        if (phy->type == B43_PHYTYPE_G) {
+                                if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
+                                    && bus->boardinfo.type == SSB_BOARD_BCM4309G
+                                    && bus->boardinfo.rev >= 30)
+                                        rf->att = 3;
+                                else if (bus->boardinfo.vendor ==
+                                         SSB_BOARDVENDOR_BCM
+                                         && bus->boardinfo.type ==
+                                         SSB_BOARD_BU4306)
+                                        rf->att = 3;
+                                else
+                                        rf->att = 1;
+                        } else {
+                                if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
+                                    && bus->boardinfo.type == SSB_BOARD_BCM4309G
+                                    && bus->boardinfo.rev >= 30)
+                                        rf->att = 7;
+                                else
+                                        rf->att = 6;
+                        }
+                        return;
+                case 2:
+                        if (phy->type == B43_PHYTYPE_G) {
+                                if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
+                                    && bus->boardinfo.type == SSB_BOARD_BCM4309G
+                                    && bus->boardinfo.rev >= 30)
+                                        rf->att = 3;
+                                else if (bus->boardinfo.vendor ==
+                                         SSB_BOARDVENDOR_BCM
+                                         && bus->boardinfo.type ==
+                                         SSB_BOARD_BU4306)
+                                        rf->att = 5;
+                                else if (bus->chip_id == 0x4320)
+                                        rf->att = 4;
+                                else
+                                        rf->att = 3;
+                        } else
+                                rf->att = 6;
+                        return;
+                case 3:
+                        rf->att = 5;
+                        return;
+                case 4:
+                case 5:
+                        rf->att = 1;
+                        return;
+                case 6:
+                case 7:
+                        rf->att = 5;
+                        return;
+                case 8:
+                        rf->att = 0xA;
+                        rf->with_padmix = 1;
+                        return;
+                case 9:
+                default:
+                        rf->att = 5;
+                        return;
+                }
+        }
+        rf->att = 5;
+}
+
+static u16 default_tx_control(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->radio_ver != 0x2050)
+                return 0;
+        if (phy->radio_rev == 1)
+                return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
+        if (phy->radio_rev < 6)
+                return B43_TXCTL_PA2DB;
+        if (phy->radio_rev == 8)
+                return B43_TXCTL_TXMIX;
+        return 0;
+}
+
+/* This func is called "PHY calibrate" in the specs... */
+void b43_phy_early_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+
+        default_baseband_attenuation(dev, &phy->bbatt);
+        default_radio_attenuation(dev, &phy->rfatt);
+        phy->tx_control = (default_tx_control(dev) << 4);
+
+        /* Commit previous writes */
+        b43_read32(dev, B43_MMIO_MACCTL);
+
+        if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
+                generate_rfatt_list(dev, &lo->rfatt_list);
+                generate_bbatt_list(dev, &lo->bbatt_list);
+        }
+        if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
+                /* Workaround: Temporarly disable gmode through the early init
+                 * phase, as the gmode stuff is not needed for phy rev 1 */
+                phy->gmode = 0;
+                b43_wireless_core_reset(dev, 0);
+                b43_phy_initg(dev);
+                phy->gmode = 1;
+                b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
+        }
+}
+
+/* GPHY_TSSI_Power_Lookup_Table_Init */
+static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        int i;
+        u16 value;
+
+        for (i = 0; i < 32; i++)
+                b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
+        for (i = 32; i < 64; i++)
+                b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
+        for (i = 0; i < 64; i += 2) {
+                value = (u16) phy->tssi2dbm[i];
+                value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
+                b43_phy_write(dev, 0x380 + (i / 2), value);
+        }
+}
+
+/* GPHY_Gain_Lookup_Table_Init */
+static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        u16 nr_written = 0;
+        u16 tmp;
+        u8 rf, bb;
+
+        if (!lo->lo_measured) {
+                b43_phy_write(dev, 0x3FF, 0);
+                return;
+        }
+
+        for (rf = 0; rf < lo->rfatt_list.len; rf++) {
+                for (bb = 0; bb < lo->bbatt_list.len; bb++) {
+                        if (nr_written >= 0x40)
+                                return;
+                        tmp = lo->bbatt_list.list[bb].att;
+                        tmp <<= 8;
+                        if (phy->radio_rev == 8)
+                                tmp |= 0x50;
+                        else
+                                tmp |= 0x40;
+                        tmp |= lo->rfatt_list.list[rf].att;
+                        b43_phy_write(dev, 0x3C0 + nr_written, tmp);
+                        nr_written++;
+                }
+        }
+}
+
+/* GPHY_DC_Lookup_Table */
+void b43_gphy_dc_lt_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct b43_txpower_lo_control *lo = phy->lo_control;
+        struct b43_loctl *loctl0;
+        struct b43_loctl *loctl1;
+        int i;
+        int rf_offset, bb_offset;
+        u16 tmp;
+
+        for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
+                rf_offset = i / lo->rfatt_list.len;
+                bb_offset = i % lo->rfatt_list.len;
+
+                loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
+                                          &lo->bbatt_list.list[bb_offset]);
+                if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
+                        rf_offset = (i + 1) / lo->rfatt_list.len;
+                        bb_offset = (i + 1) % lo->rfatt_list.len;
+
+                        loctl1 =
+                            b43_get_lo_g_ctl(dev,
+                                             &lo->rfatt_list.list[rf_offset],
+                                             &lo->bbatt_list.list[bb_offset]);
+                } else
+                        loctl1 = loctl0;
+
+                tmp = ((u16) loctl0->q & 0xF);
+                tmp |= ((u16) loctl0->i & 0xF) << 4;
+                tmp |= ((u16) loctl1->q & 0xF) << 8;
+                tmp |= ((u16) loctl1->i & 0xF) << 12;   //FIXME?
+                b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
+        }
+}
+
+static void hardware_pctl_init_aphy(struct b43_wldev *dev)
+{
+        //TODO
+}
+
+static void hardware_pctl_init_gphy(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
+                      | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
+        b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
+                      | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
+        b43_gphy_tssi_power_lt_init(dev);
+        b43_gphy_gain_lt_init(dev);
+        b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
+        b43_phy_write(dev, 0x0014, 0x0000);
+
+        B43_WARN_ON(phy->rev < 6);
+        b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
+                      | 0x0800);
+        b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
+                      & 0xFEFF);
+        b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
+                      & 0xFFBF);
+
+        b43_gphy_dc_lt_init(dev);
+}
+
+/* HardwarePowerControl init for A and G PHY */
+static void b43_hardware_pctl_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (!b43_has_hardware_pctl(phy)) {
+                /* No hardware power control */
+                b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
+                return;
+        }
+        /* Init the hwpctl related hardware */
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                hardware_pctl_init_aphy(dev);
+                break;
+        case B43_PHYTYPE_G:
+                hardware_pctl_init_gphy(dev);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        /* Enable hardware pctl in firmware. */
+        b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
+}
+
+static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (!b43_has_hardware_pctl(phy)) {
+                b43_phy_write(dev, 0x047A, 0xC111);
+                return;
+        }
+
+        b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
+        b43_phy_write(dev, 0x002F, 0x0202);
+        b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
+        b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
+        if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
+                b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
+                                            & 0xFF0F) | 0x0010);
+                b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
+                              | 0x8000);
+                b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
+                                            & 0xFFC0) | 0x0010);
+                b43_phy_write(dev, 0x002E, 0xC07F);
+                b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
+                              | 0x0400);
+        } else {
+                b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
+                              | 0x0200);
+                b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
+                              | 0x0400);
+                b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
+                              & 0x7FFF);
+                b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
+                              & 0xFFFE);
+                b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
+                                            & 0xFFC0) | 0x0010);
+                b43_phy_write(dev, 0x002E, 0xC07F);
+                b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
+                                            & 0xFF0F) | 0x0010);
+        }
+}
+
+/* Intialize B/G PHY power control
+ * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
+ */
+static void b43_phy_init_pctl(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct b43_phy *phy = &dev->phy;
+        struct b43_rfatt old_rfatt;
+        struct b43_bbatt old_bbatt;
+        u8 old_tx_control = 0;
+
+        if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
+            (bus->boardinfo.type == SSB_BOARD_BU4306))
+                return;
+
+        b43_phy_write(dev, 0x0028, 0x8018);
+
+        /* This does something with the Analog... */
+        b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
+                    & 0xFFDF);
+
+        if (phy->type == B43_PHYTYPE_G && !phy->gmode)
+                return;
+        b43_hardware_pctl_early_init(dev);
+        if (phy->cur_idle_tssi == 0) {
+                if (phy->radio_ver == 0x2050 && phy->analog == 0) {
+                        b43_radio_write16(dev, 0x0076,
+                                          (b43_radio_read16(dev, 0x0076)
+                                           & 0x00F7) | 0x0084);
+                } else {
+                        struct b43_rfatt rfatt;
+                        struct b43_bbatt bbatt;
+
+                        memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
+                        memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
+                        old_tx_control = phy->tx_control;
+
+                        bbatt.att = 11;
+                        if (phy->radio_rev == 8) {
+                                rfatt.att = 15;
+                                rfatt.with_padmix = 1;
+                        } else {
+                                rfatt.att = 9;
+                                rfatt.with_padmix = 0;
+                        }
+                        b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
+                }
+                b43_dummy_transmission(dev);
+                phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
+                if (B43_DEBUG) {
+                        /* Current-Idle-TSSI sanity check. */
+                        if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
+                                b43dbg(dev->wl,
+                                       "!WARNING! Idle-TSSI phy->cur_idle_tssi "
+                                       "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
+                                       "adjustment.\n", phy->cur_idle_tssi,
+                                       phy->tgt_idle_tssi);
+                                phy->cur_idle_tssi = 0;
+                        }
+                }
+                if (phy->radio_ver == 0x2050 && phy->analog == 0) {
+                        b43_radio_write16(dev, 0x0076,
+                                          b43_radio_read16(dev, 0x0076)
+                                          & 0xFF7B);
+                } else {
+                        b43_set_txpower_g(dev, &old_bbatt,
+                                          &old_rfatt, old_tx_control);
+                }
+        }
+        b43_hardware_pctl_init(dev);
+        b43_shm_clear_tssi(dev);
+}
+
+static void b43_phy_agcsetup(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 offset = 0x0000;
+
+        if (phy->rev == 1)
+                offset = 0x4C00;
+
+        b43_ofdmtab_write16(dev, offset, 0, 0x00FE);
+        b43_ofdmtab_write16(dev, offset, 1, 0x000D);
+        b43_ofdmtab_write16(dev, offset, 2, 0x0013);
+        b43_ofdmtab_write16(dev, offset, 3, 0x0019);
+
+        if (phy->rev == 1) {
+                b43_ofdmtab_write16(dev, 0x1800, 0, 0x2710);
+                b43_ofdmtab_write16(dev, 0x1801, 0, 0x9B83);
+                b43_ofdmtab_write16(dev, 0x1802, 0, 0x9B83);
+                b43_ofdmtab_write16(dev, 0x1803, 0, 0x0F8D);
+                b43_phy_write(dev, 0x0455, 0x0004);
+        }
+
+        b43_phy_write(dev, 0x04A5, (b43_phy_read(dev, 0x04A5)
+                                    & 0x00FF) | 0x5700);
+        b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
+                                    & 0xFF80) | 0x000F);
+        b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
+                                    & 0xC07F) | 0x2B80);
+        b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
+                                    & 0xF0FF) | 0x0300);
+
+        b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
+                          | 0x0008);
+
+        b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
+                                    & 0xFFF0) | 0x0008);
+        b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
+                                    & 0xF0FF) | 0x0600);
+        b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
+                                    & 0xF0FF) | 0x0700);
+        b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
+                                    & 0xF0FF) | 0x0100);
+
+        if (phy->rev == 1) {
+                b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
+                                            & 0xFFF0) | 0x0007);
+        }
+
+        b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
+                                    & 0xFF00) | 0x001C);
+        b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
+                                    & 0xC0FF) | 0x0200);
+        b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
+                                    & 0xFF00) | 0x001C);
+        b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
+                                    & 0xFF00) | 0x0020);
+        b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
+                                    & 0xC0FF) | 0x0200);
+        b43_phy_write(dev, 0x0482, (b43_phy_read(dev, 0x0482)
+                                    & 0xFF00) | 0x002E);
+        b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
+                                    & 0x00FF) | 0x1A00);
+        b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
+                                    & 0xFF00) | 0x0028);
+        b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
+                                    & 0x00FF) | 0x2C00);
+
+        if (phy->rev == 1) {
+                b43_phy_write(dev, 0x0430, 0x092B);
+                b43_phy_write(dev, 0x041B, (b43_phy_read(dev, 0x041B)
+                                            & 0xFFE1) | 0x0002);
+        } else {
+                b43_phy_write(dev, 0x041B, b43_phy_read(dev, 0x041B)
+                              & 0xFFE1);
+                b43_phy_write(dev, 0x041F, 0x287A);
+                b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
+                                            & 0xFFF0) | 0x0004);
+        }
+
+        if (phy->rev >= 6) {
+                b43_phy_write(dev, 0x0422, 0x287A);
+                b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
+                                            & 0x0FFF) | 0x3000);
+        }
+
+        b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
+                                    & 0x8080) | 0x7874);
+        b43_phy_write(dev, 0x048E, 0x1C00);
+
+        offset = 0x0800;
+        if (phy->rev == 1) {
+                offset = 0x5400;
+                b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
+                                            & 0xF0FF) | 0x0600);
+                b43_phy_write(dev, 0x048B, 0x005E);
+                b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
+                                            & 0xFF00) | 0x001E);
+                b43_phy_write(dev, 0x048D, 0x0002);
+        }
+        b43_ofdmtab_write16(dev, offset, 0, 0x00);
+        b43_ofdmtab_write16(dev, offset, 1, 0x07);
+        b43_ofdmtab_write16(dev, offset, 2, 0x10);
+        b43_ofdmtab_write16(dev, offset, 3, 0x1C);
+
+        if (phy->rev >= 6) {
+                b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
+                              & 0xFFFC);
+                b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
+                              & 0xEFFF);
+        }
+}
+
+static void b43_phy_setupg(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct b43_phy *phy = &dev->phy;
+        u16 i;
+
+        B43_WARN_ON(phy->type != B43_PHYTYPE_G);
+        if (phy->rev == 1) {
+                b43_phy_write(dev, 0x0406, 0x4F19);
+                b43_phy_write(dev, B43_PHY_G_CRS,
+                              (b43_phy_read(dev, B43_PHY_G_CRS) & 0xFC3F) |
+                              0x0340);
+                b43_phy_write(dev, 0x042C, 0x005A);
+                b43_phy_write(dev, 0x0427, 0x001A);
+
+                for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x5800, i,
+                                            b43_tab_finefreqg[i]);
+                for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg1[i]);
+                for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x2000, i, b43_tab_rotor[i]);
+        } else {
+                /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
+                b43_nrssi_hw_write(dev, 0xBA98, (s16) 0x7654);
+
+                if (phy->rev == 2) {
+                        b43_phy_write(dev, 0x04C0, 0x1861);
+                        b43_phy_write(dev, 0x04C1, 0x0271);
+                } else if (phy->rev > 2) {
+                        b43_phy_write(dev, 0x04C0, 0x0098);
+                        b43_phy_write(dev, 0x04C1, 0x0070);
+                        b43_phy_write(dev, 0x04C9, 0x0080);
+                }
+                b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x800);
+
+                for (i = 0; i < 64; i++)
+                        b43_ofdmtab_write16(dev, 0x4000, i, i);
+                for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg2[i]);
+        }
+
+        if (phy->rev <= 2)
+                for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x1400, i,
+                                            b43_tab_noisescaleg1[i]);
+        else if ((phy->rev >= 7) && (b43_phy_read(dev, 0x0449) & 0x0200))
+                for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x1400, i,
+                                            b43_tab_noisescaleg3[i]);
+        else
+                for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x1400, i,
+                                            b43_tab_noisescaleg2[i]);
+
+        if (phy->rev == 2)
+                for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x5000, i,
+                                            b43_tab_sigmasqr1[i]);
+        else if ((phy->rev > 2) && (phy->rev <= 8))
+                for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x5000, i,
+                                            b43_tab_sigmasqr2[i]);
+
+        if (phy->rev == 1) {
+                for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
+                        b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
+                for (i = 4; i < 20; i++)
+                        b43_ofdmtab_write16(dev, 0x5400, i, 0x0020);
+                b43_phy_agcsetup(dev);
+
+                if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
+                    (bus->boardinfo.type == SSB_BOARD_BU4306) &&
+                    (bus->boardinfo.rev == 0x17))
+                        return;
+
+                b43_ofdmtab_write16(dev, 0x5001, 0, 0x0002);
+                b43_ofdmtab_write16(dev, 0x5002, 0, 0x0001);
+        } else {
+                for (i = 0; i < 0x20; i++)
+                        b43_ofdmtab_write16(dev, 0x1000, i, 0x0820);
+                b43_phy_agcsetup(dev);
+                b43_phy_read(dev, 0x0400);      /* dummy read */
+                b43_phy_write(dev, 0x0403, 0x1000);
+                b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
+                b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
+
+                if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
+                    (bus->boardinfo.type == SSB_BOARD_BU4306) &&
+                    (bus->boardinfo.rev == 0x17))
+                        return;
+
+                b43_ofdmtab_write16(dev, 0x0401, 0, 0x0002);
+                b43_ofdmtab_write16(dev, 0x0402, 0, 0x0001);
+        }
+}
+
+/* Initialize the noisescaletable for APHY */
+static void b43_phy_init_noisescaletbl(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        int i;
+
+        for (i = 0; i < 12; i++) {
+                if (phy->rev == 2)
+                        b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
+                else
+                        b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
+        }
+        if (phy->rev == 2)
+                b43_ofdmtab_write16(dev, 0x1400, i, 0x6700);
+        else
+                b43_ofdmtab_write16(dev, 0x1400, i, 0x2300);
+        for (i = 0; i < 11; i++) {
+                if (phy->rev == 2)
+                        b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
+                else
+                        b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
+        }
+        if (phy->rev == 2)
+                b43_ofdmtab_write16(dev, 0x1400, i, 0x0067);
+        else
+                b43_ofdmtab_write16(dev, 0x1400, i, 0x0023);
+}
+
+static void b43_phy_setupa(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 i;
+
+        B43_WARN_ON(phy->type != B43_PHYTYPE_A);
+        switch (phy->rev) {
+        case 2:
+                b43_phy_write(dev, 0x008E, 0x3800);
+                b43_phy_write(dev, 0x0035, 0x03FF);
+                b43_phy_write(dev, 0x0036, 0x0400);
+
+                b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
+
+                b43_phy_write(dev, 0x001C, 0x0FF9);
+                b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
+                b43_ofdmtab_write16(dev, 0x3C0C, 0, 0x07BF);
+                b43_radio_write16(dev, 0x0002, 0x07BF);
+
+                b43_phy_write(dev, 0x0024, 0x4680);
+                b43_phy_write(dev, 0x0020, 0x0003);
+                b43_phy_write(dev, 0x001D, 0x0F40);
+                b43_phy_write(dev, 0x001F, 0x1C00);
+
+                b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
+                                            & 0x00FF) | 0x0400);
+                b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B)
+                              & 0xFBFF);
+                b43_phy_write(dev, 0x008E, 0x58C1);
+
+                b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
+                b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
+                b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
+                b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
+                b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
+
+                b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0000, 1, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0000, 2, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0000, 3, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0000, 4, 0x0015);
+                b43_ofdmtab_write16(dev, 0x0000, 5, 0x0015);
+                b43_ofdmtab_write16(dev, 0x0000, 6, 0x0019);
+
+                b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
+                b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
+                b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
+
+                for (i = 0; i < 16; i++)
+                        b43_ofdmtab_write16(dev, 0x4000, i, (0x8 + i) & 0x000F);
+
+                b43_ofdmtab_write16(dev, 0x3003, 0, 0x1044);
+                b43_ofdmtab_write16(dev, 0x3004, 0, 0x7201);
+                b43_ofdmtab_write16(dev, 0x3006, 0, 0x0040);
+                b43_ofdmtab_write16(dev, 0x3001, 0,
+                                    (b43_ofdmtab_read16(dev, 0x3001, 0) &
+                                     0x0010) | 0x0008);
+
+                for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x5800, i,
+                                            b43_tab_finefreqa[i]);
+                for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
+                        b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea2[i]);
+                for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
+                        b43_ofdmtab_write32(dev, 0x2000, i, b43_tab_rotor[i]);
+                b43_phy_init_noisescaletbl(dev);
+                for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
+                        b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
+                break;
+        case 3:
+                for (i = 0; i < 64; i++)
+                        b43_ofdmtab_write16(dev, 0x4000, i, i);
+
+                b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
+
+                b43_phy_write(dev, 0x001C, 0x0FF9);
+                b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
+                b43_radio_write16(dev, 0x0002, 0x07BF);
+
+                b43_phy_write(dev, 0x0024, 0x4680);
+                b43_phy_write(dev, 0x0020, 0x0003);
+                b43_phy_write(dev, 0x001D, 0x0F40);
+                b43_phy_write(dev, 0x001F, 0x1C00);
+                b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
+                                            & 0x00FF) | 0x0400);
+
+                b43_ofdmtab_write16(dev, 0x3000, 1,
+                                    (b43_ofdmtab_read16(dev, 0x3000, 1)
+                                     & 0x0010) | 0x0008);
+                for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++) {
+                        b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea3[i]);
+                }
+                b43_phy_init_noisescaletbl(dev);
+                for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
+                        b43_ofdmtab_write16(dev, 0x5000, i,
+                                            b43_tab_sigmasqr1[i]);
+                }
+
+                b43_phy_write(dev, 0x0003, 0x1808);
+
+                b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
+                b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
+                b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
+                b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
+                b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
+
+                b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0001, 0, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0002, 0, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0003, 0, 0x0013);
+                b43_ofdmtab_write16(dev, 0x0004, 0, 0x0015);
+                b43_ofdmtab_write16(dev, 0x0005, 0, 0x0015);
+                b43_ofdmtab_write16(dev, 0x0006, 0, 0x0019);
+
+                b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
+                b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
+                b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
+
+                b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
+                b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+/* Initialize APHY. This is also called for the GPHY in some cases. */
+static void b43_phy_inita(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct b43_phy *phy = &dev->phy;
+        u16 tval;
+
+        might_sleep();
+
+        if (phy->type == B43_PHYTYPE_A) {
+                b43_phy_setupa(dev);
+        } else {
+                b43_phy_setupg(dev);
+                if (phy->gmode &&
+                    (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL))
+                        b43_phy_write(dev, 0x046E, 0x03CF);
+                return;
+        }
+
+        b43_phy_write(dev, B43_PHY_A_CRS,
+                      (b43_phy_read(dev, B43_PHY_A_CRS) & 0xF83C) | 0x0340);
+        b43_phy_write(dev, 0x0034, 0x0001);
+
+        //TODO: RSSI AGC
+        b43_phy_write(dev, B43_PHY_A_CRS,
+                      b43_phy_read(dev, B43_PHY_A_CRS) | (1 << 14));
+        b43_radio_init2060(dev);
+
+        if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
+            ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
+             (bus->boardinfo.type == SSB_BOARD_BU4309))) {
+                if (phy->lofcal == 0xFFFF) {
+                        //TODO: LOF Cal
+                        b43_radio_set_tx_iq(dev);
+                } else
+                        b43_radio_write16(dev, 0x001E, phy->lofcal);
+        }
+
+        b43_phy_write(dev, 0x007A, 0xF111);
+
+        if (phy->cur_idle_tssi == 0) {
+                b43_radio_write16(dev, 0x0019, 0x0000);
+                b43_radio_write16(dev, 0x0017, 0x0020);
+
+                tval = b43_ofdmtab_read16(dev, 0x3001, 0);
+                if (phy->rev == 1) {
+                        b43_ofdmtab_write16(dev, 0x3001, 0,
+                                            (b43_ofdmtab_read16(dev, 0x3001, 0)
+                                             & 0xFF87)
+                                            | 0x0058);
+                } else {
+                        b43_ofdmtab_write16(dev, 0x3001, 0,
+                                            (b43_ofdmtab_read16(dev, 0x3001, 0)
+                                             & 0xFFC3)
+                                            | 0x002C);
+                }
+                b43_dummy_transmission(dev);
+                phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_A_PCTL);
+                b43_ofdmtab_write16(dev, 0x3001, 0, tval);
+
+                b43_radio_set_txpower_a(dev, 0x0018);
+        }
+        b43_shm_clear_tssi(dev);
+}
+
+static void b43_phy_initb2(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 offset, val;
+
+        b43_write16(dev, 0x03EC, 0x3F22);
+        b43_phy_write(dev, 0x0020, 0x301C);
+        b43_phy_write(dev, 0x0026, 0x0000);
+        b43_phy_write(dev, 0x0030, 0x00C6);
+        b43_phy_write(dev, 0x0088, 0x3E00);
+        val = 0x3C3D;
+        for (offset = 0x0089; offset < 0x00A7; offset++) {
+                b43_phy_write(dev, offset, val);
+                val -= 0x0202;
+        }
+        b43_phy_write(dev, 0x03E4, 0x3000);
+        if (phy->channel == 0xFF)
+                b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 0);
+        else
+                b43_radio_selectchannel(dev, phy->channel, 0);
+        if (phy->radio_ver != 0x2050) {
+                b43_radio_write16(dev, 0x0075, 0x0080);
+                b43_radio_write16(dev, 0x0079, 0x0081);
+        }
+        b43_radio_write16(dev, 0x0050, 0x0020);
+        b43_radio_write16(dev, 0x0050, 0x0023);
+        if (phy->radio_ver == 0x2050) {
+                b43_radio_write16(dev, 0x0050, 0x0020);
+                b43_radio_write16(dev, 0x005A, 0x0070);
+                b43_radio_write16(dev, 0x005B, 0x007B);
+                b43_radio_write16(dev, 0x005C, 0x00B0);
+                b43_radio_write16(dev, 0x007A, 0x000F);
+                b43_phy_write(dev, 0x0038, 0x0677);
+                b43_radio_init2050(dev);
+        }
+        b43_phy_write(dev, 0x0014, 0x0080);
+        b43_phy_write(dev, 0x0032, 0x00CA);
+        b43_phy_write(dev, 0x0032, 0x00CC);
+        b43_phy_write(dev, 0x0035, 0x07C2);
+        b43_lo_b_measure(dev);
+        b43_phy_write(dev, 0x0026, 0xCC00);
+        if (phy->radio_ver != 0x2050)
+                b43_phy_write(dev, 0x0026, 0xCE00);
+        b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
+        b43_phy_write(dev, 0x002A, 0x88A3);
+        if (phy->radio_ver != 0x2050)
+                b43_phy_write(dev, 0x002A, 0x88C2);
+        b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
+        b43_phy_init_pctl(dev);
+}
+
+static void b43_phy_initb4(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 offset, val;
+
+        b43_write16(dev, 0x03EC, 0x3F22);
+        b43_phy_write(dev, 0x0020, 0x301C);
+        b43_phy_write(dev, 0x0026, 0x0000);
+        b43_phy_write(dev, 0x0030, 0x00C6);
+        b43_phy_write(dev, 0x0088, 0x3E00);
+        val = 0x3C3D;
+        for (offset = 0x0089; offset < 0x00A7; offset++) {
+                b43_phy_write(dev, offset, val);
+                val -= 0x0202;
+        }
+        b43_phy_write(dev, 0x03E4, 0x3000);
+        if (phy->channel == 0xFF)
+                b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 0);
+        else
+                b43_radio_selectchannel(dev, phy->channel, 0);
+        if (phy->radio_ver != 0x2050) {
+                b43_radio_write16(dev, 0x0075, 0x0080);
+                b43_radio_write16(dev, 0x0079, 0x0081);
+        }
+        b43_radio_write16(dev, 0x0050, 0x0020);
+        b43_radio_write16(dev, 0x0050, 0x0023);
+        if (phy->radio_ver == 0x2050) {
+                b43_radio_write16(dev, 0x0050, 0x0020);
+                b43_radio_write16(dev, 0x005A, 0x0070);
+                b43_radio_write16(dev, 0x005B, 0x007B);
+                b43_radio_write16(dev, 0x005C, 0x00B0);
+                b43_radio_write16(dev, 0x007A, 0x000F);
+                b43_phy_write(dev, 0x0038, 0x0677);
+                b43_radio_init2050(dev);
+        }
+        b43_phy_write(dev, 0x0014, 0x0080);
+        b43_phy_write(dev, 0x0032, 0x00CA);
+        if (phy->radio_ver == 0x2050)
+                b43_phy_write(dev, 0x0032, 0x00E0);
+        b43_phy_write(dev, 0x0035, 0x07C2);
+
+        b43_lo_b_measure(dev);
+
+        b43_phy_write(dev, 0x0026, 0xCC00);
+        if (phy->radio_ver == 0x2050)
+                b43_phy_write(dev, 0x0026, 0xCE00);
+        b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
+        b43_phy_write(dev, 0x002A, 0x88A3);
+        if (phy->radio_ver == 0x2050)
+                b43_phy_write(dev, 0x002A, 0x88C2);
+        b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
+        if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
+                b43_calc_nrssi_slope(dev);
+                b43_calc_nrssi_threshold(dev);
+        }
+        b43_phy_init_pctl(dev);
+}
+
+static void b43_phy_initb5(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct b43_phy *phy = &dev->phy;
+        u16 offset, value;
+        u8 old_channel;
+
+        if (phy->analog == 1) {
+                b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
+                                  | 0x0050);
+        }
+        if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
+            (bus->boardinfo.type != SSB_BOARD_BU4306)) {
+                value = 0x2120;
+                for (offset = 0x00A8; offset < 0x00C7; offset++) {
+                        b43_phy_write(dev, offset, value);
+                        value += 0x202;
+                }
+        }
+        b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
+                      | 0x0700);
+        if (phy->radio_ver == 0x2050)
+                b43_phy_write(dev, 0x0038, 0x0667);
+
+        if (phy->gmode || phy->rev >= 2) {
+                if (phy->radio_ver == 0x2050) {
+                        b43_radio_write16(dev, 0x007A,
+                                          b43_radio_read16(dev, 0x007A)
+                                          | 0x0020);
+                        b43_radio_write16(dev, 0x0051,
+                                          b43_radio_read16(dev, 0x0051)
+                                          | 0x0004);
+                }
+                b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
+
+                b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
+                b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
+
+                b43_phy_write(dev, 0x001C, 0x186A);
+
+                b43_phy_write(dev, 0x0013,
+                              (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
+                b43_phy_write(dev, 0x0035,
+                              (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
+                b43_phy_write(dev, 0x005D,
+                              (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
+        }
+
+        if (dev->bad_frames_preempt) {
+                b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
+                              b43_phy_read(dev,
+                                           B43_PHY_RADIO_BITFIELD) | (1 << 11));
+        }
+
+        if (phy->analog == 1) {
+                b43_phy_write(dev, 0x0026, 0xCE00);
+                b43_phy_write(dev, 0x0021, 0x3763);
+                b43_phy_write(dev, 0x0022, 0x1BC3);
+                b43_phy_write(dev, 0x0023, 0x06F9);
+                b43_phy_write(dev, 0x0024, 0x037E);
+        } else
+                b43_phy_write(dev, 0x0026, 0xCC00);
+        b43_phy_write(dev, 0x0030, 0x00C6);
+        b43_write16(dev, 0x03EC, 0x3F22);
+
+        if (phy->analog == 1)
+                b43_phy_write(dev, 0x0020, 0x3E1C);
+        else
+                b43_phy_write(dev, 0x0020, 0x301C);
+
+        if (phy->analog == 0)
+                b43_write16(dev, 0x03E4, 0x3000);
+
+        old_channel = phy->channel;
+        /* Force to channel 7, even if not supported. */
+        b43_radio_selectchannel(dev, 7, 0);
+
+        if (phy->radio_ver != 0x2050) {
+                b43_radio_write16(dev, 0x0075, 0x0080);
+                b43_radio_write16(dev, 0x0079, 0x0081);
+        }
+
+        b43_radio_write16(dev, 0x0050, 0x0020);
+        b43_radio_write16(dev, 0x0050, 0x0023);
+
+        if (phy->radio_ver == 0x2050) {
+                b43_radio_write16(dev, 0x0050, 0x0020);
+                b43_radio_write16(dev, 0x005A, 0x0070);
+        }
+
+        b43_radio_write16(dev, 0x005B, 0x007B);
+        b43_radio_write16(dev, 0x005C, 0x00B0);
+
+        b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
+
+        b43_radio_selectchannel(dev, old_channel, 0);
+
+        b43_phy_write(dev, 0x0014, 0x0080);
+        b43_phy_write(dev, 0x0032, 0x00CA);
+        b43_phy_write(dev, 0x002A, 0x88A3);
+
+        b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
+
+        if (phy->radio_ver == 0x2050)
+                b43_radio_write16(dev, 0x005D, 0x000D);
+
+        b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
+}
+
+static void b43_phy_initb6(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 offset, val;
+        u8 old_channel;
+
+        b43_phy_write(dev, 0x003E, 0x817A);
+        b43_radio_write16(dev, 0x007A,
+                          (b43_radio_read16(dev, 0x007A) | 0x0058));
+        if (phy->radio_rev == 4 || phy->radio_rev == 5) {
+                b43_radio_write16(dev, 0x51, 0x37);
+                b43_radio_write16(dev, 0x52, 0x70);
+                b43_radio_write16(dev, 0x53, 0xB3);
+                b43_radio_write16(dev, 0x54, 0x9B);
+                b43_radio_write16(dev, 0x5A, 0x88);
+                b43_radio_write16(dev, 0x5B, 0x88);
+                b43_radio_write16(dev, 0x5D, 0x88);
+                b43_radio_write16(dev, 0x5E, 0x88);
+                b43_radio_write16(dev, 0x7D, 0x88);
+                b43_hf_write(dev, b43_hf_read(dev)
+                             | B43_HF_TSSIRPSMW);
+        }
+        B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
+        if (phy->radio_rev == 8) {
+                b43_radio_write16(dev, 0x51, 0);
+                b43_radio_write16(dev, 0x52, 0x40);
+                b43_radio_write16(dev, 0x53, 0xB7);
+                b43_radio_write16(dev, 0x54, 0x98);
+                b43_radio_write16(dev, 0x5A, 0x88);
+                b43_radio_write16(dev, 0x5B, 0x6B);
+                b43_radio_write16(dev, 0x5C, 0x0F);
+                if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_ALTIQ) {
+                        b43_radio_write16(dev, 0x5D, 0xFA);
+                        b43_radio_write16(dev, 0x5E, 0xD8);
+                } else {
+                        b43_radio_write16(dev, 0x5D, 0xF5);
+                        b43_radio_write16(dev, 0x5E, 0xB8);
+                }
+                b43_radio_write16(dev, 0x0073, 0x0003);
+                b43_radio_write16(dev, 0x007D, 0x00A8);
+                b43_radio_write16(dev, 0x007C, 0x0001);
+                b43_radio_write16(dev, 0x007E, 0x0008);
+        }
+        val = 0x1E1F;
+        for (offset = 0x0088; offset < 0x0098; offset++) {
+                b43_phy_write(dev, offset, val);
+                val -= 0x0202;
+        }
+        val = 0x3E3F;
+        for (offset = 0x0098; offset < 0x00A8; offset++) {
+                b43_phy_write(dev, offset, val);
+                val -= 0x0202;
+        }
+        val = 0x2120;
+        for (offset = 0x00A8; offset < 0x00C8; offset++) {
+                b43_phy_write(dev, offset, (val & 0x3F3F));
+                val += 0x0202;
+        }
+        if (phy->type == B43_PHYTYPE_G) {
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) | 0x0020);
+                b43_radio_write16(dev, 0x0051,
+                                  b43_radio_read16(dev, 0x0051) | 0x0004);
+                b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
+                b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
+                b43_phy_write(dev, 0x5B, 0);
+                b43_phy_write(dev, 0x5C, 0);
+        }
+
+        old_channel = phy->channel;
+        if (old_channel >= 8)
+                b43_radio_selectchannel(dev, 1, 0);
+        else
+                b43_radio_selectchannel(dev, 13, 0);
+
+        b43_radio_write16(dev, 0x0050, 0x0020);
+        b43_radio_write16(dev, 0x0050, 0x0023);
+        udelay(40);
+        if (phy->radio_rev < 6 || phy->radio_rev == 8) {
+                b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
+                                              | 0x0002));
+                b43_radio_write16(dev, 0x50, 0x20);
+        }
+        if (phy->radio_rev <= 2) {
+                b43_radio_write16(dev, 0x7C, 0x20);
+                b43_radio_write16(dev, 0x5A, 0x70);
+                b43_radio_write16(dev, 0x5B, 0x7B);
+                b43_radio_write16(dev, 0x5C, 0xB0);
+        }
+        b43_radio_write16(dev, 0x007A,
+                          (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
+
+        b43_radio_selectchannel(dev, old_channel, 0);
+
+        b43_phy_write(dev, 0x0014, 0x0200);
+        if (phy->radio_rev >= 6)
+                b43_phy_write(dev, 0x2A, 0x88C2);
+        else
+                b43_phy_write(dev, 0x2A, 0x8AC0);
+        b43_phy_write(dev, 0x0038, 0x0668);
+        b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
+        if (phy->radio_rev <= 5) {
+                b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
+                                          & 0xFF80) | 0x0003);
+        }
+        if (phy->radio_rev <= 2)
+                b43_radio_write16(dev, 0x005D, 0x000D);
+
+        if (phy->analog == 4) {
+                b43_write16(dev, 0x3E4, 9);
+                b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
+                              & 0x0FFF);
+        } else {
+                b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
+                              | 0x0004);
+        }
+        if (phy->type == B43_PHYTYPE_B) {
+                b43_write16(dev, 0x03E6, 0x8140);
+                b43_phy_write(dev, 0x0016, 0x0410);
+                b43_phy_write(dev, 0x0017, 0x0820);
+                b43_phy_write(dev, 0x0062, 0x0007);
+                b43_radio_init2050(dev);
+                b43_lo_g_measure(dev);
+                if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
+                        b43_calc_nrssi_slope(dev);
+                        b43_calc_nrssi_threshold(dev);
+                }
+                b43_phy_init_pctl(dev);
+        } else if (phy->type == B43_PHYTYPE_G)
+                b43_write16(dev, 0x03E6, 0x0);
+}
+
+static void b43_calc_loopback_gain(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 backup_phy[16] = { 0 };
+        u16 backup_radio[3];
+        u16 backup_bband;
+        u16 i, j, loop_i_max;
+        u16 trsw_rx;
+        u16 loop1_outer_done, loop1_inner_done;
+
+        backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
+        backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
+        backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
+        backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
+        if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
+                backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
+        }
+        backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A));
+        backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59));
+        backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58));
+        backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A));
+        backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03));
+        backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
+        backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
+        backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B));
+        backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
+        backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
+        backup_bband = phy->bbatt.att;
+        backup_radio[0] = b43_radio_read16(dev, 0x52);
+        backup_radio[1] = b43_radio_read16(dev, 0x43);
+        backup_radio[2] = b43_radio_read16(dev, 0x7A);
+
+        b43_phy_write(dev, B43_PHY_CRS0,
+                      b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
+        b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
+                      b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
+        b43_phy_write(dev, B43_PHY_RFOVER,
+                      b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
+        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                      b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
+        b43_phy_write(dev, B43_PHY_RFOVER,
+                      b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
+        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                      b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
+        if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                b43_phy_write(dev, B43_PHY_ANALOGOVER,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              b43_phy_read(dev,
+                                           B43_PHY_ANALOGOVERVAL) & 0xFFFE);
+                b43_phy_write(dev, B43_PHY_ANALOGOVER,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              b43_phy_read(dev,
+                                           B43_PHY_ANALOGOVERVAL) & 0xFFFD);
+        }
+        b43_phy_write(dev, B43_PHY_RFOVER,
+                      b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
+        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                      b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
+        b43_phy_write(dev, B43_PHY_RFOVER,
+                      b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
+        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                      (b43_phy_read(dev, B43_PHY_RFOVERVAL)
+                       & 0xFFCF) | 0x10);
+
+        b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780);
+        b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
+        b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
+
+        b43_phy_write(dev, B43_PHY_BASE(0x0A),
+                      b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000);
+        if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                b43_phy_write(dev, B43_PHY_ANALOGOVER,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              b43_phy_read(dev,
+                                           B43_PHY_ANALOGOVERVAL) & 0xFFFB);
+        }
+        b43_phy_write(dev, B43_PHY_BASE(0x03),
+                      (b43_phy_read(dev, B43_PHY_BASE(0x03))
+                       & 0xFF9F) | 0x40);
+
+        if (phy->radio_rev == 8) {
+                b43_radio_write16(dev, 0x43, 0x000F);
+        } else {
+                b43_radio_write16(dev, 0x52, 0);
+                b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
+                                              & 0xFFF0) | 0x9);
+        }
+        b43_phy_set_baseband_attenuation(dev, 11);
+
+        if (phy->rev >= 3)
+                b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
+        else
+                b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
+        b43_phy_write(dev, B43_PHY_LO_CTL, 0);
+
+        b43_phy_write(dev, B43_PHY_BASE(0x2B),
+                      (b43_phy_read(dev, B43_PHY_BASE(0x2B))
+                       & 0xFFC0) | 0x01);
+        b43_phy_write(dev, B43_PHY_BASE(0x2B),
+                      (b43_phy_read(dev, B43_PHY_BASE(0x2B))
+                       & 0xC0FF) | 0x800);
+
+        b43_phy_write(dev, B43_PHY_RFOVER,
+                      b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
+        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                      b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
+
+        if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) {
+                if (phy->rev >= 7) {
+                        b43_phy_write(dev, B43_PHY_RFOVER,
+                                      b43_phy_read(dev, B43_PHY_RFOVER)
+                                      | 0x0800);
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      b43_phy_read(dev, B43_PHY_RFOVERVAL)
+                                      | 0x8000);
+                }
+        }
+        b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
+                          & 0x00F7);
+
+        j = 0;
+        loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
+        for (i = 0; i < loop_i_max; i++) {
+                for (j = 0; j < 16; j++) {
+                        b43_radio_write16(dev, 0x43, i);
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      (b43_phy_read(dev, B43_PHY_RFOVERVAL)
+                                       & 0xF0FF) | (j << 8));
+                        b43_phy_write(dev, B43_PHY_PGACTL,
+                                      (b43_phy_read(dev, B43_PHY_PGACTL)
+                                       & 0x0FFF) | 0xA000);
+                        b43_phy_write(dev, B43_PHY_PGACTL,
+                                      b43_phy_read(dev, B43_PHY_PGACTL)
+                                      | 0xF000);
+                        udelay(20);
+                        if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
+                                goto exit_loop1;
+                }
+        }
+      exit_loop1:
+        loop1_outer_done = i;
+        loop1_inner_done = j;
+        if (j >= 8) {
+                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                              b43_phy_read(dev, B43_PHY_RFOVERVAL)
+                              | 0x30);
+                trsw_rx = 0x1B;
+                for (j = j - 8; j < 16; j++) {
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      (b43_phy_read(dev, B43_PHY_RFOVERVAL)
+                                       & 0xF0FF) | (j << 8));
+                        b43_phy_write(dev, B43_PHY_PGACTL,
+                                      (b43_phy_read(dev, B43_PHY_PGACTL)
+                                       & 0x0FFF) | 0xA000);
+                        b43_phy_write(dev, B43_PHY_PGACTL,
+                                      b43_phy_read(dev, B43_PHY_PGACTL)
+                                      | 0xF000);
+                        udelay(20);
+                        trsw_rx -= 3;
+                        if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
+                                goto exit_loop2;
+                }
+        } else
+                trsw_rx = 0x18;
+      exit_loop2:
+
+        if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
+        }
+        b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]);
+        b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]);
+        b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]);
+        b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]);
+        b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]);
+        b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
+        b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
+        b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]);
+        b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
+
+        b43_phy_set_baseband_attenuation(dev, backup_bband);
+
+        b43_radio_write16(dev, 0x52, backup_radio[0]);
+        b43_radio_write16(dev, 0x43, backup_radio[1]);
+        b43_radio_write16(dev, 0x7A, backup_radio[2]);
+
+        b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
+        udelay(10);
+        b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
+        b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
+        b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
+        b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
+
+        phy->max_lb_gain =
+            ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
+        phy->trsw_rx_gain = trsw_rx * 2;
+}
+
+static void b43_phy_initg(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 tmp;
+
+        if (phy->rev == 1)
+                b43_phy_initb5(dev);
+        else
+                b43_phy_initb6(dev);
+
+        if (phy->rev >= 2 || phy->gmode)
+                b43_phy_inita(dev);
+
+        if (phy->rev >= 2) {
+                b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
+        }
+        if (phy->rev == 2) {
+                b43_phy_write(dev, B43_PHY_RFOVER, 0);
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
+        }
+        if (phy->rev > 5) {
+                b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
+        }
+        if (phy->gmode || phy->rev >= 2) {
+                tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
+                tmp &= B43_PHYVER_VERSION;
+                if (tmp == 3 || tmp == 5) {
+                        b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
+                        b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
+                }
+                if (tmp == 5) {
+                        b43_phy_write(dev, B43_PHY_OFDM(0xCC),
+                                      (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
+                                       & 0x00FF) | 0x1F00);
+                }
+        }
+        if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
+                b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
+        if (phy->radio_rev == 8) {
+                b43_phy_write(dev, B43_PHY_EXTG(0x01),
+                              b43_phy_read(dev, B43_PHY_EXTG(0x01))
+                              | 0x80);
+                b43_phy_write(dev, B43_PHY_OFDM(0x3E),
+                              b43_phy_read(dev, B43_PHY_OFDM(0x3E))
+                              | 0x4);
+        }
+        if (has_loopback_gain(phy))
+                b43_calc_loopback_gain(dev);
+
+        if (phy->radio_rev != 8) {
+                if (phy->initval == 0xFFFF)
+                        phy->initval = b43_radio_init2050(dev);
+                else
+                        b43_radio_write16(dev, 0x0078, phy->initval);
+        }
+        if (phy->lo_control->tx_bias == 0xFF) {
+                b43_lo_g_measure(dev);
+        } else {
+                if (has_tx_magnification(phy)) {
+                        b43_radio_write16(dev, 0x52,
+                                          (b43_radio_read16(dev, 0x52) & 0xFF00)
+                                          | phy->lo_control->tx_bias | phy->
+                                          lo_control->tx_magn);
+                } else {
+                        b43_radio_write16(dev, 0x52,
+                                          (b43_radio_read16(dev, 0x52) & 0xFFF0)
+                                          | phy->lo_control->tx_bias);
+                }
+                if (phy->rev >= 6) {
+                        b43_phy_write(dev, B43_PHY_BASE(0x36),
+                                      (b43_phy_read(dev, B43_PHY_BASE(0x36))
+                                       & 0x0FFF) | (phy->lo_control->
+                                                    tx_bias << 12));
+                }
+                if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL)
+                        b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075);
+                else
+                        b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F);
+                if (phy->rev < 2)
+                        b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101);
+                else
+                        b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202);
+        }
+        if (phy->gmode || phy->rev >= 2) {
+                b43_lo_g_adjust(dev);
+                b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
+        }
+
+        if (!(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
+                /* The specs state to update the NRSSI LT with
+                 * the value 0x7FFFFFFF here. I think that is some weird
+                 * compiler optimization in the original driver.
+                 * Essentially, what we do here is resetting all NRSSI LT
+                 * entries to -32 (see the limit_value() in nrssi_hw_update())
+                 */
+                b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
+                b43_calc_nrssi_threshold(dev);
+        } else if (phy->gmode || phy->rev >= 2) {
+                if (phy->nrssi[0] == -1000) {
+                        B43_WARN_ON(phy->nrssi[1] != -1000);
+                        b43_calc_nrssi_slope(dev);
+                } else
+                        b43_calc_nrssi_threshold(dev);
+        }
+        if (phy->radio_rev == 8)
+                b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
+        b43_phy_init_pctl(dev);
+        /* FIXME: The spec says in the following if, the 0 should be replaced
+           'if OFDM may not be used in the current locale'
+           but OFDM is legal everywhere */
+        if ((dev->dev->bus->chip_id == 0x4306
+             && dev->dev->bus->chip_package == 2) || 0) {
+                b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
+                              & 0xBFFF);
+                b43_phy_write(dev, B43_PHY_OFDM(0xC3),
+                              b43_phy_read(dev, B43_PHY_OFDM(0xC3))
+                              & 0x7FFF);
+        }
+}
+
+/* Set the baseband attenuation value on chip. */
+void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
+                                      u16 baseband_attenuation)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->analog == 0) {
+                b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
+                                                 & 0xFFF0) |
+                            baseband_attenuation);
+        } else if (phy->analog > 1) {
+                b43_phy_write(dev, B43_PHY_DACCTL,
+                              (b43_phy_read(dev, B43_PHY_DACCTL)
+                               & 0xFFC3) | (baseband_attenuation << 2));
+        } else {
+                b43_phy_write(dev, B43_PHY_DACCTL,
+                              (b43_phy_read(dev, B43_PHY_DACCTL)
+                               & 0xFF87) | (baseband_attenuation << 3));
+        }
+}
+
+/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
+ * This function converts a TSSI value to dBm in Q5.2
+ */
+static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
+{
+        struct b43_phy *phy = &dev->phy;
+        s8 dbm = 0;
+        s32 tmp;
+
+        tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                tmp += 0x80;
+                tmp = limit_value(tmp, 0x00, 0xFF);
+                dbm = phy->tssi2dbm[tmp];
+                //TODO: There's a FIXME on the specs
+                break;
+        case B43_PHYTYPE_B:
+        case B43_PHYTYPE_G:
+                tmp = limit_value(tmp, 0x00, 0x3F);
+                dbm = phy->tssi2dbm[tmp];
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+
+        return dbm;
+}
+
+void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
+                                     int *_bbatt, int *_rfatt)
+{
+        int rfatt = *_rfatt;
+        int bbatt = *_bbatt;
+        struct b43_txpower_lo_control *lo = dev->phy.lo_control;
+
+        /* Get baseband and radio attenuation values into their permitted ranges.
+         * Radio attenuation affects power level 4 times as much as baseband. */
+
+        /* Range constants */
+        const int rf_min = lo->rfatt_list.min_val;
+        const int rf_max = lo->rfatt_list.max_val;
+        const int bb_min = lo->bbatt_list.min_val;
+        const int bb_max = lo->bbatt_list.max_val;
+
+        while (1) {
+                if (rfatt > rf_max && bbatt > bb_max - 4)
+                        break;  /* Can not get it into ranges */
+                if (rfatt < rf_min && bbatt < bb_min + 4)
+                        break;  /* Can not get it into ranges */
+                if (bbatt > bb_max && rfatt > rf_max - 1)
+                        break;  /* Can not get it into ranges */
+                if (bbatt < bb_min && rfatt < rf_min + 1)
+                        break;  /* Can not get it into ranges */
+
+                if (bbatt > bb_max) {
+                        bbatt -= 4;
+                        rfatt += 1;
+                        continue;
+                }
+                if (bbatt < bb_min) {
+                        bbatt += 4;
+                        rfatt -= 1;
+                        continue;
+                }
+                if (rfatt > rf_max) {
+                        rfatt -= 1;
+                        bbatt += 4;
+                        continue;
+                }
+                if (rfatt < rf_min) {
+                        rfatt += 1;
+                        bbatt -= 4;
+                        continue;
+                }
+                break;
+        }
+
+        *_rfatt = limit_value(rfatt, rf_min, rf_max);
+        *_bbatt = limit_value(bbatt, bb_min, bb_max);
+}
+
+/* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
+void b43_phy_xmitpower(struct b43_wldev *dev)
+{
+        struct ssb_bus *bus = dev->dev->bus;
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->cur_idle_tssi == 0)
+                return;
+        if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
+            (bus->boardinfo.type == SSB_BOARD_BU4306))
+                return;
+#ifdef CONFIG_B43_DEBUG
+        if (phy->manual_txpower_control)
+                return;
+#endif
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:{
+
+                        //TODO: Nothing for A PHYs yet :-/
+
+                        break;
+                }
+        case B43_PHYTYPE_B:
+        case B43_PHYTYPE_G:{
+                        u16 tmp;
+                        s8 v0, v1, v2, v3;
+                        s8 average;
+                        int max_pwr;
+                        int desired_pwr, estimated_pwr, pwr_adjust;
+                        int rfatt_delta, bbatt_delta;
+                        int rfatt, bbatt;
+                        u8 tx_control;
+                        unsigned long phylock_flags;
+
+                        tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
+                        v0 = (s8) (tmp & 0x00FF);
+                        v1 = (s8) ((tmp & 0xFF00) >> 8);
+                        tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
+                        v2 = (s8) (tmp & 0x00FF);
+                        v3 = (s8) ((tmp & 0xFF00) >> 8);
+                        tmp = 0;
+
+                        if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
+                            || v3 == 0x7F) {
+                                tmp =
+                                    b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
+                                v0 = (s8) (tmp & 0x00FF);
+                                v1 = (s8) ((tmp & 0xFF00) >> 8);
+                                tmp =
+                                    b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
+                                v2 = (s8) (tmp & 0x00FF);
+                                v3 = (s8) ((tmp & 0xFF00) >> 8);
+                                if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
+                                    || v3 == 0x7F)
+                                        return;
+                                v0 = (v0 + 0x20) & 0x3F;
+                                v1 = (v1 + 0x20) & 0x3F;
+                                v2 = (v2 + 0x20) & 0x3F;
+                                v3 = (v3 + 0x20) & 0x3F;
+                                tmp = 1;
+                        }
+                        b43_shm_clear_tssi(dev);
+
+                        average = (v0 + v1 + v2 + v3 + 2) / 4;
+
+                        if (tmp
+                            && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
+                                0x8))
+                                average -= 13;
+
+                        estimated_pwr =
+                            b43_phy_estimate_power_out(dev, average);
+
+                        max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
+                        if ((dev->dev->bus->sprom.r1.
+                             boardflags_lo & B43_BFL_PACTRL)
+                            && (phy->type == B43_PHYTYPE_G))
+                                max_pwr -= 0x3;
+                        if (unlikely(max_pwr <= 0)) {
+                                b43warn(dev->wl,
+                                        "Invalid max-TX-power value in SPROM.\n");
+                                max_pwr = 60;   /* fake it */
+                                dev->dev->bus->sprom.r1.maxpwr_bg = max_pwr;
+                        }
+
+                        /*TODO:
+                           max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
+                           where REG is the max power as per the regulatory domain
+                         */
+
+                        /* Get desired power (in Q5.2) */
+                        desired_pwr = INT_TO_Q52(phy->power_level);
+                        /* And limit it. max_pwr already is Q5.2 */
+                        desired_pwr = limit_value(desired_pwr, 0, max_pwr);
+                        if (b43_debug(dev, B43_DBG_XMITPOWER)) {
+                                b43dbg(dev->wl,
+                                       "Current TX power output: " Q52_FMT
+                                       " dBm, " "Desired TX power output: "
+                                       Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
+                                       Q52_ARG(desired_pwr));
+                        }
+
+                        /* Calculate the adjustment delta. */
+                        pwr_adjust = desired_pwr - estimated_pwr;
+
+                        /* RF attenuation delta. */
+                        rfatt_delta = ((pwr_adjust + 7) / 8);
+                        /* Lower attenuation => Bigger power output. Negate it. */
+                        rfatt_delta = -rfatt_delta;
+
+                        /* Baseband attenuation delta. */
+                        bbatt_delta = pwr_adjust / 2;
+                        /* Lower attenuation => Bigger power output. Negate it. */
+                        bbatt_delta = -bbatt_delta;
+                        /* RF att affects power level 4 times as much as
+                         * Baseband attennuation. Subtract it. */
+                        bbatt_delta -= 4 * rfatt_delta;
+
+                        /* So do we finally need to adjust something? */
+                        if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
+                                b43_lo_g_ctl_mark_cur_used(dev);
+                                return;
+                        }
+
+                        /* Calculate the new attenuation values. */
+                        bbatt = phy->bbatt.att;
+                        bbatt += bbatt_delta;
+                        rfatt = phy->rfatt.att;
+                        rfatt += rfatt_delta;
+
+                        b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
+                        tx_control = phy->tx_control;
+                        if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
+                                if (rfatt <= 1) {
+                                        if (tx_control == 0) {
+                                                tx_control =
+                                                    B43_TXCTL_PA2DB |
+                                                    B43_TXCTL_TXMIX;
+                                                rfatt += 2;
+                                                bbatt += 2;
+                                        } else if (dev->dev->bus->sprom.r1.
+                                                   boardflags_lo &
+                                                   B43_BFL_PACTRL) {
+                                                bbatt += 4 * (rfatt - 2);
+                                                rfatt = 2;
+                                        }
+                                } else if (rfatt > 4 && tx_control) {
+                                        tx_control = 0;
+                                        if (bbatt < 3) {
+                                                rfatt -= 3;
+                                                bbatt += 2;
+                                        } else {
+                                                rfatt -= 2;
+                                                bbatt -= 2;
+                                        }
+                                }
+                        }
+                        /* Save the control values */
+                        phy->tx_control = tx_control;
+                        b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
+                        phy->rfatt.att = rfatt;
+                        phy->bbatt.att = bbatt;
+
+                        /* Adjust the hardware */
+                        b43_phy_lock(dev, phylock_flags);
+                        b43_radio_lock(dev);
+                        b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
+                                          phy->tx_control);
+                        b43_lo_g_ctl_mark_cur_used(dev);
+                        b43_radio_unlock(dev);
+                        b43_phy_unlock(dev, phylock_flags);
+                        break;
+                }
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
+{
+        if (num < 0)
+                return num / den;
+        else
+                return (num + den / 2) / den;
+}
+
+static inline
+    s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
+{
+        s32 m1, m2, f = 256, q, delta;
+        s8 i = 0;
+
+        m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
+        m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
+        do {
+                if (i > 15)
+                        return -EINVAL;
+                q = b43_tssi2dbm_ad(f * 4096 -
+                                    b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
+                delta = abs(q - f);
+                f = q;
+                i++;
+        } while (delta >= 2);
+        entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
+        return 0;
+}
+
+/* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
+int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        s16 pab0, pab1, pab2;
+        u8 idx;
+        s8 *dyn_tssi2dbm;
+
+        if (phy->type == B43_PHYTYPE_A) {
+                pab0 = (s16) (dev->dev->bus->sprom.r1.pa1b0);
+                pab1 = (s16) (dev->dev->bus->sprom.r1.pa1b1);
+                pab2 = (s16) (dev->dev->bus->sprom.r1.pa1b2);
+        } else {
+                pab0 = (s16) (dev->dev->bus->sprom.r1.pa0b0);
+                pab1 = (s16) (dev->dev->bus->sprom.r1.pa0b1);
+                pab2 = (s16) (dev->dev->bus->sprom.r1.pa0b2);
+        }
+
+        if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
+                phy->tgt_idle_tssi = 0x34;
+                phy->tssi2dbm = b43_tssi2dbm_b_table;
+                return 0;
+        }
+
+        if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
+            pab0 != -1 && pab1 != -1 && pab2 != -1) {
+                /* The pabX values are set in SPROM. Use them. */
+                if (phy->type == B43_PHYTYPE_A) {
+                        if ((s8) dev->dev->bus->sprom.r1.itssi_a != 0 &&
+                            (s8) dev->dev->bus->sprom.r1.itssi_a != -1)
+                                phy->tgt_idle_tssi =
+                                    (s8) (dev->dev->bus->sprom.r1.itssi_a);
+                        else
+                                phy->tgt_idle_tssi = 62;
+                } else {
+                        if ((s8) dev->dev->bus->sprom.r1.itssi_bg != 0 &&
+                            (s8) dev->dev->bus->sprom.r1.itssi_bg != -1)
+                                phy->tgt_idle_tssi =
+                                    (s8) (dev->dev->bus->sprom.r1.itssi_bg);
+                        else
+                                phy->tgt_idle_tssi = 62;
+                }
+                dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
+                if (dyn_tssi2dbm == NULL) {
+                        b43err(dev->wl, "Could not allocate memory"
+                               "for tssi2dbm table\n");
+                        return -ENOMEM;
+                }
+                for (idx = 0; idx < 64; idx++)
+                        if (b43_tssi2dbm_entry
+                            (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
+                                phy->tssi2dbm = NULL;
+                                b43err(dev->wl, "Could not generate "
+                                       "tssi2dBm table\n");
+                                kfree(dyn_tssi2dbm);
+                                return -ENODEV;
+                        }
+                phy->tssi2dbm = dyn_tssi2dbm;
+                phy->dyn_tssi_tbl = 1;
+        } else {
+                /* pabX values not set in SPROM. */
+                switch (phy->type) {
+                case B43_PHYTYPE_A:
+                        /* APHY needs a generated table. */
+                        phy->tssi2dbm = NULL;
+                        b43err(dev->wl, "Could not generate tssi2dBm "
+                               "table (wrong SPROM info)!\n");
+                        return -ENODEV;
+                case B43_PHYTYPE_B:
+                        phy->tgt_idle_tssi = 0x34;
+                        phy->tssi2dbm = b43_tssi2dbm_b_table;
+                        break;
+                case B43_PHYTYPE_G:
+                        phy->tgt_idle_tssi = 0x34;
+                        phy->tssi2dbm = b43_tssi2dbm_g_table;
+                        break;
+                }
+        }
+
+        return 0;
+}
+
+int b43_phy_init(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        int err = -ENODEV;
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                if (phy->rev == 2 || phy->rev == 3) {
+                        b43_phy_inita(dev);
+                        err = 0;
+                }
+                break;
+        case B43_PHYTYPE_B:
+                switch (phy->rev) {
+                case 2:
+                        b43_phy_initb2(dev);
+                        err = 0;
+                        break;
+                case 4:
+                        b43_phy_initb4(dev);
+                        err = 0;
+                        break;
+                case 5:
+                        b43_phy_initb5(dev);
+                        err = 0;
+                        break;
+                case 6:
+                        b43_phy_initb6(dev);
+                        err = 0;
+                        break;
+                }
+                break;
+        case B43_PHYTYPE_G:
+                b43_phy_initg(dev);
+                err = 0;
+                break;
+        }
+        if (err)
+                b43err(dev->wl, "Unknown PHYTYPE found\n");
+
+        return err;
+}
+
+void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
+{
+        struct b43_phy *phy = &dev->phy;
+        u32 hf;
+        u16 tmp;
+        int autodiv = 0;
+
+        if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
+                autodiv = 1;
+
+        hf = b43_hf_read(dev);
+        hf &= ~B43_HF_ANTDIVHELP;
+        b43_hf_write(dev, hf);
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+        case B43_PHYTYPE_G:
+                tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
+                tmp &= ~B43_PHY_BBANDCFG_RXANT;
+                tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
+                    << B43_PHY_BBANDCFG_RXANT_SHIFT;
+                b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
+
+                if (autodiv) {
+                        tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
+                        if (antenna == B43_ANTENNA_AUTO0)
+                                tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
+                        else
+                                tmp |= B43_PHY_ANTDWELL_AUTODIV1;
+                        b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
+                }
+                if (phy->type == B43_PHYTYPE_G) {
+                        tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
+                        if (autodiv)
+                                tmp |= B43_PHY_ANTWRSETT_ARXDIV;
+                        else
+                                tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
+                        b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
+                        if (phy->rev >= 2) {
+                                tmp = b43_phy_read(dev, B43_PHY_OFDM61);
+                                tmp |= B43_PHY_OFDM61_10;
+                                b43_phy_write(dev, B43_PHY_OFDM61, tmp);
+
+                                tmp =
+                                    b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
+                                tmp = (tmp & 0xFF00) | 0x15;
+                                b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
+                                              tmp);
+
+                                if (phy->rev == 2) {
+                                        b43_phy_write(dev, B43_PHY_ADIVRELATED,
+                                                      8);
+                                } else {
+                                        tmp =
+                                            b43_phy_read(dev,
+                                                         B43_PHY_ADIVRELATED);
+                                        tmp = (tmp & 0xFF00) | 8;
+                                        b43_phy_write(dev, B43_PHY_ADIVRELATED,
+                                                      tmp);
+                                }
+                        }
+                        if (phy->rev >= 6)
+                                b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
+                } else {
+                        if (phy->rev < 3) {
+                                tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
+                                tmp = (tmp & 0xFF00) | 0x24;
+                                b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
+                        } else {
+                                tmp = b43_phy_read(dev, B43_PHY_OFDM61);
+                                tmp |= 0x10;
+                                b43_phy_write(dev, B43_PHY_OFDM61, tmp);
+                                if (phy->analog == 3) {
+                                        b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
+                                                      0x1D);
+                                        b43_phy_write(dev, B43_PHY_ADIVRELATED,
+                                                      8);
+                                } else {
+                                        b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
+                                                      0x3A);
+                                        tmp =
+                                            b43_phy_read(dev,
+                                                         B43_PHY_ADIVRELATED);
+                                        tmp = (tmp & 0xFF00) | 8;
+                                        b43_phy_write(dev, B43_PHY_ADIVRELATED,
+                                                      tmp);
+                                }
+                        }
+                }
+                break;
+        case B43_PHYTYPE_B:
+                tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
+                tmp &= ~B43_PHY_BBANDCFG_RXANT;
+                tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
+                    << B43_PHY_BBANDCFG_RXANT_SHIFT;
+                b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+
+        hf |= B43_HF_ANTDIVHELP;
+        b43_hf_write(dev, hf);
+}
+
+/* Get the freq, as it has to be written to the device. */
+static inline u16 channel2freq_bg(u8 channel)
+{
+        B43_WARN_ON(!(channel >= 1 && channel <= 14));
+
+        return b43_radio_channel_codes_bg[channel - 1];
+}
+
+/* Get the freq, as it has to be written to the device. */
+static inline u16 channel2freq_a(u8 channel)
+{
+        B43_WARN_ON(channel > 200);
+
+        return (5000 + 5 * channel);
+}
+
+void b43_radio_lock(struct b43_wldev *dev)
+{
+        u32 macctl;
+
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        macctl |= B43_MACCTL_RADIOLOCK;
+        b43_write32(dev, B43_MMIO_MACCTL, macctl);
+        /* Commit the write and wait for the device
+         * to exit any radio register access. */
+        b43_read32(dev, B43_MMIO_MACCTL);
+        udelay(10);
+}
+
+void b43_radio_unlock(struct b43_wldev *dev)
+{
+        u32 macctl;
+
+        /* Commit any write */
+        b43_read16(dev, B43_MMIO_PHY_VER);
+        /* unlock */
+        macctl = b43_read32(dev, B43_MMIO_MACCTL);
+        macctl &= ~B43_MACCTL_RADIOLOCK;
+        b43_write32(dev, B43_MMIO_MACCTL, macctl);
+}
+
+u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                offset |= 0x0040;
+                break;
+        case B43_PHYTYPE_B:
+                if (phy->radio_ver == 0x2053) {
+                        if (offset < 0x70)
+                                offset += 0x80;
+                        else if (offset < 0x80)
+                                offset += 0x70;
+                } else if (phy->radio_ver == 0x2050) {
+                        offset |= 0x80;
+                } else
+                        B43_WARN_ON(1);
+                break;
+        case B43_PHYTYPE_G:
+                offset |= 0x80;
+                break;
+        }
+
+        b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
+        return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
+}
+
+void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
+{
+        b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
+        mmiowb();
+        b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
+}
+
+static void b43_set_all_gains(struct b43_wldev *dev,
+                              s16 first, s16 second, s16 third)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 i;
+        u16 start = 0x08, end = 0x18;
+        u16 tmp;
+        u16 table;
+
+        if (phy->rev <= 1) {
+                start = 0x10;
+                end = 0x20;
+        }
+
+        table = B43_OFDMTAB_GAINX;
+        if (phy->rev <= 1)
+                table = B43_OFDMTAB_GAINX_R1;
+        for (i = 0; i < 4; i++)
+                b43_ofdmtab_write16(dev, table, i, first);
+
+        for (i = start; i < end; i++)
+                b43_ofdmtab_write16(dev, table, i, second);
+
+        if (third != -1) {
+                tmp = ((u16) third << 14) | ((u16) third << 6);
+                b43_phy_write(dev, 0x04A0,
+                              (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
+                b43_phy_write(dev, 0x04A1,
+                              (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
+                b43_phy_write(dev, 0x04A2,
+                              (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
+        }
+        b43_dummy_transmission(dev);
+}
+
+static void b43_set_original_gains(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 i, tmp;
+        u16 table;
+        u16 start = 0x0008, end = 0x0018;
+
+        if (phy->rev <= 1) {
+                start = 0x0010;
+                end = 0x0020;
+        }
+
+        table = B43_OFDMTAB_GAINX;
+        if (phy->rev <= 1)
+                table = B43_OFDMTAB_GAINX_R1;
+        for (i = 0; i < 4; i++) {
+                tmp = (i & 0xFFFC);
+                tmp |= (i & 0x0001) << 1;
+                tmp |= (i & 0x0002) >> 1;
+
+                b43_ofdmtab_write16(dev, table, i, tmp);
+        }
+
+        for (i = start; i < end; i++)
+                b43_ofdmtab_write16(dev, table, i, i - start);
+
+        b43_phy_write(dev, 0x04A0,
+                      (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
+        b43_phy_write(dev, 0x04A1,
+                      (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
+        b43_phy_write(dev, 0x04A2,
+                      (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
+        b43_dummy_transmission(dev);
+}
+
+/* Synthetic PU workaround */
+static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        might_sleep();
+
+        if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
+                /* We do not need the workaround. */
+                return;
+        }
+
+        if (channel <= 10) {
+                b43_write16(dev, B43_MMIO_CHANNEL,
+                            channel2freq_bg(channel + 4));
+        } else {
+                b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
+        }
+        msleep(1);
+        b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
+}
+
+u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
+{
+        struct b43_phy *phy = &dev->phy;
+        u8 ret = 0;
+        u16 saved, rssi, temp;
+        int i, j = 0;
+
+        saved = b43_phy_read(dev, 0x0403);
+        b43_radio_selectchannel(dev, channel, 0);
+        b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
+        if (phy->aci_hw_rssi)
+                rssi = b43_phy_read(dev, 0x048A) & 0x3F;
+        else
+                rssi = saved & 0x3F;
+        /* clamp temp to signed 5bit */
+        if (rssi > 32)
+                rssi -= 64;
+        for (i = 0; i < 100; i++) {
+                temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
+                if (temp > 32)
+                        temp -= 64;
+                if (temp < rssi)
+                        j++;
+                if (j >= 20)
+                        ret = 1;
+        }
+        b43_phy_write(dev, 0x0403, saved);
+
+        return ret;
+}
+
+u8 b43_radio_aci_scan(struct b43_wldev * dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u8 ret[13];
+        unsigned int channel = phy->channel;
+        unsigned int i, j, start, end;
+        unsigned long phylock_flags;
+
+        if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
+                return 0;
+
+        b43_phy_lock(dev, phylock_flags);
+        b43_radio_lock(dev);
+        b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
+        b43_phy_write(dev, B43_PHY_G_CRS,
+                      b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
+        b43_set_all_gains(dev, 3, 8, 1);
+
+        start = (channel - 5 > 0) ? channel - 5 : 1;
+        end = (channel + 5 < 14) ? channel + 5 : 13;
+
+        for (i = start; i <= end; i++) {
+                if (abs(channel - i) > 2)
+                        ret[i - 1] = b43_radio_aci_detect(dev, i);
+        }
+        b43_radio_selectchannel(dev, channel, 0);
+        b43_phy_write(dev, 0x0802,
+                      (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
+        b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
+        b43_phy_write(dev, B43_PHY_G_CRS,
+                      b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
+        b43_set_original_gains(dev);
+        for (i = 0; i < 13; i++) {
+                if (!ret[i])
+                        continue;
+                end = (i + 5 < 13) ? i + 5 : 13;
+                for (j = i; j < end; j++)
+                        ret[j] = 1;
+        }
+        b43_radio_unlock(dev);
+        b43_phy_unlock(dev, phylock_flags);
+
+        return ret[channel - 1];
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
+{
+        b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
+        mmiowb();
+        b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
+{
+        u16 val;
+
+        b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
+        val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
+
+        return (s16) val;
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
+{
+        u16 i;
+        s16 tmp;
+
+        for (i = 0; i < 64; i++) {
+                tmp = b43_nrssi_hw_read(dev, i);
+                tmp -= val;
+                tmp = limit_value(tmp, -32, 31);
+                b43_nrssi_hw_write(dev, i, tmp);
+        }
+}
+
+/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
+void b43_nrssi_mem_update(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        s16 i, delta;
+        s32 tmp;
+
+        delta = 0x1F - phy->nrssi[0];
+        for (i = 0; i < 64; i++) {
+                tmp = (i - delta) * phy->nrssislope;
+                tmp /= 0x10000;
+                tmp += 0x3A;
+                tmp = limit_value(tmp, 0, 0x3F);
+                phy->nrssi_lt[i] = tmp;
+        }
+}
+
+static void b43_calc_nrssi_offset(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 backup[20] = { 0 };
+        s16 v47F;
+        u16 i;
+        u16 saved = 0xFFFF;
+
+        backup[0] = b43_phy_read(dev, 0x0001);
+        backup[1] = b43_phy_read(dev, 0x0811);
+        backup[2] = b43_phy_read(dev, 0x0812);
+        if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                backup[3] = b43_phy_read(dev, 0x0814);
+                backup[4] = b43_phy_read(dev, 0x0815);
+        }
+        backup[5] = b43_phy_read(dev, 0x005A);
+        backup[6] = b43_phy_read(dev, 0x0059);
+        backup[7] = b43_phy_read(dev, 0x0058);
+        backup[8] = b43_phy_read(dev, 0x000A);
+        backup[9] = b43_phy_read(dev, 0x0003);
+        backup[10] = b43_radio_read16(dev, 0x007A);
+        backup[11] = b43_radio_read16(dev, 0x0043);
+
+        b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
+        b43_phy_write(dev, 0x0001,
+                      (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
+        b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
+        b43_phy_write(dev, 0x0812,
+                      (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
+        b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
+        if (phy->rev >= 6) {
+                backup[12] = b43_phy_read(dev, 0x002E);
+                backup[13] = b43_phy_read(dev, 0x002F);
+                backup[14] = b43_phy_read(dev, 0x080F);
+                backup[15] = b43_phy_read(dev, 0x0810);
+                backup[16] = b43_phy_read(dev, 0x0801);
+                backup[17] = b43_phy_read(dev, 0x0060);
+                backup[18] = b43_phy_read(dev, 0x0014);
+                backup[19] = b43_phy_read(dev, 0x0478);
+
+                b43_phy_write(dev, 0x002E, 0);
+                b43_phy_write(dev, 0x002F, 0);
+                b43_phy_write(dev, 0x080F, 0);
+                b43_phy_write(dev, 0x0810, 0);
+                b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
+                b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
+                b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
+                b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
+        }
+        b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
+        b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
+        udelay(30);
+
+        v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+        if (v47F >= 0x20)
+                v47F -= 0x40;
+        if (v47F == 31) {
+                for (i = 7; i >= 4; i--) {
+                        b43_radio_write16(dev, 0x007B, i);
+                        udelay(20);
+                        v47F =
+                            (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+                        if (v47F >= 0x20)
+                                v47F -= 0x40;
+                        if (v47F < 31 && saved == 0xFFFF)
+                                saved = i;
+                }
+                if (saved == 0xFFFF)
+                        saved = 4;
+        } else {
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) & 0x007F);
+                if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                        b43_phy_write(dev, 0x0814,
+                                      b43_phy_read(dev, 0x0814) | 0x0001);
+                        b43_phy_write(dev, 0x0815,
+                                      b43_phy_read(dev, 0x0815) & 0xFFFE);
+                }
+                b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
+                b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
+                b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
+                b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
+                b43_phy_write(dev, 0x005A, 0x0480);
+                b43_phy_write(dev, 0x0059, 0x0810);
+                b43_phy_write(dev, 0x0058, 0x000D);
+                if (phy->rev == 0) {
+                        b43_phy_write(dev, 0x0003, 0x0122);
+                } else {
+                        b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
+                                      | 0x2000);
+                }
+                if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                        b43_phy_write(dev, 0x0814,
+                                      b43_phy_read(dev, 0x0814) | 0x0004);
+                        b43_phy_write(dev, 0x0815,
+                                      b43_phy_read(dev, 0x0815) & 0xFFFB);
+                }
+                b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
+                              | 0x0040);
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) | 0x000F);
+                b43_set_all_gains(dev, 3, 0, 1);
+                b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
+                                                & 0x00F0) | 0x000F);
+                udelay(30);
+                v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+                if (v47F >= 0x20)
+                        v47F -= 0x40;
+                if (v47F == -32) {
+                        for (i = 0; i < 4; i++) {
+                                b43_radio_write16(dev, 0x007B, i);
+                                udelay(20);
+                                v47F =
+                                    (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
+                                           0x003F);
+                                if (v47F >= 0x20)
+                                        v47F -= 0x40;
+                                if (v47F > -31 && saved == 0xFFFF)
+                                        saved = i;
+                        }
+                        if (saved == 0xFFFF)
+                                saved = 3;
+                } else
+                        saved = 0;
+        }
+        b43_radio_write16(dev, 0x007B, saved);
+
+        if (phy->rev >= 6) {
+                b43_phy_write(dev, 0x002E, backup[12]);
+                b43_phy_write(dev, 0x002F, backup[13]);
+                b43_phy_write(dev, 0x080F, backup[14]);
+                b43_phy_write(dev, 0x0810, backup[15]);
+        }
+        if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
+                b43_phy_write(dev, 0x0814, backup[3]);
+                b43_phy_write(dev, 0x0815, backup[4]);
+        }
+        b43_phy_write(dev, 0x005A, backup[5]);
+        b43_phy_write(dev, 0x0059, backup[6]);
+        b43_phy_write(dev, 0x0058, backup[7]);
+        b43_phy_write(dev, 0x000A, backup[8]);
+        b43_phy_write(dev, 0x0003, backup[9]);
+        b43_radio_write16(dev, 0x0043, backup[11]);
+        b43_radio_write16(dev, 0x007A, backup[10]);
+        b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
+        b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
+        b43_set_original_gains(dev);
+        if (phy->rev >= 6) {
+                b43_phy_write(dev, 0x0801, backup[16]);
+                b43_phy_write(dev, 0x0060, backup[17]);
+                b43_phy_write(dev, 0x0014, backup[18]);
+                b43_phy_write(dev, 0x0478, backup[19]);
+        }
+        b43_phy_write(dev, 0x0001, backup[0]);
+        b43_phy_write(dev, 0x0812, backup[2]);
+        b43_phy_write(dev, 0x0811, backup[1]);
+}
+
+void b43_calc_nrssi_slope(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 backup[18] = { 0 };
+        u16 tmp;
+        s16 nrssi0, nrssi1;
+
+        switch (phy->type) {
+        case B43_PHYTYPE_B:
+                backup[0] = b43_radio_read16(dev, 0x007A);
+                backup[1] = b43_radio_read16(dev, 0x0052);
+                backup[2] = b43_radio_read16(dev, 0x0043);
+                backup[3] = b43_phy_read(dev, 0x0030);
+                backup[4] = b43_phy_read(dev, 0x0026);
+                backup[5] = b43_phy_read(dev, 0x0015);
+                backup[6] = b43_phy_read(dev, 0x002A);
+                backup[7] = b43_phy_read(dev, 0x0020);
+                backup[8] = b43_phy_read(dev, 0x005A);
+                backup[9] = b43_phy_read(dev, 0x0059);
+                backup[10] = b43_phy_read(dev, 0x0058);
+                backup[11] = b43_read16(dev, 0x03E2);
+                backup[12] = b43_read16(dev, 0x03E6);
+                backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
+
+                tmp = b43_radio_read16(dev, 0x007A);
+                tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
+                b43_radio_write16(dev, 0x007A, tmp);
+                b43_phy_write(dev, 0x0030, 0x00FF);
+                b43_write16(dev, 0x03EC, 0x7F7F);
+                b43_phy_write(dev, 0x0026, 0x0000);
+                b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
+                b43_phy_write(dev, 0x002A, 0x08A3);
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) | 0x0080);
+
+                nrssi0 = (s16) b43_phy_read(dev, 0x0027);
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) & 0x007F);
+                if (phy->rev >= 2) {
+                        b43_write16(dev, 0x03E6, 0x0040);
+                } else if (phy->rev == 0) {
+                        b43_write16(dev, 0x03E6, 0x0122);
+                } else {
+                        b43_write16(dev, B43_MMIO_CHANNEL_EXT,
+                                    b43_read16(dev,
+                                               B43_MMIO_CHANNEL_EXT) & 0x2000);
+                }
+                b43_phy_write(dev, 0x0020, 0x3F3F);
+                b43_phy_write(dev, 0x0015, 0xF330);
+                b43_radio_write16(dev, 0x005A, 0x0060);
+                b43_radio_write16(dev, 0x0043,
+                                  b43_radio_read16(dev, 0x0043) & 0x00F0);
+                b43_phy_write(dev, 0x005A, 0x0480);
+                b43_phy_write(dev, 0x0059, 0x0810);
+                b43_phy_write(dev, 0x0058, 0x000D);
+                udelay(20);
+
+                nrssi1 = (s16) b43_phy_read(dev, 0x0027);
+                b43_phy_write(dev, 0x0030, backup[3]);
+                b43_radio_write16(dev, 0x007A, backup[0]);
+                b43_write16(dev, 0x03E2, backup[11]);
+                b43_phy_write(dev, 0x0026, backup[4]);
+                b43_phy_write(dev, 0x0015, backup[5]);
+                b43_phy_write(dev, 0x002A, backup[6]);
+                b43_synth_pu_workaround(dev, phy->channel);
+                if (phy->rev != 0)
+                        b43_write16(dev, 0x03F4, backup[13]);
+
+                b43_phy_write(dev, 0x0020, backup[7]);
+                b43_phy_write(dev, 0x005A, backup[8]);
+                b43_phy_write(dev, 0x0059, backup[9]);
+                b43_phy_write(dev, 0x0058, backup[10]);
+                b43_radio_write16(dev, 0x0052, backup[1]);
+                b43_radio_write16(dev, 0x0043, backup[2]);
+
+                if (nrssi0 == nrssi1)
+                        phy->nrssislope = 0x00010000;
+                else
+                        phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
+
+                if (nrssi0 <= -4) {
+                        phy->nrssi[0] = nrssi0;
+                        phy->nrssi[1] = nrssi1;
+                }
+                break;
+        case B43_PHYTYPE_G:
+                if (phy->radio_rev >= 9)
+                        return;
+                if (phy->radio_rev == 8)
+                        b43_calc_nrssi_offset(dev);
+
+                b43_phy_write(dev, B43_PHY_G_CRS,
+                              b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
+                b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
+                backup[7] = b43_read16(dev, 0x03E2);
+                b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
+                backup[0] = b43_radio_read16(dev, 0x007A);
+                backup[1] = b43_radio_read16(dev, 0x0052);
+                backup[2] = b43_radio_read16(dev, 0x0043);
+                backup[3] = b43_phy_read(dev, 0x0015);
+                backup[4] = b43_phy_read(dev, 0x005A);
+                backup[5] = b43_phy_read(dev, 0x0059);
+                backup[6] = b43_phy_read(dev, 0x0058);
+                backup[8] = b43_read16(dev, 0x03E6);
+                backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
+                if (phy->rev >= 3) {
+                        backup[10] = b43_phy_read(dev, 0x002E);
+                        backup[11] = b43_phy_read(dev, 0x002F);
+                        backup[12] = b43_phy_read(dev, 0x080F);
+                        backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
+                        backup[14] = b43_phy_read(dev, 0x0801);
+                        backup[15] = b43_phy_read(dev, 0x0060);
+                        backup[16] = b43_phy_read(dev, 0x0014);
+                        backup[17] = b43_phy_read(dev, 0x0478);
+                        b43_phy_write(dev, 0x002E, 0);
+                        b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
+                        switch (phy->rev) {
+                        case 4:
+                        case 6:
+                        case 7:
+                                b43_phy_write(dev, 0x0478,
+                                              b43_phy_read(dev, 0x0478)
+                                              | 0x0100);
+                                b43_phy_write(dev, 0x0801,
+                                              b43_phy_read(dev, 0x0801)
+                                              | 0x0040);
+                                break;
+                        case 3:
+                        case 5:
+                                b43_phy_write(dev, 0x0801,
+                                              b43_phy_read(dev, 0x0801)
+                                              & 0xFFBF);
+                                break;
+                        }
+                        b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
+                                      | 0x0040);
+                        b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
+                                      | 0x0200);
+                }
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) | 0x0070);
+                b43_set_all_gains(dev, 0, 8, 0);
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) & 0x00F7);
+                if (phy->rev >= 2) {
+                        b43_phy_write(dev, 0x0811,
+                                      (b43_phy_read(dev, 0x0811) & 0xFFCF) |
+                                      0x0030);
+                        b43_phy_write(dev, 0x0812,
+                                      (b43_phy_read(dev, 0x0812) & 0xFFCF) |
+                                      0x0010);
+                }
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) | 0x0080);
+                udelay(20);
+
+                nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+                if (nrssi0 >= 0x0020)
+                        nrssi0 -= 0x0040;
+
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) & 0x007F);
+                if (phy->rev >= 2) {
+                        b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
+                                                    & 0xFF9F) | 0x0040);
+                }
+
+                b43_write16(dev, B43_MMIO_CHANNEL_EXT,
+                            b43_read16(dev, B43_MMIO_CHANNEL_EXT)
+                            | 0x2000);
+                b43_radio_write16(dev, 0x007A,
+                                  b43_radio_read16(dev, 0x007A) | 0x000F);
+                b43_phy_write(dev, 0x0015, 0xF330);
+                if (phy->rev >= 2) {
+                        b43_phy_write(dev, 0x0812,
+                                      (b43_phy_read(dev, 0x0812) & 0xFFCF) |
+                                      0x0020);
+                        b43_phy_write(dev, 0x0811,
+                                      (b43_phy_read(dev, 0x0811) & 0xFFCF) |
+                                      0x0020);
+                }
+
+                b43_set_all_gains(dev, 3, 0, 1);
+                if (phy->radio_rev == 8) {
+                        b43_radio_write16(dev, 0x0043, 0x001F);
+                } else {
+                        tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
+                        b43_radio_write16(dev, 0x0052, tmp | 0x0060);
+                        tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
+                        b43_radio_write16(dev, 0x0043, tmp | 0x0009);
+                }
+                b43_phy_write(dev, 0x005A, 0x0480);
+                b43_phy_write(dev, 0x0059, 0x0810);
+                b43_phy_write(dev, 0x0058, 0x000D);
+                udelay(20);
+                nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
+                if (nrssi1 >= 0x0020)
+                        nrssi1 -= 0x0040;
+                if (nrssi0 == nrssi1)
+                        phy->nrssislope = 0x00010000;
+                else
+                        phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
+                if (nrssi0 >= -4) {
+                        phy->nrssi[0] = nrssi1;
+                        phy->nrssi[1] = nrssi0;
+                }
+                if (phy->rev >= 3) {
+                        b43_phy_write(dev, 0x002E, backup[10]);
+                        b43_phy_write(dev, 0x002F, backup[11]);
+                        b43_phy_write(dev, 0x080F, backup[12]);
+                        b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
+                }
+                if (phy->rev >= 2) {
+                        b43_phy_write(dev, 0x0812,
+                                      b43_phy_read(dev, 0x0812) & 0xFFCF);
+                        b43_phy_write(dev, 0x0811,
+                                      b43_phy_read(dev, 0x0811) & 0xFFCF);
+                }
+
+                b43_radio_write16(dev, 0x007A, backup[0]);
+                b43_radio_write16(dev, 0x0052, backup[1]);
+                b43_radio_write16(dev, 0x0043, backup[2]);
+                b43_write16(dev, 0x03E2, backup[7]);
+                b43_write16(dev, 0x03E6, backup[8]);
+                b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
+                b43_phy_write(dev, 0x0015, backup[3]);
+                b43_phy_write(dev, 0x005A, backup[4]);
+                b43_phy_write(dev, 0x0059, backup[5]);
+                b43_phy_write(dev, 0x0058, backup[6]);
+                b43_synth_pu_workaround(dev, phy->channel);
+                b43_phy_write(dev, 0x0802,
+                              b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
+                b43_set_original_gains(dev);
+                b43_phy_write(dev, B43_PHY_G_CRS,
+                              b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
+                if (phy->rev >= 3) {
+                        b43_phy_write(dev, 0x0801, backup[14]);
+                        b43_phy_write(dev, 0x0060, backup[15]);
+                        b43_phy_write(dev, 0x0014, backup[16]);
+                        b43_phy_write(dev, 0x0478, backup[17]);
+                }
+                b43_nrssi_mem_update(dev);
+                b43_calc_nrssi_threshold(dev);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+void b43_calc_nrssi_threshold(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        s32 threshold;
+        s32 a, b;
+        s16 tmp16;
+        u16 tmp_u16;
+
+        switch (phy->type) {
+        case B43_PHYTYPE_B:{
+                        if (phy->radio_ver != 0x2050)
+                                return;
+                        if (!
+                            (dev->dev->bus->sprom.r1.
+                             boardflags_lo & B43_BFL_RSSI))
+                                return;
+
+                        if (phy->radio_rev >= 6) {
+                                threshold =
+                                    (phy->nrssi[1] - phy->nrssi[0]) * 32;
+                                threshold += 20 * (phy->nrssi[0] + 1);
+                                threshold /= 40;
+                        } else
+                                threshold = phy->nrssi[1] - 5;
+
+                        threshold = limit_value(threshold, 0, 0x3E);
+                        b43_phy_read(dev, 0x0020);      /* dummy read */
+                        b43_phy_write(dev, 0x0020,
+                                      (((u16) threshold) << 8) | 0x001C);
+
+                        if (phy->radio_rev >= 6) {
+                                b43_phy_write(dev, 0x0087, 0x0E0D);
+                                b43_phy_write(dev, 0x0086, 0x0C0B);
+                                b43_phy_write(dev, 0x0085, 0x0A09);
+                                b43_phy_write(dev, 0x0084, 0x0808);
+                                b43_phy_write(dev, 0x0083, 0x0808);
+                                b43_phy_write(dev, 0x0082, 0x0604);
+                                b43_phy_write(dev, 0x0081, 0x0302);
+                                b43_phy_write(dev, 0x0080, 0x0100);
+                        }
+                        break;
+                }
+        case B43_PHYTYPE_G:
+                if (!phy->gmode ||
+                    !(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
+                        tmp16 = b43_nrssi_hw_read(dev, 0x20);
+                        if (tmp16 >= 0x20)
+                                tmp16 -= 0x40;
+                        if (tmp16 < 3) {
+                                b43_phy_write(dev, 0x048A,
+                                              (b43_phy_read(dev, 0x048A)
+                                               & 0xF000) | 0x09EB);
+                        } else {
+                                b43_phy_write(dev, 0x048A,
+                                              (b43_phy_read(dev, 0x048A)
+                                               & 0xF000) | 0x0AED);
+                        }
+                } else {
+                        if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
+                                a = 0xE;
+                                b = 0xA;
+                        } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
+                                a = 0x13;
+                                b = 0x12;
+                        } else {
+                                a = 0xE;
+                                b = 0x11;
+                        }
+
+                        a = a * (phy->nrssi[1] - phy->nrssi[0]);
+                        a += (phy->nrssi[0] << 6);
+                        if (a < 32)
+                                a += 31;
+                        else
+                                a += 32;
+                        a = a >> 6;
+                        a = limit_value(a, -31, 31);
+
+                        b = b * (phy->nrssi[1] - phy->nrssi[0]);
+                        b += (phy->nrssi[0] << 6);
+                        if (b < 32)
+                                b += 31;
+                        else
+                                b += 32;
+                        b = b >> 6;
+                        b = limit_value(b, -31, 31);
+
+                        tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
+                        tmp_u16 |= ((u32) b & 0x0000003F);
+                        tmp_u16 |= (((u32) a & 0x0000003F) << 6);
+                        b43_phy_write(dev, 0x048A, tmp_u16);
+                }
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+/* Stack implementation to save/restore values from the
+ * interference mitigation code.
+ * It is save to restore values in random order.
+ */
+static void _stack_save(u32 * _stackptr, size_t * stackidx,
+                        u8 id, u16 offset, u16 value)
+{
+        u32 *stackptr = &(_stackptr[*stackidx]);
+
+        B43_WARN_ON(offset & 0xF000);
+        B43_WARN_ON(id & 0xF0);
+        *stackptr = offset;
+        *stackptr |= ((u32) id) << 12;
+        *stackptr |= ((u32) value) << 16;
+        (*stackidx)++;
+        B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
+}
+
+static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
+{
+        size_t i;
+
+        B43_WARN_ON(offset & 0xF000);
+        B43_WARN_ON(id & 0xF0);
+        for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
+                if ((*stackptr & 0x00000FFF) != offset)
+                        continue;
+                if (((*stackptr & 0x0000F000) >> 12) != id)
+                        continue;
+                return ((*stackptr & 0xFFFF0000) >> 16);
+        }
+        B43_WARN_ON(1);
+
+        return 0;
+}
+
+#define phy_stacksave(offset)                                   \
+        do {                                                    \
+                _stack_save(stack, &stackidx, 0x1, (offset),    \
+                            b43_phy_read(dev, (offset)));       \
+        } while (0)
+#define phy_stackrestore(offset)                                \
+        do {                                                    \
+                b43_phy_write(dev, (offset),            \
+                                  _stack_restore(stack, 0x1,    \
+                                                 (offset)));    \
+        } while (0)
+#define radio_stacksave(offset)                                         \
+        do {                                                            \
+                _stack_save(stack, &stackidx, 0x2, (offset),            \
+                            b43_radio_read16(dev, (offset)));   \
+        } while (0)
+#define radio_stackrestore(offset)                                      \
+        do {                                                            \
+                b43_radio_write16(dev, (offset),                        \
+                                      _stack_restore(stack, 0x2,        \
+                                                     (offset)));        \
+        } while (0)
+#define ofdmtab_stacksave(table, offset)                        \
+        do {                                                    \
+                _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
+                            b43_ofdmtab_read16(dev, (table), (offset)));        \
+        } while (0)
+#define ofdmtab_stackrestore(table, offset)                     \
+        do {                                                    \
+                b43_ofdmtab_write16(dev, (table),       (offset),       \
+                                  _stack_restore(stack, 0x3,    \
+                                                 (offset)|(table)));    \
+        } while (0)
+
+static void
+b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 tmp, flipped;
+        size_t stackidx = 0;
+        u32 *stack = phy->interfstack;
+
+        switch (mode) {
+        case B43_INTERFMODE_NONWLAN:
+                if (phy->rev != 1) {
+                        b43_phy_write(dev, 0x042B,
+                                      b43_phy_read(dev, 0x042B) | 0x0800);
+                        b43_phy_write(dev, B43_PHY_G_CRS,
+                                      b43_phy_read(dev,
+                                                   B43_PHY_G_CRS) & ~0x4000);
+                        break;
+                }
+                radio_stacksave(0x0078);
+                tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
+                flipped = flip_4bit(tmp);
+                if (flipped < 10 && flipped >= 8)
+                        flipped = 7;
+                else if (flipped >= 10)
+                        flipped -= 3;
+                flipped = flip_4bit(flipped);
+                flipped = (flipped << 1) | 0x0020;
+                b43_radio_write16(dev, 0x0078, flipped);
+
+                b43_calc_nrssi_threshold(dev);
+
+                phy_stacksave(0x0406);
+                b43_phy_write(dev, 0x0406, 0x7E28);
+
+                b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
+                b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
+                              b43_phy_read(dev,
+                                           B43_PHY_RADIO_BITFIELD) | 0x1000);
+
+                phy_stacksave(0x04A0);
+                b43_phy_write(dev, 0x04A0,
+                              (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
+                phy_stacksave(0x04A1);
+                b43_phy_write(dev, 0x04A1,
+                              (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
+                phy_stacksave(0x04A2);
+                b43_phy_write(dev, 0x04A2,
+                              (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
+                phy_stacksave(0x04A8);
+                b43_phy_write(dev, 0x04A8,
+                              (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
+                phy_stacksave(0x04AB);
+                b43_phy_write(dev, 0x04AB,
+                              (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
+
+                phy_stacksave(0x04A7);
+                b43_phy_write(dev, 0x04A7, 0x0002);
+                phy_stacksave(0x04A3);
+                b43_phy_write(dev, 0x04A3, 0x287A);
+                phy_stacksave(0x04A9);
+                b43_phy_write(dev, 0x04A9, 0x2027);
+                phy_stacksave(0x0493);
+                b43_phy_write(dev, 0x0493, 0x32F5);
+                phy_stacksave(0x04AA);
+                b43_phy_write(dev, 0x04AA, 0x2027);
+                phy_stacksave(0x04AC);
+                b43_phy_write(dev, 0x04AC, 0x32F5);
+                break;
+        case B43_INTERFMODE_MANUALWLAN:
+                if (b43_phy_read(dev, 0x0033) & 0x0800)
+                        break;
+
+                phy->aci_enable = 1;
+
+                phy_stacksave(B43_PHY_RADIO_BITFIELD);
+                phy_stacksave(B43_PHY_G_CRS);
+                if (phy->rev < 2) {
+                        phy_stacksave(0x0406);
+                } else {
+                        phy_stacksave(0x04C0);
+                        phy_stacksave(0x04C1);
+                }
+                phy_stacksave(0x0033);
+                phy_stacksave(0x04A7);
+                phy_stacksave(0x04A3);
+                phy_stacksave(0x04A9);
+                phy_stacksave(0x04AA);
+                phy_stacksave(0x04AC);
+                phy_stacksave(0x0493);
+                phy_stacksave(0x04A1);
+                phy_stacksave(0x04A0);
+                phy_stacksave(0x04A2);
+                phy_stacksave(0x048A);
+                phy_stacksave(0x04A8);
+                phy_stacksave(0x04AB);
+                if (phy->rev == 2) {
+                        phy_stacksave(0x04AD);
+                        phy_stacksave(0x04AE);
+                } else if (phy->rev >= 3) {
+                        phy_stacksave(0x04AD);
+                        phy_stacksave(0x0415);
+                        phy_stacksave(0x0416);
+                        phy_stacksave(0x0417);
+                        ofdmtab_stacksave(0x1A00, 0x2);
+                        ofdmtab_stacksave(0x1A00, 0x3);
+                }
+                phy_stacksave(0x042B);
+                phy_stacksave(0x048C);
+
+                b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
+                              b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
+                              & ~0x1000);
+                b43_phy_write(dev, B43_PHY_G_CRS,
+                              (b43_phy_read(dev, B43_PHY_G_CRS)
+                               & 0xFFFC) | 0x0002);
+
+                b43_phy_write(dev, 0x0033, 0x0800);
+                b43_phy_write(dev, 0x04A3, 0x2027);
+                b43_phy_write(dev, 0x04A9, 0x1CA8);
+                b43_phy_write(dev, 0x0493, 0x287A);
+                b43_phy_write(dev, 0x04AA, 0x1CA8);
+                b43_phy_write(dev, 0x04AC, 0x287A);
+
+                b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
+                                            & 0xFFC0) | 0x001A);
+                b43_phy_write(dev, 0x04A7, 0x000D);
+
+                if (phy->rev < 2) {
+                        b43_phy_write(dev, 0x0406, 0xFF0D);
+                } else if (phy->rev == 2) {
+                        b43_phy_write(dev, 0x04C0, 0xFFFF);
+                        b43_phy_write(dev, 0x04C1, 0x00A9);
+                } else {
+                        b43_phy_write(dev, 0x04C0, 0x00C1);
+                        b43_phy_write(dev, 0x04C1, 0x0059);
+                }
+
+                b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
+                                            & 0xC0FF) | 0x1800);
+                b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
+                                            & 0xFFC0) | 0x0015);
+                b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
+                                            & 0xCFFF) | 0x1000);
+                b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
+                                            & 0xF0FF) | 0x0A00);
+                b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
+                                            & 0xCFFF) | 0x1000);
+                b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
+                                            & 0xF0FF) | 0x0800);
+                b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
+                                            & 0xFFCF) | 0x0010);
+                b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
+                                            & 0xFFF0) | 0x0005);
+                b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
+                                            & 0xFFCF) | 0x0010);
+                b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
+                                            & 0xFFF0) | 0x0006);
+                b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
+                                            & 0xF0FF) | 0x0800);
+                b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
+                                            & 0xF0FF) | 0x0500);
+                b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
+                                            & 0xFFF0) | 0x000B);
+
+                if (phy->rev >= 3) {
+                        b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
+                                      & ~0x8000);
+                        b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
+                                                    & 0x8000) | 0x36D8);
+                        b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
+                                                    & 0x8000) | 0x36D8);
+                        b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
+                                                    & 0xFE00) | 0x016D);
+                } else {
+                        b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
+                                      | 0x1000);
+                        b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
+                                                    & 0x9FFF) | 0x2000);
+                        b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
+                }
+                if (phy->rev >= 2) {
+                        b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
+                                      | 0x0800);
+                }
+                b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
+                                            & 0xF0FF) | 0x0200);
+                if (phy->rev == 2) {
+                        b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
+                                                    & 0xFF00) | 0x007F);
+                        b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
+                                                    & 0x00FF) | 0x1300);
+                } else if (phy->rev >= 6) {
+                        b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
+                        b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
+                        b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
+                                      & 0x00FF);
+                }
+                b43_calc_nrssi_slope(dev);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+static void
+b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
+{
+        struct b43_phy *phy = &dev->phy;
+        u32 *stack = phy->interfstack;
+
+        switch (mode) {
+        case B43_INTERFMODE_NONWLAN:
+                if (phy->rev != 1) {
+                        b43_phy_write(dev, 0x042B,
+                                      b43_phy_read(dev, 0x042B) & ~0x0800);
+                        b43_phy_write(dev, B43_PHY_G_CRS,
+                                      b43_phy_read(dev,
+                                                   B43_PHY_G_CRS) | 0x4000);
+                        break;
+                }
+                radio_stackrestore(0x0078);
+                b43_calc_nrssi_threshold(dev);
+                phy_stackrestore(0x0406);
+                b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
+                if (!dev->bad_frames_preempt) {
+                        b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
+                                      b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
+                                      & ~(1 << 11));
+                }
+                b43_phy_write(dev, B43_PHY_G_CRS,
+                              b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
+                phy_stackrestore(0x04A0);
+                phy_stackrestore(0x04A1);
+                phy_stackrestore(0x04A2);
+                phy_stackrestore(0x04A8);
+                phy_stackrestore(0x04AB);
+                phy_stackrestore(0x04A7);
+                phy_stackrestore(0x04A3);
+                phy_stackrestore(0x04A9);
+                phy_stackrestore(0x0493);
+                phy_stackrestore(0x04AA);
+                phy_stackrestore(0x04AC);
+                break;
+        case B43_INTERFMODE_MANUALWLAN:
+                if (!(b43_phy_read(dev, 0x0033) & 0x0800))
+                        break;
+
+                phy->aci_enable = 0;
+
+                phy_stackrestore(B43_PHY_RADIO_BITFIELD);
+                phy_stackrestore(B43_PHY_G_CRS);
+                phy_stackrestore(0x0033);
+                phy_stackrestore(0x04A3);
+                phy_stackrestore(0x04A9);
+                phy_stackrestore(0x0493);
+                phy_stackrestore(0x04AA);
+                phy_stackrestore(0x04AC);
+                phy_stackrestore(0x04A0);
+                phy_stackrestore(0x04A7);
+                if (phy->rev >= 2) {
+                        phy_stackrestore(0x04C0);
+                        phy_stackrestore(0x04C1);
+                } else
+                        phy_stackrestore(0x0406);
+                phy_stackrestore(0x04A1);
+                phy_stackrestore(0x04AB);
+                phy_stackrestore(0x04A8);
+                if (phy->rev == 2) {
+                        phy_stackrestore(0x04AD);
+                        phy_stackrestore(0x04AE);
+                } else if (phy->rev >= 3) {
+                        phy_stackrestore(0x04AD);
+                        phy_stackrestore(0x0415);
+                        phy_stackrestore(0x0416);
+                        phy_stackrestore(0x0417);
+                        ofdmtab_stackrestore(0x1A00, 0x2);
+                        ofdmtab_stackrestore(0x1A00, 0x3);
+                }
+                phy_stackrestore(0x04A2);
+                phy_stackrestore(0x048A);
+                phy_stackrestore(0x042B);
+                phy_stackrestore(0x048C);
+                b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
+                b43_calc_nrssi_slope(dev);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+}
+
+#undef phy_stacksave
+#undef phy_stackrestore
+#undef radio_stacksave
+#undef radio_stackrestore
+#undef ofdmtab_stacksave
+#undef ofdmtab_stackrestore
+
+int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
+{
+        struct b43_phy *phy = &dev->phy;
+        int currentmode;
+
+        if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
+                return -ENODEV;
+
+        phy->aci_wlan_automatic = 0;
+        switch (mode) {
+        case B43_INTERFMODE_AUTOWLAN:
+                phy->aci_wlan_automatic = 1;
+                if (phy->aci_enable)
+                        mode = B43_INTERFMODE_MANUALWLAN;
+                else
+                        mode = B43_INTERFMODE_NONE;
+                break;
+        case B43_INTERFMODE_NONE:
+        case B43_INTERFMODE_NONWLAN:
+        case B43_INTERFMODE_MANUALWLAN:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        currentmode = phy->interfmode;
+        if (currentmode == mode)
+                return 0;
+        if (currentmode != B43_INTERFMODE_NONE)
+                b43_radio_interference_mitigation_disable(dev, currentmode);
+
+        if (mode == B43_INTERFMODE_NONE) {
+                phy->aci_enable = 0;
+                phy->aci_hw_rssi = 0;
+        } else
+                b43_radio_interference_mitigation_enable(dev, mode);
+        phy->interfmode = mode;
+
+        return 0;
+}
+
+static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
+{
+        u16 reg, index, ret;
+
+        static const u8 rcc_table[] = {
+                0x02, 0x03, 0x01, 0x0F,
+                0x06, 0x07, 0x05, 0x0F,
+                0x0A, 0x0B, 0x09, 0x0F,
+                0x0E, 0x0F, 0x0D, 0x0F,
+        };
+
+        reg = b43_radio_read16(dev, 0x60);
+        index = (reg & 0x001E) >> 1;
+        ret = rcc_table[index] << 1;
+        ret |= (reg & 0x0001);
+        ret |= 0x0020;
+
+        return ret;
+}
+
+#define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
+static u16 radio2050_rfover_val(struct b43_wldev *dev,
+                                u16 phy_register, unsigned int lpd)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
+
+        if (!phy->gmode)
+                return 0;
+
+        if (has_loopback_gain(phy)) {
+                int max_lb_gain = phy->max_lb_gain;
+                u16 extlna;
+                u16 i;
+
+                if (phy->radio_rev == 8)
+                        max_lb_gain += 0x3E;
+                else
+                        max_lb_gain += 0x26;
+                if (max_lb_gain >= 0x46) {
+                        extlna = 0x3000;
+                        max_lb_gain -= 0x46;
+                } else if (max_lb_gain >= 0x3A) {
+                        extlna = 0x1000;
+                        max_lb_gain -= 0x3A;
+                } else if (max_lb_gain >= 0x2E) {
+                        extlna = 0x2000;
+                        max_lb_gain -= 0x2E;
+                } else {
+                        extlna = 0;
+                        max_lb_gain -= 0x10;
+                }
+
+                for (i = 0; i < 16; i++) {
+                        max_lb_gain -= (i * 6);
+                        if (max_lb_gain < 6)
+                                break;
+                }
+
+                if ((phy->rev < 7) ||
+                    !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
+                        if (phy_register == B43_PHY_RFOVER) {
+                                return 0x1B3;
+                        } else if (phy_register == B43_PHY_RFOVERVAL) {
+                                extlna |= (i << 8);
+                                switch (lpd) {
+                                case LPD(0, 1, 1):
+                                        return 0x0F92;
+                                case LPD(0, 0, 1):
+                                case LPD(1, 0, 1):
+                                        return (0x0092 | extlna);
+                                case LPD(1, 0, 0):
+                                        return (0x0093 | extlna);
+                                }
+                                B43_WARN_ON(1);
+                        }
+                        B43_WARN_ON(1);
+                } else {
+                        if (phy_register == B43_PHY_RFOVER) {
+                                return 0x9B3;
+                        } else if (phy_register == B43_PHY_RFOVERVAL) {
+                                if (extlna)
+                                        extlna |= 0x8000;
+                                extlna |= (i << 8);
+                                switch (lpd) {
+                                case LPD(0, 1, 1):
+                                        return 0x8F92;
+                                case LPD(0, 0, 1):
+                                        return (0x8092 | extlna);
+                                case LPD(1, 0, 1):
+                                        return (0x2092 | extlna);
+                                case LPD(1, 0, 0):
+                                        return (0x2093 | extlna);
+                                }
+                                B43_WARN_ON(1);
+                        }
+                        B43_WARN_ON(1);
+                }
+        } else {
+                if ((phy->rev < 7) ||
+                    !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
+                        if (phy_register == B43_PHY_RFOVER) {
+                                return 0x1B3;
+                        } else if (phy_register == B43_PHY_RFOVERVAL) {
+                                switch (lpd) {
+                                case LPD(0, 1, 1):
+                                        return 0x0FB2;
+                                case LPD(0, 0, 1):
+                                        return 0x00B2;
+                                case LPD(1, 0, 1):
+                                        return 0x30B2;
+                                case LPD(1, 0, 0):
+                                        return 0x30B3;
+                                }
+                                B43_WARN_ON(1);
+                        }
+                        B43_WARN_ON(1);
+                } else {
+                        if (phy_register == B43_PHY_RFOVER) {
+                                return 0x9B3;
+                        } else if (phy_register == B43_PHY_RFOVERVAL) {
+                                switch (lpd) {
+                                case LPD(0, 1, 1):
+                                        return 0x8FB2;
+                                case LPD(0, 0, 1):
+                                        return 0x80B2;
+                                case LPD(1, 0, 1):
+                                        return 0x20B2;
+                                case LPD(1, 0, 0):
+                                        return 0x20B3;
+                                }
+                                B43_WARN_ON(1);
+                        }
+                        B43_WARN_ON(1);
+                }
+        }
+        return 0;
+}
+
+struct init2050_saved_values {
+        /* Core registers */
+        u16 reg_3EC;
+        u16 reg_3E6;
+        u16 reg_3F4;
+        /* Radio registers */
+        u16 radio_43;
+        u16 radio_51;
+        u16 radio_52;
+        /* PHY registers */
+        u16 phy_pgactl;
+        u16 phy_base_5A;
+        u16 phy_base_59;
+        u16 phy_base_58;
+        u16 phy_base_30;
+        u16 phy_rfover;
+        u16 phy_rfoverval;
+        u16 phy_analogover;
+        u16 phy_analogoverval;
+        u16 phy_crs0;
+        u16 phy_classctl;
+        u16 phy_lo_mask;
+        u16 phy_lo_ctl;
+        u16 phy_syncctl;
+};
+
+u16 b43_radio_init2050(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        struct init2050_saved_values sav;
+        u16 rcc;
+        u16 radio78;
+        u16 ret;
+        u16 i, j;
+        u32 tmp1 = 0, tmp2 = 0;
+
+        memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
+
+        sav.radio_43 = b43_radio_read16(dev, 0x43);
+        sav.radio_51 = b43_radio_read16(dev, 0x51);
+        sav.radio_52 = b43_radio_read16(dev, 0x52);
+        sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
+        sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A));
+        sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59));
+        sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58));
+
+        if (phy->type == B43_PHYTYPE_B) {
+                sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
+                sav.reg_3EC = b43_read16(dev, 0x3EC);
+
+                b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF);
+                b43_write16(dev, 0x3EC, 0x3F3F);
+        } else if (phy->gmode || phy->rev >= 2) {
+                sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
+                sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
+                sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
+                sav.phy_analogoverval =
+                    b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
+                sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
+                sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
+
+                b43_phy_write(dev, B43_PHY_ANALOGOVER,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVER)
+                              | 0x0003);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
+                              & 0xFFFC);
+                b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
+                              & 0x7FFF);
+                b43_phy_write(dev, B43_PHY_CLASSCTL,
+                              b43_phy_read(dev, B43_PHY_CLASSCTL)
+                              & 0xFFFC);
+                if (has_loopback_gain(phy)) {
+                        sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
+                        sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
+
+                        if (phy->rev >= 3)
+                                b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
+                        else
+                                b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
+                        b43_phy_write(dev, B43_PHY_LO_CTL, 0);
+                }
+
+                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                              radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
+                                                   LPD(0, 1, 1)));
+                b43_phy_write(dev, B43_PHY_RFOVER,
+                              radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
+        }
+        b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
+
+        sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
+        b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
+                      & 0xFF7F);
+        sav.reg_3E6 = b43_read16(dev, 0x3E6);
+        sav.reg_3F4 = b43_read16(dev, 0x3F4);
+
+        if (phy->analog == 0) {
+                b43_write16(dev, 0x03E6, 0x0122);
+        } else {
+                if (phy->analog >= 2) {
+                        b43_phy_write(dev, B43_PHY_BASE(0x03),
+                                      (b43_phy_read(dev, B43_PHY_BASE(0x03))
+                                       & 0xFFBF) | 0x40);
+                }
+                b43_write16(dev, B43_MMIO_CHANNEL_EXT,
+                            (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
+        }
+
+        rcc = b43_radio_core_calibration_value(dev);
+
+        if (phy->type == B43_PHYTYPE_B)
+                b43_radio_write16(dev, 0x78, 0x26);
+        if (phy->gmode || phy->rev >= 2) {
+                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                              radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
+                                                   LPD(0, 1, 1)));
+        }
+        b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
+        b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403);
+        if (phy->gmode || phy->rev >= 2) {
+                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                              radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
+                                                   LPD(0, 0, 1)));
+        }
+        b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
+        b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
+                          | 0x0004);
+        if (phy->radio_rev == 8) {
+                b43_radio_write16(dev, 0x43, 0x1F);
+        } else {
+                b43_radio_write16(dev, 0x52, 0);
+                b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
+                                              & 0xFFF0) | 0x0009);
+        }
+        b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
+
+        for (i = 0; i < 16; i++) {
+                b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480);
+                b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
+                b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
+                if (phy->gmode || phy->rev >= 2) {
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      radio2050_rfover_val(dev,
+                                                           B43_PHY_RFOVERVAL,
+                                                           LPD(1, 0, 1)));
+                }
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
+                udelay(10);
+                if (phy->gmode || phy->rev >= 2) {
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      radio2050_rfover_val(dev,
+                                                           B43_PHY_RFOVERVAL,
+                                                           LPD(1, 0, 1)));
+                }
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
+                udelay(10);
+                if (phy->gmode || phy->rev >= 2) {
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      radio2050_rfover_val(dev,
+                                                           B43_PHY_RFOVERVAL,
+                                                           LPD(1, 0, 0)));
+                }
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
+                udelay(20);
+                tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
+                b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
+                if (phy->gmode || phy->rev >= 2) {
+                        b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                      radio2050_rfover_val(dev,
+                                                           B43_PHY_RFOVERVAL,
+                                                           LPD(1, 0, 1)));
+                }
+                b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
+        }
+        udelay(10);
+
+        b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
+        tmp1++;
+        tmp1 >>= 9;
+
+        for (i = 0; i < 16; i++) {
+                radio78 = ((flip_4bit(i) << 1) | 0x20);
+                b43_radio_write16(dev, 0x78, radio78);
+                udelay(10);
+                for (j = 0; j < 16; j++) {
+                        b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80);
+                        b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
+                        b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
+                        if (phy->gmode || phy->rev >= 2) {
+                                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                              radio2050_rfover_val(dev,
+                                                                   B43_PHY_RFOVERVAL,
+                                                                   LPD(1, 0,
+                                                                       1)));
+                        }
+                        b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
+                        udelay(10);
+                        if (phy->gmode || phy->rev >= 2) {
+                                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                              radio2050_rfover_val(dev,
+                                                                   B43_PHY_RFOVERVAL,
+                                                                   LPD(1, 0,
+                                                                       1)));
+                        }
+                        b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
+                        udelay(10);
+                        if (phy->gmode || phy->rev >= 2) {
+                                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                              radio2050_rfover_val(dev,
+                                                                   B43_PHY_RFOVERVAL,
+                                                                   LPD(1, 0,
+                                                                       0)));
+                        }
+                        b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
+                        udelay(10);
+                        tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
+                        b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
+                        if (phy->gmode || phy->rev >= 2) {
+                                b43_phy_write(dev, B43_PHY_RFOVERVAL,
+                                              radio2050_rfover_val(dev,
+                                                                   B43_PHY_RFOVERVAL,
+                                                                   LPD(1, 0,
+                                                                       1)));
+                        }
+                        b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
+                }
+                tmp2++;
+                tmp2 >>= 8;
+                if (tmp1 < tmp2)
+                        break;
+        }
+
+        /* Restore the registers */
+        b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
+        b43_radio_write16(dev, 0x51, sav.radio_51);
+        b43_radio_write16(dev, 0x52, sav.radio_52);
+        b43_radio_write16(dev, 0x43, sav.radio_43);
+        b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A);
+        b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59);
+        b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58);
+        b43_write16(dev, 0x3E6, sav.reg_3E6);
+        if (phy->analog != 0)
+                b43_write16(dev, 0x3F4, sav.reg_3F4);
+        b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
+        b43_synth_pu_workaround(dev, phy->channel);
+        if (phy->type == B43_PHYTYPE_B) {
+                b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30);
+                b43_write16(dev, 0x3EC, sav.reg_3EC);
+        } else if (phy->gmode) {
+                b43_write16(dev, B43_MMIO_PHY_RADIO,
+                            b43_read16(dev, B43_MMIO_PHY_RADIO)
+                            & 0x7FFF);
+                b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
+                b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
+                b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
+                b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
+                              sav.phy_analogoverval);
+                b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
+                b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
+                if (has_loopback_gain(phy)) {
+                        b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
+                        b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
+                }
+        }
+        if (i > 15)
+                ret = radio78;
+        else
+                ret = rcc;
+
+        return ret;
+}
+
+void b43_radio_init2060(struct b43_wldev *dev)
+{
+        int err;
+
+        b43_radio_write16(dev, 0x0004, 0x00C0);
+        b43_radio_write16(dev, 0x0005, 0x0008);
+        b43_radio_write16(dev, 0x0009, 0x0040);
+        b43_radio_write16(dev, 0x0005, 0x00AA);
+        b43_radio_write16(dev, 0x0032, 0x008F);
+        b43_radio_write16(dev, 0x0006, 0x008F);
+        b43_radio_write16(dev, 0x0034, 0x008F);
+        b43_radio_write16(dev, 0x002C, 0x0007);
+        b43_radio_write16(dev, 0x0082, 0x0080);
+        b43_radio_write16(dev, 0x0080, 0x0000);
+        b43_radio_write16(dev, 0x003F, 0x00DA);
+        b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
+        b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
+        b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
+        b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
+        msleep(1);              /* delay 400usec */
+
+        b43_radio_write16(dev, 0x0081,
+                          (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
+        msleep(1);              /* delay 400usec */
+
+        b43_radio_write16(dev, 0x0005,
+                          (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
+        b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
+        b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
+        b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
+        b43_radio_write16(dev, 0x0081,
+                          (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
+        b43_radio_write16(dev, 0x0005,
+                          (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
+        b43_phy_write(dev, 0x0063, 0xDDC6);
+        b43_phy_write(dev, 0x0069, 0x07BE);
+        b43_phy_write(dev, 0x006A, 0x0000);
+
+        err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
+        B43_WARN_ON(err);
+
+        msleep(1);
+}
+
+static inline u16 freq_r3A_value(u16 frequency)
+{
+        u16 value;
+
+        if (frequency < 5091)
+                value = 0x0040;
+        else if (frequency < 5321)
+                value = 0x0000;
+        else if (frequency < 5806)
+                value = 0x0080;
+        else
+                value = 0x0040;
+
+        return value;
+}
+
+void b43_radio_set_tx_iq(struct b43_wldev *dev)
+{
+        static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
+        static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
+        u16 tmp = b43_radio_read16(dev, 0x001E);
+        int i, j;
+
+        for (i = 0; i < 5; i++) {
+                for (j = 0; j < 5; j++) {
+                        if (tmp == (data_high[i] << 4 | data_low[j])) {
+                                b43_phy_write(dev, 0x0069,
+                                              (i - j) << 8 | 0x00C0);
+                                return;
+                        }
+                }
+        }
+}
+
+int b43_radio_selectchannel(struct b43_wldev *dev,
+                            u8 channel, int synthetic_pu_workaround)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 r8, tmp;
+        u16 freq;
+        u16 channelcookie;
+
+        /* First we set the channel radio code to prevent the
+         * firmware from sending ghost packets.
+         */
+        channelcookie = channel;
+        if (phy->type == B43_PHYTYPE_A)
+                channelcookie |= 0x100;
+        b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
+
+        if (phy->type == B43_PHYTYPE_A) {
+                if (channel > 200)
+                        return -EINVAL;
+                freq = channel2freq_a(channel);
+
+                r8 = b43_radio_read16(dev, 0x0008);
+                b43_write16(dev, 0x03F0, freq);
+                b43_radio_write16(dev, 0x0008, r8);
+
+                //TODO: write max channel TX power? to Radio 0x2D
+                tmp = b43_radio_read16(dev, 0x002E);
+                tmp &= 0x0080;
+                //TODO: OR tmp with the Power out estimation for this channel?
+                b43_radio_write16(dev, 0x002E, tmp);
+
+                if (freq >= 4920 && freq <= 5500) {
+                        /*
+                         * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
+                         *    = (freq * 0.025862069
+                         */
+                        r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
+                }
+                b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
+                b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
+                b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
+                b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
+                                                & 0x000F) | (r8 << 4));
+                b43_radio_write16(dev, 0x002A, (r8 << 4));
+                b43_radio_write16(dev, 0x002B, (r8 << 4));
+                b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
+                                                & 0x00F0) | (r8 << 4));
+                b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
+                                                & 0xFF0F) | 0x00B0);
+                b43_radio_write16(dev, 0x0035, 0x00AA);
+                b43_radio_write16(dev, 0x0036, 0x0085);
+                b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
+                                                & 0xFF20) |
+                                  freq_r3A_value(freq));
+                b43_radio_write16(dev, 0x003D,
+                                  b43_radio_read16(dev, 0x003D) & 0x00FF);
+                b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
+                                                & 0xFF7F) | 0x0080);
+                b43_radio_write16(dev, 0x0035,
+                                  b43_radio_read16(dev, 0x0035) & 0xFFEF);
+                b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
+                                                & 0xFFEF) | 0x0010);
+                b43_radio_set_tx_iq(dev);
+                //TODO: TSSI2dbm workaround
+                b43_phy_xmitpower(dev); //FIXME correct?
+        } else {
+                if ((channel < 1) || (channel > 14))
+                        return -EINVAL;
+
+                if (synthetic_pu_workaround)
+                        b43_synth_pu_workaround(dev, channel);
+
+                b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
+
+                if (channel == 14) {
+                        if (dev->dev->bus->sprom.r1.country_code ==
+                            SSB_SPROM1CCODE_JAPAN)
+                                b43_hf_write(dev,
+                                             b43_hf_read(dev) & ~B43_HF_ACPR);
+                        else
+                                b43_hf_write(dev,
+                                             b43_hf_read(dev) | B43_HF_ACPR);
+                        b43_write16(dev, B43_MMIO_CHANNEL_EXT,
+                                    b43_read16(dev, B43_MMIO_CHANNEL_EXT)
+                                    | (1 << 11));
+                } else {
+                        b43_write16(dev, B43_MMIO_CHANNEL_EXT,
+                                    b43_read16(dev, B43_MMIO_CHANNEL_EXT)
+                                    & 0xF7BF);
+                }
+        }
+
+        phy->channel = channel;
+        /* Wait for the radio to tune to the channel and stabilize. */
+        msleep(8);
+
+        return 0;
+}
+
+/* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
+static u16 b43_get_txgain_base_band(u16 txpower)
+{
+        u16 ret;
+
+        B43_WARN_ON(txpower > 63);
+
+        if (txpower >= 54)
+                ret = 2;
+        else if (txpower >= 49)
+                ret = 4;
+        else if (txpower >= 44)
+                ret = 5;
+        else
+                ret = 6;
+
+        return ret;
+}
+
+/* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
+static u16 b43_get_txgain_freq_power_amp(u16 txpower)
+{
+        u16 ret;
+
+        B43_WARN_ON(txpower > 63);
+
+        if (txpower >= 32)
+                ret = 0;
+        else if (txpower >= 25)
+                ret = 1;
+        else if (txpower >= 20)
+                ret = 2;
+        else if (txpower >= 12)
+                ret = 3;
+        else
+                ret = 4;
+
+        return ret;
+}
+
+/* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
+static u16 b43_get_txgain_dac(u16 txpower)
+{
+        u16 ret;
+
+        B43_WARN_ON(txpower > 63);
+
+        if (txpower >= 54)
+                ret = txpower - 53;
+        else if (txpower >= 49)
+                ret = txpower - 42;
+        else if (txpower >= 44)
+                ret = txpower - 37;
+        else if (txpower >= 32)
+                ret = txpower - 32;
+        else if (txpower >= 25)
+                ret = txpower - 20;
+        else if (txpower >= 20)
+                ret = txpower - 13;
+        else if (txpower >= 12)
+                ret = txpower - 8;
+        else
+                ret = txpower;
+
+        return ret;
+}
+
+static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower)
+{
+        struct b43_phy *phy = &dev->phy;
+        u16 pamp, base, dac, t;
+
+        txpower = limit_value(txpower, 0, 63);
+
+        pamp = b43_get_txgain_freq_power_amp(txpower);
+        pamp <<= 5;
+        pamp &= 0x00E0;
+        b43_phy_write(dev, 0x0019, pamp);
+
+        base = b43_get_txgain_base_band(txpower);
+        base &= 0x000F;
+        b43_phy_write(dev, 0x0017, base | 0x0020);
+
+        t = b43_ofdmtab_read16(dev, 0x3000, 1);
+        t &= 0x0007;
+
+        dac = b43_get_txgain_dac(txpower);
+        dac <<= 3;
+        dac |= t;
+
+        b43_ofdmtab_write16(dev, 0x3000, 1, dac);
+
+        phy->txpwr_offset = txpower;
+
+        //TODO: FuncPlaceholder (Adjust BB loft cancel)
+}
+
+void b43_radio_turn_on(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+        int err;
+
+        might_sleep();
+
+        if (phy->radio_on)
+                return;
+
+        switch (phy->type) {
+        case B43_PHYTYPE_A:
+                b43_radio_write16(dev, 0x0004, 0x00C0);
+                b43_radio_write16(dev, 0x0005, 0x0008);
+                b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
+                b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
+                b43_radio_init2060(dev);
+                break;
+        case B43_PHYTYPE_B:
+        case B43_PHYTYPE_G:
+                b43_phy_write(dev, 0x0015, 0x8000);
+                b43_phy_write(dev, 0x0015, 0xCC00);
+                b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
+                err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
+                B43_WARN_ON(err);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        phy->radio_on = 1;
+        b43dbg(dev->wl, "Radio turned on\n");
+}
+
+void b43_radio_turn_off(struct b43_wldev *dev)
+{
+        struct b43_phy *phy = &dev->phy;
+
+        if (phy->type == B43_PHYTYPE_A) {
+                b43_radio_write16(dev, 0x0004, 0x00FF);
+                b43_radio_write16(dev, 0x0005, 0x00FB);
+                b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
+                b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
+        }
+        if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) {
+                b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x008C);
+                b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) & 0xFF73);
+        } else
+                b43_phy_write(dev, 0x0015, 0xAA00);
+        phy->radio_on = 0;
+        b43dbg(dev->wl, "Radio turned off\n");
+}
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h
new file mode 100644
index 000000000000..d1f623cb9b34
--- /dev/null
+++ b/drivers/net/wireless/b43/phy.h
@@ -0,0 +1,297 @@
+#ifndef B43_PHY_H_
+#define B43_PHY_H_
+
+#include <linux/types.h>
+
+struct b43_wldev;
+struct b43_phy;
+
+/*** PHY Registers ***/
+
+/* Routing */
+#define B43_PHYROUTE_OFDM_GPHY          0x400
+#define B43_PHYROUTE_EXT_GPHY           0x800
+
+/* Base registers. */
+#define B43_PHY_BASE(reg)               (reg)
+/* OFDM (A) registers of a G-PHY */
+#define B43_PHY_OFDM(reg)               ((reg) | B43_PHYROUTE_OFDM_GPHY)
+/* Extended G-PHY registers */
+#define B43_PHY_EXTG(reg)               ((reg) | B43_PHYROUTE_EXT_GPHY)
+
+/* OFDM (A) PHY Registers */
+#define B43_PHY_VERSION_OFDM            B43_PHY_OFDM(0x00)      /* Versioning register for A-PHY */
+#define B43_PHY_BBANDCFG                B43_PHY_OFDM(0x01)      /* Baseband config */
+#define  B43_PHY_BBANDCFG_RXANT         0x180   /* RX Antenna selection */
+#define  B43_PHY_BBANDCFG_RXANT_SHIFT   7
+#define B43_PHY_PWRDOWN                 B43_PHY_OFDM(0x03)      /* Powerdown */
+#define B43_PHY_CRSTHRES1               B43_PHY_OFDM(0x06)      /* CRS Threshold 1 */
+#define B43_PHY_LNAHPFCTL               B43_PHY_OFDM(0x1C)      /* LNA/HPF control */
+#define B43_PHY_ADIVRELATED             B43_PHY_OFDM(0x27)      /* FIXME rename */
+#define B43_PHY_CRS0                    B43_PHY_OFDM(0x29)
+#define B43_PHY_ANTDWELL                B43_PHY_OFDM(0x2B)      /* Antenna dwell */
+#define  B43_PHY_ANTDWELL_AUTODIV1      0x0100  /* Automatic RX diversity start antenna */
+#define B43_PHY_ENCORE                  B43_PHY_OFDM(0x49)      /* "Encore" (RangeMax / BroadRange) */
+#define  B43_PHY_ENCORE_EN              0x0200  /* Encore enable */
+#define B43_PHY_LMS                     B43_PHY_OFDM(0x55)
+#define B43_PHY_OFDM61                  B43_PHY_OFDM(0x61)      /* FIXME rename */
+#define  B43_PHY_OFDM61_10              0x0010  /* FIXME rename */
+#define B43_PHY_IQBAL                   B43_PHY_OFDM(0x69)      /* I/Q balance */
+#define B43_PHY_OTABLECTL               B43_PHY_OFDM(0x72)      /* OFDM table control (see below) */
+#define  B43_PHY_OTABLEOFF              0x03FF  /* OFDM table offset (see below) */
+#define  B43_PHY_OTABLENR               0xFC00  /* OFDM table number (see below) */
+#define  B43_PHY_OTABLENR_SHIFT         10
+#define B43_PHY_OTABLEI                 B43_PHY_OFDM(0x73)      /* OFDM table data I */
+#define B43_PHY_OTABLEQ                 B43_PHY_OFDM(0x74)      /* OFDM table data Q */
+#define B43_PHY_HPWR_TSSICTL            B43_PHY_OFDM(0x78)      /* Hardware power TSSI control */
+#define B43_PHY_NRSSITHRES              B43_PHY_OFDM(0x8A)      /* NRSSI threshold */
+#define B43_PHY_ANTWRSETT               B43_PHY_OFDM(0x8C)      /* Antenna WR settle */
+#define  B43_PHY_ANTWRSETT_ARXDIV       0x2000  /* Automatic RX diversity enabled */
+#define B43_PHY_CLIPPWRDOWNT            B43_PHY_OFDM(0x93)      /* Clip powerdown threshold */
+#define B43_PHY_OFDM9B                  B43_PHY_OFDM(0x9B)      /* FIXME rename */
+#define B43_PHY_N1P1GAIN                B43_PHY_OFDM(0xA0)
+#define B43_PHY_P1P2GAIN                B43_PHY_OFDM(0xA1)
+#define B43_PHY_N1N2GAIN                B43_PHY_OFDM(0xA2)
+#define B43_PHY_CLIPTHRES               B43_PHY_OFDM(0xA3)
+#define B43_PHY_CLIPN1P2THRES           B43_PHY_OFDM(0xA4)
+#define B43_PHY_DIVSRCHIDX              B43_PHY_OFDM(0xA8)      /* Divider search gain/index */
+#define B43_PHY_CLIPP2THRES             B43_PHY_OFDM(0xA9)
+#define B43_PHY_CLIPP3THRES             B43_PHY_OFDM(0xAA)
+#define B43_PHY_DIVP1P2GAIN             B43_PHY_OFDM(0xAB)
+#define B43_PHY_DIVSRCHGAINBACK         B43_PHY_OFDM(0xAD)      /* Divider search gain back */
+#define B43_PHY_DIVSRCHGAINCHNG         B43_PHY_OFDM(0xAE)      /* Divider search gain change */
+#define B43_PHY_CRSTHRES1_R1            B43_PHY_OFDM(0xC0)      /* CRS Threshold 1 (rev 1 only) */
+#define B43_PHY_CRSTHRES2_R1            B43_PHY_OFDM(0xC1)      /* CRS Threshold 2 (rev 1 only) */
+#define B43_PHY_TSSIP_LTBASE            B43_PHY_OFDM(0x380)     /* TSSI power lookup table base */
+#define B43_PHY_DC_LTBASE               B43_PHY_OFDM(0x3A0)     /* DC lookup table base */
+#define B43_PHY_GAIN_LTBASE             B43_PHY_OFDM(0x3C0)     /* Gain lookup table base */
+
+/* CCK (B) PHY Registers */
+#define B43_PHY_VERSION_CCK             B43_PHY_BASE(0x00)      /* Versioning register for B-PHY */
+#define B43_PHY_CCKBBANDCFG             B43_PHY_BASE(0x01)      /* Contains antenna 0/1 control bit */
+#define B43_PHY_PGACTL                  B43_PHY_BASE(0x15)      /* PGA control */
+#define  B43_PHY_PGACTL_LPF             0x1000  /* Low pass filter (?) */
+#define  B43_PHY_PGACTL_LOWBANDW        0x0040  /* Low bandwidth flag */
+#define  B43_PHY_PGACTL_UNKNOWN         0xEFA0
+#define B43_PHY_FBCTL1                  B43_PHY_BASE(0x18)      /* Frequency bandwidth control 1 */
+#define B43_PHY_ITSSI                   B43_PHY_BASE(0x29)      /* Idle TSSI */
+#define B43_PHY_LO_LEAKAGE              B43_PHY_BASE(0x2D)      /* Measured LO leakage */
+#define B43_PHY_ENERGY                  B43_PHY_BASE(0x33)      /* Energy */
+#define B43_PHY_SYNCCTL                 B43_PHY_BASE(0x35)
+#define B43_PHY_FBCTL2                  B43_PHY_BASE(0x38)      /* Frequency bandwidth control 2 */
+#define B43_PHY_DACCTL                  B43_PHY_BASE(0x60)      /* DAC control */
+#define B43_PHY_RCCALOVER               B43_PHY_BASE(0x78)      /* RC calibration override */
+
+/* Extended G-PHY Registers */
+#define B43_PHY_CLASSCTL                B43_PHY_EXTG(0x02)      /* Classify control */
+#define B43_PHY_GTABCTL                 B43_PHY_EXTG(0x03)      /* G-PHY table control (see below) */
+#define  B43_PHY_GTABOFF                0x03FF  /* G-PHY table offset (see below) */
+#define  B43_PHY_GTABNR                 0xFC00  /* G-PHY table number (see below) */
+#define  B43_PHY_GTABNR_SHIFT           10
+#define B43_PHY_GTABDATA                B43_PHY_EXTG(0x04)      /* G-PHY table data */
+#define B43_PHY_LO_MASK                 B43_PHY_EXTG(0x0F)      /* Local Oscillator control mask */
+#define B43_PHY_LO_CTL                  B43_PHY_EXTG(0x10)      /* Local Oscillator control */
+#define B43_PHY_RFOVER                  B43_PHY_EXTG(0x11)      /* RF override */
+#define B43_PHY_RFOVERVAL               B43_PHY_EXTG(0x12)      /* RF override value */
+#define  B43_PHY_RFOVERVAL_EXTLNA       0x8000
+#define  B43_PHY_RFOVERVAL_LNA          0x7000
+#define  B43_PHY_RFOVERVAL_LNA_SHIFT    12
+#define  B43_PHY_RFOVERVAL_PGA          0x0F00
+#define  B43_PHY_RFOVERVAL_PGA_SHIFT    8
+#define  B43_PHY_RFOVERVAL_UNK          0x0010  /* Unknown, always set. */
+#define  B43_PHY_RFOVERVAL_TRSWRX       0x00E0
+#define  B43_PHY_RFOVERVAL_BW           0x0003  /* Bandwidth flags */
+#define   B43_PHY_RFOVERVAL_BW_LPF      0x0001  /* Low Pass Filter */
+#define   B43_PHY_RFOVERVAL_BW_LBW      0x0002  /* Low Bandwidth (when set), high when unset */
+#define B43_PHY_ANALOGOVER              B43_PHY_EXTG(0x14)      /* Analog override */
+#define B43_PHY_ANALOGOVERVAL           B43_PHY_EXTG(0x15)      /* Analog override value */
+
+/*** OFDM table numbers ***/
+#define B43_OFDMTAB(number, offset)     (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
+#define B43_OFDMTAB_AGC1                B43_OFDMTAB(0x00, 0)
+#define B43_OFDMTAB_GAIN0               B43_OFDMTAB(0x00, 0)
+#define B43_OFDMTAB_GAINX               B43_OFDMTAB(0x01, 0)    //TODO rename
+#define B43_OFDMTAB_GAIN1               B43_OFDMTAB(0x01, 4)
+#define B43_OFDMTAB_AGC3                B43_OFDMTAB(0x02, 0)
+#define B43_OFDMTAB_GAIN2               B43_OFDMTAB(0x02, 3)
+#define B43_OFDMTAB_LNAHPFGAIN1         B43_OFDMTAB(0x03, 0)
+#define B43_OFDMTAB_WRSSI               B43_OFDMTAB(0x04, 0)
+#define B43_OFDMTAB_LNAHPFGAIN2         B43_OFDMTAB(0x04, 0)
+#define B43_OFDMTAB_NOISESCALE          B43_OFDMTAB(0x05, 0)
+#define B43_OFDMTAB_AGC2                B43_OFDMTAB(0x06, 0)
+#define B43_OFDMTAB_ROTOR               B43_OFDMTAB(0x08, 0)
+#define B43_OFDMTAB_ADVRETARD           B43_OFDMTAB(0x09, 0)
+#define B43_OFDMTAB_DAC                 B43_OFDMTAB(0x0C, 0)
+#define B43_OFDMTAB_DC                  B43_OFDMTAB(0x0E, 7)
+#define B43_OFDMTAB_PWRDYN2             B43_OFDMTAB(0x0E, 12)
+#define B43_OFDMTAB_LNAGAIN             B43_OFDMTAB(0x0E, 13)
+//TODO
+#define B43_OFDMTAB_LPFGAIN             B43_OFDMTAB(0x0F, 12)
+#define B43_OFDMTAB_RSSI                B43_OFDMTAB(0x10, 0)
+//TODO
+#define B43_OFDMTAB_AGC1_R1             B43_OFDMTAB(0x13, 0)
+#define B43_OFDMTAB_GAINX_R1            B43_OFDMTAB(0x14, 0)    //TODO rename
+#define B43_OFDMTAB_MINSIGSQ            B43_OFDMTAB(0x14, 1)
+#define B43_OFDMTAB_AGC3_R1             B43_OFDMTAB(0x15, 0)
+#define B43_OFDMTAB_WRSSI_R1            B43_OFDMTAB(0x15, 4)
+#define B43_OFDMTAB_TSSI                B43_OFDMTAB(0x15, 0)
+#define B43_OFDMTAB_DACRFPABB           B43_OFDMTAB(0x16, 0)
+#define B43_OFDMTAB_DACOFF              B43_OFDMTAB(0x17, 0)
+#define B43_OFDMTAB_DCBIAS              B43_OFDMTAB(0x18, 0)
+
+u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
+void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
+                         u16 offset, u16 value);
+u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
+void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
+                         u16 offset, u32 value);
+
+/*** G-PHY table numbers */
+#define B43_GTAB(number, offset)        (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
+#define B43_GTAB_NRSSI                  B43_GTAB(0x00, 0)
+#define B43_GTAB_TRFEMW                 B43_GTAB(0x0C, 0x120)
+#define B43_GTAB_ORIGTR                 B43_GTAB(0x2E, 0x298)
+
+u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);        //TODO implement
+void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);   //TODO implement
+
+#define B43_DEFAULT_CHANNEL_A   36
+#define B43_DEFAULT_CHANNEL_BG  6
+
+enum {
+        B43_ANTENNA0,           /* Antenna 0 */
+        B43_ANTENNA1,           /* Antenna 0 */
+        B43_ANTENNA_AUTO1,      /* Automatic, starting with antenna 1 */
+        B43_ANTENNA_AUTO0,      /* Automatic, starting with antenna 0 */
+
+        B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
+        B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
+};
+
+enum {
+        B43_INTERFMODE_NONE,
+        B43_INTERFMODE_NONWLAN,
+        B43_INTERFMODE_MANUALWLAN,
+        B43_INTERFMODE_AUTOWLAN,
+};
+
+/* Masks for the different PHY versioning registers. */
+#define B43_PHYVER_ANALOG               0xF000
+#define B43_PHYVER_ANALOG_SHIFT         12
+#define B43_PHYVER_TYPE                 0x0F00
+#define B43_PHYVER_TYPE_SHIFT           8
+#define B43_PHYVER_VERSION              0x00FF
+
+void b43_raw_phy_lock(struct b43_wldev *dev);
+#define b43_phy_lock(dev, flags) \
+        do {                                    \
+                local_irq_save(flags);          \
+                b43_raw_phy_lock(dev);  \
+        } while (0)
+void b43_raw_phy_unlock(struct b43_wldev *dev);
+#define b43_phy_unlock(dev, flags) \
+        do {                                    \
+                b43_raw_phy_unlock(dev);        \
+                local_irq_restore(flags);       \
+        } while (0)
+
+u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
+void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
+
+int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
+
+void b43_phy_early_init(struct b43_wldev *dev);
+int b43_phy_init(struct b43_wldev *dev);
+
+void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
+
+void b43_phy_xmitpower(struct b43_wldev *dev);
+void b43_gphy_dc_lt_init(struct b43_wldev *dev);
+
+/* Returns the boolean whether the board has HardwarePowerControl */
+bool b43_has_hardware_pctl(struct b43_phy *phy);
+/* Returns the boolean whether "TX Magnification" is enabled. */
+#define has_tx_magnification(phy) \
+        (((phy)->rev >= 2) &&                   \
+         ((phy)->radio_ver == 0x2050) &&        \
+         ((phy)->radio_rev == 8))
+/* Card uses the loopback gain stuff */
+#define has_loopback_gain(phy) \
+        (((phy)->rev > 1) || ((phy)->gmode))
+
+/* Radio Attenuation (RF Attenuation) */
+struct b43_rfatt {
+        u8 att;                 /* Attenuation value */
+        bool with_padmix;       /* Flag, PAD Mixer enabled. */
+};
+struct b43_rfatt_list {
+        /* Attenuation values list */
+        const struct b43_rfatt *list;
+        u8 len;
+        /* Minimum/Maximum attenuation values */
+        u8 min_val;
+        u8 max_val;
+};
+
+/* Baseband Attenuation */
+struct b43_bbatt {
+        u8 att;                 /* Attenuation value */
+};
+struct b43_bbatt_list {
+        /* Attenuation values list */
+        const struct b43_bbatt *list;
+        u8 len;
+        /* Minimum/Maximum attenuation values */
+        u8 min_val;
+        u8 max_val;
+};
+
+/* tx_control bits. */
+#define B43_TXCTL_PA3DB         0x40    /* PA Gain 3dB */
+#define B43_TXCTL_PA2DB         0x20    /* PA Gain 2dB */
+#define B43_TXCTL_TXMIX         0x10    /* TX Mixer Gain */
+
+/* Write BasebandAttenuation value to the device. */
+void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
+                                      u16 baseband_attenuation);
+
+extern const u8 b43_radio_channel_codes_bg[];
+
+void b43_radio_lock(struct b43_wldev *dev);
+void b43_radio_unlock(struct b43_wldev *dev);
+
+u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
+void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
+
+u16 b43_radio_init2050(struct b43_wldev *dev);
+void b43_radio_init2060(struct b43_wldev *dev);
+
+void b43_radio_turn_on(struct b43_wldev *dev);
+void b43_radio_turn_off(struct b43_wldev *dev);
+
+int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
+                            int synthetic_pu_workaround);
+
+u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
+u8 b43_radio_aci_scan(struct b43_wldev *dev);
+
+int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
+
+void b43_calc_nrssi_slope(struct b43_wldev *dev);
+void b43_calc_nrssi_threshold(struct b43_wldev *dev);
+s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
+void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
+void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
+void b43_nrssi_mem_update(struct b43_wldev *dev);
+
+void b43_radio_set_tx_iq(struct b43_wldev *dev);
+u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
+
+void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
+                                     int *_bbatt, int *_rfatt);
+
+void b43_set_txpower_g(struct b43_wldev *dev,
+                       const struct b43_bbatt *bbatt,
+                       const struct b43_rfatt *rfatt, u8 tx_control);
+
+#endif /* B43_PHY_H_ */
diff --git a/drivers/net/wireless/b43/pio.c b/drivers/net/wireless/b43/pio.c
new file mode 100644
index 000000000000..4ac91fdd356e
--- /dev/null
+++ b/drivers/net/wireless/b43/pio.c
@@ -0,0 +1,650 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  PIO Transmission
+
+  Copyright (c) 2005 Michael Buesch <mb@bu3sch.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "b43.h"
+#include "pio.h"
+#include "main.h"
+#include "xmit.h"
+
+#include <linux/delay.h>
+
+static void tx_start(struct b43_pioqueue *queue)
+{
+        b43_pio_write(queue, B43_PIO_TXCTL, B43_PIO_TXCTL_INIT);
+}
+
+static void tx_octet(struct b43_pioqueue *queue, u8 octet)
+{
+        if (queue->need_workarounds) {
+                b43_pio_write(queue, B43_PIO_TXDATA, octet);
+                b43_pio_write(queue, B43_PIO_TXCTL, B43_PIO_TXCTL_WRITELO);
+        } else {
+                b43_pio_write(queue, B43_PIO_TXCTL, B43_PIO_TXCTL_WRITELO);
+                b43_pio_write(queue, B43_PIO_TXDATA, octet);
+        }
+}
+
+static u16 tx_get_next_word(const u8 * txhdr,
+                            const u8 * packet,
+                            size_t txhdr_size, unsigned int *pos)
+{
+        const u8 *source;
+        unsigned int i = *pos;
+        u16 ret;
+
+        if (i < txhdr_size) {
+                source = txhdr;
+        } else {
+                source = packet;
+                i -= txhdr_size;
+        }
+        ret = le16_to_cpu(*((u16 *) (source + i)));
+        *pos += 2;
+
+        return ret;
+}
+
+static void tx_data(struct b43_pioqueue *queue,
+                    u8 * txhdr, const u8 * packet, unsigned int octets)
+{
+        u16 data;
+        unsigned int i = 0;
+
+        if (queue->need_workarounds) {
+                data = tx_get_next_word(txhdr, packet,
+                                        sizeof(struct b43_txhdr_fw4), &i);
+                b43_pio_write(queue, B43_PIO_TXDATA, data);
+        }
+        b43_pio_write(queue, B43_PIO_TXCTL,
+                      B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_WRITEHI);
+        while (i < octets - 1) {
+                data = tx_get_next_word(txhdr, packet,
+                                        sizeof(struct b43_txhdr_fw4), &i);
+                b43_pio_write(queue, B43_PIO_TXDATA, data);
+        }
+        if (octets % 2)
+                tx_octet(queue,
+                         packet[octets - sizeof(struct b43_txhdr_fw4) - 1]);
+}
+
+static void tx_complete(struct b43_pioqueue *queue, struct sk_buff *skb)
+{
+        if (queue->need_workarounds) {
+                b43_pio_write(queue, B43_PIO_TXDATA, skb->data[skb->len - 1]);
+                b43_pio_write(queue, B43_PIO_TXCTL,
+                              B43_PIO_TXCTL_WRITELO | B43_PIO_TXCTL_COMPLETE);
+        } else {
+                b43_pio_write(queue, B43_PIO_TXCTL, B43_PIO_TXCTL_COMPLETE);
+        }
+}
+
+static u16 generate_cookie(struct b43_pioqueue *queue,
+                           struct b43_pio_txpacket *packet)
+{
+        u16 cookie = 0x0000;
+        int packetindex;
+
+        /* We use the upper 4 bits for the PIO
+         * controller ID and the lower 12 bits
+         * for the packet index (in the cache).
+         */
+        switch (queue->mmio_base) {
+        case B43_MMIO_PIO1_BASE:
+                break;
+        case B43_MMIO_PIO2_BASE:
+                cookie = 0x1000;
+                break;
+        case B43_MMIO_PIO3_BASE:
+                cookie = 0x2000;
+                break;
+        case B43_MMIO_PIO4_BASE:
+                cookie = 0x3000;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        packetindex = pio_txpacket_getindex(packet);
+        B43_WARN_ON(packetindex & ~0x0FFF);
+        cookie |= (u16) packetindex;
+
+        return cookie;
+}
+
+static
+struct b43_pioqueue *parse_cookie(struct b43_wldev *dev,
+                                  u16 cookie, struct b43_pio_txpacket **packet)
+{
+        struct b43_pio *pio = &dev->pio;
+        struct b43_pioqueue *queue = NULL;
+        int packetindex;
+
+        switch (cookie & 0xF000) {
+        case 0x0000:
+                queue = pio->queue0;
+                break;
+        case 0x1000:
+                queue = pio->queue1;
+                break;
+        case 0x2000:
+                queue = pio->queue2;
+                break;
+        case 0x3000:
+                queue = pio->queue3;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+        packetindex = (cookie & 0x0FFF);
+        B43_WARN_ON(!(packetindex >= 0 && packetindex < B43_PIO_MAXTXPACKETS));
+        *packet = &(queue->tx_packets_cache[packetindex]);
+
+        return queue;
+}
+
+union txhdr_union {
+        struct b43_txhdr_fw4 txhdr_fw4;
+};
+
+static void pio_tx_write_fragment(struct b43_pioqueue *queue,
+                                  struct sk_buff *skb,
+                                  struct b43_pio_txpacket *packet,
+                                  size_t txhdr_size)
+{
+        union txhdr_union txhdr_data;
+        u8 *txhdr = NULL;
+        unsigned int octets;
+
+        txhdr = (u8 *) (&txhdr_data.txhdr_fw4);
+
+        B43_WARN_ON(skb_shinfo(skb)->nr_frags);
+        b43_generate_txhdr(queue->dev,
+                           txhdr, skb->data, skb->len,
+                           &packet->txstat.control,
+                           generate_cookie(queue, packet));
+
+        tx_start(queue);
+        octets = skb->len + txhdr_size;
+        if (queue->need_workarounds)
+                octets--;
+        tx_data(queue, txhdr, (u8 *) skb->data, octets);
+        tx_complete(queue, skb);
+}
+
+static void free_txpacket(struct b43_pio_txpacket *packet)
+{
+        struct b43_pioqueue *queue = packet->queue;
+
+        if (packet->skb)
+                dev_kfree_skb_any(packet->skb);
+        list_move(&packet->list, &queue->txfree);
+        queue->nr_txfree++;
+}
+
+static int pio_tx_packet(struct b43_pio_txpacket *packet)
+{
+        struct b43_pioqueue *queue = packet->queue;
+        struct sk_buff *skb = packet->skb;
+        u16 octets;
+
+        octets = (u16) skb->len + sizeof(struct b43_txhdr_fw4);
+        if (queue->tx_devq_size < octets) {
+                b43warn(queue->dev->wl, "PIO queue too small. "
+                        "Dropping packet.\n");
+                /* Drop it silently (return success) */
+                free_txpacket(packet);
+                return 0;
+        }
+        B43_WARN_ON(queue->tx_devq_packets > B43_PIO_MAXTXDEVQPACKETS);
+        B43_WARN_ON(queue->tx_devq_used > queue->tx_devq_size);
+        /* Check if there is sufficient free space on the device
+         * TX queue. If not, return and let the TX tasklet
+         * retry later.
+         */
+        if (queue->tx_devq_packets == B43_PIO_MAXTXDEVQPACKETS)
+                return -EBUSY;
+        if (queue->tx_devq_used + octets > queue->tx_devq_size)
+                return -EBUSY;
+        /* Now poke the device. */
+        pio_tx_write_fragment(queue, skb, packet, sizeof(struct b43_txhdr_fw4));
+
+        /* Account for the packet size.
+         * (We must not overflow the device TX queue)
+         */
+        queue->tx_devq_packets++;
+        queue->tx_devq_used += octets;
+
+        /* Transmission started, everything ok, move the
+         * packet to the txrunning list.
+         */
+        list_move_tail(&packet->list, &queue->txrunning);
+
+        return 0;
+}
+
+static void tx_tasklet(unsigned long d)
+{
+        struct b43_pioqueue *queue = (struct b43_pioqueue *)d;
+        struct b43_wldev *dev = queue->dev;
+        unsigned long flags;
+        struct b43_pio_txpacket *packet, *tmp_packet;
+        int err;
+        u16 txctl;
+
+        spin_lock_irqsave(&dev->wl->irq_lock, flags);
+        if (queue->tx_frozen)
+                goto out_unlock;
+        txctl = b43_pio_read(queue, B43_PIO_TXCTL);
+        if (txctl & B43_PIO_TXCTL_SUSPEND)
+                goto out_unlock;
+
+        list_for_each_entry_safe(packet, tmp_packet, &queue->txqueue, list) {
+                /* Try to transmit the packet. This can fail, if
+                 * the device queue is full. In case of failure, the
+                 * packet is left in the txqueue.
+                 * If transmission succeed, the packet is moved to txrunning.
+                 * If it is impossible to transmit the packet, it
+                 * is dropped.
+                 */
+                err = pio_tx_packet(packet);
+                if (err)
+                        break;
+        }
+      out_unlock:
+        spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
+}
+
+static void setup_txqueues(struct b43_pioqueue *queue)
+{
+        struct b43_pio_txpacket *packet;
+        int i;
+
+        queue->nr_txfree = B43_PIO_MAXTXPACKETS;
+        for (i = 0; i < B43_PIO_MAXTXPACKETS; i++) {
+                packet = &(queue->tx_packets_cache[i]);
+
+                packet->queue = queue;
+                INIT_LIST_HEAD(&packet->list);
+
+                list_add(&packet->list, &queue->txfree);
+        }
+}
+
+static
+struct b43_pioqueue *b43_setup_pioqueue(struct b43_wldev *dev,
+                                        u16 pio_mmio_base)
+{
+        struct b43_pioqueue *queue;
+        u16 qsize;
+
+        queue = kzalloc(sizeof(*queue), GFP_KERNEL);
+        if (!queue)
+                goto out;
+
+        queue->dev = dev;
+        queue->mmio_base = pio_mmio_base;
+        queue->need_workarounds = (dev->dev->id.revision < 3);
+
+        INIT_LIST_HEAD(&queue->txfree);
+        INIT_LIST_HEAD(&queue->txqueue);
+        INIT_LIST_HEAD(&queue->txrunning);
+        tasklet_init(&queue->txtask, tx_tasklet, (unsigned long)queue);
+
+        b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
+                    & ~B43_MACCTL_BE);
+
+        qsize = b43_read16(dev, queue->mmio_base + B43_PIO_TXQBUFSIZE);
+        if (qsize == 0) {
+                b43err(dev->wl, "This card does not support PIO "
+                       "operation mode. Please use DMA mode "
+                       "(module parameter pio=0).\n");
+                goto err_freequeue;
+        }
+        if (qsize <= B43_PIO_TXQADJUST) {
+                b43err(dev->wl, "PIO tx device-queue too small (%u)\n", qsize);
+                goto err_freequeue;
+        }
+        qsize -= B43_PIO_TXQADJUST;
+        queue->tx_devq_size = qsize;
+
+        setup_txqueues(queue);
+
+      out:
+        return queue;
+
+      err_freequeue:
+        kfree(queue);
+        queue = NULL;
+        goto out;
+}
+
+static void cancel_transfers(struct b43_pioqueue *queue)
+{
+        struct b43_pio_txpacket *packet, *tmp_packet;
+
+        tasklet_disable(&queue->txtask);
+
+        list_for_each_entry_safe(packet, tmp_packet, &queue->txrunning, list)
+            free_txpacket(packet);
+        list_for_each_entry_safe(packet, tmp_packet, &queue->txqueue, list)
+            free_txpacket(packet);
+}
+
+static void b43_destroy_pioqueue(struct b43_pioqueue *queue)
+{
+        if (!queue)
+                return;
+
+        cancel_transfers(queue);
+        kfree(queue);
+}
+
+void b43_pio_free(struct b43_wldev *dev)
+{
+        struct b43_pio *pio;
+
+        if (!b43_using_pio(dev))
+                return;
+        pio = &dev->pio;
+
+        b43_destroy_pioqueue(pio->queue3);
+        pio->queue3 = NULL;
+        b43_destroy_pioqueue(pio->queue2);
+        pio->queue2 = NULL;
+        b43_destroy_pioqueue(pio->queue1);
+        pio->queue1 = NULL;
+        b43_destroy_pioqueue(pio->queue0);
+        pio->queue0 = NULL;
+}
+
+int b43_pio_init(struct b43_wldev *dev)
+{
+        struct b43_pio *pio = &dev->pio;
+        struct b43_pioqueue *queue;
+        int err = -ENOMEM;
+
+        queue = b43_setup_pioqueue(dev, B43_MMIO_PIO1_BASE);
+        if (!queue)
+                goto out;
+        pio->queue0 = queue;
+
+        queue = b43_setup_pioqueue(dev, B43_MMIO_PIO2_BASE);
+        if (!queue)
+                goto err_destroy0;
+        pio->queue1 = queue;
+
+        queue = b43_setup_pioqueue(dev, B43_MMIO_PIO3_BASE);
+        if (!queue)
+                goto err_destroy1;
+        pio->queue2 = queue;
+
+        queue = b43_setup_pioqueue(dev, B43_MMIO_PIO4_BASE);
+        if (!queue)
+                goto err_destroy2;
+        pio->queue3 = queue;
+
+        if (dev->dev->id.revision < 3)
+                dev->irq_savedstate |= B43_IRQ_PIO_WORKAROUND;
+
+        b43dbg(dev->wl, "PIO initialized\n");
+        err = 0;
+      out:
+        return err;
+
+      err_destroy2:
+        b43_destroy_pioqueue(pio->queue2);
+        pio->queue2 = NULL;
+      err_destroy1:
+        b43_destroy_pioqueue(pio->queue1);
+        pio->queue1 = NULL;
+      err_destroy0:
+        b43_destroy_pioqueue(pio->queue0);
+        pio->queue0 = NULL;
+        goto out;
+}
+
+int b43_pio_tx(struct b43_wldev *dev,
+               struct sk_buff *skb, struct ieee80211_tx_control *ctl)
+{
+        struct b43_pioqueue *queue = dev->pio.queue1;
+        struct b43_pio_txpacket *packet;
+
+        B43_WARN_ON(queue->tx_suspended);
+        B43_WARN_ON(list_empty(&queue->txfree));
+
+        packet = list_entry(queue->txfree.next, struct b43_pio_txpacket, list);
+        packet->skb = skb;
+
+        memset(&packet->txstat, 0, sizeof(packet->txstat));
+        memcpy(&packet->txstat.control, ctl, sizeof(*ctl));
+
+        list_move_tail(&packet->list, &queue->txqueue);
+        queue->nr_txfree--;
+        queue->nr_tx_packets++;
+        B43_WARN_ON(queue->nr_txfree >= B43_PIO_MAXTXPACKETS);
+
+        tasklet_schedule(&queue->txtask);
+
+        return 0;
+}
+
+void b43_pio_handle_txstatus(struct b43_wldev *dev,
+                             const struct b43_txstatus *status)
+{
+        struct b43_pioqueue *queue;
+        struct b43_pio_txpacket *packet;
+
+        queue = parse_cookie(dev, status->cookie, &packet);
+        if (B43_WARN_ON(!queue))
+                return;
+
+        queue->tx_devq_packets--;
+        queue->tx_devq_used -=
+            (packet->skb->len + sizeof(struct b43_txhdr_fw4));
+
+        if (status->acked) {
+                packet->txstat.flags |= IEEE80211_TX_STATUS_ACK;
+        } else {
+                if (!(packet->txstat.control.flags & IEEE80211_TXCTL_NO_ACK))
+                        packet->txstat.excessive_retries = 1;
+        }
+        if (status->frame_count == 0) {
+                /* The frame was not transmitted at all. */
+                packet->txstat.retry_count = 0;
+        } else
+                packet->txstat.retry_count = status->frame_count - 1;
+        ieee80211_tx_status_irqsafe(dev->wl->hw, packet->skb,
+                                    &(packet->txstat));
+        packet->skb = NULL;
+
+        free_txpacket(packet);
+        /* If there are packets on the txqueue, poke the tasklet
+         * to transmit them.
+         */
+        if (!list_empty(&queue->txqueue))
+                tasklet_schedule(&queue->txtask);
+}
+
+void b43_pio_get_tx_stats(struct b43_wldev *dev,
+                          struct ieee80211_tx_queue_stats *stats)
+{
+        struct b43_pio *pio = &dev->pio;
+        struct b43_pioqueue *queue;
+        struct ieee80211_tx_queue_stats_data *data;
+
+        queue = pio->queue1;
+        data = &(stats->data[0]);
+        data->len = B43_PIO_MAXTXPACKETS - queue->nr_txfree;
+        data->limit = B43_PIO_MAXTXPACKETS;
+        data->count = queue->nr_tx_packets;
+}
+
+static void pio_rx_error(struct b43_pioqueue *queue,
+                         int clear_buffers, const char *error)
+{
+        int i;
+
+        b43err(queue->dev->wl, "PIO RX error: %s\n", error);
+        b43_pio_write(queue, B43_PIO_RXCTL, B43_PIO_RXCTL_READY);
+        if (clear_buffers) {
+                B43_WARN_ON(queue->mmio_base != B43_MMIO_PIO1_BASE);
+                for (i = 0; i < 15; i++) {
+                        /* Dummy read. */
+                        b43_pio_read(queue, B43_PIO_RXDATA);
+                }
+        }
+}
+
+void b43_pio_rx(struct b43_pioqueue *queue)
+{
+        u16 preamble[21] = { 0 };
+        struct b43_rxhdr_fw4 *rxhdr;
+        u16 tmp, len, macstat;
+        int i, preamble_readwords;
+        struct sk_buff *skb;
+
+        tmp = b43_pio_read(queue, B43_PIO_RXCTL);
+        if (!(tmp & B43_PIO_RXCTL_DATAAVAILABLE))
+                return;
+        b43_pio_write(queue, B43_PIO_RXCTL, B43_PIO_RXCTL_DATAAVAILABLE);
+
+        for (i = 0; i < 10; i++) {
+                tmp = b43_pio_read(queue, B43_PIO_RXCTL);
+                if (tmp & B43_PIO_RXCTL_READY)
+                        goto data_ready;
+                udelay(10);
+        }
+        b43dbg(queue->dev->wl, "PIO RX timed out\n");
+        return;
+      data_ready:
+
+        len = b43_pio_read(queue, B43_PIO_RXDATA);
+        if (unlikely(len > 0x700)) {
+                pio_rx_error(queue, 0, "len > 0x700");
+                return;
+        }
+        if (unlikely(len == 0 && queue->mmio_base != B43_MMIO_PIO4_BASE)) {
+                pio_rx_error(queue, 0, "len == 0");
+                return;
+        }
+        preamble[0] = cpu_to_le16(len);
+        if (queue->mmio_base == B43_MMIO_PIO4_BASE)
+                preamble_readwords = 14 / sizeof(u16);
+        else
+                preamble_readwords = 18 / sizeof(u16);
+        for (i = 0; i < preamble_readwords; i++) {
+                tmp = b43_pio_read(queue, B43_PIO_RXDATA);
+                preamble[i + 1] = cpu_to_le16(tmp);
+        }
+        rxhdr = (struct b43_rxhdr_fw4 *)preamble;
+        macstat = le16_to_cpu(rxhdr->mac_status);
+        if (macstat & B43_RX_MAC_FCSERR) {
+                pio_rx_error(queue,
+                             (queue->mmio_base == B43_MMIO_PIO1_BASE),
+                             "Frame FCS error");
+                return;
+        }
+        if (queue->mmio_base == B43_MMIO_PIO4_BASE) {
+                /* We received an xmit status. */
+                struct b43_hwtxstatus *hw;
+
+                hw = (struct b43_hwtxstatus *)(preamble + 1);
+                b43_handle_hwtxstatus(queue->dev, hw);
+
+                return;
+        }
+
+        skb = dev_alloc_skb(len);
+        if (unlikely(!skb)) {
+                pio_rx_error(queue, 1, "OOM");
+                return;
+        }
+        skb_put(skb, len);
+        for (i = 0; i < len - 1; i += 2) {
+                tmp = b43_pio_read(queue, B43_PIO_RXDATA);
+                *((u16 *) (skb->data + i)) = cpu_to_le16(tmp);
+        }
+        if (len % 2) {
+                tmp = b43_pio_read(queue, B43_PIO_RXDATA);
+                skb->data[len - 1] = (tmp & 0x00FF);
+/* The specs say the following is required, but
+ * it is wrong and corrupts the PLCP. If we don't do
+ * this, the PLCP seems to be correct. So ifdef it out for now.
+ */
+#if 0
+                if (rxflags2 & B43_RXHDR_FLAGS2_TYPE2FRAME)
+                        skb->data[2] = (tmp & 0xFF00) >> 8;
+                else
+                        skb->data[0] = (tmp & 0xFF00) >> 8;
+#endif
+        }
+        b43_rx(queue->dev, skb, rxhdr);
+}
+
+void b43_pio_tx_suspend(struct b43_pioqueue *queue)
+{
+        b43_power_saving_ctl_bits(queue->dev, B43_PS_AWAKE);
+        b43_pio_write(queue, B43_PIO_TXCTL, b43_pio_read(queue, B43_PIO_TXCTL)
+                      | B43_PIO_TXCTL_SUSPEND);
+}
+
+void b43_pio_tx_resume(struct b43_pioqueue *queue)
+{
+        b43_pio_write(queue, B43_PIO_TXCTL, b43_pio_read(queue, B43_PIO_TXCTL)
+                      & ~B43_PIO_TXCTL_SUSPEND);
+        b43_power_saving_ctl_bits(queue->dev, 0);
+        tasklet_schedule(&queue->txtask);
+}
+
+void b43_pio_freeze_txqueues(struct b43_wldev *dev)
+{
+        struct b43_pio *pio;
+
+        B43_WARN_ON(!b43_using_pio(dev));
+        pio = &dev->pio;
+        pio->queue0->tx_frozen = 1;
+        pio->queue1->tx_frozen = 1;
+        pio->queue2->tx_frozen = 1;
+        pio->queue3->tx_frozen = 1;
+}
+
+void b43_pio_thaw_txqueues(struct b43_wldev *dev)
+{
+        struct b43_pio *pio;
+
+        B43_WARN_ON(!b43_using_pio(dev));
+        pio = &dev->pio;
+        pio->queue0->tx_frozen = 0;
+        pio->queue1->tx_frozen = 0;
+        pio->queue2->tx_frozen = 0;
+        pio->queue3->tx_frozen = 0;
+        if (!list_empty(&pio->queue0->txqueue))
+                tasklet_schedule(&pio->queue0->txtask);
+        if (!list_empty(&pio->queue1->txqueue))
+                tasklet_schedule(&pio->queue1->txtask);
+        if (!list_empty(&pio->queue2->txqueue))
+                tasklet_schedule(&pio->queue2->txtask);
+        if (!list_empty(&pio->queue3->txqueue))
+                tasklet_schedule(&pio->queue3->txtask);
+}
diff --git a/drivers/net/wireless/b43/pio.h b/drivers/net/wireless/b43/pio.h
new file mode 100644
index 000000000000..46d6d2ea9b5f
--- /dev/null
+++ b/drivers/net/wireless/b43/pio.h
@@ -0,0 +1,153 @@
+#ifndef B43_PIO_H_
+#define B43_PIO_H_
+
+#include "b43.h"
+
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/skbuff.h>
+
+#define B43_PIO_TXCTL           0x00
+#define B43_PIO_TXDATA          0x02
+#define B43_PIO_TXQBUFSIZE              0x04
+#define B43_PIO_RXCTL           0x08
+#define B43_PIO_RXDATA          0x0A
+
+#define B43_PIO_TXCTL_WRITELO   (1 << 0)
+#define B43_PIO_TXCTL_WRITEHI   (1 << 1)
+#define B43_PIO_TXCTL_COMPLETE  (1 << 2)
+#define B43_PIO_TXCTL_INIT              (1 << 3)
+#define B43_PIO_TXCTL_SUSPEND   (1 << 7)
+
+#define B43_PIO_RXCTL_DATAAVAILABLE     (1 << 0)
+#define B43_PIO_RXCTL_READY             (1 << 1)
+
+/* PIO constants */
+#define B43_PIO_MAXTXDEVQPACKETS        31
+#define B43_PIO_TXQADJUST               80
+
+/* PIO tuning knobs */
+#define B43_PIO_MAXTXPACKETS    256
+
+#ifdef CONFIG_B43_PIO
+
+struct b43_pioqueue;
+struct b43_xmitstatus;
+
+struct b43_pio_txpacket {
+        struct b43_pioqueue *queue;
+        struct sk_buff *skb;
+        struct ieee80211_tx_status txstat;
+        struct list_head list;
+};
+
+#define pio_txpacket_getindex(packet) ((int)((packet) - (packet)->queue->tx_packets_cache))
+
+struct b43_pioqueue {
+        struct b43_wldev *dev;
+        u16 mmio_base;
+
+        bool tx_suspended;
+        bool tx_frozen;
+        bool need_workarounds;  /* Workarounds needed for core.rev < 3 */
+
+        /* Adjusted size of the device internal TX buffer. */
+        u16 tx_devq_size;
+        /* Used octets of the device internal TX buffer. */
+        u16 tx_devq_used;
+        /* Used packet slots in the device internal TX buffer. */
+        u8 tx_devq_packets;
+        /* Packets from the txfree list can
+         * be taken on incoming TX requests.
+         */
+        struct list_head txfree;
+        unsigned int nr_txfree;
+        /* Packets on the txqueue are queued,
+         * but not completely written to the chip, yet.
+         */
+        struct list_head txqueue;
+        /* Packets on the txrunning queue are completely
+         * posted to the device. We are waiting for the txstatus.
+         */
+        struct list_head txrunning;
+        /* Total number or packets sent.
+         * (This counter can obviously wrap).
+         */
+        unsigned int nr_tx_packets;
+        struct tasklet_struct txtask;
+        struct b43_pio_txpacket tx_packets_cache[B43_PIO_MAXTXPACKETS];
+};
+
+static inline u16 b43_pio_read(struct b43_pioqueue *queue, u16 offset)
+{
+        return b43_read16(queue->dev, queue->mmio_base + offset);
+}
+
+static inline
+    void b43_pio_write(struct b43_pioqueue *queue, u16 offset, u16 value)
+{
+        b43_write16(queue->dev, queue->mmio_base + offset, value);
+        mmiowb();
+}
+
+int b43_pio_init(struct b43_wldev *dev);
+void b43_pio_free(struct b43_wldev *dev);
+
+int b43_pio_tx(struct b43_wldev *dev,
+               struct sk_buff *skb, struct ieee80211_tx_control *ctl);
+void b43_pio_handle_txstatus(struct b43_wldev *dev,
+                             const struct b43_txstatus *status);
+void b43_pio_get_tx_stats(struct b43_wldev *dev,
+                          struct ieee80211_tx_queue_stats *stats);
+void b43_pio_rx(struct b43_pioqueue *queue);
+
+/* Suspend TX queue in hardware. */
+void b43_pio_tx_suspend(struct b43_pioqueue *queue);
+void b43_pio_tx_resume(struct b43_pioqueue *queue);
+/* Suspend (freeze) the TX tasklet (software level). */
+void b43_pio_freeze_txqueues(struct b43_wldev *dev);
+void b43_pio_thaw_txqueues(struct b43_wldev *dev);
+
+#else /* CONFIG_B43_PIO */
+
+static inline int b43_pio_init(struct b43_wldev *dev)
+{
+        return 0;
+}
+static inline void b43_pio_free(struct b43_wldev *dev)
+{
+}
+static inline
+    int b43_pio_tx(struct b43_wldev *dev,
+                   struct sk_buff *skb, struct ieee80211_tx_control *ctl)
+{
+        return 0;
+}
+static inline
+    void b43_pio_handle_txstatus(struct b43_wldev *dev,
+                                 const struct b43_txstatus *status)
+{
+}
+static inline
+    void b43_pio_get_tx_stats(struct b43_wldev *dev,
+                              struct ieee80211_tx_queue_stats *stats)
+{
+}
+static inline void b43_pio_rx(struct b43_pioqueue *queue)
+{
+}
+static inline void b43_pio_tx_suspend(struct b43_pioqueue *queue)
+{
+}
+static inline void b43_pio_tx_resume(struct b43_pioqueue *queue)
+{
+}
+static inline void b43_pio_freeze_txqueues(struct b43_wldev *dev)
+{
+}
+static inline void b43_pio_thaw_txqueues(struct b43_wldev *dev)
+{
+}
+
+#endif /* CONFIG_B43_PIO */
+#endif /* B43_PIO_H_ */
diff --git a/drivers/net/wireless/b43/sysfs.c b/drivers/net/wireless/b43/sysfs.c
new file mode 100644
index 000000000000..fcb777383e70
--- /dev/null
+++ b/drivers/net/wireless/b43/sysfs.c
@@ -0,0 +1,235 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  SYSFS support routines
+
+  Copyright (c) 2006 Michael Buesch <mb@bu3sch.de>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "b43.h"
+#include "sysfs.h"
+#include "main.h"
+#include "phy.h"
+
+#include <linux/capability.h>
+
+#define GENERIC_FILESIZE        64
+
+static int get_integer(const char *buf, size_t count)
+{
+        char tmp[10 + 1] = { 0 };
+        int ret = -EINVAL;
+
+        if (count == 0)
+                goto out;
+        count = min(count, (size_t) 10);
+        memcpy(tmp, buf, count);
+        ret = simple_strtol(tmp, NULL, 10);
+      out:
+        return ret;
+}
+
+static int get_boolean(const char *buf, size_t count)
+{
+        if (count != 0) {
+                if (buf[0] == '1')
+                        return 1;
+                if (buf[0] == '0')
+                        return 0;
+                if (count >= 4 && memcmp(buf, "true", 4) == 0)
+                        return 1;
+                if (count >= 5 && memcmp(buf, "false", 5) == 0)
+                        return 0;
+                if (count >= 3 && memcmp(buf, "yes", 3) == 0)
+                        return 1;
+                if (count >= 2 && memcmp(buf, "no", 2) == 0)
+                        return 0;
+                if (count >= 2 && memcmp(buf, "on", 2) == 0)
+                        return 1;
+                if (count >= 3 && memcmp(buf, "off", 3) == 0)
+                        return 0;
+        }
+        return -EINVAL;
+}
+
+static ssize_t b43_attr_interfmode_show(struct device *dev,
+                                        struct device_attribute *attr,
+                                        char *buf)
+{
+        struct b43_wldev *wldev = dev_to_b43_wldev(dev);
+        ssize_t count = 0;
+
+        if (!capable(CAP_NET_ADMIN))
+                return -EPERM;
+
+        mutex_lock(&wldev->wl->mutex);
+
+        switch (wldev->phy.interfmode) {
+        case B43_INTERFMODE_NONE:
+                count =
+                    snprintf(buf, PAGE_SIZE,
+                             "0 (No Interference Mitigation)\n");
+                break;
+        case B43_INTERFMODE_NONWLAN:
+                count =
+                    snprintf(buf, PAGE_SIZE,
+                             "1 (Non-WLAN Interference Mitigation)\n");
+                break;
+        case B43_INTERFMODE_MANUALWLAN:
+                count =
+                    snprintf(buf, PAGE_SIZE,
+                             "2 (WLAN Interference Mitigation)\n");
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+
+        mutex_unlock(&wldev->wl->mutex);
+
+        return count;
+}
+
+static ssize_t b43_attr_interfmode_store(struct device *dev,
+                                         struct device_attribute *attr,
+                                         const char *buf, size_t count)
+{
+        struct b43_wldev *wldev = dev_to_b43_wldev(dev);
+        unsigned long flags;
+        int err;
+        int mode;
+
+        if (!capable(CAP_NET_ADMIN))
+                return -EPERM;
+
+        mode = get_integer(buf, count);
+        switch (mode) {
+        case 0:
+                mode = B43_INTERFMODE_NONE;
+                break;
+        case 1:
+                mode = B43_INTERFMODE_NONWLAN;
+                break;
+        case 2:
+                mode = B43_INTERFMODE_MANUALWLAN;
+                break;
+        case 3:
+                mode = B43_INTERFMODE_AUTOWLAN;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        mutex_lock(&wldev->wl->mutex);
+        spin_lock_irqsave(&wldev->wl->irq_lock, flags);
+
+        err = b43_radio_set_interference_mitigation(wldev, mode);
+        if (err) {
+                b43err(wldev->wl, "Interference Mitigation not "
+                       "supported by device\n");
+        }
+        mmiowb();
+        spin_unlock_irqrestore(&wldev->wl->irq_lock, flags);
+        mutex_unlock(&wldev->wl->mutex);
+
+        return err ? err : count;
+}
+
+static DEVICE_ATTR(interference, 0644,
+                   b43_attr_interfmode_show, b43_attr_interfmode_store);
+
+static ssize_t b43_attr_preamble_show(struct device *dev,
+                                      struct device_attribute *attr, char *buf)
+{
+        struct b43_wldev *wldev = dev_to_b43_wldev(dev);
+        ssize_t count;
+
+        if (!capable(CAP_NET_ADMIN))
+                return -EPERM;
+
+        mutex_lock(&wldev->wl->mutex);
+
+        if (wldev->short_preamble)
+                count =
+                    snprintf(buf, PAGE_SIZE, "1 (Short Preamble enabled)\n");
+        else
+                count =
+                    snprintf(buf, PAGE_SIZE, "0 (Short Preamble disabled)\n");
+
+        mutex_unlock(&wldev->wl->mutex);
+
+        return count;
+}
+
+static ssize_t b43_attr_preamble_store(struct device *dev,
+                                       struct device_attribute *attr,
+                                       const char *buf, size_t count)
+{
+        struct b43_wldev *wldev = dev_to_b43_wldev(dev);
+        unsigned long flags;
+        int value;
+
+        if (!capable(CAP_NET_ADMIN))
+                return -EPERM;
+
+        value = get_boolean(buf, count);
+        if (value < 0)
+                return value;
+        mutex_lock(&wldev->wl->mutex);
+        spin_lock_irqsave(&wldev->wl->irq_lock, flags);
+
+        wldev->short_preamble = !!value;
+
+        spin_unlock_irqrestore(&wldev->wl->irq_lock, flags);
+        mutex_unlock(&wldev->wl->mutex);
+
+        return count;
+}
+
+static DEVICE_ATTR(shortpreamble, 0644,
+                   b43_attr_preamble_show, b43_attr_preamble_store);
+
+int b43_sysfs_register(struct b43_wldev *wldev)
+{
+        struct device *dev = wldev->dev->dev;
+        int err;
+
+        B43_WARN_ON(b43_status(wldev) != B43_STAT_INITIALIZED);
+
+        err = device_create_file(dev, &dev_attr_interference);
+        if (err)
+                goto out;
+        err = device_create_file(dev, &dev_attr_shortpreamble);
+        if (err)
+                goto err_remove_interfmode;
+
+      out:
+        return err;
+      err_remove_interfmode:
+        device_remove_file(dev, &dev_attr_interference);
+        goto out;
+}
+
+void b43_sysfs_unregister(struct b43_wldev *wldev)
+{
+        struct device *dev = wldev->dev->dev;
+
+        device_remove_file(dev, &dev_attr_shortpreamble);
+        device_remove_file(dev, &dev_attr_interference);
+}
diff --git a/drivers/net/wireless/b43/sysfs.h b/drivers/net/wireless/b43/sysfs.h
new file mode 100644
index 000000000000..12bda9ef1a85
--- /dev/null
+++ b/drivers/net/wireless/b43/sysfs.h
@@ -0,0 +1,9 @@
+#ifndef B43_SYSFS_H_
+#define B43_SYSFS_H_
+
+struct b43_wldev;
+
+int b43_sysfs_register(struct b43_wldev *dev);
+void b43_sysfs_unregister(struct b43_wldev *dev);
+
+#endif /* B43_SYSFS_H_ */
diff --git a/drivers/net/wireless/b43/tables.c b/drivers/net/wireless/b43/tables.c
new file mode 100644
index 000000000000..15a87183a572
--- /dev/null
+++ b/drivers/net/wireless/b43/tables.c
@@ -0,0 +1,375 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
+  Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
+  Copyright (c) 2006, 2006 Michael Buesch <mb@bu3sch.de>
+  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "b43.h"
+#include "tables.h"
+#include "phy.h"
+
+const u32 b43_tab_rotor[] = {
+        0xFEB93FFD, 0xFEC63FFD, /* 0 */
+        0xFED23FFD, 0xFEDF3FFD,
+        0xFEEC3FFE, 0xFEF83FFE,
+        0xFF053FFE, 0xFF113FFE,
+        0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
+        0xFF373FFF, 0xFF443FFF,
+        0xFF503FFF, 0xFF5D3FFF,
+        0xFF693FFF, 0xFF763FFF,
+        0xFF824000, 0xFF8F4000, /* 16 */
+        0xFF9B4000, 0xFFA84000,
+        0xFFB54000, 0xFFC14000,
+        0xFFCE4000, 0xFFDA4000,
+        0xFFE74000, 0xFFF34000, /* 24 */
+        0x00004000, 0x000D4000,
+        0x00194000, 0x00264000,
+        0x00324000, 0x003F4000,
+        0x004B4000, 0x00584000, /* 32 */
+        0x00654000, 0x00714000,
+        0x007E4000, 0x008A3FFF,
+        0x00973FFF, 0x00A33FFF,
+        0x00B03FFF, 0x00BC3FFF, /* 40 */
+        0x00C93FFF, 0x00D63FFF,
+        0x00E23FFE, 0x00EF3FFE,
+        0x00FB3FFE, 0x01083FFE,
+        0x01143FFE, 0x01213FFD, /* 48 */
+        0x012E3FFD, 0x013A3FFD,
+        0x01473FFD,
+};
+
+const u32 b43_tab_retard[] = {
+        0xDB93CB87, 0xD666CF64, /* 0 */
+        0xD1FDD358, 0xCDA6D826,
+        0xCA38DD9F, 0xC729E2B4,
+        0xC469E88E, 0xC26AEE2B,
+        0xC0DEF46C, 0xC073FA62, /* 8 */
+        0xC01D00D5, 0xC0760743,
+        0xC1560D1E, 0xC2E51369,
+        0xC4ED18FF, 0xC7AC1ED7,
+        0xCB2823B2, 0xCEFA28D9, /* 16 */
+        0xD2F62D3F, 0xD7BB3197,
+        0xDCE53568, 0xE1FE3875,
+        0xE7D13B35, 0xED663D35,
+        0xF39B3EC4, 0xF98E3FA7, /* 24 */
+        0x00004000, 0x06723FA7,
+        0x0C653EC4, 0x129A3D35,
+        0x182F3B35, 0x1E023875,
+        0x231B3568, 0x28453197, /* 32 */
+        0x2D0A2D3F, 0x310628D9,
+        0x34D823B2, 0x38541ED7,
+        0x3B1318FF, 0x3D1B1369,
+        0x3EAA0D1E, 0x3F8A0743, /* 40 */
+        0x3FE300D5, 0x3F8DFA62,
+        0x3F22F46C, 0x3D96EE2B,
+        0x3B97E88E, 0x38D7E2B4,
+        0x35C8DD9F, 0x325AD826, /* 48 */
+        0x2E03D358, 0x299ACF64,
+        0x246DCB87,
+};
+
+const u16 b43_tab_finefreqa[] = {
+        0x0082, 0x0082, 0x0102, 0x0182, /* 0 */
+        0x0202, 0x0282, 0x0302, 0x0382,
+        0x0402, 0x0482, 0x0502, 0x0582,
+        0x05E2, 0x0662, 0x06E2, 0x0762,
+        0x07E2, 0x0842, 0x08C2, 0x0942, /* 16 */
+        0x09C2, 0x0A22, 0x0AA2, 0x0B02,
+        0x0B82, 0x0BE2, 0x0C62, 0x0CC2,
+        0x0D42, 0x0DA2, 0x0E02, 0x0E62,
+        0x0EE2, 0x0F42, 0x0FA2, 0x1002, /* 32 */
+        0x1062, 0x10C2, 0x1122, 0x1182,
+        0x11E2, 0x1242, 0x12A2, 0x12E2,
+        0x1342, 0x13A2, 0x1402, 0x1442,
+        0x14A2, 0x14E2, 0x1542, 0x1582, /* 48 */
+        0x15E2, 0x1622, 0x1662, 0x16C1,
+        0x1701, 0x1741, 0x1781, 0x17E1,
+        0x1821, 0x1861, 0x18A1, 0x18E1,
+        0x1921, 0x1961, 0x19A1, 0x19E1, /* 64 */
+        0x1A21, 0x1A61, 0x1AA1, 0x1AC1,
+        0x1B01, 0x1B41, 0x1B81, 0x1BA1,
+        0x1BE1, 0x1C21, 0x1C41, 0x1C81,
+        0x1CA1, 0x1CE1, 0x1D01, 0x1D41, /* 80 */
+        0x1D61, 0x1DA1, 0x1DC1, 0x1E01,
+        0x1E21, 0x1E61, 0x1E81, 0x1EA1,
+        0x1EE1, 0x1F01, 0x1F21, 0x1F41,
+        0x1F81, 0x1FA1, 0x1FC1, 0x1FE1, /* 96 */
+        0x2001, 0x2041, 0x2061, 0x2081,
+        0x20A1, 0x20C1, 0x20E1, 0x2101,
+        0x2121, 0x2141, 0x2161, 0x2181,
+        0x21A1, 0x21C1, 0x21E1, 0x2201, /* 112 */
+        0x2221, 0x2241, 0x2261, 0x2281,
+        0x22A1, 0x22C1, 0x22C1, 0x22E1,
+        0x2301, 0x2321, 0x2341, 0x2361,
+        0x2361, 0x2381, 0x23A1, 0x23C1, /* 128 */
+        0x23E1, 0x23E1, 0x2401, 0x2421,
+        0x2441, 0x2441, 0x2461, 0x2481,
+        0x2481, 0x24A1, 0x24C1, 0x24C1,
+        0x24E1, 0x2501, 0x2501, 0x2521, /* 144 */
+        0x2541, 0x2541, 0x2561, 0x2561,
+        0x2581, 0x25A1, 0x25A1, 0x25C1,
+        0x25C1, 0x25E1, 0x2601, 0x2601,
+        0x2621, 0x2621, 0x2641, 0x2641, /* 160 */
+        0x2661, 0x2661, 0x2681, 0x2681,
+        0x26A1, 0x26A1, 0x26C1, 0x26C1,
+        0x26E1, 0x26E1, 0x2701, 0x2701,
+        0x2721, 0x2721, 0x2740, 0x2740, /* 176 */
+        0x2760, 0x2760, 0x2780, 0x2780,
+        0x2780, 0x27A0, 0x27A0, 0x27C0,
+        0x27C0, 0x27E0, 0x27E0, 0x27E0,
+        0x2800, 0x2800, 0x2820, 0x2820, /* 192 */
+        0x2820, 0x2840, 0x2840, 0x2840,
+        0x2860, 0x2860, 0x2880, 0x2880,
+        0x2880, 0x28A0, 0x28A0, 0x28A0,
+        0x28C0, 0x28C0, 0x28C0, 0x28E0, /* 208 */
+        0x28E0, 0x28E0, 0x2900, 0x2900,
+        0x2900, 0x2920, 0x2920, 0x2920,
+        0x2940, 0x2940, 0x2940, 0x2960,
+        0x2960, 0x2960, 0x2960, 0x2980, /* 224 */
+        0x2980, 0x2980, 0x29A0, 0x29A0,
+        0x29A0, 0x29A0, 0x29C0, 0x29C0,
+        0x29C0, 0x29E0, 0x29E0, 0x29E0,
+        0x29E0, 0x2A00, 0x2A00, 0x2A00, /* 240 */
+        0x2A00, 0x2A20, 0x2A20, 0x2A20,
+        0x2A20, 0x2A40, 0x2A40, 0x2A40,
+        0x2A40, 0x2A60, 0x2A60, 0x2A60,
+};
+
+const u16 b43_tab_finefreqg[] = {
+        0x0089, 0x02E9, 0x0409, 0x04E9, /* 0 */
+        0x05A9, 0x0669, 0x0709, 0x0789,
+        0x0829, 0x08A9, 0x0929, 0x0989,
+        0x0A09, 0x0A69, 0x0AC9, 0x0B29,
+        0x0BA9, 0x0BE9, 0x0C49, 0x0CA9, /* 16 */
+        0x0D09, 0x0D69, 0x0DA9, 0x0E09,
+        0x0E69, 0x0EA9, 0x0F09, 0x0F49,
+        0x0FA9, 0x0FE9, 0x1029, 0x1089,
+        0x10C9, 0x1109, 0x1169, 0x11A9, /* 32 */
+        0x11E9, 0x1229, 0x1289, 0x12C9,
+        0x1309, 0x1349, 0x1389, 0x13C9,
+        0x1409, 0x1449, 0x14A9, 0x14E9,
+        0x1529, 0x1569, 0x15A9, 0x15E9, /* 48 */
+        0x1629, 0x1669, 0x16A9, 0x16E8,
+        0x1728, 0x1768, 0x17A8, 0x17E8,
+        0x1828, 0x1868, 0x18A8, 0x18E8,
+        0x1928, 0x1968, 0x19A8, 0x19E8, /* 64 */
+        0x1A28, 0x1A68, 0x1AA8, 0x1AE8,
+        0x1B28, 0x1B68, 0x1BA8, 0x1BE8,
+        0x1C28, 0x1C68, 0x1CA8, 0x1CE8,
+        0x1D28, 0x1D68, 0x1DC8, 0x1E08, /* 80 */
+        0x1E48, 0x1E88, 0x1EC8, 0x1F08,
+        0x1F48, 0x1F88, 0x1FE8, 0x2028,
+        0x2068, 0x20A8, 0x2108, 0x2148,
+        0x2188, 0x21C8, 0x2228, 0x2268, /* 96 */
+        0x22C8, 0x2308, 0x2348, 0x23A8,
+        0x23E8, 0x2448, 0x24A8, 0x24E8,
+        0x2548, 0x25A8, 0x2608, 0x2668,
+        0x26C8, 0x2728, 0x2787, 0x27E7, /* 112 */
+        0x2847, 0x28C7, 0x2947, 0x29A7,
+        0x2A27, 0x2AC7, 0x2B47, 0x2BE7,
+        0x2CA7, 0x2D67, 0x2E47, 0x2F67,
+        0x3247, 0x3526, 0x3646, 0x3726, /* 128 */
+        0x3806, 0x38A6, 0x3946, 0x39E6,
+        0x3A66, 0x3AE6, 0x3B66, 0x3BC6,
+        0x3C45, 0x3CA5, 0x3D05, 0x3D85,
+        0x3DE5, 0x3E45, 0x3EA5, 0x3EE5, /* 144 */
+        0x3F45, 0x3FA5, 0x4005, 0x4045,
+        0x40A5, 0x40E5, 0x4145, 0x4185,
+        0x41E5, 0x4225, 0x4265, 0x42C5,
+        0x4305, 0x4345, 0x43A5, 0x43E5, /* 160 */
+        0x4424, 0x4464, 0x44C4, 0x4504,
+        0x4544, 0x4584, 0x45C4, 0x4604,
+        0x4644, 0x46A4, 0x46E4, 0x4724,
+        0x4764, 0x47A4, 0x47E4, 0x4824, /* 176 */
+        0x4864, 0x48A4, 0x48E4, 0x4924,
+        0x4964, 0x49A4, 0x49E4, 0x4A24,
+        0x4A64, 0x4AA4, 0x4AE4, 0x4B23,
+        0x4B63, 0x4BA3, 0x4BE3, 0x4C23, /* 192 */
+        0x4C63, 0x4CA3, 0x4CE3, 0x4D23,
+        0x4D63, 0x4DA3, 0x4DE3, 0x4E23,
+        0x4E63, 0x4EA3, 0x4EE3, 0x4F23,
+        0x4F63, 0x4FC3, 0x5003, 0x5043, /* 208 */
+        0x5083, 0x50C3, 0x5103, 0x5143,
+        0x5183, 0x51E2, 0x5222, 0x5262,
+        0x52A2, 0x52E2, 0x5342, 0x5382,
+        0x53C2, 0x5402, 0x5462, 0x54A2, /* 224 */
+        0x5502, 0x5542, 0x55A2, 0x55E2,
+        0x5642, 0x5682, 0x56E2, 0x5722,
+        0x5782, 0x57E1, 0x5841, 0x58A1,
+        0x5901, 0x5961, 0x59C1, 0x5A21, /* 240 */
+        0x5AA1, 0x5B01, 0x5B81, 0x5BE1,
+        0x5C61, 0x5D01, 0x5D80, 0x5E20,
+        0x5EE0, 0x5FA0, 0x6080, 0x61C0,
+};
+
+const u16 b43_tab_noisea2[] = {
+        0x0001, 0x0001, 0x0001, 0xFFFE,
+        0xFFFE, 0x3FFF, 0x1000, 0x0393,
+};
+
+const u16 b43_tab_noisea3[] = {
+        0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
+        0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
+};
+
+const u16 b43_tab_noiseg1[] = {
+        0x013C, 0x01F5, 0x031A, 0x0631,
+        0x0001, 0x0001, 0x0001, 0x0001,
+};
+
+const u16 b43_tab_noiseg2[] = {
+        0x5484, 0x3C40, 0x0000, 0x0000,
+        0x0000, 0x0000, 0x0000, 0x0000,
+};
+
+const u16 b43_tab_noisescaleg1[] = {
+        0x6C77, 0x5162, 0x3B40, 0x3335, /* 0 */
+        0x2F2D, 0x2A2A, 0x2527, 0x1F21,
+        0x1A1D, 0x1719, 0x1616, 0x1414,
+        0x1414, 0x1400, 0x1414, 0x1614,
+        0x1716, 0x1A19, 0x1F1D, 0x2521, /* 16 */
+        0x2A27, 0x2F2A, 0x332D, 0x3B35,
+        0x5140, 0x6C62, 0x0077,
+};
+
+const u16 b43_tab_noisescaleg2[] = {
+        0xD8DD, 0xCBD4, 0xBCC0, 0XB6B7, /* 0 */
+        0xB2B0, 0xADAD, 0xA7A9, 0x9FA1,
+        0x969B, 0x9195, 0x8F8F, 0x8A8A,
+        0x8A8A, 0x8A00, 0x8A8A, 0x8F8A,
+        0x918F, 0x9695, 0x9F9B, 0xA7A1, /* 16 */
+        0xADA9, 0xB2AD, 0xB6B0, 0xBCB7,
+        0xCBC0, 0xD8D4, 0x00DD,
+};
+
+const u16 b43_tab_noisescaleg3[] = {
+        0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 0 */
+        0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
+        0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
+        0xA4A4, 0xA400, 0xA4A4, 0xA4A4,
+        0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4, /* 16 */
+        0xA4A4, 0xA4A4, 0xA4A4, 0xA4A4,
+        0xA4A4, 0xA4A4, 0x00A4,
+};
+
+const u16 b43_tab_sigmasqr1[] = {
+        0x007A, 0x0075, 0x0071, 0x006C, /* 0 */
+        0x0067, 0x0063, 0x005E, 0x0059,
+        0x0054, 0x0050, 0x004B, 0x0046,
+        0x0042, 0x003D, 0x003D, 0x003D,
+        0x003D, 0x003D, 0x003D, 0x003D, /* 16 */
+        0x003D, 0x003D, 0x003D, 0x003D,
+        0x003D, 0x003D, 0x0000, 0x003D,
+        0x003D, 0x003D, 0x003D, 0x003D,
+        0x003D, 0x003D, 0x003D, 0x003D, /* 32 */
+        0x003D, 0x003D, 0x003D, 0x003D,
+        0x0042, 0x0046, 0x004B, 0x0050,
+        0x0054, 0x0059, 0x005E, 0x0063,
+        0x0067, 0x006C, 0x0071, 0x0075, /* 48 */
+        0x007A,
+};
+
+const u16 b43_tab_sigmasqr2[] = {
+        0x00DE, 0x00DC, 0x00DA, 0x00D8, /* 0 */
+        0x00D6, 0x00D4, 0x00D2, 0x00CF,
+        0x00CD, 0x00CA, 0x00C7, 0x00C4,
+        0x00C1, 0x00BE, 0x00BE, 0x00BE,
+        0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 16 */
+        0x00BE, 0x00BE, 0x00BE, 0x00BE,
+        0x00BE, 0x00BE, 0x0000, 0x00BE,
+        0x00BE, 0x00BE, 0x00BE, 0x00BE,
+        0x00BE, 0x00BE, 0x00BE, 0x00BE, /* 32 */
+        0x00BE, 0x00BE, 0x00BE, 0x00BE,
+        0x00C1, 0x00C4, 0x00C7, 0x00CA,
+        0x00CD, 0x00CF, 0x00D2, 0x00D4,
+        0x00D6, 0x00D8, 0x00DA, 0x00DC, /* 48 */
+        0x00DE,
+};
+
+static inline void assert_sizes(void)
+{
+        BUILD_BUG_ON(B43_TAB_ROTOR_SIZE != ARRAY_SIZE(b43_tab_rotor));
+        BUILD_BUG_ON(B43_TAB_RETARD_SIZE != ARRAY_SIZE(b43_tab_retard));
+        BUILD_BUG_ON(B43_TAB_FINEFREQA_SIZE != ARRAY_SIZE(b43_tab_finefreqa));
+        BUILD_BUG_ON(B43_TAB_FINEFREQG_SIZE != ARRAY_SIZE(b43_tab_finefreqg));
+        BUILD_BUG_ON(B43_TAB_NOISEA2_SIZE != ARRAY_SIZE(b43_tab_noisea2));
+        BUILD_BUG_ON(B43_TAB_NOISEA3_SIZE != ARRAY_SIZE(b43_tab_noisea3));
+        BUILD_BUG_ON(B43_TAB_NOISEG1_SIZE != ARRAY_SIZE(b43_tab_noiseg1));
+        BUILD_BUG_ON(B43_TAB_NOISEG2_SIZE != ARRAY_SIZE(b43_tab_noiseg2));
+        BUILD_BUG_ON(B43_TAB_NOISESCALEG_SIZE !=
+                     ARRAY_SIZE(b43_tab_noisescaleg1));
+        BUILD_BUG_ON(B43_TAB_NOISESCALEG_SIZE !=
+                     ARRAY_SIZE(b43_tab_noisescaleg2));
+        BUILD_BUG_ON(B43_TAB_NOISESCALEG_SIZE !=
+                     ARRAY_SIZE(b43_tab_noisescaleg3));
+        BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr1));
+        BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr2));
+}
+
+u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset)
+{
+        assert_sizes();
+
+        b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
+        return b43_phy_read(dev, B43_PHY_OTABLEI);
+}
+
+void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
+                         u16 offset, u16 value)
+{
+        b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
+        b43_phy_write(dev, B43_PHY_OTABLEI, value);
+}
+
+u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
+{
+        u32 ret;
+
+        b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
+        ret = b43_phy_read(dev, B43_PHY_OTABLEQ);
+        ret <<= 16;
+        ret |= b43_phy_read(dev, B43_PHY_OTABLEI);
+
+        return ret;
+}
+
+void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
+                         u16 offset, u32 value)
+{
+        b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
+        b43_phy_write(dev, B43_PHY_OTABLEI, value);
+        b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16));
+}
+
+u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset)
+{
+        b43_phy_write(dev, B43_PHY_GTABCTL, table + offset);
+        return b43_phy_read(dev, B43_PHY_GTABDATA);
+}
+
+void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value)
+{
+        b43_phy_write(dev, B43_PHY_GTABCTL, table + offset);
+        b43_phy_write(dev, B43_PHY_GTABDATA, value);
+}
diff --git a/drivers/net/wireless/b43/tables.h b/drivers/net/wireless/b43/tables.h
new file mode 100644
index 000000000000..64635d7b518c
--- /dev/null
+++ b/drivers/net/wireless/b43/tables.h
@@ -0,0 +1,28 @@
+#ifndef B43_TABLES_H_
+#define B43_TABLES_H_
+
+#define B43_TAB_ROTOR_SIZE              53
+extern const u32 b43_tab_rotor[];
+#define B43_TAB_RETARD_SIZE             53
+extern const u32 b43_tab_retard[];
+#define B43_TAB_FINEFREQA_SIZE  256
+extern const u16 b43_tab_finefreqa[];
+#define B43_TAB_FINEFREQG_SIZE  256
+extern const u16 b43_tab_finefreqg[];
+#define B43_TAB_NOISEA2_SIZE    8
+extern const u16 b43_tab_noisea2[];
+#define B43_TAB_NOISEA3_SIZE    8
+extern const u16 b43_tab_noisea3[];
+#define B43_TAB_NOISEG1_SIZE    8
+extern const u16 b43_tab_noiseg1[];
+#define B43_TAB_NOISEG2_SIZE    8
+extern const u16 b43_tab_noiseg2[];
+#define B43_TAB_NOISESCALEG_SIZE        27
+extern const u16 b43_tab_noisescaleg1[];
+extern const u16 b43_tab_noisescaleg2[];
+extern const u16 b43_tab_noisescaleg3[];
+#define B43_TAB_SIGMASQR_SIZE   53
+extern const u16 b43_tab_sigmasqr1[];
+extern const u16 b43_tab_sigmasqr2[];
+
+#endif /* B43_TABLES_H_ */
diff --git a/drivers/net/wireless/b43/xmit.c b/drivers/net/wireless/b43/xmit.c
new file mode 100644
index 000000000000..e6174b6f11fb
--- /dev/null
+++ b/drivers/net/wireless/b43/xmit.c
@@ -0,0 +1,648 @@
+/*
+
+  Broadcom B43 wireless driver
+
+  Transmission (TX/RX) related functions.
+
+  Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
+  Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
+  Copyright (C) 2005, 2006 Michael Buesch <mb@bu3sch.de>
+  Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
+  Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
+
+  This program is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program; see the file COPYING.  If not, write to
+  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
+  Boston, MA 02110-1301, USA.
+
+*/
+
+#include "xmit.h"
+#include "phy.h"
+#include "dma.h"
+#include "pio.h"
+
+/* Extract the bitrate out of a CCK PLCP header. */
+static u8 b43_plcp_get_bitrate_cck(struct b43_plcp_hdr6 *plcp)
+{
+        switch (plcp->raw[0]) {
+        case 0x0A:
+                return B43_CCK_RATE_1MB;
+        case 0x14:
+                return B43_CCK_RATE_2MB;
+        case 0x37:
+                return B43_CCK_RATE_5MB;
+        case 0x6E:
+                return B43_CCK_RATE_11MB;
+        }
+        B43_WARN_ON(1);
+        return 0;
+}
+
+/* Extract the bitrate out of an OFDM PLCP header. */
+static u8 b43_plcp_get_bitrate_ofdm(struct b43_plcp_hdr6 *plcp)
+{
+        switch (plcp->raw[0] & 0xF) {
+        case 0xB:
+                return B43_OFDM_RATE_6MB;
+        case 0xF:
+                return B43_OFDM_RATE_9MB;
+        case 0xA:
+                return B43_OFDM_RATE_12MB;
+        case 0xE:
+                return B43_OFDM_RATE_18MB;
+        case 0x9:
+                return B43_OFDM_RATE_24MB;
+        case 0xD:
+                return B43_OFDM_RATE_36MB;
+        case 0x8:
+                return B43_OFDM_RATE_48MB;
+        case 0xC:
+                return B43_OFDM_RATE_54MB;
+        }
+        B43_WARN_ON(1);
+        return 0;
+}
+
+u8 b43_plcp_get_ratecode_cck(const u8 bitrate)
+{
+        switch (bitrate) {
+        case B43_CCK_RATE_1MB:
+                return 0x0A;
+        case B43_CCK_RATE_2MB:
+                return 0x14;
+        case B43_CCK_RATE_5MB:
+                return 0x37;
+        case B43_CCK_RATE_11MB:
+                return 0x6E;
+        }
+        B43_WARN_ON(1);
+        return 0;
+}
+
+u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate)
+{
+        switch (bitrate) {
+        case B43_OFDM_RATE_6MB:
+                return 0xB;
+        case B43_OFDM_RATE_9MB:
+                return 0xF;
+        case B43_OFDM_RATE_12MB:
+                return 0xA;
+        case B43_OFDM_RATE_18MB:
+                return 0xE;
+        case B43_OFDM_RATE_24MB:
+                return 0x9;
+        case B43_OFDM_RATE_36MB:
+                return 0xD;
+        case B43_OFDM_RATE_48MB:
+                return 0x8;
+        case B43_OFDM_RATE_54MB:
+                return 0xC;
+        }
+        B43_WARN_ON(1);
+        return 0;
+}
+
+void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
+                           const u16 octets, const u8 bitrate)
+{
+        __le32 *data = &(plcp->data);
+        __u8 *raw = plcp->raw;
+
+        if (b43_is_ofdm_rate(bitrate)) {
+                *data = b43_plcp_get_ratecode_ofdm(bitrate);
+                B43_WARN_ON(octets & 0xF000);
+                *data |= (octets << 5);
+                *data = cpu_to_le32(*data);
+        } else {
+                u32 plen;
+
+                plen = octets * 16 / bitrate;
+                if ((octets * 16 % bitrate) > 0) {
+                        plen++;
+                        if ((bitrate == B43_CCK_RATE_11MB)
+                            && ((octets * 8 % 11) < 4)) {
+                                raw[1] = 0x84;
+                        } else
+                                raw[1] = 0x04;
+                } else
+                        raw[1] = 0x04;
+                *data |= cpu_to_le32(plen << 16);
+                raw[0] = b43_plcp_get_ratecode_cck(bitrate);
+        }
+}
+
+static u8 b43_calc_fallback_rate(u8 bitrate)
+{
+        switch (bitrate) {
+        case B43_CCK_RATE_1MB:
+                return B43_CCK_RATE_1MB;
+        case B43_CCK_RATE_2MB:
+                return B43_CCK_RATE_1MB;
+        case B43_CCK_RATE_5MB:
+                return B43_CCK_RATE_2MB;
+        case B43_CCK_RATE_11MB:
+                return B43_CCK_RATE_5MB;
+        case B43_OFDM_RATE_6MB:
+                return B43_CCK_RATE_5MB;
+        case B43_OFDM_RATE_9MB:
+                return B43_OFDM_RATE_6MB;
+        case B43_OFDM_RATE_12MB:
+                return B43_OFDM_RATE_9MB;
+        case B43_OFDM_RATE_18MB:
+                return B43_OFDM_RATE_12MB;
+        case B43_OFDM_RATE_24MB:
+                return B43_OFDM_RATE_18MB;
+        case B43_OFDM_RATE_36MB:
+                return B43_OFDM_RATE_24MB;
+        case B43_OFDM_RATE_48MB:
+                return B43_OFDM_RATE_36MB;
+        case B43_OFDM_RATE_54MB:
+                return B43_OFDM_RATE_48MB;
+        }
+        B43_WARN_ON(1);
+        return 0;
+}
+
+static void generate_txhdr_fw4(struct b43_wldev *dev,
+                               struct b43_txhdr_fw4 *txhdr,
+                               const unsigned char *fragment_data,
+                               unsigned int fragment_len,
+                               const struct ieee80211_tx_control *txctl,
+                               u16 cookie)
+{
+        const struct b43_phy *phy = &dev->phy;
+        const struct ieee80211_hdr *wlhdr =
+            (const struct ieee80211_hdr *)fragment_data;
+        int use_encryption = (!(txctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT));
+        u16 fctl = le16_to_cpu(wlhdr->frame_control);
+        u8 rate, rate_fb;
+        int rate_ofdm, rate_fb_ofdm;
+        unsigned int plcp_fragment_len;
+        u32 mac_ctl = 0;
+        u16 phy_ctl = 0;
+        u8 extra_ft = 0;
+
+        memset(txhdr, 0, sizeof(*txhdr));
+
+        rate = txctl->tx_rate;
+        rate_ofdm = b43_is_ofdm_rate(rate);
+        rate_fb = (txctl->alt_retry_rate == -1) ? rate : txctl->alt_retry_rate;
+        rate_fb_ofdm = b43_is_ofdm_rate(rate_fb);
+
+        if (rate_ofdm)
+                txhdr->phy_rate = b43_plcp_get_ratecode_ofdm(rate);
+        else
+                txhdr->phy_rate = b43_plcp_get_ratecode_cck(rate);
+        txhdr->mac_frame_ctl = wlhdr->frame_control;
+        memcpy(txhdr->tx_receiver, wlhdr->addr1, 6);
+
+        /* Calculate duration for fallback rate */
+        if ((rate_fb == rate) ||
+            (wlhdr->duration_id & cpu_to_le16(0x8000)) ||
+            (wlhdr->duration_id == cpu_to_le16(0))) {
+                /* If the fallback rate equals the normal rate or the
+                 * dur_id field contains an AID, CFP magic or 0,
+                 * use the original dur_id field. */
+                txhdr->dur_fb = wlhdr->duration_id;
+        } else {
+                int fbrate_base100kbps = B43_RATE_TO_BASE100KBPS(rate_fb);
+                txhdr->dur_fb = ieee80211_generic_frame_duration(dev->wl->hw,
+                                                                 dev->wl->if_id,
+                                                                 fragment_len,
+                                                                 fbrate_base100kbps);
+        }
+
+        plcp_fragment_len = fragment_len + FCS_LEN;
+        if (use_encryption) {
+                u8 key_idx = (u16) (txctl->key_idx);
+                struct b43_key *key;
+                int wlhdr_len;
+                size_t iv_len;
+
+                B43_WARN_ON(key_idx >= dev->max_nr_keys);
+                key = &(dev->key[key_idx]);
+                B43_WARN_ON(!key->keyconf);
+
+                /* Hardware appends ICV. */
+                plcp_fragment_len += txctl->icv_len;
+
+                key_idx = b43_kidx_to_fw(dev, key_idx);
+                mac_ctl |= (key_idx << B43_TX4_MAC_KEYIDX_SHIFT) &
+                           B43_TX4_MAC_KEYIDX;
+                mac_ctl |= (key->algorithm << B43_TX4_MAC_KEYALG_SHIFT) &
+                           B43_TX4_MAC_KEYALG;
+                wlhdr_len = ieee80211_get_hdrlen(fctl);
+                iv_len = min((size_t) txctl->iv_len,
+                             ARRAY_SIZE(txhdr->iv));
+                memcpy(txhdr->iv, ((u8 *) wlhdr) + wlhdr_len, iv_len);
+        }
+        b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp),
+                              plcp_fragment_len, rate);
+        b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->plcp_fb),
+                              plcp_fragment_len, rate_fb);
+
+        /* Extra Frame Types */
+        if (rate_fb_ofdm)
+                extra_ft |= B43_TX4_EFT_FBOFDM;
+
+        /* Set channel radio code. Note that the micrcode ORs 0x100 to
+         * this value before comparing it to the value in SHM, if this
+         * is a 5Ghz packet.
+         */
+        txhdr->chan_radio_code = phy->channel;
+
+        /* PHY TX Control word */
+        if (rate_ofdm)
+                phy_ctl |= B43_TX4_PHY_OFDM;
+        if (dev->short_preamble)
+                phy_ctl |= B43_TX4_PHY_SHORTPRMBL;
+        switch (txctl->antenna_sel_tx) {
+        case 0:
+                phy_ctl |= B43_TX4_PHY_ANTLAST;
+                break;
+        case 1:
+                phy_ctl |= B43_TX4_PHY_ANT0;
+                break;
+        case 2:
+                phy_ctl |= B43_TX4_PHY_ANT1;
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+
+        /* MAC control */
+        if (!(txctl->flags & IEEE80211_TXCTL_NO_ACK))
+                mac_ctl |= B43_TX4_MAC_ACK;
+        if (!(((fctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_CTL) &&
+              ((fctl & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_PSPOLL)))
+                mac_ctl |= B43_TX4_MAC_HWSEQ;
+        if (txctl->flags & IEEE80211_TXCTL_FIRST_FRAGMENT)
+                mac_ctl |= B43_TX4_MAC_STMSDU;
+        if (phy->type == B43_PHYTYPE_A)
+                mac_ctl |= B43_TX4_MAC_5GHZ;
+
+        /* Generate the RTS or CTS-to-self frame */
+        if ((txctl->flags & IEEE80211_TXCTL_USE_RTS_CTS) ||
+            (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)) {
+                unsigned int len;
+                struct ieee80211_hdr *hdr;
+                int rts_rate, rts_rate_fb;
+                int rts_rate_ofdm, rts_rate_fb_ofdm;
+
+                rts_rate = txctl->rts_cts_rate;
+                rts_rate_ofdm = b43_is_ofdm_rate(rts_rate);
+                rts_rate_fb = b43_calc_fallback_rate(rts_rate);
+                rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb);
+
+                if (txctl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
+                        ieee80211_ctstoself_get(dev->wl->hw, dev->wl->if_id,
+                                                fragment_data, fragment_len,
+                                                txctl,
+                                                (struct ieee80211_cts *)(txhdr->
+                                                                         rts_frame));
+                        mac_ctl |= B43_TX4_MAC_SENDCTS;
+                        len = sizeof(struct ieee80211_cts);
+                } else {
+                        ieee80211_rts_get(dev->wl->hw, dev->wl->if_id,
+                                          fragment_data, fragment_len, txctl,
+                                          (struct ieee80211_rts *)(txhdr->
+                                                                   rts_frame));
+                        mac_ctl |= B43_TX4_MAC_SENDRTS;
+                        len = sizeof(struct ieee80211_rts);
+                }
+                len += FCS_LEN;
+                b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->
+                                                               rts_plcp), len,
+                                      rts_rate);
+                b43_generate_plcp_hdr((struct b43_plcp_hdr4 *)(&txhdr->
+                                                               rts_plcp_fb),
+                                      len, rts_rate_fb);
+                hdr = (struct ieee80211_hdr *)(&txhdr->rts_frame);
+                txhdr->rts_dur_fb = hdr->duration_id;
+                if (rts_rate_ofdm) {
+                        extra_ft |= B43_TX4_EFT_RTSOFDM;
+                        txhdr->phy_rate_rts =
+                            b43_plcp_get_ratecode_ofdm(rts_rate);
+                } else
+                        txhdr->phy_rate_rts =
+                            b43_plcp_get_ratecode_cck(rts_rate);
+                if (rts_rate_fb_ofdm)
+                        extra_ft |= B43_TX4_EFT_RTSFBOFDM;
+                mac_ctl |= B43_TX4_MAC_LONGFRAME;
+        }
+
+        /* Magic cookie */
+        txhdr->cookie = cpu_to_le16(cookie);
+
+        /* Apply the bitfields */
+        txhdr->mac_ctl = cpu_to_le32(mac_ctl);
+        txhdr->phy_ctl = cpu_to_le16(phy_ctl);
+        txhdr->extra_ft = extra_ft;
+}
+
+void b43_generate_txhdr(struct b43_wldev *dev,
+                        u8 * txhdr,
+                        const unsigned char *fragment_data,
+                        unsigned int fragment_len,
+                        const struct ieee80211_tx_control *txctl, u16 cookie)
+{
+        generate_txhdr_fw4(dev, (struct b43_txhdr_fw4 *)txhdr,
+                           fragment_data, fragment_len, txctl, cookie);
+}
+
+static s8 b43_rssi_postprocess(struct b43_wldev *dev,
+                               u8 in_rssi, int ofdm,
+                               int adjust_2053, int adjust_2050)
+{
+        struct b43_phy *phy = &dev->phy;
+        s32 tmp;
+
+        switch (phy->radio_ver) {
+        case 0x2050:
+                if (ofdm) {
+                        tmp = in_rssi;
+                        if (tmp > 127)
+                                tmp -= 256;
+                        tmp *= 73;
+                        tmp /= 64;
+                        if (adjust_2050)
+                                tmp += 25;
+                        else
+                                tmp -= 3;
+                } else {
+                        if (dev->dev->bus->sprom.r1.
+                            boardflags_lo & B43_BFL_RSSI) {
+                                if (in_rssi > 63)
+                                        in_rssi = 63;
+                                tmp = phy->nrssi_lt[in_rssi];
+                                tmp = 31 - tmp;
+                                tmp *= -131;
+                                tmp /= 128;
+                                tmp -= 57;
+                        } else {
+                                tmp = in_rssi;
+                                tmp = 31 - tmp;
+                                tmp *= -149;
+                                tmp /= 128;
+                                tmp -= 68;
+                        }
+                        if (phy->type == B43_PHYTYPE_G && adjust_2050)
+                                tmp += 25;
+                }
+                break;
+        case 0x2060:
+                if (in_rssi > 127)
+                        tmp = in_rssi - 256;
+                else
+                        tmp = in_rssi;
+                break;
+        default:
+                tmp = in_rssi;
+                tmp -= 11;
+                tmp *= 103;
+                tmp /= 64;
+                if (adjust_2053)
+                        tmp -= 109;
+                else
+                        tmp -= 83;
+        }
+
+        return (s8) tmp;
+}
+
+//TODO
+#if 0
+static s8 b43_rssinoise_postprocess(struct b43_wldev *dev, u8 in_rssi)
+{
+        struct b43_phy *phy = &dev->phy;
+        s8 ret;
+
+        if (phy->type == B43_PHYTYPE_A) {
+                //TODO: Incomplete specs.
+                ret = 0;
+        } else
+                ret = b43_rssi_postprocess(dev, in_rssi, 0, 1, 1);
+
+        return ret;
+}
+#endif
+
+void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr)
+{
+        struct ieee80211_rx_status status;
+        struct b43_plcp_hdr6 *plcp;
+        struct ieee80211_hdr *wlhdr;
+        const struct b43_rxhdr_fw4 *rxhdr = _rxhdr;
+        u16 fctl;
+        u16 phystat0, phystat3, chanstat, mactime;
+        u32 macstat;
+        u16 chanid;
+        u8 jssi;
+        int padding;
+
+        memset(&status, 0, sizeof(status));
+
+        /* Get metadata about the frame from the header. */
+        phystat0 = le16_to_cpu(rxhdr->phy_status0);
+        phystat3 = le16_to_cpu(rxhdr->phy_status3);
+        jssi = rxhdr->jssi;
+        macstat = le32_to_cpu(rxhdr->mac_status);
+        mactime = le16_to_cpu(rxhdr->mac_time);
+        chanstat = le16_to_cpu(rxhdr->channel);
+
+        if (macstat & B43_RX_MAC_FCSERR)
+                dev->wl->ieee_stats.dot11FCSErrorCount++;
+        if (macstat & B43_RX_MAC_DECERR) {
+                /* Decryption with the given key failed.
+                 * Drop the packet. We also won't be able to decrypt it with
+                 * the key in software. */
+                goto drop;
+        }
+
+        /* Skip PLCP and padding */
+        padding = (macstat & B43_RX_MAC_PADDING) ? 2 : 0;
+        if (unlikely(skb->len < (sizeof(struct b43_plcp_hdr6) + padding))) {
+                b43dbg(dev->wl, "RX: Packet size underrun (1)\n");
+                goto drop;
+        }
+        plcp = (struct b43_plcp_hdr6 *)(skb->data + padding);
+        skb_pull(skb, sizeof(struct b43_plcp_hdr6) + padding);
+        /* The skb contains the Wireless Header + payload data now */
+        if (unlikely(skb->len < (2 + 2 + 6 /*minimum hdr */  + FCS_LEN))) {
+                b43dbg(dev->wl, "RX: Packet size underrun (2)\n");
+                goto drop;
+        }
+        wlhdr = (struct ieee80211_hdr *)(skb->data);
+        fctl = le16_to_cpu(wlhdr->frame_control);
+        skb_trim(skb, skb->len - FCS_LEN);
+
+        if (macstat & B43_RX_MAC_DEC) {
+                unsigned int keyidx;
+                int wlhdr_len;
+
+                keyidx = ((macstat & B43_RX_MAC_KEYIDX)
+                          >> B43_RX_MAC_KEYIDX_SHIFT);
+                /* We must adjust the key index here. We want the "physical"
+                 * key index, but the ucode passed it slightly different.
+                 */
+                keyidx = b43_kidx_to_raw(dev, keyidx);
+                B43_WARN_ON(keyidx >= dev->max_nr_keys);
+
+                if (dev->key[keyidx].algorithm != B43_SEC_ALGO_NONE) {
+                        wlhdr_len = ieee80211_get_hdrlen(fctl);
+                        if (unlikely(skb->len < (wlhdr_len + 3))) {
+                                b43dbg(dev->wl,
+                                       "RX: Packet size underrun (3)\n");
+                                goto drop;
+                        }
+                        status.flag |= RX_FLAG_DECRYPTED;
+                }
+        }
+
+        status.ssi = b43_rssi_postprocess(dev, jssi,
+                                          (phystat0 & B43_RX_PHYST0_OFDM),
+                                          (phystat0 & B43_RX_PHYST0_GAINCTL),
+                                          (phystat3 & B43_RX_PHYST3_TRSTATE));
+        status.noise = dev->stats.link_noise;
+        /* the next line looks wrong, but is what mac80211 wants */
+        status.signal = (jssi * 100) / B43_RX_MAX_SSI;
+        if (phystat0 & B43_RX_PHYST0_OFDM)
+                status.rate = b43_plcp_get_bitrate_ofdm(plcp);
+        else
+                status.rate = b43_plcp_get_bitrate_cck(plcp);
+        status.antenna = !!(phystat0 & B43_RX_PHYST0_ANT);
+        status.mactime = mactime;
+
+        chanid = (chanstat & B43_RX_CHAN_ID) >> B43_RX_CHAN_ID_SHIFT;
+        switch (chanstat & B43_RX_CHAN_PHYTYPE) {
+        case B43_PHYTYPE_A:
+                status.phymode = MODE_IEEE80211A;
+                status.freq = chanid;
+                status.channel = b43_freq_to_channel_a(chanid);
+                break;
+        case B43_PHYTYPE_B:
+                status.phymode = MODE_IEEE80211B;
+                status.freq = chanid + 2400;
+                status.channel = b43_freq_to_channel_bg(chanid + 2400);
+                break;
+        case B43_PHYTYPE_G:
+                status.phymode = MODE_IEEE80211G;
+                status.freq = chanid + 2400;
+                status.channel = b43_freq_to_channel_bg(chanid + 2400);
+                break;
+        default:
+                B43_WARN_ON(1);
+        }
+
+        dev->stats.last_rx = jiffies;
+        ieee80211_rx_irqsafe(dev->wl->hw, skb, &status);
+
+        return;
+drop:
+        b43dbg(dev->wl, "RX: Packet dropped\n");
+        dev_kfree_skb_any(skb);
+}
+
+void b43_handle_txstatus(struct b43_wldev *dev,
+                         const struct b43_txstatus *status)
+{
+        b43_debugfs_log_txstat(dev, status);
+
+        if (status->intermediate)
+                return;
+        if (status->for_ampdu)
+                return;
+        if (!status->acked)
+                dev->wl->ieee_stats.dot11ACKFailureCount++;
+        if (status->rts_count) {
+                if (status->rts_count == 0xF)   //FIXME
+                        dev->wl->ieee_stats.dot11RTSFailureCount++;
+                else
+                        dev->wl->ieee_stats.dot11RTSSuccessCount++;
+        }
+
+        if (b43_using_pio(dev))
+                b43_pio_handle_txstatus(dev, status);
+        else
+                b43_dma_handle_txstatus(dev, status);
+}
+
+/* Handle TX status report as received through DMA/PIO queues */
+void b43_handle_hwtxstatus(struct b43_wldev *dev,
+                           const struct b43_hwtxstatus *hw)
+{
+        struct b43_txstatus status;
+        u8 tmp;
+
+        status.cookie = le16_to_cpu(hw->cookie);
+        status.seq = le16_to_cpu(hw->seq);
+        status.phy_stat = hw->phy_stat;
+        tmp = hw->count;
+        status.frame_count = (tmp >> 4);
+        status.rts_count = (tmp & 0x0F);
+        tmp = hw->flags;
+        status.supp_reason = ((tmp & 0x1C) >> 2);
+        status.pm_indicated = !!(tmp & 0x80);
+        status.intermediate = !!(tmp & 0x40);
+        status.for_ampdu = !!(tmp & 0x20);
+        status.acked = !!(tmp & 0x02);
+
+        b43_handle_txstatus(dev, &status);
+}
+
+/* Stop any TX operation on the device (suspend the hardware queues) */
+void b43_tx_suspend(struct b43_wldev *dev)
+{
+        if (b43_using_pio(dev))
+                b43_pio_freeze_txqueues(dev);
+        else
+                b43_dma_tx_suspend(dev);
+}
+
+/* Resume any TX operation on the device (resume the hardware queues) */
+void b43_tx_resume(struct b43_wldev *dev)
+{
+        if (b43_using_pio(dev))
+                b43_pio_thaw_txqueues(dev);
+        else
+                b43_dma_tx_resume(dev);
+}
+
+#if 0
+static void upload_qos_parms(struct b43_wldev *dev,
+                             const u16 * parms, u16 offset)
+{
+        int i;
+
+        for (i = 0; i < B43_NR_QOSPARMS; i++) {
+                b43_shm_write16(dev, B43_SHM_SHARED,
+                                offset + (i * 2), parms[i]);
+        }
+}
+#endif
+
+/* Initialize the QoS parameters */
+void b43_qos_init(struct b43_wldev *dev)
+{
+        /* FIXME: This function must probably be called from the mac80211
+         * config callback. */
+        return;
+
+        b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
+        //FIXME kill magic
+        b43_write16(dev, 0x688, b43_read16(dev, 0x688) | 0x4);
+
+        /*TODO: We might need some stack support here to get the values. */
+}
diff --git a/drivers/net/wireless/b43/xmit.h b/drivers/net/wireless/b43/xmit.h
new file mode 100644
index 000000000000..03bddd251618
--- /dev/null
+++ b/drivers/net/wireless/b43/xmit.h
@@ -0,0 +1,250 @@
+#ifndef B43_XMIT_H_
+#define B43_XMIT_H_
+
+#include "main.h"
+
+#define _b43_declare_plcp_hdr(size) \
+        struct b43_plcp_hdr##size {             \
+                union {                         \
+                        __le32 data;            \
+                        __u8 raw[size];         \
+                } __attribute__((__packed__));  \
+        } __attribute__((__packed__))
+
+/* struct b43_plcp_hdr4 */
+_b43_declare_plcp_hdr(4);
+/* struct b43_plcp_hdr6 */
+_b43_declare_plcp_hdr(6);
+
+#undef _b43_declare_plcp_hdr
+
+/* TX header for v4 firmware */
+struct b43_txhdr_fw4 {
+        __le32 mac_ctl;         /* MAC TX control */
+        __le16 mac_frame_ctl;   /* Copy of the FrameControl field */
+        __le16 tx_fes_time_norm;        /* TX FES Time Normal */
+        __le16 phy_ctl;         /* PHY TX control */
+        __le16 phy_ctl_0;       /* Unused */
+        __le16 phy_ctl_1;       /* Unused */
+        __le16 phy_ctl_rts_0;   /* Unused */
+        __le16 phy_ctl_rts_1;   /* Unused */
+        __u8 phy_rate;          /* PHY rate */
+        __u8 phy_rate_rts;      /* PHY rate for RTS/CTS */
+        __u8 extra_ft;          /* Extra Frame Types */
+        __u8 chan_radio_code;   /* Channel Radio Code */
+        __u8 iv[16];            /* Encryption IV */
+        __u8 tx_receiver[6];    /* TX Frame Receiver address */
+        __le16 tx_fes_time_fb;  /* TX FES Time Fallback */
+        struct b43_plcp_hdr6 rts_plcp_fb;       /* RTS fallback PLCP */
+        __le16 rts_dur_fb;      /* RTS fallback duration */
+        struct b43_plcp_hdr6 plcp_fb;   /* Fallback PLCP */
+        __le16 dur_fb;          /* Fallback duration */
+        __le16 mm_dur_time;     /* Unused */
+        __le16 mm_dur_time_fb;  /* Unused */
+        __le32 time_stamp;      /* Timestamp */
+         PAD_BYTES(2);
+        __le16 cookie;          /* TX frame cookie */
+        __le16 tx_status;       /* TX status */
+        struct b43_plcp_hdr6 rts_plcp;  /* RTS PLCP */
+        __u8 rts_frame[16];     /* The RTS frame (if used) */
+         PAD_BYTES(2);
+        struct b43_plcp_hdr6 plcp;      /* Main PLCP */
+} __attribute__ ((__packed__));
+
+/* MAC TX control */
+#define B43_TX4_MAC_KEYIDX              0x0FF00000      /* Security key index */
+#define B43_TX4_MAC_KEYIDX_SHIFT        20
+#define B43_TX4_MAC_KEYALG              0x00070000      /* Security key algorithm */
+#define B43_TX4_MAC_KEYALG_SHIFT        16
+#define B43_TX4_MAC_LIFETIME    0x00001000
+#define B43_TX4_MAC_FRAMEBURST  0x00000800
+#define B43_TX4_MAC_SENDCTS             0x00000400
+#define B43_TX4_MAC_AMPDU               0x00000300
+#define B43_TX4_MAC_AMPDU_SHIFT 8
+#define B43_TX4_MAC_5GHZ                0x00000080
+#define B43_TX4_MAC_IGNPMQ              0x00000020
+#define B43_TX4_MAC_HWSEQ               0x00000010      /* Use Hardware Sequence Number */
+#define B43_TX4_MAC_STMSDU              0x00000008      /* Start MSDU */
+#define B43_TX4_MAC_SENDRTS             0x00000004
+#define B43_TX4_MAC_LONGFRAME   0x00000002
+#define B43_TX4_MAC_ACK         0x00000001
+
+/* Extra Frame Types */
+#define B43_TX4_EFT_FBOFDM              0x0001  /* Data frame fallback rate type */
+#define B43_TX4_EFT_RTSOFDM             0x0004  /* RTS/CTS rate type */
+#define B43_TX4_EFT_RTSFBOFDM   0x0010  /* RTS/CTS fallback rate type */
+
+/* PHY TX control word */
+#define B43_TX4_PHY_OFDM                0x0001  /* Data frame rate type */
+#define B43_TX4_PHY_SHORTPRMBL  0x0010  /* Use short preamble */
+#define B43_TX4_PHY_ANT         0x03C0  /* Antenna selection */
+#define  B43_TX4_PHY_ANT0               0x0000  /* Use antenna 0 */
+#define  B43_TX4_PHY_ANT1               0x0100  /* Use antenna 1 */
+#define  B43_TX4_PHY_ANTLAST    0x0300  /* Use last used antenna */
+
+void b43_generate_txhdr(struct b43_wldev *dev,
+                        u8 * txhdr,
+                        const unsigned char *fragment_data,
+                        unsigned int fragment_len,
+                        const struct ieee80211_tx_control *txctl, u16 cookie);
+
+/* Transmit Status */
+struct b43_txstatus {
+        u16 cookie;             /* The cookie from the txhdr */
+        u16 seq;                /* Sequence number */
+        u8 phy_stat;            /* PHY TX status */
+        u8 frame_count;         /* Frame transmit count */
+        u8 rts_count;           /* RTS transmit count */
+        u8 supp_reason;         /* Suppression reason */
+        /* flags */
+        u8 pm_indicated;        /* PM mode indicated to AP */
+        u8 intermediate;        /* Intermediate status notification (not final) */
+        u8 for_ampdu;           /* Status is for an AMPDU (afterburner) */
+        u8 acked;               /* Wireless ACK received */
+};
+
+/* txstatus supp_reason values */
+enum {
+        B43_TXST_SUPP_NONE,     /* Not suppressed */
+        B43_TXST_SUPP_PMQ,      /* Suppressed due to PMQ entry */
+        B43_TXST_SUPP_FLUSH,    /* Suppressed due to flush request */
+        B43_TXST_SUPP_PREV,     /* Previous fragment failed */
+        B43_TXST_SUPP_CHAN,     /* Channel mismatch */
+        B43_TXST_SUPP_LIFE,     /* Lifetime expired */
+        B43_TXST_SUPP_UNDER,    /* Buffer underflow */
+        B43_TXST_SUPP_ABNACK,   /* Afterburner NACK */
+};
+
+/* Transmit Status as received through DMA/PIO on old chips */
+struct b43_hwtxstatus {
+        PAD_BYTES(4);
+        __le16 cookie;
+        u8 flags;
+        u8 count;
+         PAD_BYTES(2);
+        __le16 seq;
+        u8 phy_stat;
+         PAD_BYTES(1);
+} __attribute__ ((__packed__));
+
+/* Receive header for v4 firmware. */
+struct b43_rxhdr_fw4 {
+        __le16 frame_len;       /* Frame length */
+         PAD_BYTES(2);
+        __le16 phy_status0;     /* PHY RX Status 0 */
+        __u8 jssi;              /* PHY RX Status 1: JSSI */
+        __u8 sig_qual;          /* PHY RX Status 1: Signal Quality */
+        __le16 phy_status2;     /* PHY RX Status 2 */
+        __le16 phy_status3;     /* PHY RX Status 3 */
+        __le32 mac_status;      /* MAC RX status */
+        __le16 mac_time;
+        __le16 channel;
+} __attribute__ ((__packed__));
+
+/* PHY RX Status 0 */
+#define B43_RX_PHYST0_GAINCTL   0x4000  /* Gain Control */
+#define B43_RX_PHYST0_PLCPHCF   0x0200
+#define B43_RX_PHYST0_PLCPFV    0x0100
+#define B43_RX_PHYST0_SHORTPRMBL        0x0080  /* Received with Short Preamble */
+#define B43_RX_PHYST0_LCRS              0x0040
+#define B43_RX_PHYST0_ANT               0x0020  /* Antenna */
+#define B43_RX_PHYST0_UNSRATE   0x0010
+#define B43_RX_PHYST0_CLIP              0x000C
+#define B43_RX_PHYST0_CLIP_SHIFT        2
+#define B43_RX_PHYST0_FTYPE             0x0003  /* Frame type */
+#define  B43_RX_PHYST0_CCK              0x0000  /* Frame type: CCK */
+#define  B43_RX_PHYST0_OFDM             0x0001  /* Frame type: OFDM */
+#define  B43_RX_PHYST0_PRE_N    0x0002  /* Pre-standard N-PHY frame */
+#define  B43_RX_PHYST0_STD_N    0x0003  /* Standard N-PHY frame */
+
+/* PHY RX Status 2 */
+#define B43_RX_PHYST2_LNAG              0xC000  /* LNA Gain */
+#define B43_RX_PHYST2_LNAG_SHIFT        14
+#define B43_RX_PHYST2_PNAG              0x3C00  /* PNA Gain */
+#define B43_RX_PHYST2_PNAG_SHIFT        10
+#define B43_RX_PHYST2_FOFF              0x03FF  /* F offset */
+
+/* PHY RX Status 3 */
+#define B43_RX_PHYST3_DIGG              0x1800  /* DIG Gain */
+#define B43_RX_PHYST3_DIGG_SHIFT        11
+#define B43_RX_PHYST3_TRSTATE   0x0400  /* TR state */
+
+/* MAC RX Status */
+#define B43_RX_MAC_BEACONSENT   0x00008000      /* Beacon send flag */
+#define B43_RX_MAC_KEYIDX               0x000007E0      /* Key index */
+#define B43_RX_MAC_KEYIDX_SHIFT 5
+#define B43_RX_MAC_DECERR               0x00000010      /* Decrypt error */
+#define B43_RX_MAC_DEC          0x00000008      /* Decryption attempted */
+#define B43_RX_MAC_PADDING              0x00000004      /* Pad bytes present */
+#define B43_RX_MAC_RESP         0x00000002      /* Response frame transmitted */
+#define B43_RX_MAC_FCSERR               0x00000001      /* FCS error */
+
+/* RX channel */
+#define B43_RX_CHAN_GAIN                0xFC00  /* Gain */
+#define B43_RX_CHAN_GAIN_SHIFT  10
+#define B43_RX_CHAN_ID          0x03FC  /* Channel ID */
+#define B43_RX_CHAN_ID_SHIFT    2
+#define B43_RX_CHAN_PHYTYPE             0x0003  /* PHY type */
+
+u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
+u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
+
+void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
+                           const u16 octets, const u8 bitrate);
+
+void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
+
+void b43_handle_txstatus(struct b43_wldev *dev,
+                         const struct b43_txstatus *status);
+
+void b43_handle_hwtxstatus(struct b43_wldev *dev,
+                           const struct b43_hwtxstatus *hw);
+
+void b43_tx_suspend(struct b43_wldev *dev);
+void b43_tx_resume(struct b43_wldev *dev);
+
+#define B43_NR_QOSPARMS         22
+enum {
+        B43_QOSPARM_TXOP = 0,
+        B43_QOSPARM_CWMIN,
+        B43_QOSPARM_CWMAX,
+        B43_QOSPARM_CWCUR,
+        B43_QOSPARM_AIFS,
+        B43_QOSPARM_BSLOTS,
+        B43_QOSPARM_REGGAP,
+        B43_QOSPARM_STATUS,
+};
+void b43_qos_init(struct b43_wldev *dev);
+
+/* Helper functions for converting the key-table index from "firmware-format"
+ * to "raw-format" and back. The firmware API changed for this at some revision.
+ * We need to account for that here. */
+static inline int b43_new_kidx_api(struct b43_wldev *dev)
+{
+        /* FIXME: Not sure the change was at rev 351 */
+        return (dev->fw.rev >= 351);
+}
+static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
+{
+        u8 firmware_kidx;
+        if (b43_new_kidx_api(dev)) {
+                firmware_kidx = raw_kidx;
+        } else {
+                if (raw_kidx >= 4)      /* Is per STA key? */
+                        firmware_kidx = raw_kidx - 4;
+                else
+                        firmware_kidx = raw_kidx;       /* TX default key */
+        }
+        return firmware_kidx;
+}
+static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
+{
+        u8 raw_kidx;
+        if (b43_new_kidx_api(dev))
+                raw_kidx = firmware_kidx;
+        else
+                raw_kidx = firmware_kidx + 4;   /* RX default keys or per STA keys */
+        return raw_kidx;
+}
+
+#endif /* B43_XMIT_H_ */