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authorMichael Buesch <mb@bu3sch.de>2008-08-27 12:53:02 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-08-29 16:24:12 -0400
commitef1a628d83fc0423c36e773281162be790503168 (patch)
tree436d3d7d91434febb1813dcea16060e6937288b9 /drivers/net/wireless/b43
parent35e032d82f3e2a9b0d92077b4fbc97166525ed53 (diff)
b43: Implement dynamic PHY API
This patch implements a dynamic "ops" based PHY API. This is needed in order to conveniently support future PHY types to avoid the "switch"-hell. This patch does not change any functionality. It just moves lots of code from one place to another and adjusts it for the changed data structures. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r--drivers/net/wireless/b43/Makefile4
-rw-r--r--drivers/net/wireless/b43/b43.h127
-rw-r--r--drivers/net/wireless/b43/debugfs.c79
-rw-r--r--drivers/net/wireless/b43/lo.c120
-rw-r--r--drivers/net/wireless/b43/lo.h4
-rw-r--r--drivers/net/wireless/b43/main.c172
-rw-r--r--drivers/net/wireless/b43/nphy.c143
-rw-r--r--drivers/net/wireless/b43/nphy.h54
-rw-r--r--drivers/net/wireless/b43/phy.c3421
-rw-r--r--drivers/net/wireless/b43/phy.h340
-rw-r--r--drivers/net/wireless/b43/phy_a.c536
-rw-r--r--drivers/net/wireless/b43/phy_a.h124
-rw-r--r--drivers/net/wireless/b43/phy_common.c276
-rw-r--r--drivers/net/wireless/b43/phy_common.h312
-rw-r--r--drivers/net/wireless/b43/phy_g.c3229
-rw-r--r--drivers/net/wireless/b43/phy_g.h201
-rw-r--r--drivers/net/wireless/b43/rfkill.c5
-rw-r--r--drivers/net/wireless/b43/sysfs.c23
-rw-r--r--drivers/net/wireless/b43/tables.c43
-rw-r--r--drivers/net/wireless/b43/tables_nphy.c2
-rw-r--r--drivers/net/wireless/b43/wa.c2
-rw-r--r--drivers/net/wireless/b43/xmit.c6
22 files changed, 4998 insertions, 4225 deletions
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 8c52b0b9862a..fb6ffce03f0a 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -1,7 +1,9 @@
1b43-y += main.o 1b43-y += main.o
2b43-y += tables.o 2b43-y += tables.o
3b43-$(CONFIG_B43_NPHY) += tables_nphy.o 3b43-$(CONFIG_B43_NPHY) += tables_nphy.o
4b43-y += phy.o 4b43-y += phy_common.o
5b43-y += phy_g.o
6b43-y += phy_a.o
5b43-$(CONFIG_B43_NPHY) += nphy.o 7b43-$(CONFIG_B43_NPHY) += nphy.o
6b43-y += sysfs.o 8b43-y += sysfs.o
7b43-y += xmit.o 9b43-y += xmit.o
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index edcdfa366452..fc280157596c 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -12,7 +12,7 @@
12#include "leds.h" 12#include "leds.h"
13#include "rfkill.h" 13#include "rfkill.h"
14#include "lo.h" 14#include "lo.h"
15#include "phy.h" 15#include "phy_common.h"
16 16
17 17
18/* The unique identifier of the firmware that's officially supported by 18/* The unique identifier of the firmware that's officially supported by
@@ -508,122 +508,6 @@ struct b43_iv {
508} __attribute__((__packed__)); 508} __attribute__((__packed__));
509 509
510 510
511struct b43_phy {
512 /* Band support flags. */
513 bool supports_2ghz;
514 bool supports_5ghz;
515
516 /* GMODE bit enabled? */
517 bool gmode;
518
519 /* Analog Type */
520 u8 analog;
521 /* B43_PHYTYPE_ */
522 u8 type;
523 /* PHY revision number. */
524 u8 rev;
525
526 /* Radio versioning */
527 u16 radio_manuf; /* Radio manufacturer */
528 u16 radio_ver; /* Radio version */
529 u8 radio_rev; /* Radio revision */
530
531 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
532
533 /* ACI (adjacent channel interference) flags. */
534 bool aci_enable;
535 bool aci_wlan_automatic;
536 bool aci_hw_rssi;
537
538 /* Radio switched on/off */
539 bool radio_on;
540 struct {
541 /* Values saved when turning the radio off.
542 * They are needed when turning it on again. */
543 bool valid;
544 u16 rfover;
545 u16 rfoverval;
546 } radio_off_context;
547
548 u16 minlowsig[2];
549 u16 minlowsigpos[2];
550
551 /* TSSI to dBm table in use */
552 const s8 *tssi2dbm;
553 /* Target idle TSSI */
554 int tgt_idle_tssi;
555 /* Current idle TSSI */
556 int cur_idle_tssi;
557
558 /* LocalOscillator control values. */
559 struct b43_txpower_lo_control *lo_control;
560 /* Values from b43_calc_loopback_gain() */
561 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
562 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
563 s16 lna_lod_gain; /* LNA lod */
564 s16 lna_gain; /* LNA */
565 s16 pga_gain; /* PGA */
566
567 /* Desired TX power level (in dBm).
568 * This is set by the user and adjusted in b43_phy_xmitpower(). */
569 u8 power_level;
570 /* A-PHY TX Power control value. */
571 u16 txpwr_offset;
572
573 /* Current TX power level attenuation control values */
574 struct b43_bbatt bbatt;
575 struct b43_rfatt rfatt;
576 u8 tx_control; /* B43_TXCTL_XXX */
577
578 /* Hardware Power Control enabled? */
579 bool hardware_power_control;
580
581 /* Current Interference Mitigation mode */
582 int interfmode;
583 /* Stack of saved values from the Interference Mitigation code.
584 * Each value in the stack is layed out as follows:
585 * bit 0-11: offset
586 * bit 12-15: register ID
587 * bit 16-32: value
588 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
589 */
590#define B43_INTERFSTACK_SIZE 26
591 u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
592
593 /* Saved values from the NRSSI Slope calculation */
594 s16 nrssi[2];
595 s32 nrssislope;
596 /* In memory nrssi lookup table. */
597 s8 nrssi_lt[64];
598
599 /* current channel */
600 u8 channel;
601
602 u16 lofcal;
603
604 u16 initval; //FIXME rename?
605
606 /* PHY TX errors counter. */
607 atomic_t txerr_cnt;
608
609 /* The device does address auto increment for the OFDM tables.
610 * We cache the previously used address here and omit the address
611 * write on the next table access, if possible. */
612 u16 ofdmtab_addr; /* The address currently set in hardware. */
613 enum { /* The last data flow direction. */
614 B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
615 B43_OFDMTAB_DIRECTION_READ,
616 B43_OFDMTAB_DIRECTION_WRITE,
617 } ofdmtab_addr_direction;
618
619#if B43_DEBUG
620 /* Manual TX-power control enabled? */
621 bool manual_txpower_control;
622 /* PHY registers locked by b43_phy_lock()? */
623 bool phy_locked;
624#endif /* B43_DEBUG */
625};
626
627/* Data structures for DMA transmission, per 80211 core. */ 511/* Data structures for DMA transmission, per 80211 core. */
628struct b43_dma { 512struct b43_dma {
629 struct b43_dmaring *tx_ring_AC_BK; /* Background */ 513 struct b43_dmaring *tx_ring_AC_BK; /* Background */
@@ -908,6 +792,15 @@ static inline int b43_is_mode(struct b43_wl *wl, int type)
908 return (wl->operating && wl->if_type == type); 792 return (wl->operating && wl->if_type == type);
909} 793}
910 794
795/**
796 * b43_current_band - Returns the currently used band.
797 * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ.
798 */
799static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
800{
801 return wl->hw->conf.channel->band;
802}
803
911static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) 804static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
912{ 805{
913 return ssb_read16(dev->dev, offset); 806 return ssb_read16(dev->dev, offset);
diff --git a/drivers/net/wireless/b43/debugfs.c b/drivers/net/wireless/b43/debugfs.c
index 29851bc1101f..06a01da80160 100644
--- a/drivers/net/wireless/b43/debugfs.c
+++ b/drivers/net/wireless/b43/debugfs.c
@@ -443,76 +443,6 @@ out_unlock:
443 return count; 443 return count;
444} 444}
445 445
446static ssize_t txpower_g_read_file(struct b43_wldev *dev,
447 char *buf, size_t bufsize)
448{
449 ssize_t count = 0;
450
451 if (dev->phy.type != B43_PHYTYPE_G) {
452 fappend("Device is not a G-PHY\n");
453 goto out;
454 }
455 fappend("Control: %s\n", dev->phy.manual_txpower_control ?
456 "MANUAL" : "AUTOMATIC");
457 fappend("Baseband attenuation: %u\n", dev->phy.bbatt.att);
458 fappend("Radio attenuation: %u\n", dev->phy.rfatt.att);
459 fappend("TX Mixer Gain: %s\n",
460 (dev->phy.tx_control & B43_TXCTL_TXMIX) ? "ON" : "OFF");
461 fappend("PA Gain 2dB: %s\n",
462 (dev->phy.tx_control & B43_TXCTL_PA2DB) ? "ON" : "OFF");
463 fappend("PA Gain 3dB: %s\n",
464 (dev->phy.tx_control & B43_TXCTL_PA3DB) ? "ON" : "OFF");
465 fappend("\n\n");
466 fappend("You can write to this file:\n");
467 fappend("Writing \"auto\" enables automatic txpower control.\n");
468 fappend
469 ("Writing the attenuation values as \"bbatt rfatt txmix pa2db pa3db\" "
470 "enables manual txpower control.\n");
471 fappend("Example: 5 4 0 0 1\n");
472 fappend("Enables manual control with Baseband attenuation 5, "
473 "Radio attenuation 4, No TX Mixer Gain, "
474 "No PA Gain 2dB, With PA Gain 3dB.\n");
475out:
476 return count;
477}
478
479static int txpower_g_write_file(struct b43_wldev *dev,
480 const char *buf, size_t count)
481{
482 if (dev->phy.type != B43_PHYTYPE_G)
483 return -ENODEV;
484 if ((count >= 4) && (memcmp(buf, "auto", 4) == 0)) {
485 /* Automatic control */
486 dev->phy.manual_txpower_control = 0;
487 b43_phy_xmitpower(dev);
488 } else {
489 int bbatt = 0, rfatt = 0, txmix = 0, pa2db = 0, pa3db = 0;
490 /* Manual control */
491 if (sscanf(buf, "%d %d %d %d %d", &bbatt, &rfatt,
492 &txmix, &pa2db, &pa3db) != 5)
493 return -EINVAL;
494 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
495 dev->phy.manual_txpower_control = 1;
496 dev->phy.bbatt.att = bbatt;
497 dev->phy.rfatt.att = rfatt;
498 dev->phy.tx_control = 0;
499 if (txmix)
500 dev->phy.tx_control |= B43_TXCTL_TXMIX;
501 if (pa2db)
502 dev->phy.tx_control |= B43_TXCTL_PA2DB;
503 if (pa3db)
504 dev->phy.tx_control |= B43_TXCTL_PA3DB;
505 b43_phy_lock(dev);
506 b43_radio_lock(dev);
507 b43_set_txpower_g(dev, &dev->phy.bbatt,
508 &dev->phy.rfatt, dev->phy.tx_control);
509 b43_radio_unlock(dev);
510 b43_phy_unlock(dev);
511 }
512
513 return 0;
514}
515
516/* wl->irq_lock is locked */ 446/* wl->irq_lock is locked */
517static int restart_write_file(struct b43_wldev *dev, 447static int restart_write_file(struct b43_wldev *dev,
518 const char *buf, size_t count) 448 const char *buf, size_t count)
@@ -560,7 +490,7 @@ static ssize_t loctls_read_file(struct b43_wldev *dev,
560 err = -ENODEV; 490 err = -ENODEV;
561 goto out; 491 goto out;
562 } 492 }
563 lo = phy->lo_control; 493 lo = phy->g->lo_control;
564 fappend("-- Local Oscillator calibration data --\n\n"); 494 fappend("-- Local Oscillator calibration data --\n\n");
565 fappend("HW-power-control enabled: %d\n", 495 fappend("HW-power-control enabled: %d\n",
566 dev->phy.hardware_power_control); 496 dev->phy.hardware_power_control);
@@ -578,8 +508,8 @@ static ssize_t loctls_read_file(struct b43_wldev *dev,
578 list_for_each_entry(cal, &lo->calib_list, list) { 508 list_for_each_entry(cal, &lo->calib_list, list) {
579 bool active; 509 bool active;
580 510
581 active = (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) && 511 active = (b43_compare_bbatt(&cal->bbatt, &phy->g->bbatt) &&
582 b43_compare_rfatt(&cal->rfatt, &phy->rfatt)); 512 b43_compare_rfatt(&cal->rfatt, &phy->g->rfatt));
583 fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d " 513 fappend("BB(%d), RF(%d,%d) -> I=%d, Q=%d "
584 "(expires in %lu sec)%s\n", 514 "(expires in %lu sec)%s\n",
585 cal->bbatt.att, 515 cal->bbatt.att,
@@ -763,7 +693,6 @@ B43_DEBUGFS_FOPS(mmio32read, mmio32read__read_file, mmio32read__write_file, 1);
763B43_DEBUGFS_FOPS(mmio32write, NULL, mmio32write__write_file, 1); 693B43_DEBUGFS_FOPS(mmio32write, NULL, mmio32write__write_file, 1);
764B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1); 694B43_DEBUGFS_FOPS(tsf, tsf_read_file, tsf_write_file, 1);
765B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0); 695B43_DEBUGFS_FOPS(txstat, txstat_read_file, NULL, 0);
766B43_DEBUGFS_FOPS(txpower_g, txpower_g_read_file, txpower_g_write_file, 0);
767B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1); 696B43_DEBUGFS_FOPS(restart, NULL, restart_write_file, 1);
768B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL, 0); 697B43_DEBUGFS_FOPS(loctls, loctls_read_file, NULL, 0);
769 698
@@ -877,7 +806,6 @@ void b43_debugfs_add_device(struct b43_wldev *dev)
877 ADD_FILE(mmio32write, 0200); 806 ADD_FILE(mmio32write, 0200);
878 ADD_FILE(tsf, 0600); 807 ADD_FILE(tsf, 0600);
879 ADD_FILE(txstat, 0400); 808 ADD_FILE(txstat, 0400);
880 ADD_FILE(txpower_g, 0600);
881 ADD_FILE(restart, 0200); 809 ADD_FILE(restart, 0200);
882 ADD_FILE(loctls, 0400); 810 ADD_FILE(loctls, 0400);
883 811
@@ -907,7 +835,6 @@ void b43_debugfs_remove_device(struct b43_wldev *dev)
907 debugfs_remove(e->file_mmio32write.dentry); 835 debugfs_remove(e->file_mmio32write.dentry);
908 debugfs_remove(e->file_tsf.dentry); 836 debugfs_remove(e->file_tsf.dentry);
909 debugfs_remove(e->file_txstat.dentry); 837 debugfs_remove(e->file_txstat.dentry);
910 debugfs_remove(e->file_txpower_g.dentry);
911 debugfs_remove(e->file_restart.dentry); 838 debugfs_remove(e->file_restart.dentry);
912 debugfs_remove(e->file_loctls.dentry); 839 debugfs_remove(e->file_loctls.dentry);
913 840
diff --git a/drivers/net/wireless/b43/lo.c b/drivers/net/wireless/b43/lo.c
index 9c854d6aae36..6a18a1470465 100644
--- a/drivers/net/wireless/b43/lo.c
+++ b/drivers/net/wireless/b43/lo.c
@@ -29,7 +29,7 @@
29 29
30#include "b43.h" 30#include "b43.h"
31#include "lo.h" 31#include "lo.h"
32#include "phy.h" 32#include "phy_g.h"
33#include "main.h" 33#include "main.h"
34 34
35#include <linux/delay.h> 35#include <linux/delay.h>
@@ -174,7 +174,8 @@ static u16 lo_txctl_register_table(struct b43_wldev *dev,
174static void lo_measure_txctl_values(struct b43_wldev *dev) 174static void lo_measure_txctl_values(struct b43_wldev *dev)
175{ 175{
176 struct b43_phy *phy = &dev->phy; 176 struct b43_phy *phy = &dev->phy;
177 struct b43_txpower_lo_control *lo = phy->lo_control; 177 struct b43_phy_g *gphy = phy->g;
178 struct b43_txpower_lo_control *lo = gphy->lo_control;
178 u16 reg, mask; 179 u16 reg, mask;
179 u16 trsw_rx, pga; 180 u16 trsw_rx, pga;
180 u16 radio_pctl_reg; 181 u16 radio_pctl_reg;
@@ -195,7 +196,7 @@ static void lo_measure_txctl_values(struct b43_wldev *dev)
195 int lb_gain; /* Loopback gain (in dB) */ 196 int lb_gain; /* Loopback gain (in dB) */
196 197
197 trsw_rx = 0; 198 trsw_rx = 0;
198 lb_gain = phy->max_lb_gain / 2; 199 lb_gain = gphy->max_lb_gain / 2;
199 if (lb_gain > 10) { 200 if (lb_gain > 10) {
200 radio_pctl_reg = 0; 201 radio_pctl_reg = 0;
201 pga = abs(10 - lb_gain) / 6; 202 pga = abs(10 - lb_gain) / 6;
@@ -226,7 +227,7 @@ static void lo_measure_txctl_values(struct b43_wldev *dev)
226 } 227 }
227 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43) 228 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
228 & 0xFFF0) | radio_pctl_reg); 229 & 0xFFF0) | radio_pctl_reg);
229 b43_phy_set_baseband_attenuation(dev, 2); 230 b43_gphy_set_baseband_attenuation(dev, 2);
230 231
231 reg = lo_txctl_register_table(dev, &mask, NULL); 232 reg = lo_txctl_register_table(dev, &mask, NULL);
232 mask = ~mask; 233 mask = ~mask;
@@ -277,7 +278,8 @@ static void lo_measure_txctl_values(struct b43_wldev *dev)
277static void lo_read_power_vector(struct b43_wldev *dev) 278static void lo_read_power_vector(struct b43_wldev *dev)
278{ 279{
279 struct b43_phy *phy = &dev->phy; 280 struct b43_phy *phy = &dev->phy;
280 struct b43_txpower_lo_control *lo = phy->lo_control; 281 struct b43_phy_g *gphy = phy->g;
282 struct b43_txpower_lo_control *lo = gphy->lo_control;
281 int i; 283 int i;
282 u64 tmp; 284 u64 tmp;
283 u64 power_vector = 0; 285 u64 power_vector = 0;
@@ -298,6 +300,7 @@ static void lo_measure_gain_values(struct b43_wldev *dev,
298 s16 max_rx_gain, int use_trsw_rx) 300 s16 max_rx_gain, int use_trsw_rx)
299{ 301{
300 struct b43_phy *phy = &dev->phy; 302 struct b43_phy *phy = &dev->phy;
303 struct b43_phy_g *gphy = phy->g;
301 u16 tmp; 304 u16 tmp;
302 305
303 if (max_rx_gain < 0) 306 if (max_rx_gain < 0)
@@ -308,7 +311,7 @@ static void lo_measure_gain_values(struct b43_wldev *dev,
308 int trsw_rx_gain; 311 int trsw_rx_gain;
309 312
310 if (use_trsw_rx) { 313 if (use_trsw_rx) {
311 trsw_rx_gain = phy->trsw_rx_gain / 2; 314 trsw_rx_gain = gphy->trsw_rx_gain / 2;
312 if (max_rx_gain >= trsw_rx_gain) { 315 if (max_rx_gain >= trsw_rx_gain) {
313 trsw_rx_gain = max_rx_gain - trsw_rx_gain; 316 trsw_rx_gain = max_rx_gain - trsw_rx_gain;
314 trsw_rx = 0x20; 317 trsw_rx = 0x20;
@@ -316,38 +319,38 @@ static void lo_measure_gain_values(struct b43_wldev *dev,
316 } else 319 } else
317 trsw_rx_gain = max_rx_gain; 320 trsw_rx_gain = max_rx_gain;
318 if (trsw_rx_gain < 9) { 321 if (trsw_rx_gain < 9) {
319 phy->lna_lod_gain = 0; 322 gphy->lna_lod_gain = 0;
320 } else { 323 } else {
321 phy->lna_lod_gain = 1; 324 gphy->lna_lod_gain = 1;
322 trsw_rx_gain -= 8; 325 trsw_rx_gain -= 8;
323 } 326 }
324 trsw_rx_gain = clamp_val(trsw_rx_gain, 0, 0x2D); 327 trsw_rx_gain = clamp_val(trsw_rx_gain, 0, 0x2D);
325 phy->pga_gain = trsw_rx_gain / 3; 328 gphy->pga_gain = trsw_rx_gain / 3;
326 if (phy->pga_gain >= 5) { 329 if (gphy->pga_gain >= 5) {
327 phy->pga_gain -= 5; 330 gphy->pga_gain -= 5;
328 phy->lna_gain = 2; 331 gphy->lna_gain = 2;
329 } else 332 } else
330 phy->lna_gain = 0; 333 gphy->lna_gain = 0;
331 } else { 334 } else {
332 phy->lna_gain = 0; 335 gphy->lna_gain = 0;
333 phy->trsw_rx_gain = 0x20; 336 gphy->trsw_rx_gain = 0x20;
334 if (max_rx_gain >= 0x14) { 337 if (max_rx_gain >= 0x14) {
335 phy->lna_lod_gain = 1; 338 gphy->lna_lod_gain = 1;
336 phy->pga_gain = 2; 339 gphy->pga_gain = 2;
337 } else if (max_rx_gain >= 0x12) { 340 } else if (max_rx_gain >= 0x12) {
338 phy->lna_lod_gain = 1; 341 gphy->lna_lod_gain = 1;
339 phy->pga_gain = 1; 342 gphy->pga_gain = 1;
340 } else if (max_rx_gain >= 0xF) { 343 } else if (max_rx_gain >= 0xF) {
341 phy->lna_lod_gain = 1; 344 gphy->lna_lod_gain = 1;
342 phy->pga_gain = 0; 345 gphy->pga_gain = 0;
343 } else { 346 } else {
344 phy->lna_lod_gain = 0; 347 gphy->lna_lod_gain = 0;
345 phy->pga_gain = 0; 348 gphy->pga_gain = 0;
346 } 349 }
347 } 350 }
348 351
349 tmp = b43_radio_read16(dev, 0x7A); 352 tmp = b43_radio_read16(dev, 0x7A);
350 if (phy->lna_lod_gain == 0) 353 if (gphy->lna_lod_gain == 0)
351 tmp &= ~0x0008; 354 tmp &= ~0x0008;
352 else 355 else
353 tmp |= 0x0008; 356 tmp |= 0x0008;
@@ -392,10 +395,11 @@ static void lo_measure_setup(struct b43_wldev *dev,
392{ 395{
393 struct ssb_sprom *sprom = &dev->dev->bus->sprom; 396 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
394 struct b43_phy *phy = &dev->phy; 397 struct b43_phy *phy = &dev->phy;
395 struct b43_txpower_lo_control *lo = phy->lo_control; 398 struct b43_phy_g *gphy = phy->g;
399 struct b43_txpower_lo_control *lo = gphy->lo_control;
396 u16 tmp; 400 u16 tmp;
397 401
398 if (b43_has_hardware_pctl(phy)) { 402 if (b43_has_hardware_pctl(dev)) {
399 sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); 403 sav->phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
400 sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01)); 404 sav->phy_extg_01 = b43_phy_read(dev, B43_PHY_EXTG(0x01));
401 sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL); 405 sav->phy_dacctl_hwpctl = b43_phy_read(dev, B43_PHY_DACCTL);
@@ -496,7 +500,7 @@ static void lo_measure_setup(struct b43_wldev *dev,
496 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802); 500 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x0802);
497 if (phy->rev >= 2) 501 if (phy->rev >= 2)
498 b43_dummy_transmission(dev); 502 b43_dummy_transmission(dev);
499 b43_radio_selectchannel(dev, 6, 0); 503 b43_gphy_channel_switch(dev, 6, 0);
500 b43_radio_read16(dev, 0x51); /* dummy read */ 504 b43_radio_read16(dev, 0x51); /* dummy read */
501 if (phy->type == B43_PHYTYPE_G) 505 if (phy->type == B43_PHYTYPE_G)
502 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0); 506 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0);
@@ -520,18 +524,19 @@ static void lo_measure_restore(struct b43_wldev *dev,
520 struct lo_g_saved_values *sav) 524 struct lo_g_saved_values *sav)
521{ 525{
522 struct b43_phy *phy = &dev->phy; 526 struct b43_phy *phy = &dev->phy;
527 struct b43_phy_g *gphy = phy->g;
523 u16 tmp; 528 u16 tmp;
524 529
525 if (phy->rev >= 2) { 530 if (phy->rev >= 2) {
526 b43_phy_write(dev, B43_PHY_PGACTL, 0xE300); 531 b43_phy_write(dev, B43_PHY_PGACTL, 0xE300);
527 tmp = (phy->pga_gain << 8); 532 tmp = (gphy->pga_gain << 8);
528 b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA0); 533 b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA0);
529 udelay(5); 534 udelay(5);
530 b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA2); 535 b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA2);
531 udelay(2); 536 udelay(2);
532 b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA3); 537 b43_phy_write(dev, B43_PHY_RFOVERVAL, tmp | 0xA3);
533 } else { 538 } else {
534 tmp = (phy->pga_gain | 0xEFA0); 539 tmp = (gphy->pga_gain | 0xEFA0);
535 b43_phy_write(dev, B43_PHY_PGACTL, tmp); 540 b43_phy_write(dev, B43_PHY_PGACTL, tmp);
536 } 541 }
537 if (phy->type == B43_PHYTYPE_G) { 542 if (phy->type == B43_PHYTYPE_G) {
@@ -572,7 +577,7 @@ static void lo_measure_restore(struct b43_wldev *dev,
572 b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E); 577 b43_phy_write(dev, B43_PHY_CCK(0x3E), sav->phy_cck_3E);
573 b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0); 578 b43_phy_write(dev, B43_PHY_CRS0, sav->phy_crs0);
574 } 579 }
575 if (b43_has_hardware_pctl(phy)) { 580 if (b43_has_hardware_pctl(dev)) {
576 tmp = (sav->phy_lo_mask & 0xBFFF); 581 tmp = (sav->phy_lo_mask & 0xBFFF);
577 b43_phy_write(dev, B43_PHY_LO_MASK, tmp); 582 b43_phy_write(dev, B43_PHY_LO_MASK, tmp);
578 b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01); 583 b43_phy_write(dev, B43_PHY_EXTG(0x01), sav->phy_extg_01);
@@ -580,7 +585,7 @@ static void lo_measure_restore(struct b43_wldev *dev,
580 b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14); 585 b43_phy_write(dev, B43_PHY_CCK(0x14), sav->phy_cck_14);
581 b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl); 586 b43_phy_write(dev, B43_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl);
582 } 587 }
583 b43_radio_selectchannel(dev, sav->old_channel, 1); 588 b43_gphy_channel_switch(dev, sav->old_channel, 1);
584} 589}
585 590
586struct b43_lo_g_statemachine { 591struct b43_lo_g_statemachine {
@@ -597,6 +602,7 @@ static int lo_probe_possible_loctls(struct b43_wldev *dev,
597 struct b43_lo_g_statemachine *d) 602 struct b43_lo_g_statemachine *d)
598{ 603{
599 struct b43_phy *phy = &dev->phy; 604 struct b43_phy *phy = &dev->phy;
605 struct b43_phy_g *gphy = phy->g;
600 struct b43_loctl test_loctl; 606 struct b43_loctl test_loctl;
601 struct b43_loctl orig_loctl; 607 struct b43_loctl orig_loctl;
602 struct b43_loctl prev_loctl = { 608 struct b43_loctl prev_loctl = {
@@ -646,9 +652,9 @@ static int lo_probe_possible_loctls(struct b43_wldev *dev,
646 test_loctl.q != prev_loctl.q) && 652 test_loctl.q != prev_loctl.q) &&
647 (abs(test_loctl.i) <= 16 && abs(test_loctl.q) <= 16)) { 653 (abs(test_loctl.i) <= 16 && abs(test_loctl.q) <= 16)) {
648 b43_lo_write(dev, &test_loctl); 654 b43_lo_write(dev, &test_loctl);
649 feedth = lo_measure_feedthrough(dev, phy->lna_gain, 655 feedth = lo_measure_feedthrough(dev, gphy->lna_gain,
650 phy->pga_gain, 656 gphy->pga_gain,
651 phy->trsw_rx_gain); 657 gphy->trsw_rx_gain);
652 if (feedth < d->lowest_feedth) { 658 if (feedth < d->lowest_feedth) {
653 memcpy(probe_loctl, &test_loctl, 659 memcpy(probe_loctl, &test_loctl,
654 sizeof(struct b43_loctl)); 660 sizeof(struct b43_loctl));
@@ -677,6 +683,7 @@ static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
677 int *max_rx_gain) 683 int *max_rx_gain)
678{ 684{
679 struct b43_phy *phy = &dev->phy; 685 struct b43_phy *phy = &dev->phy;
686 struct b43_phy_g *gphy = phy->g;
680 struct b43_lo_g_statemachine d; 687 struct b43_lo_g_statemachine d;
681 u16 feedth; 688 u16 feedth;
682 int found_lower; 689 int found_lower;
@@ -693,17 +700,17 @@ static void lo_probe_loctls_statemachine(struct b43_wldev *dev,
693 max_repeat = 4; 700 max_repeat = 4;
694 do { 701 do {
695 b43_lo_write(dev, &d.min_loctl); 702 b43_lo_write(dev, &d.min_loctl);
696 feedth = lo_measure_feedthrough(dev, phy->lna_gain, 703 feedth = lo_measure_feedthrough(dev, gphy->lna_gain,
697 phy->pga_gain, 704 gphy->pga_gain,
698 phy->trsw_rx_gain); 705 gphy->trsw_rx_gain);
699 if (feedth < 0x258) { 706 if (feedth < 0x258) {
700 if (feedth >= 0x12C) 707 if (feedth >= 0x12C)
701 *max_rx_gain += 6; 708 *max_rx_gain += 6;
702 else 709 else
703 *max_rx_gain += 3; 710 *max_rx_gain += 3;
704 feedth = lo_measure_feedthrough(dev, phy->lna_gain, 711 feedth = lo_measure_feedthrough(dev, gphy->lna_gain,
705 phy->pga_gain, 712 gphy->pga_gain,
706 phy->trsw_rx_gain); 713 gphy->trsw_rx_gain);
707 } 714 }
708 d.lowest_feedth = feedth; 715 d.lowest_feedth = feedth;
709 716
@@ -752,6 +759,7 @@ struct b43_lo_calib * b43_calibrate_lo_setting(struct b43_wldev *dev,
752 const struct b43_rfatt *rfatt) 759 const struct b43_rfatt *rfatt)
753{ 760{
754 struct b43_phy *phy = &dev->phy; 761 struct b43_phy *phy = &dev->phy;
762 struct b43_phy_g *gphy = phy->g;
755 struct b43_loctl loctl = { 763 struct b43_loctl loctl = {
756 .i = 0, 764 .i = 0,
757 .q = 0, 765 .q = 0,
@@ -782,11 +790,11 @@ struct b43_lo_calib * b43_calibrate_lo_setting(struct b43_wldev *dev,
782 if (rfatt->with_padmix) 790 if (rfatt->with_padmix)
783 max_rx_gain -= pad_mix_gain; 791 max_rx_gain -= pad_mix_gain;
784 if (has_loopback_gain(phy)) 792 if (has_loopback_gain(phy))
785 max_rx_gain += phy->max_lb_gain; 793 max_rx_gain += gphy->max_lb_gain;
786 lo_measure_gain_values(dev, max_rx_gain, 794 lo_measure_gain_values(dev, max_rx_gain,
787 has_loopback_gain(phy)); 795 has_loopback_gain(phy));
788 796
789 b43_phy_set_baseband_attenuation(dev, bbatt->att); 797 b43_gphy_set_baseband_attenuation(dev, bbatt->att);
790 lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain); 798 lo_probe_loctls_statemachine(dev, &loctl, &max_rx_gain);
791 799
792 lo_measure_restore(dev, &saved_regs); 800 lo_measure_restore(dev, &saved_regs);
@@ -820,7 +828,7 @@ struct b43_lo_calib * b43_get_calib_lo_settings(struct b43_wldev *dev,
820 const struct b43_bbatt *bbatt, 828 const struct b43_bbatt *bbatt,
821 const struct b43_rfatt *rfatt) 829 const struct b43_rfatt *rfatt)
822{ 830{
823 struct b43_txpower_lo_control *lo = dev->phy.lo_control; 831 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
824 struct b43_lo_calib *c; 832 struct b43_lo_calib *c;
825 833
826 c = b43_find_lo_calib(lo, bbatt, rfatt); 834 c = b43_find_lo_calib(lo, bbatt, rfatt);
@@ -839,7 +847,8 @@ struct b43_lo_calib * b43_get_calib_lo_settings(struct b43_wldev *dev,
839void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all) 847void b43_gphy_dc_lt_init(struct b43_wldev *dev, bool update_all)
840{ 848{
841 struct b43_phy *phy = &dev->phy; 849 struct b43_phy *phy = &dev->phy;
842 struct b43_txpower_lo_control *lo = phy->lo_control; 850 struct b43_phy_g *gphy = phy->g;
851 struct b43_txpower_lo_control *lo = gphy->lo_control;
843 int i; 852 int i;
844 int rf_offset, bb_offset; 853 int rf_offset, bb_offset;
845 const struct b43_rfatt *rfatt; 854 const struct b43_rfatt *rfatt;
@@ -917,14 +926,14 @@ static inline void b43_lo_fixup_rfatt(struct b43_rfatt *rf)
917 926
918void b43_lo_g_adjust(struct b43_wldev *dev) 927void b43_lo_g_adjust(struct b43_wldev *dev)
919{ 928{
920 struct b43_phy *phy = &dev->phy; 929 struct b43_phy_g *gphy = dev->phy.g;
921 struct b43_lo_calib *cal; 930 struct b43_lo_calib *cal;
922 struct b43_rfatt rf; 931 struct b43_rfatt rf;
923 932
924 memcpy(&rf, &phy->rfatt, sizeof(rf)); 933 memcpy(&rf, &gphy->rfatt, sizeof(rf));
925 b43_lo_fixup_rfatt(&rf); 934 b43_lo_fixup_rfatt(&rf);
926 935
927 cal = b43_get_calib_lo_settings(dev, &phy->bbatt, &rf); 936 cal = b43_get_calib_lo_settings(dev, &gphy->bbatt, &rf);
928 if (!cal) 937 if (!cal)
929 return; 938 return;
930 b43_lo_write(dev, &cal->ctl); 939 b43_lo_write(dev, &cal->ctl);
@@ -952,7 +961,8 @@ void b43_lo_g_adjust_to(struct b43_wldev *dev,
952void b43_lo_g_maintanance_work(struct b43_wldev *dev) 961void b43_lo_g_maintanance_work(struct b43_wldev *dev)
953{ 962{
954 struct b43_phy *phy = &dev->phy; 963 struct b43_phy *phy = &dev->phy;
955 struct b43_txpower_lo_control *lo = phy->lo_control; 964 struct b43_phy_g *gphy = phy->g;
965 struct b43_txpower_lo_control *lo = gphy->lo_control;
956 unsigned long now; 966 unsigned long now;
957 unsigned long expire; 967 unsigned long expire;
958 struct b43_lo_calib *cal, *tmp; 968 struct b43_lo_calib *cal, *tmp;
@@ -962,7 +972,7 @@ void b43_lo_g_maintanance_work(struct b43_wldev *dev)
962 if (!lo) 972 if (!lo)
963 return; 973 return;
964 now = jiffies; 974 now = jiffies;
965 hwpctl = b43_has_hardware_pctl(phy); 975 hwpctl = b43_has_hardware_pctl(dev);
966 976
967 if (hwpctl) { 977 if (hwpctl) {
968 /* Read the power vector and update it, if needed. */ 978 /* Read the power vector and update it, if needed. */
@@ -983,8 +993,8 @@ void b43_lo_g_maintanance_work(struct b43_wldev *dev)
983 if (!time_before(cal->calib_time, expire)) 993 if (!time_before(cal->calib_time, expire))
984 continue; 994 continue;
985 /* This item expired. */ 995 /* This item expired. */
986 if (b43_compare_bbatt(&cal->bbatt, &phy->bbatt) && 996 if (b43_compare_bbatt(&cal->bbatt, &gphy->bbatt) &&
987 b43_compare_rfatt(&cal->rfatt, &phy->rfatt)) { 997 b43_compare_rfatt(&cal->rfatt, &gphy->rfatt)) {
988 B43_WARN_ON(current_item_expired); 998 B43_WARN_ON(current_item_expired);
989 current_item_expired = 1; 999 current_item_expired = 1;
990 } 1000 }
@@ -1002,7 +1012,7 @@ void b43_lo_g_maintanance_work(struct b43_wldev *dev)
1002 /* Recalibrate currently used LO setting. */ 1012 /* Recalibrate currently used LO setting. */
1003 if (b43_debug(dev, B43_DBG_LO)) 1013 if (b43_debug(dev, B43_DBG_LO))
1004 b43dbg(dev->wl, "LO: Recalibrating current LO setting\n"); 1014 b43dbg(dev->wl, "LO: Recalibrating current LO setting\n");
1005 cal = b43_calibrate_lo_setting(dev, &phy->bbatt, &phy->rfatt); 1015 cal = b43_calibrate_lo_setting(dev, &gphy->bbatt, &gphy->rfatt);
1006 if (cal) { 1016 if (cal) {
1007 list_add(&cal->list, &lo->calib_list); 1017 list_add(&cal->list, &lo->calib_list);
1008 b43_lo_write(dev, &cal->ctl); 1018 b43_lo_write(dev, &cal->ctl);
@@ -1013,7 +1023,7 @@ void b43_lo_g_maintanance_work(struct b43_wldev *dev)
1013 1023
1014void b43_lo_g_cleanup(struct b43_wldev *dev) 1024void b43_lo_g_cleanup(struct b43_wldev *dev)
1015{ 1025{
1016 struct b43_txpower_lo_control *lo = dev->phy.lo_control; 1026 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
1017 struct b43_lo_calib *cal, *tmp; 1027 struct b43_lo_calib *cal, *tmp;
1018 1028
1019 if (!lo) 1029 if (!lo)
@@ -1027,9 +1037,7 @@ void b43_lo_g_cleanup(struct b43_wldev *dev)
1027/* LO Initialization */ 1037/* LO Initialization */
1028void b43_lo_g_init(struct b43_wldev *dev) 1038void b43_lo_g_init(struct b43_wldev *dev)
1029{ 1039{
1030 struct b43_phy *phy = &dev->phy; 1040 if (b43_has_hardware_pctl(dev)) {
1031
1032 if (b43_has_hardware_pctl(phy)) {
1033 lo_read_power_vector(dev); 1041 lo_read_power_vector(dev);
1034 b43_gphy_dc_lt_init(dev, 1); 1042 b43_gphy_dc_lt_init(dev, 1);
1035 } 1043 }
diff --git a/drivers/net/wireless/b43/lo.h b/drivers/net/wireless/b43/lo.h
index 1da321cabc12..3b27e20eff80 100644
--- a/drivers/net/wireless/b43/lo.h
+++ b/drivers/net/wireless/b43/lo.h
@@ -1,7 +1,9 @@
1#ifndef B43_LO_H_ 1#ifndef B43_LO_H_
2#define B43_LO_H_ 2#define B43_LO_H_
3 3
4#include "phy.h" 4/* G-PHY Local Oscillator */
5
6#include "phy_g.h"
5 7
6struct b43_wldev; 8struct b43_wldev;
7 9
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 7205a936ec74..af43f03b3189 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -44,7 +44,8 @@
44#include "b43.h" 44#include "b43.h"
45#include "main.h" 45#include "main.h"
46#include "debugfs.h" 46#include "debugfs.h"
47#include "phy.h" 47#include "phy_common.h"
48#include "phy_g.h"
48#include "nphy.h" 49#include "nphy.h"
49#include "dma.h" 50#include "dma.h"
50#include "pio.h" 51#include "pio.h"
@@ -1174,6 +1175,8 @@ static void b43_calculate_link_quality(struct b43_wldev *dev)
1174{ 1175{
1175 /* Top half of Link Quality calculation. */ 1176 /* Top half of Link Quality calculation. */
1176 1177
1178 if (dev->phy.type != B43_PHYTYPE_G)
1179 return;
1177 if (dev->noisecalc.calculation_running) 1180 if (dev->noisecalc.calculation_running)
1178 return; 1181 return;
1179 dev->noisecalc.calculation_running = 1; 1182 dev->noisecalc.calculation_running = 1;
@@ -1184,7 +1187,7 @@ static void b43_calculate_link_quality(struct b43_wldev *dev)
1184 1187
1185static void handle_irq_noise(struct b43_wldev *dev) 1188static void handle_irq_noise(struct b43_wldev *dev)
1186{ 1189{
1187 struct b43_phy *phy = &dev->phy; 1190 struct b43_phy_g *phy = dev->phy.g;
1188 u16 tmp; 1191 u16 tmp;
1189 u8 noise[4]; 1192 u8 noise[4];
1190 u8 i, j; 1193 u8 i, j;
@@ -1192,6 +1195,9 @@ static void handle_irq_noise(struct b43_wldev *dev)
1192 1195
1193 /* Bottom half of Link Quality calculation. */ 1196 /* Bottom half of Link Quality calculation. */
1194 1197
1198 if (dev->phy.type != B43_PHYTYPE_G)
1199 return;
1200
1195 /* Possible race condition: It might be possible that the user 1201 /* Possible race condition: It might be possible that the user
1196 * changed to a different channel in the meantime since we 1202 * changed to a different channel in the meantime since we
1197 * started the calculation. We ignore that fact, since it's 1203 * started the calculation. We ignore that fact, since it's
@@ -2688,9 +2694,7 @@ static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2688/* This is the opposite of b43_chip_init() */ 2694/* This is the opposite of b43_chip_init() */
2689static void b43_chip_exit(struct b43_wldev *dev) 2695static void b43_chip_exit(struct b43_wldev *dev)
2690{ 2696{
2691 b43_radio_turn_off(dev, 1);
2692 b43_gpio_cleanup(dev); 2697 b43_gpio_cleanup(dev);
2693 b43_lo_g_cleanup(dev);
2694 /* firmware is released later */ 2698 /* firmware is released later */
2695} 2699}
2696 2700
@@ -2700,7 +2704,7 @@ static void b43_chip_exit(struct b43_wldev *dev)
2700static int b43_chip_init(struct b43_wldev *dev) 2704static int b43_chip_init(struct b43_wldev *dev)
2701{ 2705{
2702 struct b43_phy *phy = &dev->phy; 2706 struct b43_phy *phy = &dev->phy;
2703 int err, tmp; 2707 int err;
2704 u32 value32, macctl; 2708 u32 value32, macctl;
2705 u16 value16; 2709 u16 value16;
2706 2710
@@ -2725,19 +2729,19 @@ static int b43_chip_init(struct b43_wldev *dev)
2725 err = b43_upload_initvals(dev); 2729 err = b43_upload_initvals(dev);
2726 if (err) 2730 if (err)
2727 goto err_gpio_clean; 2731 goto err_gpio_clean;
2728 b43_radio_turn_on(dev);
2729 2732
2730 b43_write16(dev, 0x03E6, 0x0000); 2733 b43_write16(dev, 0x03E6, 0x0000);
2731 err = b43_phy_init(dev); 2734 err = b43_phy_init(dev);
2732 if (err) 2735 if (err)
2733 goto err_radio_off; 2736 goto err_gpio_clean;
2734 2737
2735 /* Select initial Interference Mitigation. */ 2738 /* Disable Interference Mitigation. */
2736 tmp = phy->interfmode; 2739 if (phy->ops->interf_mitigation)
2737 phy->interfmode = B43_INTERFMODE_NONE; 2740 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2738 b43_radio_set_interference_mitigation(dev, tmp);
2739 2741
2740 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); 2742 /* Select the antennae */
2743 if (phy->ops->set_rx_antenna)
2744 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2741 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); 2745 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2742 2746
2743 if (phy->type == B43_PHYTYPE_B) { 2747 if (phy->type == B43_PHYTYPE_B) {
@@ -2790,8 +2794,6 @@ static int b43_chip_init(struct b43_wldev *dev)
2790out: 2794out:
2791 return err; 2795 return err;
2792 2796
2793err_radio_off:
2794 b43_radio_turn_off(dev, 1);
2795err_gpio_clean: 2797err_gpio_clean:
2796 b43_gpio_cleanup(dev); 2798 b43_gpio_cleanup(dev);
2797 return err; 2799 return err;
@@ -2799,25 +2801,10 @@ err_gpio_clean:
2799 2801
2800static void b43_periodic_every60sec(struct b43_wldev *dev) 2802static void b43_periodic_every60sec(struct b43_wldev *dev)
2801{ 2803{
2802 struct b43_phy *phy = &dev->phy; 2804 const struct b43_phy_operations *ops = dev->phy.ops;
2803 2805
2804 if (phy->type != B43_PHYTYPE_G) 2806 if (ops->pwork_60sec)
2805 return; 2807 ops->pwork_60sec(dev);
2806 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2807 b43_mac_suspend(dev);
2808 b43_calc_nrssi_slope(dev);
2809 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2810 u8 old_chan = phy->channel;
2811
2812 /* VCO Calibration */
2813 if (old_chan >= 8)
2814 b43_radio_selectchannel(dev, 1, 0);
2815 else
2816 b43_radio_selectchannel(dev, 13, 0);
2817 b43_radio_selectchannel(dev, old_chan, 0);
2818 }
2819 b43_mac_enable(dev);
2820 }
2821} 2808}
2822 2809
2823static void b43_periodic_every30sec(struct b43_wldev *dev) 2810static void b43_periodic_every30sec(struct b43_wldev *dev)
@@ -2845,32 +2832,10 @@ static void b43_periodic_every15sec(struct b43_wldev *dev)
2845 } 2832 }
2846 } 2833 }
2847 2834
2848 if (phy->type == B43_PHYTYPE_G) { 2835 if (phy->ops->pwork_15sec)
2849 //TODO: update_aci_moving_average 2836 phy->ops->pwork_15sec(dev);
2850 if (phy->aci_enable && phy->aci_wlan_automatic) { 2837
2851 b43_mac_suspend(dev); 2838 phy->ops->xmitpower(dev);
2852 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2853 if (0 /*TODO: bunch of conditions */ ) {
2854 b43_radio_set_interference_mitigation
2855 (dev, B43_INTERFMODE_MANUALWLAN);
2856 }
2857 } else if (1 /*TODO*/) {
2858 /*
2859 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2860 b43_radio_set_interference_mitigation(dev,
2861 B43_INTERFMODE_NONE);
2862 }
2863 */
2864 }
2865 b43_mac_enable(dev);
2866 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2867 phy->rev == 1) {
2868 //TODO: implement rev1 workaround
2869 }
2870 }
2871 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2872 b43_lo_g_maintanance_work(dev);
2873 //TODO for APHY (temperature?)
2874 2839
2875 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 2840 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2876 wmb(); 2841 wmb();
@@ -3401,7 +3366,7 @@ static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3401 /* Switch to the requested channel. 3366 /* Switch to the requested channel.
3402 * The firmware takes care of races with the TX handler. */ 3367 * The firmware takes care of races with the TX handler. */
3403 if (conf->channel->hw_value != phy->channel) 3368 if (conf->channel->hw_value != phy->channel)
3404 b43_radio_selectchannel(dev, conf->channel->hw_value, 0); 3369 b43_switch_channel(dev, conf->channel->hw_value);
3405 3370
3406 /* Enable/Disable ShortSlot timing. */ 3371 /* Enable/Disable ShortSlot timing. */
3407 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != 3372 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
@@ -3419,7 +3384,7 @@ static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3419 if (conf->power_level != 0) { 3384 if (conf->power_level != 0) {
3420 if (conf->power_level != phy->power_level) { 3385 if (conf->power_level != phy->power_level) {
3421 phy->power_level = conf->power_level; 3386 phy->power_level = conf->power_level;
3422 b43_phy_xmitpower(dev); 3387 phy->ops->xmitpower(dev);
3423 } 3388 }
3424 } 3389 }
3425 3390
@@ -3427,7 +3392,8 @@ static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3427 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx); 3392 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
3428 b43_mgmtframe_txantenna(dev, antenna); 3393 b43_mgmtframe_txantenna(dev, antenna);
3429 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); 3394 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
3430 b43_set_rx_antenna(dev, antenna); 3395 if (phy->ops->set_rx_antenna)
3396 phy->ops->set_rx_antenna(dev, antenna);
3431 3397
3432 /* Update templates for AP/mesh mode. */ 3398 /* Update templates for AP/mesh mode. */
3433 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) || 3399 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP) ||
@@ -3436,7 +3402,7 @@ static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3436 3402
3437 if (!!conf->radio_enabled != phy->radio_on) { 3403 if (!!conf->radio_enabled != phy->radio_on) {
3438 if (conf->radio_enabled) { 3404 if (conf->radio_enabled) {
3439 b43_radio_turn_on(dev); 3405 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
3440 b43info(dev->wl, "Radio turned on by software\n"); 3406 b43info(dev->wl, "Radio turned on by software\n");
3441 if (!dev->radio_hw_enable) { 3407 if (!dev->radio_hw_enable) {
3442 b43info(dev->wl, "The hardware RF-kill button " 3408 b43info(dev->wl, "The hardware RF-kill button "
@@ -3444,7 +3410,7 @@ static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
3444 "Press the button to turn it on.\n"); 3410 "Press the button to turn it on.\n");
3445 } 3411 }
3446 } else { 3412 } else {
3447 b43_radio_turn_off(dev, 0); 3413 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
3448 b43info(dev->wl, "Radio turned off by software\n"); 3414 b43info(dev->wl, "Radio turned off by software\n");
3449 } 3415 }
3450 } 3416 }
@@ -3818,48 +3784,9 @@ static int b43_phy_versioning(struct b43_wldev *dev)
3818static void setup_struct_phy_for_init(struct b43_wldev *dev, 3784static void setup_struct_phy_for_init(struct b43_wldev *dev,
3819 struct b43_phy *phy) 3785 struct b43_phy *phy)
3820{ 3786{
3821 struct b43_txpower_lo_control *lo;
3822 int i;
3823
3824 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3825 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3826
3827 phy->aci_enable = 0;
3828 phy->aci_wlan_automatic = 0;
3829 phy->aci_hw_rssi = 0;
3830
3831 phy->radio_off_context.valid = 0;
3832
3833 lo = phy->lo_control;
3834 if (lo) {
3835 memset(lo, 0, sizeof(*(phy->lo_control)));
3836 lo->tx_bias = 0xFF;
3837 INIT_LIST_HEAD(&lo->calib_list);
3838 }
3839 phy->max_lb_gain = 0;
3840 phy->trsw_rx_gain = 0;
3841 phy->txpwr_offset = 0;
3842
3843 /* NRSSI */
3844 phy->nrssislope = 0;
3845 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3846 phy->nrssi[i] = -1000;
3847 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3848 phy->nrssi_lt[i] = i;
3849
3850 phy->lofcal = 0xFFFF;
3851 phy->initval = 0xFFFF;
3852
3853 phy->interfmode = B43_INTERFMODE_NONE;
3854 phy->channel = 0xFF;
3855
3856 phy->hardware_power_control = !!modparam_hwpctl; 3787 phy->hardware_power_control = !!modparam_hwpctl;
3857
3858 /* PHY TX errors counter. */ 3788 /* PHY TX errors counter. */
3859 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); 3789 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3860
3861 /* OFDM-table address caching. */
3862 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3863} 3790}
3864 3791
3865static void setup_struct_wldev_for_init(struct b43_wldev *dev) 3792static void setup_struct_wldev_for_init(struct b43_wldev *dev)
@@ -3995,7 +3922,6 @@ static void b43_set_pretbtt(struct b43_wldev *dev)
3995/* Locking: wl->mutex */ 3922/* Locking: wl->mutex */
3996static void b43_wireless_core_exit(struct b43_wldev *dev) 3923static void b43_wireless_core_exit(struct b43_wldev *dev)
3997{ 3924{
3998 struct b43_phy *phy = &dev->phy;
3999 u32 macctl; 3925 u32 macctl;
4000 3926
4001 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); 3927 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
@@ -4016,16 +3942,12 @@ static void b43_wireless_core_exit(struct b43_wldev *dev)
4016 b43_dma_free(dev); 3942 b43_dma_free(dev);
4017 b43_pio_free(dev); 3943 b43_pio_free(dev);
4018 b43_chip_exit(dev); 3944 b43_chip_exit(dev);
4019 b43_radio_turn_off(dev, 1);
4020 b43_switch_analog(dev, 0); 3945 b43_switch_analog(dev, 0);
4021 if (phy->dyn_tssi_tbl)
4022 kfree(phy->tssi2dbm);
4023 kfree(phy->lo_control);
4024 phy->lo_control = NULL;
4025 if (dev->wl->current_beacon) { 3946 if (dev->wl->current_beacon) {
4026 dev_kfree_skb_any(dev->wl->current_beacon); 3947 dev_kfree_skb_any(dev->wl->current_beacon);
4027 dev->wl->current_beacon = NULL; 3948 dev->wl->current_beacon = NULL;
4028 } 3949 }
3950 b43_phy_exit(dev);
4029 3951
4030 ssb_device_disable(dev->dev, 0); 3952 ssb_device_disable(dev->dev, 0);
4031 ssb_bus_may_powerdown(dev->dev->bus); 3953 ssb_bus_may_powerdown(dev->dev->bus);
@@ -4052,29 +3974,24 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
4052 b43_wireless_core_reset(dev, tmp); 3974 b43_wireless_core_reset(dev, tmp);
4053 } 3975 }
4054 3976
4055 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
4056 phy->lo_control =
4057 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
4058 if (!phy->lo_control) {
4059 err = -ENOMEM;
4060 goto err_busdown;
4061 }
4062 }
4063 setup_struct_wldev_for_init(dev); 3977 setup_struct_wldev_for_init(dev);
4064 3978 err = b43_phy_operations_setup(dev);
4065 err = b43_phy_init_tssi2dbm_table(dev);
4066 if (err) 3979 if (err)
4067 goto err_kfree_lo_control; 3980 goto err_busdown;
4068 3981
4069 /* Enable IRQ routing to this device. */ 3982 /* Enable IRQ routing to this device. */
4070 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); 3983 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4071 3984
4072 b43_imcfglo_timeouts_workaround(dev); 3985 b43_imcfglo_timeouts_workaround(dev);
4073 b43_bluetooth_coext_disable(dev); 3986 b43_bluetooth_coext_disable(dev);
4074 b43_phy_early_init(dev); 3987 if (phy->ops->prepare) {
3988 err = phy->ops->prepare(dev);
3989 if (err)
3990 goto err_phy_exit;
3991 }
4075 err = b43_chip_init(dev); 3992 err = b43_chip_init(dev);
4076 if (err) 3993 if (err)
4077 goto err_kfree_tssitbl; 3994 goto err_phy_exit;
4078 b43_shm_write16(dev, B43_SHM_SHARED, 3995 b43_shm_write16(dev, B43_SHM_SHARED,
4079 B43_SHM_SH_WLCOREREV, dev->dev->id.revision); 3996 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4080 hf = b43_hf_read(dev); 3997 hf = b43_hf_read(dev);
@@ -4140,15 +4057,11 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
4140out: 4057out:
4141 return err; 4058 return err;
4142 4059
4143 err_chip_exit: 4060err_chip_exit:
4144 b43_chip_exit(dev); 4061 b43_chip_exit(dev);
4145 err_kfree_tssitbl: 4062err_phy_exit:
4146 if (phy->dyn_tssi_tbl) 4063 b43_phy_exit(dev);
4147 kfree(phy->tssi2dbm); 4064err_busdown:
4148 err_kfree_lo_control:
4149 kfree(phy->lo_control);
4150 phy->lo_control = NULL;
4151 err_busdown:
4152 ssb_bus_may_powerdown(bus); 4065 ssb_bus_may_powerdown(bus);
4153 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4066 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4154 return err; 4067 return err;
@@ -4511,7 +4424,6 @@ static int b43_wireless_core_attach(struct b43_wldev *dev)
4511 wl->current_dev = dev; 4424 wl->current_dev = dev;
4512 INIT_WORK(&dev->restart_work, b43_chip_reset); 4425 INIT_WORK(&dev->restart_work, b43_chip_reset);
4513 4426
4514 b43_radio_turn_off(dev, 1);
4515 b43_switch_analog(dev, 0); 4427 b43_switch_analog(dev, 0);
4516 ssb_device_disable(dev->dev, 0); 4428 ssb_device_disable(dev->dev, 0);
4517 ssb_bus_may_powerdown(bus); 4429 ssb_bus_may_powerdown(bus);
diff --git a/drivers/net/wireless/b43/nphy.c b/drivers/net/wireless/b43/nphy.c
index 644eed993bea..831986c459f8 100644
--- a/drivers/net/wireless/b43/nphy.c
+++ b/drivers/net/wireless/b43/nphy.c
@@ -81,9 +81,8 @@ static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
81 //TODO 81 //TODO
82} 82}
83 83
84/* Tune the hardware to a new channel. Don't call this directly. 84/* Tune the hardware to a new channel. */
85 * Use b43_radio_selectchannel() */ 85static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
86int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
87{ 86{
88 const struct b43_nphy_channeltab_entry *tabent; 87 const struct b43_nphy_channeltab_entry *tabent;
89 88
@@ -162,7 +161,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
162 msleep(1); 161 msleep(1);
163 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 162 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
164 msleep(1); 163 msleep(1);
165 b43_radio_selectchannel(dev, dev->phy.channel, 0); 164 nphy_channel_switch(dev, dev->phy.channel);
166 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9); 165 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
167 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9); 166 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
168 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83); 167 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
@@ -484,3 +483,139 @@ int b43_phy_initn(struct b43_wldev *dev)
484 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); 483 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
485 return 0; 484 return 0;
486} 485}
486
487static int b43_nphy_op_allocate(struct b43_wldev *dev)
488{
489 struct b43_phy_n *nphy;
490
491 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
492 if (!nphy)
493 return -ENOMEM;
494 dev->phy.n = nphy;
495
496 //TODO init struct b43_phy_n
497
498 return 0;
499}
500
501static int b43_nphy_op_init(struct b43_wldev *dev)
502{
503 struct b43_phy_n *nphy = dev->phy.n;
504 int err;
505
506 err = b43_phy_initn(dev);
507 if (err)
508 return err;
509 nphy->initialised = 1;
510
511 return 0;
512}
513
514static void b43_nphy_op_exit(struct b43_wldev *dev)
515{
516 struct b43_phy_n *nphy = dev->phy.n;
517
518 if (nphy->initialised) {
519 //TODO
520 nphy->initialised = 0;
521 }
522 //TODO
523 kfree(nphy);
524 dev->phy.n = NULL;
525}
526
527static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
528{
529#if B43_DEBUG
530 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
531 /* OFDM registers are onnly available on A/G-PHYs */
532 b43err(dev->wl, "Invalid OFDM PHY access at "
533 "0x%04X on N-PHY\n", offset);
534 dump_stack();
535 }
536 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
537 /* Ext-G registers are only available on G-PHYs */
538 b43err(dev->wl, "Invalid EXT-G PHY access at "
539 "0x%04X on N-PHY\n", offset);
540 dump_stack();
541 }
542#endif /* B43_DEBUG */
543}
544
545static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
546{
547 check_phyreg(dev, reg);
548 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
549 return b43_read16(dev, B43_MMIO_PHY_DATA);
550}
551
552static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
553{
554 check_phyreg(dev, reg);
555 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
556 b43_write16(dev, B43_MMIO_PHY_DATA, value);
557}
558
559static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
560{
561 /* Register 1 is a 32-bit register. */
562 B43_WARN_ON(reg == 1);
563 /* N-PHY needs 0x100 for read access */
564 reg |= 0x100;
565
566 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
567 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
568}
569
570static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
571{
572 /* Register 1 is a 32-bit register. */
573 B43_WARN_ON(reg == 1);
574
575 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
576 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
577}
578
579static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
580 enum rfkill_state state)
581{//TODO
582}
583
584static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
585 unsigned int new_channel)
586{
587 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
588 if ((new_channel < 1) || (new_channel > 14))
589 return -EINVAL;
590 } else {
591 if (new_channel > 200)
592 return -EINVAL;
593 }
594
595 return nphy_channel_switch(dev, new_channel);
596}
597
598static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
599{
600 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
601 return 1;
602 return 36;
603}
604
605static void b43_nphy_op_xmitpower(struct b43_wldev *dev)
606{//TODO
607}
608
609const struct b43_phy_operations b43_phyops_n = {
610 .allocate = b43_nphy_op_allocate,
611 .init = b43_nphy_op_init,
612 .exit = b43_nphy_op_exit,
613 .phy_read = b43_nphy_op_read,
614 .phy_write = b43_nphy_op_write,
615 .radio_read = b43_nphy_op_radio_read,
616 .radio_write = b43_nphy_op_radio_write,
617 .software_rfkill = b43_nphy_op_software_rfkill,
618 .switch_channel = b43_nphy_op_switch_channel,
619 .get_default_chan = b43_nphy_op_get_default_chan,
620 .xmitpower = b43_nphy_op_xmitpower,
621};
diff --git a/drivers/net/wireless/b43/nphy.h b/drivers/net/wireless/b43/nphy.h
index faf46b9cbf1b..3d1f65ed2012 100644
--- a/drivers/net/wireless/b43/nphy.h
+++ b/drivers/net/wireless/b43/nphy.h
@@ -1,7 +1,7 @@
1#ifndef B43_NPHY_H_ 1#ifndef B43_NPHY_H_
2#define B43_NPHY_H_ 2#define B43_NPHY_H_
3 3
4#include "phy.h" 4#include "phy_common.h"
5 5
6 6
7/* N-PHY registers. */ 7/* N-PHY registers. */
@@ -919,54 +919,14 @@
919 919
920struct b43_wldev; 920struct b43_wldev;
921 921
922struct b43_phy_n {
923 bool initialised;
922 924
923#ifdef CONFIG_B43_NPHY 925 //TODO lots of missing stuff
924/* N-PHY support enabled */ 926};
925 927
926int b43_phy_initn(struct b43_wldev *dev);
927 928
928void b43_nphy_radio_turn_on(struct b43_wldev *dev); 929struct b43_phy_operations;
929void b43_nphy_radio_turn_off(struct b43_wldev *dev); 930extern const struct b43_phy_operations b43_phyops_n;
930 931
931int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel);
932
933void b43_nphy_xmitpower(struct b43_wldev *dev);
934void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna);
935
936
937#else /* CONFIG_B43_NPHY */
938/* N-PHY support disabled */
939
940
941static inline
942int b43_phy_initn(struct b43_wldev *dev)
943{
944 return -EOPNOTSUPP;
945}
946
947static inline
948void b43_nphy_radio_turn_on(struct b43_wldev *dev)
949{
950}
951static inline
952void b43_nphy_radio_turn_off(struct b43_wldev *dev)
953{
954}
955
956static inline
957int b43_nphy_selectchannel(struct b43_wldev *dev, u8 channel)
958{
959 return -ENOSYS;
960}
961
962static inline
963void b43_nphy_xmitpower(struct b43_wldev *dev)
964{
965}
966static inline
967void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
968{
969}
970
971#endif /* CONFIG_B43_NPHY */
972#endif /* B43_NPHY_H_ */ 932#endif /* B43_NPHY_H_ */
diff --git a/drivers/net/wireless/b43/phy.c b/drivers/net/wireless/b43/phy.c
index 305d4cd6fd03..02ae450beb00 100644
--- a/drivers/net/wireless/b43/phy.c
+++ b/drivers/net/wireless/b43/phy.c
@@ -39,160 +39,6 @@
39#include "wa.h" 39#include "wa.h"
40 40
41 41
42static const s8 b43_tssi2dbm_b_table[] = {
43 0x4D, 0x4C, 0x4B, 0x4A,
44 0x4A, 0x49, 0x48, 0x47,
45 0x47, 0x46, 0x45, 0x45,
46 0x44, 0x43, 0x42, 0x42,
47 0x41, 0x40, 0x3F, 0x3E,
48 0x3D, 0x3C, 0x3B, 0x3A,
49 0x39, 0x38, 0x37, 0x36,
50 0x35, 0x34, 0x32, 0x31,
51 0x30, 0x2F, 0x2D, 0x2C,
52 0x2B, 0x29, 0x28, 0x26,
53 0x25, 0x23, 0x21, 0x1F,
54 0x1D, 0x1A, 0x17, 0x14,
55 0x10, 0x0C, 0x06, 0x00,
56 -7, -7, -7, -7,
57 -7, -7, -7, -7,
58 -7, -7, -7, -7,
59};
60
61static const s8 b43_tssi2dbm_g_table[] = {
62 77, 77, 77, 76,
63 76, 76, 75, 75,
64 74, 74, 73, 73,
65 73, 72, 72, 71,
66 71, 70, 70, 69,
67 68, 68, 67, 67,
68 66, 65, 65, 64,
69 63, 63, 62, 61,
70 60, 59, 58, 57,
71 56, 55, 54, 53,
72 52, 50, 49, 47,
73 45, 43, 40, 37,
74 33, 28, 22, 14,
75 5, -7, -20, -20,
76 -20, -20, -20, -20,
77 -20, -20, -20, -20,
78};
79
80const u8 b43_radio_channel_codes_bg[] = {
81 12, 17, 22, 27,
82 32, 37, 42, 47,
83 52, 57, 62, 67,
84 72, 84,
85};
86
87#define bitrev4(tmp) (bitrev8(tmp) >> 4)
88static void b43_phy_initg(struct b43_wldev *dev);
89
90static void generate_rfatt_list(struct b43_wldev *dev,
91 struct b43_rfatt_list *list)
92{
93 struct b43_phy *phy = &dev->phy;
94
95 /* APHY.rev < 5 || GPHY.rev < 6 */
96 static const struct b43_rfatt rfatt_0[] = {
97 {.att = 3,.with_padmix = 0,},
98 {.att = 1,.with_padmix = 0,},
99 {.att = 5,.with_padmix = 0,},
100 {.att = 7,.with_padmix = 0,},
101 {.att = 9,.with_padmix = 0,},
102 {.att = 2,.with_padmix = 0,},
103 {.att = 0,.with_padmix = 0,},
104 {.att = 4,.with_padmix = 0,},
105 {.att = 6,.with_padmix = 0,},
106 {.att = 8,.with_padmix = 0,},
107 {.att = 1,.with_padmix = 1,},
108 {.att = 2,.with_padmix = 1,},
109 {.att = 3,.with_padmix = 1,},
110 {.att = 4,.with_padmix = 1,},
111 };
112 /* Radio.rev == 8 && Radio.version == 0x2050 */
113 static const struct b43_rfatt rfatt_1[] = {
114 {.att = 2,.with_padmix = 1,},
115 {.att = 4,.with_padmix = 1,},
116 {.att = 6,.with_padmix = 1,},
117 {.att = 8,.with_padmix = 1,},
118 {.att = 10,.with_padmix = 1,},
119 {.att = 12,.with_padmix = 1,},
120 {.att = 14,.with_padmix = 1,},
121 };
122 /* Otherwise */
123 static const struct b43_rfatt rfatt_2[] = {
124 {.att = 0,.with_padmix = 1,},
125 {.att = 2,.with_padmix = 1,},
126 {.att = 4,.with_padmix = 1,},
127 {.att = 6,.with_padmix = 1,},
128 {.att = 8,.with_padmix = 1,},
129 {.att = 9,.with_padmix = 1,},
130 {.att = 9,.with_padmix = 1,},
131 };
132
133 if (!b43_has_hardware_pctl(phy)) {
134 /* Software pctl */
135 list->list = rfatt_0;
136 list->len = ARRAY_SIZE(rfatt_0);
137 list->min_val = 0;
138 list->max_val = 9;
139 return;
140 }
141 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
142 /* Hardware pctl */
143 list->list = rfatt_1;
144 list->len = ARRAY_SIZE(rfatt_1);
145 list->min_val = 0;
146 list->max_val = 14;
147 return;
148 }
149 /* Hardware pctl */
150 list->list = rfatt_2;
151 list->len = ARRAY_SIZE(rfatt_2);
152 list->min_val = 0;
153 list->max_val = 9;
154}
155
156static void generate_bbatt_list(struct b43_wldev *dev,
157 struct b43_bbatt_list *list)
158{
159 static const struct b43_bbatt bbatt_0[] = {
160 {.att = 0,},
161 {.att = 1,},
162 {.att = 2,},
163 {.att = 3,},
164 {.att = 4,},
165 {.att = 5,},
166 {.att = 6,},
167 {.att = 7,},
168 {.att = 8,},
169 };
170
171 list->list = bbatt_0;
172 list->len = ARRAY_SIZE(bbatt_0);
173 list->min_val = 0;
174 list->max_val = 8;
175}
176
177bool b43_has_hardware_pctl(struct b43_phy *phy)
178{
179 if (!phy->hardware_power_control)
180 return 0;
181 switch (phy->type) {
182 case B43_PHYTYPE_A:
183 if (phy->rev >= 5)
184 return 1;
185 break;
186 case B43_PHYTYPE_G:
187 if (phy->rev >= 6)
188 return 1;
189 break;
190 default:
191 B43_WARN_ON(1);
192 }
193 return 0;
194}
195
196static void b43_shm_clear_tssi(struct b43_wldev *dev) 42static void b43_shm_clear_tssi(struct b43_wldev *dev)
197{ 43{
198 struct b43_phy *phy = &dev->phy; 44 struct b43_phy *phy = &dev->phy;
@@ -212,1242 +58,6 @@ static void b43_shm_clear_tssi(struct b43_wldev *dev)
212 } 58 }
213} 59}
214 60
215/* Lock the PHY registers against concurrent access from the microcode.
216 * This lock is nonrecursive. */
217void b43_phy_lock(struct b43_wldev *dev)
218{
219#if B43_DEBUG
220 B43_WARN_ON(dev->phy.phy_locked);
221 dev->phy.phy_locked = 1;
222#endif
223 B43_WARN_ON(dev->dev->id.revision < 3);
224
225 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
226 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
227}
228
229void b43_phy_unlock(struct b43_wldev *dev)
230{
231#if B43_DEBUG
232 B43_WARN_ON(!dev->phy.phy_locked);
233 dev->phy.phy_locked = 0;
234#endif
235 B43_WARN_ON(dev->dev->id.revision < 3);
236
237 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
238 b43_power_saving_ctl_bits(dev, 0);
239}
240
241/* Different PHYs require different register routing flags.
242 * This adjusts (and does sanity checks on) the routing flags.
243 */
244static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
245 u16 offset, struct b43_wldev *dev)
246{
247 if (phy->type == B43_PHYTYPE_A) {
248 /* OFDM registers are base-registers for the A-PHY. */
249 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
250 offset &= ~B43_PHYROUTE;
251 offset |= B43_PHYROUTE_BASE;
252 }
253 }
254
255#if B43_DEBUG
256 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
257 /* Ext-G registers are only available on G-PHYs */
258 if (phy->type != B43_PHYTYPE_G) {
259 b43err(dev->wl, "Invalid EXT-G PHY access at "
260 "0x%04X on PHY type %u\n", offset, phy->type);
261 dump_stack();
262 }
263 }
264 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
265 /* N-BMODE registers are only available on N-PHYs */
266 if (phy->type != B43_PHYTYPE_N) {
267 b43err(dev->wl, "Invalid N-BMODE PHY access at "
268 "0x%04X on PHY type %u\n", offset, phy->type);
269 dump_stack();
270 }
271 }
272#endif /* B43_DEBUG */
273
274 return offset;
275}
276
277u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
278{
279 struct b43_phy *phy = &dev->phy;
280
281 offset = adjust_phyreg_for_phytype(phy, offset, dev);
282 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
283 return b43_read16(dev, B43_MMIO_PHY_DATA);
284}
285
286void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
287{
288 struct b43_phy *phy = &dev->phy;
289
290 offset = adjust_phyreg_for_phytype(phy, offset, dev);
291 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
292 b43_write16(dev, B43_MMIO_PHY_DATA, val);
293}
294
295void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
296{
297 b43_phy_write(dev, offset,
298 b43_phy_read(dev, offset) & mask);
299}
300
301void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
302{
303 b43_phy_write(dev, offset,
304 b43_phy_read(dev, offset) | set);
305}
306
307void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
308{
309 b43_phy_write(dev, offset,
310 (b43_phy_read(dev, offset) & mask) | set);
311}
312
313/* Adjust the transmission power output (G-PHY) */
314void b43_set_txpower_g(struct b43_wldev *dev,
315 const struct b43_bbatt *bbatt,
316 const struct b43_rfatt *rfatt, u8 tx_control)
317{
318 struct b43_phy *phy = &dev->phy;
319 struct b43_txpower_lo_control *lo = phy->lo_control;
320 u16 bb, rf;
321 u16 tx_bias, tx_magn;
322
323 bb = bbatt->att;
324 rf = rfatt->att;
325 tx_bias = lo->tx_bias;
326 tx_magn = lo->tx_magn;
327 if (unlikely(tx_bias == 0xFF))
328 tx_bias = 0;
329
330 /* Save the values for later */
331 phy->tx_control = tx_control;
332 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
333 phy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
334 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
335
336 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
337 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
338 "rfatt(%u), tx_control(0x%02X), "
339 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
340 bb, rf, tx_control, tx_bias, tx_magn);
341 }
342
343 b43_phy_set_baseband_attenuation(dev, bb);
344 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
345 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
346 b43_radio_write16(dev, 0x43,
347 (rf & 0x000F) | (tx_control & 0x0070));
348 } else {
349 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
350 & 0xFFF0) | (rf & 0x000F));
351 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
352 & ~0x0070) | (tx_control &
353 0x0070));
354 }
355 if (has_tx_magnification(phy)) {
356 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
357 } else {
358 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
359 & 0xFFF0) | (tx_bias & 0x000F));
360 }
361 if (phy->type == B43_PHYTYPE_G)
362 b43_lo_g_adjust(dev);
363}
364
365static void default_baseband_attenuation(struct b43_wldev *dev,
366 struct b43_bbatt *bb)
367{
368 struct b43_phy *phy = &dev->phy;
369
370 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
371 bb->att = 0;
372 else
373 bb->att = 2;
374}
375
376static void default_radio_attenuation(struct b43_wldev *dev,
377 struct b43_rfatt *rf)
378{
379 struct ssb_bus *bus = dev->dev->bus;
380 struct b43_phy *phy = &dev->phy;
381
382 rf->with_padmix = 0;
383
384 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
385 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
386 if (bus->boardinfo.rev < 0x43) {
387 rf->att = 2;
388 return;
389 } else if (bus->boardinfo.rev < 0x51) {
390 rf->att = 3;
391 return;
392 }
393 }
394
395 if (phy->type == B43_PHYTYPE_A) {
396 rf->att = 0x60;
397 return;
398 }
399
400 switch (phy->radio_ver) {
401 case 0x2053:
402 switch (phy->radio_rev) {
403 case 1:
404 rf->att = 6;
405 return;
406 }
407 break;
408 case 0x2050:
409 switch (phy->radio_rev) {
410 case 0:
411 rf->att = 5;
412 return;
413 case 1:
414 if (phy->type == B43_PHYTYPE_G) {
415 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
416 && bus->boardinfo.type == SSB_BOARD_BCM4309G
417 && bus->boardinfo.rev >= 30)
418 rf->att = 3;
419 else if (bus->boardinfo.vendor ==
420 SSB_BOARDVENDOR_BCM
421 && bus->boardinfo.type ==
422 SSB_BOARD_BU4306)
423 rf->att = 3;
424 else
425 rf->att = 1;
426 } else {
427 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
428 && bus->boardinfo.type == SSB_BOARD_BCM4309G
429 && bus->boardinfo.rev >= 30)
430 rf->att = 7;
431 else
432 rf->att = 6;
433 }
434 return;
435 case 2:
436 if (phy->type == B43_PHYTYPE_G) {
437 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
438 && bus->boardinfo.type == SSB_BOARD_BCM4309G
439 && bus->boardinfo.rev >= 30)
440 rf->att = 3;
441 else if (bus->boardinfo.vendor ==
442 SSB_BOARDVENDOR_BCM
443 && bus->boardinfo.type ==
444 SSB_BOARD_BU4306)
445 rf->att = 5;
446 else if (bus->chip_id == 0x4320)
447 rf->att = 4;
448 else
449 rf->att = 3;
450 } else
451 rf->att = 6;
452 return;
453 case 3:
454 rf->att = 5;
455 return;
456 case 4:
457 case 5:
458 rf->att = 1;
459 return;
460 case 6:
461 case 7:
462 rf->att = 5;
463 return;
464 case 8:
465 rf->att = 0xA;
466 rf->with_padmix = 1;
467 return;
468 case 9:
469 default:
470 rf->att = 5;
471 return;
472 }
473 }
474 rf->att = 5;
475}
476
477static u16 default_tx_control(struct b43_wldev *dev)
478{
479 struct b43_phy *phy = &dev->phy;
480
481 if (phy->radio_ver != 0x2050)
482 return 0;
483 if (phy->radio_rev == 1)
484 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
485 if (phy->radio_rev < 6)
486 return B43_TXCTL_PA2DB;
487 if (phy->radio_rev == 8)
488 return B43_TXCTL_TXMIX;
489 return 0;
490}
491
492/* This func is called "PHY calibrate" in the specs... */
493void b43_phy_early_init(struct b43_wldev *dev)
494{
495 struct b43_phy *phy = &dev->phy;
496 struct b43_txpower_lo_control *lo = phy->lo_control;
497
498 default_baseband_attenuation(dev, &phy->bbatt);
499 default_radio_attenuation(dev, &phy->rfatt);
500 phy->tx_control = (default_tx_control(dev) << 4);
501
502 /* Commit previous writes */
503 b43_read32(dev, B43_MMIO_MACCTL);
504
505 if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
506 generate_rfatt_list(dev, &lo->rfatt_list);
507 generate_bbatt_list(dev, &lo->bbatt_list);
508 }
509 if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
510 /* Workaround: Temporarly disable gmode through the early init
511 * phase, as the gmode stuff is not needed for phy rev 1 */
512 phy->gmode = 0;
513 b43_wireless_core_reset(dev, 0);
514 b43_phy_initg(dev);
515 phy->gmode = 1;
516 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
517 }
518}
519
520/* GPHY_TSSI_Power_Lookup_Table_Init */
521static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
522{
523 struct b43_phy *phy = &dev->phy;
524 int i;
525 u16 value;
526
527 for (i = 0; i < 32; i++)
528 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
529 for (i = 32; i < 64; i++)
530 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
531 for (i = 0; i < 64; i += 2) {
532 value = (u16) phy->tssi2dbm[i];
533 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
534 b43_phy_write(dev, 0x380 + (i / 2), value);
535 }
536}
537
538/* GPHY_Gain_Lookup_Table_Init */
539static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
540{
541 struct b43_phy *phy = &dev->phy;
542 struct b43_txpower_lo_control *lo = phy->lo_control;
543 u16 nr_written = 0;
544 u16 tmp;
545 u8 rf, bb;
546
547 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
548 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
549 if (nr_written >= 0x40)
550 return;
551 tmp = lo->bbatt_list.list[bb].att;
552 tmp <<= 8;
553 if (phy->radio_rev == 8)
554 tmp |= 0x50;
555 else
556 tmp |= 0x40;
557 tmp |= lo->rfatt_list.list[rf].att;
558 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
559 nr_written++;
560 }
561 }
562}
563
564static void hardware_pctl_init_aphy(struct b43_wldev *dev)
565{
566 //TODO
567}
568
569static void hardware_pctl_init_gphy(struct b43_wldev *dev)
570{
571 struct b43_phy *phy = &dev->phy;
572
573 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
574 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
575 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
576 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
577 b43_gphy_tssi_power_lt_init(dev);
578 b43_gphy_gain_lt_init(dev);
579 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
580 b43_phy_write(dev, 0x0014, 0x0000);
581
582 B43_WARN_ON(phy->rev < 6);
583 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
584 | 0x0800);
585 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
586 & 0xFEFF);
587 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
588 & 0xFFBF);
589
590 b43_gphy_dc_lt_init(dev, 1);
591}
592
593/* HardwarePowerControl init for A and G PHY */
594static void b43_hardware_pctl_init(struct b43_wldev *dev)
595{
596 struct b43_phy *phy = &dev->phy;
597
598 if (!b43_has_hardware_pctl(phy)) {
599 /* No hardware power control */
600 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
601 return;
602 }
603 /* Init the hwpctl related hardware */
604 switch (phy->type) {
605 case B43_PHYTYPE_A:
606 hardware_pctl_init_aphy(dev);
607 break;
608 case B43_PHYTYPE_G:
609 hardware_pctl_init_gphy(dev);
610 break;
611 default:
612 B43_WARN_ON(1);
613 }
614 /* Enable hardware pctl in firmware. */
615 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
616}
617
618static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
619{
620 struct b43_phy *phy = &dev->phy;
621
622 if (!b43_has_hardware_pctl(phy)) {
623 b43_phy_write(dev, 0x047A, 0xC111);
624 return;
625 }
626
627 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
628 b43_phy_write(dev, 0x002F, 0x0202);
629 b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
630 b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
631 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
632 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
633 & 0xFF0F) | 0x0010);
634 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
635 | 0x8000);
636 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
637 & 0xFFC0) | 0x0010);
638 b43_phy_write(dev, 0x002E, 0xC07F);
639 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
640 | 0x0400);
641 } else {
642 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
643 | 0x0200);
644 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
645 | 0x0400);
646 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
647 & 0x7FFF);
648 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
649 & 0xFFFE);
650 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
651 & 0xFFC0) | 0x0010);
652 b43_phy_write(dev, 0x002E, 0xC07F);
653 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
654 & 0xFF0F) | 0x0010);
655 }
656}
657
658/* Intialize B/G PHY power control
659 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
660 */
661static void b43_phy_init_pctl(struct b43_wldev *dev)
662{
663 struct ssb_bus *bus = dev->dev->bus;
664 struct b43_phy *phy = &dev->phy;
665 struct b43_rfatt old_rfatt;
666 struct b43_bbatt old_bbatt;
667 u8 old_tx_control = 0;
668
669 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
670 (bus->boardinfo.type == SSB_BOARD_BU4306))
671 return;
672
673 b43_phy_write(dev, 0x0028, 0x8018);
674
675 /* This does something with the Analog... */
676 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
677 & 0xFFDF);
678
679 if (phy->type == B43_PHYTYPE_G && !phy->gmode)
680 return;
681 b43_hardware_pctl_early_init(dev);
682 if (phy->cur_idle_tssi == 0) {
683 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
684 b43_radio_write16(dev, 0x0076,
685 (b43_radio_read16(dev, 0x0076)
686 & 0x00F7) | 0x0084);
687 } else {
688 struct b43_rfatt rfatt;
689 struct b43_bbatt bbatt;
690
691 memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
692 memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
693 old_tx_control = phy->tx_control;
694
695 bbatt.att = 11;
696 if (phy->radio_rev == 8) {
697 rfatt.att = 15;
698 rfatt.with_padmix = 1;
699 } else {
700 rfatt.att = 9;
701 rfatt.with_padmix = 0;
702 }
703 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
704 }
705 b43_dummy_transmission(dev);
706 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
707 if (B43_DEBUG) {
708 /* Current-Idle-TSSI sanity check. */
709 if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
710 b43dbg(dev->wl,
711 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
712 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
713 "adjustment.\n", phy->cur_idle_tssi,
714 phy->tgt_idle_tssi);
715 phy->cur_idle_tssi = 0;
716 }
717 }
718 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
719 b43_radio_write16(dev, 0x0076,
720 b43_radio_read16(dev, 0x0076)
721 & 0xFF7B);
722 } else {
723 b43_set_txpower_g(dev, &old_bbatt,
724 &old_rfatt, old_tx_control);
725 }
726 }
727 b43_hardware_pctl_init(dev);
728 b43_shm_clear_tssi(dev);
729}
730
731static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
732{
733 int i;
734
735 if (dev->phy.rev < 3) {
736 if (enable)
737 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
738 b43_ofdmtab_write16(dev,
739 B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
740 b43_ofdmtab_write16(dev,
741 B43_OFDMTAB_WRSSI, i, 0xFFF8);
742 }
743 else
744 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
745 b43_ofdmtab_write16(dev,
746 B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
747 b43_ofdmtab_write16(dev,
748 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
749 }
750 } else {
751 if (enable)
752 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
753 b43_ofdmtab_write16(dev,
754 B43_OFDMTAB_WRSSI, i, 0x0820);
755 else
756 for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
757 b43_ofdmtab_write16(dev,
758 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
759 }
760}
761
762static void b43_phy_ww(struct b43_wldev *dev)
763{
764 u16 b, curr_s, best_s = 0xFFFF;
765 int i;
766
767 b43_phy_write(dev, B43_PHY_CRS0,
768 b43_phy_read(dev, B43_PHY_CRS0) & ~B43_PHY_CRS0_EN);
769 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
770 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) | 0x1000);
771 b43_phy_write(dev, B43_PHY_OFDM(0x82),
772 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
773 b43_radio_write16(dev, 0x0009,
774 b43_radio_read16(dev, 0x0009) | 0x0080);
775 b43_radio_write16(dev, 0x0012,
776 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
777 b43_wa_initgains(dev);
778 b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
779 b = b43_phy_read(dev, B43_PHY_PWRDOWN);
780 b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
781 b43_radio_write16(dev, 0x0004,
782 b43_radio_read16(dev, 0x0004) | 0x0004);
783 for (i = 0x10; i <= 0x20; i++) {
784 b43_radio_write16(dev, 0x0013, i);
785 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
786 if (!curr_s) {
787 best_s = 0x0000;
788 break;
789 } else if (curr_s >= 0x0080)
790 curr_s = 0x0100 - curr_s;
791 if (curr_s < best_s)
792 best_s = curr_s;
793 }
794 b43_phy_write(dev, B43_PHY_PWRDOWN, b);
795 b43_radio_write16(dev, 0x0004,
796 b43_radio_read16(dev, 0x0004) & 0xFFFB);
797 b43_radio_write16(dev, 0x0013, best_s);
798 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
799 b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
800 b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
801 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
802 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
803 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
804 b43_phy_write(dev, B43_PHY_OFDM(0xBB),
805 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
806 b43_phy_write(dev, B43_PHY_OFDM61,
807 (b43_phy_read(dev, B43_PHY_OFDM61) & 0xFE1F) | 0x0120);
808 b43_phy_write(dev, B43_PHY_OFDM(0x13),
809 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
810 b43_phy_write(dev, B43_PHY_OFDM(0x14),
811 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
812 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
813 for (i = 0; i < 6; i++)
814 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
815 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
816 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
817 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
818 b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
819 b43_phy_write(dev, B43_PHY_CRS0,
820 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
821}
822
823/* Initialize APHY. This is also called for the GPHY in some cases. */
824static void b43_phy_inita(struct b43_wldev *dev)
825{
826 struct ssb_bus *bus = dev->dev->bus;
827 struct b43_phy *phy = &dev->phy;
828
829 might_sleep();
830
831 if (phy->rev >= 6) {
832 if (phy->type == B43_PHYTYPE_A)
833 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
834 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x1000);
835 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
836 b43_phy_write(dev, B43_PHY_ENCORE,
837 b43_phy_read(dev, B43_PHY_ENCORE) | 0x0010);
838 else
839 b43_phy_write(dev, B43_PHY_ENCORE,
840 b43_phy_read(dev, B43_PHY_ENCORE) & ~0x1010);
841 }
842
843 b43_wa_all(dev);
844
845 if (phy->type == B43_PHYTYPE_A) {
846 if (phy->gmode && (phy->rev < 3))
847 b43_phy_write(dev, 0x0034,
848 b43_phy_read(dev, 0x0034) | 0x0001);
849 b43_phy_rssiagc(dev, 0);
850
851 b43_phy_write(dev, B43_PHY_CRS0,
852 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
853
854 b43_radio_init2060(dev);
855
856 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
857 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
858 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
859 ; //TODO: A PHY LO
860 }
861
862 if (phy->rev >= 3)
863 b43_phy_ww(dev);
864
865 hardware_pctl_init_aphy(dev);
866
867 //TODO: radar detection
868 }
869
870 if ((phy->type == B43_PHYTYPE_G) &&
871 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
872 b43_phy_write(dev, B43_PHY_OFDM(0x6E),
873 (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
874 & 0xE000) | 0x3CF);
875 }
876}
877
878static void b43_phy_initb5(struct b43_wldev *dev)
879{
880 struct ssb_bus *bus = dev->dev->bus;
881 struct b43_phy *phy = &dev->phy;
882 u16 offset, value;
883 u8 old_channel;
884
885 if (phy->analog == 1) {
886 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
887 | 0x0050);
888 }
889 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
890 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
891 value = 0x2120;
892 for (offset = 0x00A8; offset < 0x00C7; offset++) {
893 b43_phy_write(dev, offset, value);
894 value += 0x202;
895 }
896 }
897 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
898 | 0x0700);
899 if (phy->radio_ver == 0x2050)
900 b43_phy_write(dev, 0x0038, 0x0667);
901
902 if (phy->gmode || phy->rev >= 2) {
903 if (phy->radio_ver == 0x2050) {
904 b43_radio_write16(dev, 0x007A,
905 b43_radio_read16(dev, 0x007A)
906 | 0x0020);
907 b43_radio_write16(dev, 0x0051,
908 b43_radio_read16(dev, 0x0051)
909 | 0x0004);
910 }
911 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
912
913 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
914 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
915
916 b43_phy_write(dev, 0x001C, 0x186A);
917
918 b43_phy_write(dev, 0x0013,
919 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
920 b43_phy_write(dev, 0x0035,
921 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
922 b43_phy_write(dev, 0x005D,
923 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
924 }
925
926 if (dev->bad_frames_preempt) {
927 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
928 b43_phy_read(dev,
929 B43_PHY_RADIO_BITFIELD) | (1 << 11));
930 }
931
932 if (phy->analog == 1) {
933 b43_phy_write(dev, 0x0026, 0xCE00);
934 b43_phy_write(dev, 0x0021, 0x3763);
935 b43_phy_write(dev, 0x0022, 0x1BC3);
936 b43_phy_write(dev, 0x0023, 0x06F9);
937 b43_phy_write(dev, 0x0024, 0x037E);
938 } else
939 b43_phy_write(dev, 0x0026, 0xCC00);
940 b43_phy_write(dev, 0x0030, 0x00C6);
941 b43_write16(dev, 0x03EC, 0x3F22);
942
943 if (phy->analog == 1)
944 b43_phy_write(dev, 0x0020, 0x3E1C);
945 else
946 b43_phy_write(dev, 0x0020, 0x301C);
947
948 if (phy->analog == 0)
949 b43_write16(dev, 0x03E4, 0x3000);
950
951 old_channel = phy->channel;
952 /* Force to channel 7, even if not supported. */
953 b43_radio_selectchannel(dev, 7, 0);
954
955 if (phy->radio_ver != 0x2050) {
956 b43_radio_write16(dev, 0x0075, 0x0080);
957 b43_radio_write16(dev, 0x0079, 0x0081);
958 }
959
960 b43_radio_write16(dev, 0x0050, 0x0020);
961 b43_radio_write16(dev, 0x0050, 0x0023);
962
963 if (phy->radio_ver == 0x2050) {
964 b43_radio_write16(dev, 0x0050, 0x0020);
965 b43_radio_write16(dev, 0x005A, 0x0070);
966 }
967
968 b43_radio_write16(dev, 0x005B, 0x007B);
969 b43_radio_write16(dev, 0x005C, 0x00B0);
970
971 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
972
973 b43_radio_selectchannel(dev, old_channel, 0);
974
975 b43_phy_write(dev, 0x0014, 0x0080);
976 b43_phy_write(dev, 0x0032, 0x00CA);
977 b43_phy_write(dev, 0x002A, 0x88A3);
978
979 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
980
981 if (phy->radio_ver == 0x2050)
982 b43_radio_write16(dev, 0x005D, 0x000D);
983
984 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
985}
986
987static void b43_phy_initb6(struct b43_wldev *dev)
988{
989 struct b43_phy *phy = &dev->phy;
990 u16 offset, val;
991 u8 old_channel;
992
993 b43_phy_write(dev, 0x003E, 0x817A);
994 b43_radio_write16(dev, 0x007A,
995 (b43_radio_read16(dev, 0x007A) | 0x0058));
996 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
997 b43_radio_write16(dev, 0x51, 0x37);
998 b43_radio_write16(dev, 0x52, 0x70);
999 b43_radio_write16(dev, 0x53, 0xB3);
1000 b43_radio_write16(dev, 0x54, 0x9B);
1001 b43_radio_write16(dev, 0x5A, 0x88);
1002 b43_radio_write16(dev, 0x5B, 0x88);
1003 b43_radio_write16(dev, 0x5D, 0x88);
1004 b43_radio_write16(dev, 0x5E, 0x88);
1005 b43_radio_write16(dev, 0x7D, 0x88);
1006 b43_hf_write(dev, b43_hf_read(dev)
1007 | B43_HF_TSSIRPSMW);
1008 }
1009 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1010 if (phy->radio_rev == 8) {
1011 b43_radio_write16(dev, 0x51, 0);
1012 b43_radio_write16(dev, 0x52, 0x40);
1013 b43_radio_write16(dev, 0x53, 0xB7);
1014 b43_radio_write16(dev, 0x54, 0x98);
1015 b43_radio_write16(dev, 0x5A, 0x88);
1016 b43_radio_write16(dev, 0x5B, 0x6B);
1017 b43_radio_write16(dev, 0x5C, 0x0F);
1018 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1019 b43_radio_write16(dev, 0x5D, 0xFA);
1020 b43_radio_write16(dev, 0x5E, 0xD8);
1021 } else {
1022 b43_radio_write16(dev, 0x5D, 0xF5);
1023 b43_radio_write16(dev, 0x5E, 0xB8);
1024 }
1025 b43_radio_write16(dev, 0x0073, 0x0003);
1026 b43_radio_write16(dev, 0x007D, 0x00A8);
1027 b43_radio_write16(dev, 0x007C, 0x0001);
1028 b43_radio_write16(dev, 0x007E, 0x0008);
1029 }
1030 val = 0x1E1F;
1031 for (offset = 0x0088; offset < 0x0098; offset++) {
1032 b43_phy_write(dev, offset, val);
1033 val -= 0x0202;
1034 }
1035 val = 0x3E3F;
1036 for (offset = 0x0098; offset < 0x00A8; offset++) {
1037 b43_phy_write(dev, offset, val);
1038 val -= 0x0202;
1039 }
1040 val = 0x2120;
1041 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1042 b43_phy_write(dev, offset, (val & 0x3F3F));
1043 val += 0x0202;
1044 }
1045 if (phy->type == B43_PHYTYPE_G) {
1046 b43_radio_write16(dev, 0x007A,
1047 b43_radio_read16(dev, 0x007A) | 0x0020);
1048 b43_radio_write16(dev, 0x0051,
1049 b43_radio_read16(dev, 0x0051) | 0x0004);
1050 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1051 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1052 b43_phy_write(dev, 0x5B, 0);
1053 b43_phy_write(dev, 0x5C, 0);
1054 }
1055
1056 old_channel = phy->channel;
1057 if (old_channel >= 8)
1058 b43_radio_selectchannel(dev, 1, 0);
1059 else
1060 b43_radio_selectchannel(dev, 13, 0);
1061
1062 b43_radio_write16(dev, 0x0050, 0x0020);
1063 b43_radio_write16(dev, 0x0050, 0x0023);
1064 udelay(40);
1065 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1066 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1067 | 0x0002));
1068 b43_radio_write16(dev, 0x50, 0x20);
1069 }
1070 if (phy->radio_rev <= 2) {
1071 b43_radio_write16(dev, 0x7C, 0x20);
1072 b43_radio_write16(dev, 0x5A, 0x70);
1073 b43_radio_write16(dev, 0x5B, 0x7B);
1074 b43_radio_write16(dev, 0x5C, 0xB0);
1075 }
1076 b43_radio_write16(dev, 0x007A,
1077 (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1078
1079 b43_radio_selectchannel(dev, old_channel, 0);
1080
1081 b43_phy_write(dev, 0x0014, 0x0200);
1082 if (phy->radio_rev >= 6)
1083 b43_phy_write(dev, 0x2A, 0x88C2);
1084 else
1085 b43_phy_write(dev, 0x2A, 0x8AC0);
1086 b43_phy_write(dev, 0x0038, 0x0668);
1087 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1088 if (phy->radio_rev <= 5) {
1089 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1090 & 0xFF80) | 0x0003);
1091 }
1092 if (phy->radio_rev <= 2)
1093 b43_radio_write16(dev, 0x005D, 0x000D);
1094
1095 if (phy->analog == 4) {
1096 b43_write16(dev, 0x3E4, 9);
1097 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1098 & 0x0FFF);
1099 } else {
1100 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1101 | 0x0004);
1102 }
1103 if (phy->type == B43_PHYTYPE_B)
1104 B43_WARN_ON(1);
1105 else if (phy->type == B43_PHYTYPE_G)
1106 b43_write16(dev, 0x03E6, 0x0);
1107}
1108
1109static void b43_calc_loopback_gain(struct b43_wldev *dev)
1110{
1111 struct b43_phy *phy = &dev->phy;
1112 u16 backup_phy[16] = { 0 };
1113 u16 backup_radio[3];
1114 u16 backup_bband;
1115 u16 i, j, loop_i_max;
1116 u16 trsw_rx;
1117 u16 loop1_outer_done, loop1_inner_done;
1118
1119 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1120 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1121 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1122 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1123 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1124 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1125 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1126 }
1127 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1128 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1129 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1130 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1131 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1132 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1133 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1134 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1135 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1136 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1137 backup_bband = phy->bbatt.att;
1138 backup_radio[0] = b43_radio_read16(dev, 0x52);
1139 backup_radio[1] = b43_radio_read16(dev, 0x43);
1140 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1141
1142 b43_phy_write(dev, B43_PHY_CRS0,
1143 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1144 b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1145 b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1146 b43_phy_write(dev, B43_PHY_RFOVER,
1147 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1148 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1149 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1150 b43_phy_write(dev, B43_PHY_RFOVER,
1151 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1152 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1153 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1154 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1155 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1156 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1157 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1158 b43_phy_read(dev,
1159 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1160 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1161 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1162 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1163 b43_phy_read(dev,
1164 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1165 }
1166 b43_phy_write(dev, B43_PHY_RFOVER,
1167 b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1168 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1169 b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1170 b43_phy_write(dev, B43_PHY_RFOVER,
1171 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1172 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1173 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1174 & 0xFFCF) | 0x10);
1175
1176 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1177 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1178 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1179
1180 b43_phy_write(dev, B43_PHY_CCK(0x0A),
1181 b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
1182 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1183 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1184 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1185 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1186 b43_phy_read(dev,
1187 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1188 }
1189 b43_phy_write(dev, B43_PHY_CCK(0x03),
1190 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1191 & 0xFF9F) | 0x40);
1192
1193 if (phy->radio_rev == 8) {
1194 b43_radio_write16(dev, 0x43, 0x000F);
1195 } else {
1196 b43_radio_write16(dev, 0x52, 0);
1197 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1198 & 0xFFF0) | 0x9);
1199 }
1200 b43_phy_set_baseband_attenuation(dev, 11);
1201
1202 if (phy->rev >= 3)
1203 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1204 else
1205 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1206 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1207
1208 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1209 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1210 & 0xFFC0) | 0x01);
1211 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1212 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1213 & 0xC0FF) | 0x800);
1214
1215 b43_phy_write(dev, B43_PHY_RFOVER,
1216 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1217 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1218 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1219
1220 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1221 if (phy->rev >= 7) {
1222 b43_phy_write(dev, B43_PHY_RFOVER,
1223 b43_phy_read(dev, B43_PHY_RFOVER)
1224 | 0x0800);
1225 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1226 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1227 | 0x8000);
1228 }
1229 }
1230 b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1231 & 0x00F7);
1232
1233 j = 0;
1234 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1235 for (i = 0; i < loop_i_max; i++) {
1236 for (j = 0; j < 16; j++) {
1237 b43_radio_write16(dev, 0x43, i);
1238 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1239 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1240 & 0xF0FF) | (j << 8));
1241 b43_phy_write(dev, B43_PHY_PGACTL,
1242 (b43_phy_read(dev, B43_PHY_PGACTL)
1243 & 0x0FFF) | 0xA000);
1244 b43_phy_write(dev, B43_PHY_PGACTL,
1245 b43_phy_read(dev, B43_PHY_PGACTL)
1246 | 0xF000);
1247 udelay(20);
1248 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1249 goto exit_loop1;
1250 }
1251 }
1252 exit_loop1:
1253 loop1_outer_done = i;
1254 loop1_inner_done = j;
1255 if (j >= 8) {
1256 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1257 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1258 | 0x30);
1259 trsw_rx = 0x1B;
1260 for (j = j - 8; j < 16; j++) {
1261 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1262 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1263 & 0xF0FF) | (j << 8));
1264 b43_phy_write(dev, B43_PHY_PGACTL,
1265 (b43_phy_read(dev, B43_PHY_PGACTL)
1266 & 0x0FFF) | 0xA000);
1267 b43_phy_write(dev, B43_PHY_PGACTL,
1268 b43_phy_read(dev, B43_PHY_PGACTL)
1269 | 0xF000);
1270 udelay(20);
1271 trsw_rx -= 3;
1272 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1273 goto exit_loop2;
1274 }
1275 } else
1276 trsw_rx = 0x18;
1277 exit_loop2:
1278
1279 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1280 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1281 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1282 }
1283 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1284 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1285 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1286 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1287 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1288 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1289 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1290 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1291 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1292
1293 b43_phy_set_baseband_attenuation(dev, backup_bband);
1294
1295 b43_radio_write16(dev, 0x52, backup_radio[0]);
1296 b43_radio_write16(dev, 0x43, backup_radio[1]);
1297 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1298
1299 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1300 udelay(10);
1301 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1302 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1303 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1304 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1305
1306 phy->max_lb_gain =
1307 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1308 phy->trsw_rx_gain = trsw_rx * 2;
1309}
1310
1311static void b43_phy_initg(struct b43_wldev *dev)
1312{
1313 struct b43_phy *phy = &dev->phy;
1314 u16 tmp;
1315
1316 if (phy->rev == 1)
1317 b43_phy_initb5(dev);
1318 else
1319 b43_phy_initb6(dev);
1320
1321 if (phy->rev >= 2 || phy->gmode)
1322 b43_phy_inita(dev);
1323
1324 if (phy->rev >= 2) {
1325 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1326 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1327 }
1328 if (phy->rev == 2) {
1329 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1330 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1331 }
1332 if (phy->rev > 5) {
1333 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1334 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1335 }
1336 if (phy->gmode || phy->rev >= 2) {
1337 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1338 tmp &= B43_PHYVER_VERSION;
1339 if (tmp == 3 || tmp == 5) {
1340 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1341 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1342 }
1343 if (tmp == 5) {
1344 b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1345 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1346 & 0x00FF) | 0x1F00);
1347 }
1348 }
1349 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1350 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1351 if (phy->radio_rev == 8) {
1352 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1353 b43_phy_read(dev, B43_PHY_EXTG(0x01))
1354 | 0x80);
1355 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1356 b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1357 | 0x4);
1358 }
1359 if (has_loopback_gain(phy))
1360 b43_calc_loopback_gain(dev);
1361
1362 if (phy->radio_rev != 8) {
1363 if (phy->initval == 0xFFFF)
1364 phy->initval = b43_radio_init2050(dev);
1365 else
1366 b43_radio_write16(dev, 0x0078, phy->initval);
1367 }
1368 b43_lo_g_init(dev);
1369 if (has_tx_magnification(phy)) {
1370 b43_radio_write16(dev, 0x52,
1371 (b43_radio_read16(dev, 0x52) & 0xFF00)
1372 | phy->lo_control->tx_bias | phy->
1373 lo_control->tx_magn);
1374 } else {
1375 b43_radio_write16(dev, 0x52,
1376 (b43_radio_read16(dev, 0x52) & 0xFFF0)
1377 | phy->lo_control->tx_bias);
1378 }
1379 if (phy->rev >= 6) {
1380 b43_phy_write(dev, B43_PHY_CCK(0x36),
1381 (b43_phy_read(dev, B43_PHY_CCK(0x36))
1382 & 0x0FFF) | (phy->lo_control->
1383 tx_bias << 12));
1384 }
1385 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
1386 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
1387 else
1388 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
1389 if (phy->rev < 2)
1390 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
1391 else
1392 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
1393 if (phy->gmode || phy->rev >= 2) {
1394 b43_lo_g_adjust(dev);
1395 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1396 }
1397
1398 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
1399 /* The specs state to update the NRSSI LT with
1400 * the value 0x7FFFFFFF here. I think that is some weird
1401 * compiler optimization in the original driver.
1402 * Essentially, what we do here is resetting all NRSSI LT
1403 * entries to -32 (see the clamp_val() in nrssi_hw_update())
1404 */
1405 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
1406 b43_calc_nrssi_threshold(dev);
1407 } else if (phy->gmode || phy->rev >= 2) {
1408 if (phy->nrssi[0] == -1000) {
1409 B43_WARN_ON(phy->nrssi[1] != -1000);
1410 b43_calc_nrssi_slope(dev);
1411 } else
1412 b43_calc_nrssi_threshold(dev);
1413 }
1414 if (phy->radio_rev == 8)
1415 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1416 b43_phy_init_pctl(dev);
1417 /* FIXME: The spec says in the following if, the 0 should be replaced
1418 'if OFDM may not be used in the current locale'
1419 but OFDM is legal everywhere */
1420 if ((dev->dev->bus->chip_id == 0x4306
1421 && dev->dev->bus->chip_package == 2) || 0) {
1422 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1423 & 0xBFFF);
1424 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1425 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1426 & 0x7FFF);
1427 }
1428}
1429
1430/* Set the baseband attenuation value on chip. */
1431void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1432 u16 baseband_attenuation)
1433{
1434 struct b43_phy *phy = &dev->phy;
1435
1436 if (phy->analog == 0) {
1437 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1438 & 0xFFF0) |
1439 baseband_attenuation);
1440 } else if (phy->analog > 1) {
1441 b43_phy_write(dev, B43_PHY_DACCTL,
1442 (b43_phy_read(dev, B43_PHY_DACCTL)
1443 & 0xFFC3) | (baseband_attenuation << 2));
1444 } else {
1445 b43_phy_write(dev, B43_PHY_DACCTL,
1446 (b43_phy_read(dev, B43_PHY_DACCTL)
1447 & 0xFF87) | (baseband_attenuation << 3));
1448 }
1449}
1450
1451/* http://bcm-specs.sipsolutions.net/EstimatePowerOut 61/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1452 * This function converts a TSSI value to dBm in Q5.2 62 * This function converts a TSSI value to dBm in Q5.2
1453 */ 63 */
@@ -1819,2009 +429,6 @@ int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
1819 return 0; 429 return 0;
1820} 430}
1821 431
1822int b43_phy_init(struct b43_wldev *dev)
1823{
1824 struct b43_phy *phy = &dev->phy;
1825 bool unsupported = 0;
1826 int err = 0;
1827
1828 switch (phy->type) {
1829 case B43_PHYTYPE_A:
1830 if (phy->rev == 2 || phy->rev == 3)
1831 b43_phy_inita(dev);
1832 else
1833 unsupported = 1;
1834 break;
1835 case B43_PHYTYPE_G:
1836 b43_phy_initg(dev);
1837 break;
1838 case B43_PHYTYPE_N:
1839 err = b43_phy_initn(dev);
1840 break;
1841 default:
1842 unsupported = 1;
1843 }
1844 if (unsupported)
1845 b43err(dev->wl, "Unknown PHYTYPE found\n");
1846
1847 return err;
1848}
1849
1850void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
1851{
1852 struct b43_phy *phy = &dev->phy;
1853 u64 hf;
1854 u16 tmp;
1855 int autodiv = 0;
1856
1857 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
1858 autodiv = 1;
1859
1860 hf = b43_hf_read(dev);
1861 hf &= ~B43_HF_ANTDIVHELP;
1862 b43_hf_write(dev, hf);
1863
1864 switch (phy->type) {
1865 case B43_PHYTYPE_A:
1866 case B43_PHYTYPE_G:
1867 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
1868 tmp &= ~B43_PHY_BBANDCFG_RXANT;
1869 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
1870 << B43_PHY_BBANDCFG_RXANT_SHIFT;
1871 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
1872
1873 if (autodiv) {
1874 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
1875 if (antenna == B43_ANTENNA_AUTO0)
1876 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
1877 else
1878 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
1879 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
1880 }
1881 if (phy->type == B43_PHYTYPE_G) {
1882 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
1883 if (autodiv)
1884 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
1885 else
1886 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
1887 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
1888 if (phy->rev >= 2) {
1889 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
1890 tmp |= B43_PHY_OFDM61_10;
1891 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
1892
1893 tmp =
1894 b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
1895 tmp = (tmp & 0xFF00) | 0x15;
1896 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
1897 tmp);
1898
1899 if (phy->rev == 2) {
1900 b43_phy_write(dev, B43_PHY_ADIVRELATED,
1901 8);
1902 } else {
1903 tmp =
1904 b43_phy_read(dev,
1905 B43_PHY_ADIVRELATED);
1906 tmp = (tmp & 0xFF00) | 8;
1907 b43_phy_write(dev, B43_PHY_ADIVRELATED,
1908 tmp);
1909 }
1910 }
1911 if (phy->rev >= 6)
1912 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
1913 } else {
1914 if (phy->rev < 3) {
1915 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
1916 tmp = (tmp & 0xFF00) | 0x24;
1917 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
1918 } else {
1919 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
1920 tmp |= 0x10;
1921 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
1922 if (phy->analog == 3) {
1923 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
1924 0x1D);
1925 b43_phy_write(dev, B43_PHY_ADIVRELATED,
1926 8);
1927 } else {
1928 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
1929 0x3A);
1930 tmp =
1931 b43_phy_read(dev,
1932 B43_PHY_ADIVRELATED);
1933 tmp = (tmp & 0xFF00) | 8;
1934 b43_phy_write(dev, B43_PHY_ADIVRELATED,
1935 tmp);
1936 }
1937 }
1938 }
1939 break;
1940 case B43_PHYTYPE_B:
1941 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1942 tmp &= ~B43_PHY_BBANDCFG_RXANT;
1943 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
1944 << B43_PHY_BBANDCFG_RXANT_SHIFT;
1945 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
1946 break;
1947 case B43_PHYTYPE_N:
1948 b43_nphy_set_rxantenna(dev, antenna);
1949 break;
1950 default:
1951 B43_WARN_ON(1);
1952 }
1953
1954 hf |= B43_HF_ANTDIVHELP;
1955 b43_hf_write(dev, hf);
1956}
1957
1958/* Get the freq, as it has to be written to the device. */
1959static inline u16 channel2freq_bg(u8 channel)
1960{
1961 B43_WARN_ON(!(channel >= 1 && channel <= 14));
1962
1963 return b43_radio_channel_codes_bg[channel - 1];
1964}
1965
1966/* Get the freq, as it has to be written to the device. */
1967static inline u16 channel2freq_a(u8 channel)
1968{
1969 B43_WARN_ON(channel > 200);
1970
1971 return (5000 + 5 * channel);
1972}
1973
1974void b43_radio_lock(struct b43_wldev *dev)
1975{
1976 u32 macctl;
1977
1978 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1979 B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
1980 macctl |= B43_MACCTL_RADIOLOCK;
1981 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1982 /* Commit the write and wait for the device
1983 * to exit any radio register access. */
1984 b43_read32(dev, B43_MMIO_MACCTL);
1985 udelay(10);
1986}
1987
1988void b43_radio_unlock(struct b43_wldev *dev)
1989{
1990 u32 macctl;
1991
1992 /* Commit any write */
1993 b43_read16(dev, B43_MMIO_PHY_VER);
1994 /* unlock */
1995 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1996 B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
1997 macctl &= ~B43_MACCTL_RADIOLOCK;
1998 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1999}
2000
2001u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2002{
2003 struct b43_phy *phy = &dev->phy;
2004
2005 /* Offset 1 is a 32-bit register. */
2006 B43_WARN_ON(offset == 1);
2007
2008 switch (phy->type) {
2009 case B43_PHYTYPE_A:
2010 offset |= 0x40;
2011 break;
2012 case B43_PHYTYPE_B:
2013 if (phy->radio_ver == 0x2053) {
2014 if (offset < 0x70)
2015 offset += 0x80;
2016 else if (offset < 0x80)
2017 offset += 0x70;
2018 } else if (phy->radio_ver == 0x2050) {
2019 offset |= 0x80;
2020 } else
2021 B43_WARN_ON(1);
2022 break;
2023 case B43_PHYTYPE_G:
2024 offset |= 0x80;
2025 break;
2026 case B43_PHYTYPE_N:
2027 offset |= 0x100;
2028 break;
2029 case B43_PHYTYPE_LP:
2030 /* No adjustment required. */
2031 break;
2032 default:
2033 B43_WARN_ON(1);
2034 }
2035
2036 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2037 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2038}
2039
2040void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2041{
2042 /* Offset 1 is a 32-bit register. */
2043 B43_WARN_ON(offset == 1);
2044
2045 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2046 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2047}
2048
2049void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
2050{
2051 b43_radio_write16(dev, offset,
2052 b43_radio_read16(dev, offset) & mask);
2053}
2054
2055void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
2056{
2057 b43_radio_write16(dev, offset,
2058 b43_radio_read16(dev, offset) | set);
2059}
2060
2061void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
2062{
2063 b43_radio_write16(dev, offset,
2064 (b43_radio_read16(dev, offset) & mask) | set);
2065}
2066
2067static void b43_set_all_gains(struct b43_wldev *dev,
2068 s16 first, s16 second, s16 third)
2069{
2070 struct b43_phy *phy = &dev->phy;
2071 u16 i;
2072 u16 start = 0x08, end = 0x18;
2073 u16 tmp;
2074 u16 table;
2075
2076 if (phy->rev <= 1) {
2077 start = 0x10;
2078 end = 0x20;
2079 }
2080
2081 table = B43_OFDMTAB_GAINX;
2082 if (phy->rev <= 1)
2083 table = B43_OFDMTAB_GAINX_R1;
2084 for (i = 0; i < 4; i++)
2085 b43_ofdmtab_write16(dev, table, i, first);
2086
2087 for (i = start; i < end; i++)
2088 b43_ofdmtab_write16(dev, table, i, second);
2089
2090 if (third != -1) {
2091 tmp = ((u16) third << 14) | ((u16) third << 6);
2092 b43_phy_write(dev, 0x04A0,
2093 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2094 b43_phy_write(dev, 0x04A1,
2095 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2096 b43_phy_write(dev, 0x04A2,
2097 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2098 }
2099 b43_dummy_transmission(dev);
2100}
2101
2102static void b43_set_original_gains(struct b43_wldev *dev)
2103{
2104 struct b43_phy *phy = &dev->phy;
2105 u16 i, tmp;
2106 u16 table;
2107 u16 start = 0x0008, end = 0x0018;
2108
2109 if (phy->rev <= 1) {
2110 start = 0x0010;
2111 end = 0x0020;
2112 }
2113
2114 table = B43_OFDMTAB_GAINX;
2115 if (phy->rev <= 1)
2116 table = B43_OFDMTAB_GAINX_R1;
2117 for (i = 0; i < 4; i++) {
2118 tmp = (i & 0xFFFC);
2119 tmp |= (i & 0x0001) << 1;
2120 tmp |= (i & 0x0002) >> 1;
2121
2122 b43_ofdmtab_write16(dev, table, i, tmp);
2123 }
2124
2125 for (i = start; i < end; i++)
2126 b43_ofdmtab_write16(dev, table, i, i - start);
2127
2128 b43_phy_write(dev, 0x04A0,
2129 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2130 b43_phy_write(dev, 0x04A1,
2131 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2132 b43_phy_write(dev, 0x04A2,
2133 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2134 b43_dummy_transmission(dev);
2135}
2136
2137/* Synthetic PU workaround */
2138static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2139{
2140 struct b43_phy *phy = &dev->phy;
2141
2142 might_sleep();
2143
2144 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2145 /* We do not need the workaround. */
2146 return;
2147 }
2148
2149 if (channel <= 10) {
2150 b43_write16(dev, B43_MMIO_CHANNEL,
2151 channel2freq_bg(channel + 4));
2152 } else {
2153 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2154 }
2155 msleep(1);
2156 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2157}
2158
2159u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2160{
2161 struct b43_phy *phy = &dev->phy;
2162 u8 ret = 0;
2163 u16 saved, rssi, temp;
2164 int i, j = 0;
2165
2166 saved = b43_phy_read(dev, 0x0403);
2167 b43_radio_selectchannel(dev, channel, 0);
2168 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2169 if (phy->aci_hw_rssi)
2170 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2171 else
2172 rssi = saved & 0x3F;
2173 /* clamp temp to signed 5bit */
2174 if (rssi > 32)
2175 rssi -= 64;
2176 for (i = 0; i < 100; i++) {
2177 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2178 if (temp > 32)
2179 temp -= 64;
2180 if (temp < rssi)
2181 j++;
2182 if (j >= 20)
2183 ret = 1;
2184 }
2185 b43_phy_write(dev, 0x0403, saved);
2186
2187 return ret;
2188}
2189
2190u8 b43_radio_aci_scan(struct b43_wldev * dev)
2191{
2192 struct b43_phy *phy = &dev->phy;
2193 u8 ret[13];
2194 unsigned int channel = phy->channel;
2195 unsigned int i, j, start, end;
2196
2197 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2198 return 0;
2199
2200 b43_phy_lock(dev);
2201 b43_radio_lock(dev);
2202 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2203 b43_phy_write(dev, B43_PHY_G_CRS,
2204 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2205 b43_set_all_gains(dev, 3, 8, 1);
2206
2207 start = (channel - 5 > 0) ? channel - 5 : 1;
2208 end = (channel + 5 < 14) ? channel + 5 : 13;
2209
2210 for (i = start; i <= end; i++) {
2211 if (abs(channel - i) > 2)
2212 ret[i - 1] = b43_radio_aci_detect(dev, i);
2213 }
2214 b43_radio_selectchannel(dev, channel, 0);
2215 b43_phy_write(dev, 0x0802,
2216 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2217 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2218 b43_phy_write(dev, B43_PHY_G_CRS,
2219 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2220 b43_set_original_gains(dev);
2221 for (i = 0; i < 13; i++) {
2222 if (!ret[i])
2223 continue;
2224 end = (i + 5 < 13) ? i + 5 : 13;
2225 for (j = i; j < end; j++)
2226 ret[j] = 1;
2227 }
2228 b43_radio_unlock(dev);
2229 b43_phy_unlock(dev);
2230
2231 return ret[channel - 1];
2232}
2233
2234/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2235void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2236{
2237 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2238 mmiowb();
2239 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2240}
2241
2242/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2243s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2244{
2245 u16 val;
2246
2247 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2248 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2249
2250 return (s16) val;
2251}
2252
2253/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2254void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2255{
2256 u16 i;
2257 s16 tmp;
2258
2259 for (i = 0; i < 64; i++) {
2260 tmp = b43_nrssi_hw_read(dev, i);
2261 tmp -= val;
2262 tmp = clamp_val(tmp, -32, 31);
2263 b43_nrssi_hw_write(dev, i, tmp);
2264 }
2265}
2266
2267/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2268void b43_nrssi_mem_update(struct b43_wldev *dev)
2269{
2270 struct b43_phy *phy = &dev->phy;
2271 s16 i, delta;
2272 s32 tmp;
2273
2274 delta = 0x1F - phy->nrssi[0];
2275 for (i = 0; i < 64; i++) {
2276 tmp = (i - delta) * phy->nrssislope;
2277 tmp /= 0x10000;
2278 tmp += 0x3A;
2279 tmp = clamp_val(tmp, 0, 0x3F);
2280 phy->nrssi_lt[i] = tmp;
2281 }
2282}
2283
2284static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2285{
2286 struct b43_phy *phy = &dev->phy;
2287 u16 backup[20] = { 0 };
2288 s16 v47F;
2289 u16 i;
2290 u16 saved = 0xFFFF;
2291
2292 backup[0] = b43_phy_read(dev, 0x0001);
2293 backup[1] = b43_phy_read(dev, 0x0811);
2294 backup[2] = b43_phy_read(dev, 0x0812);
2295 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2296 backup[3] = b43_phy_read(dev, 0x0814);
2297 backup[4] = b43_phy_read(dev, 0x0815);
2298 }
2299 backup[5] = b43_phy_read(dev, 0x005A);
2300 backup[6] = b43_phy_read(dev, 0x0059);
2301 backup[7] = b43_phy_read(dev, 0x0058);
2302 backup[8] = b43_phy_read(dev, 0x000A);
2303 backup[9] = b43_phy_read(dev, 0x0003);
2304 backup[10] = b43_radio_read16(dev, 0x007A);
2305 backup[11] = b43_radio_read16(dev, 0x0043);
2306
2307 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2308 b43_phy_write(dev, 0x0001,
2309 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2310 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2311 b43_phy_write(dev, 0x0812,
2312 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2313 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2314 if (phy->rev >= 6) {
2315 backup[12] = b43_phy_read(dev, 0x002E);
2316 backup[13] = b43_phy_read(dev, 0x002F);
2317 backup[14] = b43_phy_read(dev, 0x080F);
2318 backup[15] = b43_phy_read(dev, 0x0810);
2319 backup[16] = b43_phy_read(dev, 0x0801);
2320 backup[17] = b43_phy_read(dev, 0x0060);
2321 backup[18] = b43_phy_read(dev, 0x0014);
2322 backup[19] = b43_phy_read(dev, 0x0478);
2323
2324 b43_phy_write(dev, 0x002E, 0);
2325 b43_phy_write(dev, 0x002F, 0);
2326 b43_phy_write(dev, 0x080F, 0);
2327 b43_phy_write(dev, 0x0810, 0);
2328 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2329 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2330 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2331 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2332 }
2333 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2334 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2335 udelay(30);
2336
2337 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2338 if (v47F >= 0x20)
2339 v47F -= 0x40;
2340 if (v47F == 31) {
2341 for (i = 7; i >= 4; i--) {
2342 b43_radio_write16(dev, 0x007B, i);
2343 udelay(20);
2344 v47F =
2345 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2346 if (v47F >= 0x20)
2347 v47F -= 0x40;
2348 if (v47F < 31 && saved == 0xFFFF)
2349 saved = i;
2350 }
2351 if (saved == 0xFFFF)
2352 saved = 4;
2353 } else {
2354 b43_radio_write16(dev, 0x007A,
2355 b43_radio_read16(dev, 0x007A) & 0x007F);
2356 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2357 b43_phy_write(dev, 0x0814,
2358 b43_phy_read(dev, 0x0814) | 0x0001);
2359 b43_phy_write(dev, 0x0815,
2360 b43_phy_read(dev, 0x0815) & 0xFFFE);
2361 }
2362 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2363 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2364 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2365 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2366 b43_phy_write(dev, 0x005A, 0x0480);
2367 b43_phy_write(dev, 0x0059, 0x0810);
2368 b43_phy_write(dev, 0x0058, 0x000D);
2369 if (phy->rev == 0) {
2370 b43_phy_write(dev, 0x0003, 0x0122);
2371 } else {
2372 b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2373 | 0x2000);
2374 }
2375 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2376 b43_phy_write(dev, 0x0814,
2377 b43_phy_read(dev, 0x0814) | 0x0004);
2378 b43_phy_write(dev, 0x0815,
2379 b43_phy_read(dev, 0x0815) & 0xFFFB);
2380 }
2381 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2382 | 0x0040);
2383 b43_radio_write16(dev, 0x007A,
2384 b43_radio_read16(dev, 0x007A) | 0x000F);
2385 b43_set_all_gains(dev, 3, 0, 1);
2386 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2387 & 0x00F0) | 0x000F);
2388 udelay(30);
2389 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2390 if (v47F >= 0x20)
2391 v47F -= 0x40;
2392 if (v47F == -32) {
2393 for (i = 0; i < 4; i++) {
2394 b43_radio_write16(dev, 0x007B, i);
2395 udelay(20);
2396 v47F =
2397 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2398 0x003F);
2399 if (v47F >= 0x20)
2400 v47F -= 0x40;
2401 if (v47F > -31 && saved == 0xFFFF)
2402 saved = i;
2403 }
2404 if (saved == 0xFFFF)
2405 saved = 3;
2406 } else
2407 saved = 0;
2408 }
2409 b43_radio_write16(dev, 0x007B, saved);
2410
2411 if (phy->rev >= 6) {
2412 b43_phy_write(dev, 0x002E, backup[12]);
2413 b43_phy_write(dev, 0x002F, backup[13]);
2414 b43_phy_write(dev, 0x080F, backup[14]);
2415 b43_phy_write(dev, 0x0810, backup[15]);
2416 }
2417 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2418 b43_phy_write(dev, 0x0814, backup[3]);
2419 b43_phy_write(dev, 0x0815, backup[4]);
2420 }
2421 b43_phy_write(dev, 0x005A, backup[5]);
2422 b43_phy_write(dev, 0x0059, backup[6]);
2423 b43_phy_write(dev, 0x0058, backup[7]);
2424 b43_phy_write(dev, 0x000A, backup[8]);
2425 b43_phy_write(dev, 0x0003, backup[9]);
2426 b43_radio_write16(dev, 0x0043, backup[11]);
2427 b43_radio_write16(dev, 0x007A, backup[10]);
2428 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2429 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2430 b43_set_original_gains(dev);
2431 if (phy->rev >= 6) {
2432 b43_phy_write(dev, 0x0801, backup[16]);
2433 b43_phy_write(dev, 0x0060, backup[17]);
2434 b43_phy_write(dev, 0x0014, backup[18]);
2435 b43_phy_write(dev, 0x0478, backup[19]);
2436 }
2437 b43_phy_write(dev, 0x0001, backup[0]);
2438 b43_phy_write(dev, 0x0812, backup[2]);
2439 b43_phy_write(dev, 0x0811, backup[1]);
2440}
2441
2442void b43_calc_nrssi_slope(struct b43_wldev *dev)
2443{
2444 struct b43_phy *phy = &dev->phy;
2445 u16 backup[18] = { 0 };
2446 u16 tmp;
2447 s16 nrssi0, nrssi1;
2448
2449 switch (phy->type) {
2450 case B43_PHYTYPE_B:
2451 backup[0] = b43_radio_read16(dev, 0x007A);
2452 backup[1] = b43_radio_read16(dev, 0x0052);
2453 backup[2] = b43_radio_read16(dev, 0x0043);
2454 backup[3] = b43_phy_read(dev, 0x0030);
2455 backup[4] = b43_phy_read(dev, 0x0026);
2456 backup[5] = b43_phy_read(dev, 0x0015);
2457 backup[6] = b43_phy_read(dev, 0x002A);
2458 backup[7] = b43_phy_read(dev, 0x0020);
2459 backup[8] = b43_phy_read(dev, 0x005A);
2460 backup[9] = b43_phy_read(dev, 0x0059);
2461 backup[10] = b43_phy_read(dev, 0x0058);
2462 backup[11] = b43_read16(dev, 0x03E2);
2463 backup[12] = b43_read16(dev, 0x03E6);
2464 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2465
2466 tmp = b43_radio_read16(dev, 0x007A);
2467 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2468 b43_radio_write16(dev, 0x007A, tmp);
2469 b43_phy_write(dev, 0x0030, 0x00FF);
2470 b43_write16(dev, 0x03EC, 0x7F7F);
2471 b43_phy_write(dev, 0x0026, 0x0000);
2472 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2473 b43_phy_write(dev, 0x002A, 0x08A3);
2474 b43_radio_write16(dev, 0x007A,
2475 b43_radio_read16(dev, 0x007A) | 0x0080);
2476
2477 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2478 b43_radio_write16(dev, 0x007A,
2479 b43_radio_read16(dev, 0x007A) & 0x007F);
2480 if (phy->rev >= 2) {
2481 b43_write16(dev, 0x03E6, 0x0040);
2482 } else if (phy->rev == 0) {
2483 b43_write16(dev, 0x03E6, 0x0122);
2484 } else {
2485 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2486 b43_read16(dev,
2487 B43_MMIO_CHANNEL_EXT) & 0x2000);
2488 }
2489 b43_phy_write(dev, 0x0020, 0x3F3F);
2490 b43_phy_write(dev, 0x0015, 0xF330);
2491 b43_radio_write16(dev, 0x005A, 0x0060);
2492 b43_radio_write16(dev, 0x0043,
2493 b43_radio_read16(dev, 0x0043) & 0x00F0);
2494 b43_phy_write(dev, 0x005A, 0x0480);
2495 b43_phy_write(dev, 0x0059, 0x0810);
2496 b43_phy_write(dev, 0x0058, 0x000D);
2497 udelay(20);
2498
2499 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2500 b43_phy_write(dev, 0x0030, backup[3]);
2501 b43_radio_write16(dev, 0x007A, backup[0]);
2502 b43_write16(dev, 0x03E2, backup[11]);
2503 b43_phy_write(dev, 0x0026, backup[4]);
2504 b43_phy_write(dev, 0x0015, backup[5]);
2505 b43_phy_write(dev, 0x002A, backup[6]);
2506 b43_synth_pu_workaround(dev, phy->channel);
2507 if (phy->rev != 0)
2508 b43_write16(dev, 0x03F4, backup[13]);
2509
2510 b43_phy_write(dev, 0x0020, backup[7]);
2511 b43_phy_write(dev, 0x005A, backup[8]);
2512 b43_phy_write(dev, 0x0059, backup[9]);
2513 b43_phy_write(dev, 0x0058, backup[10]);
2514 b43_radio_write16(dev, 0x0052, backup[1]);
2515 b43_radio_write16(dev, 0x0043, backup[2]);
2516
2517 if (nrssi0 == nrssi1)
2518 phy->nrssislope = 0x00010000;
2519 else
2520 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2521
2522 if (nrssi0 <= -4) {
2523 phy->nrssi[0] = nrssi0;
2524 phy->nrssi[1] = nrssi1;
2525 }
2526 break;
2527 case B43_PHYTYPE_G:
2528 if (phy->radio_rev >= 9)
2529 return;
2530 if (phy->radio_rev == 8)
2531 b43_calc_nrssi_offset(dev);
2532
2533 b43_phy_write(dev, B43_PHY_G_CRS,
2534 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2535 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2536 backup[7] = b43_read16(dev, 0x03E2);
2537 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2538 backup[0] = b43_radio_read16(dev, 0x007A);
2539 backup[1] = b43_radio_read16(dev, 0x0052);
2540 backup[2] = b43_radio_read16(dev, 0x0043);
2541 backup[3] = b43_phy_read(dev, 0x0015);
2542 backup[4] = b43_phy_read(dev, 0x005A);
2543 backup[5] = b43_phy_read(dev, 0x0059);
2544 backup[6] = b43_phy_read(dev, 0x0058);
2545 backup[8] = b43_read16(dev, 0x03E6);
2546 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2547 if (phy->rev >= 3) {
2548 backup[10] = b43_phy_read(dev, 0x002E);
2549 backup[11] = b43_phy_read(dev, 0x002F);
2550 backup[12] = b43_phy_read(dev, 0x080F);
2551 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2552 backup[14] = b43_phy_read(dev, 0x0801);
2553 backup[15] = b43_phy_read(dev, 0x0060);
2554 backup[16] = b43_phy_read(dev, 0x0014);
2555 backup[17] = b43_phy_read(dev, 0x0478);
2556 b43_phy_write(dev, 0x002E, 0);
2557 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2558 switch (phy->rev) {
2559 case 4:
2560 case 6:
2561 case 7:
2562 b43_phy_write(dev, 0x0478,
2563 b43_phy_read(dev, 0x0478)
2564 | 0x0100);
2565 b43_phy_write(dev, 0x0801,
2566 b43_phy_read(dev, 0x0801)
2567 | 0x0040);
2568 break;
2569 case 3:
2570 case 5:
2571 b43_phy_write(dev, 0x0801,
2572 b43_phy_read(dev, 0x0801)
2573 & 0xFFBF);
2574 break;
2575 }
2576 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2577 | 0x0040);
2578 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2579 | 0x0200);
2580 }
2581 b43_radio_write16(dev, 0x007A,
2582 b43_radio_read16(dev, 0x007A) | 0x0070);
2583 b43_set_all_gains(dev, 0, 8, 0);
2584 b43_radio_write16(dev, 0x007A,
2585 b43_radio_read16(dev, 0x007A) & 0x00F7);
2586 if (phy->rev >= 2) {
2587 b43_phy_write(dev, 0x0811,
2588 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2589 0x0030);
2590 b43_phy_write(dev, 0x0812,
2591 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2592 0x0010);
2593 }
2594 b43_radio_write16(dev, 0x007A,
2595 b43_radio_read16(dev, 0x007A) | 0x0080);
2596 udelay(20);
2597
2598 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2599 if (nrssi0 >= 0x0020)
2600 nrssi0 -= 0x0040;
2601
2602 b43_radio_write16(dev, 0x007A,
2603 b43_radio_read16(dev, 0x007A) & 0x007F);
2604 if (phy->rev >= 2) {
2605 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
2606 & 0xFF9F) | 0x0040);
2607 }
2608
2609 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2610 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2611 | 0x2000);
2612 b43_radio_write16(dev, 0x007A,
2613 b43_radio_read16(dev, 0x007A) | 0x000F);
2614 b43_phy_write(dev, 0x0015, 0xF330);
2615 if (phy->rev >= 2) {
2616 b43_phy_write(dev, 0x0812,
2617 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2618 0x0020);
2619 b43_phy_write(dev, 0x0811,
2620 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2621 0x0020);
2622 }
2623
2624 b43_set_all_gains(dev, 3, 0, 1);
2625 if (phy->radio_rev == 8) {
2626 b43_radio_write16(dev, 0x0043, 0x001F);
2627 } else {
2628 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
2629 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
2630 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
2631 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
2632 }
2633 b43_phy_write(dev, 0x005A, 0x0480);
2634 b43_phy_write(dev, 0x0059, 0x0810);
2635 b43_phy_write(dev, 0x0058, 0x000D);
2636 udelay(20);
2637 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2638 if (nrssi1 >= 0x0020)
2639 nrssi1 -= 0x0040;
2640 if (nrssi0 == nrssi1)
2641 phy->nrssislope = 0x00010000;
2642 else
2643 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2644 if (nrssi0 >= -4) {
2645 phy->nrssi[0] = nrssi1;
2646 phy->nrssi[1] = nrssi0;
2647 }
2648 if (phy->rev >= 3) {
2649 b43_phy_write(dev, 0x002E, backup[10]);
2650 b43_phy_write(dev, 0x002F, backup[11]);
2651 b43_phy_write(dev, 0x080F, backup[12]);
2652 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
2653 }
2654 if (phy->rev >= 2) {
2655 b43_phy_write(dev, 0x0812,
2656 b43_phy_read(dev, 0x0812) & 0xFFCF);
2657 b43_phy_write(dev, 0x0811,
2658 b43_phy_read(dev, 0x0811) & 0xFFCF);
2659 }
2660
2661 b43_radio_write16(dev, 0x007A, backup[0]);
2662 b43_radio_write16(dev, 0x0052, backup[1]);
2663 b43_radio_write16(dev, 0x0043, backup[2]);
2664 b43_write16(dev, 0x03E2, backup[7]);
2665 b43_write16(dev, 0x03E6, backup[8]);
2666 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
2667 b43_phy_write(dev, 0x0015, backup[3]);
2668 b43_phy_write(dev, 0x005A, backup[4]);
2669 b43_phy_write(dev, 0x0059, backup[5]);
2670 b43_phy_write(dev, 0x0058, backup[6]);
2671 b43_synth_pu_workaround(dev, phy->channel);
2672 b43_phy_write(dev, 0x0802,
2673 b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
2674 b43_set_original_gains(dev);
2675 b43_phy_write(dev, B43_PHY_G_CRS,
2676 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2677 if (phy->rev >= 3) {
2678 b43_phy_write(dev, 0x0801, backup[14]);
2679 b43_phy_write(dev, 0x0060, backup[15]);
2680 b43_phy_write(dev, 0x0014, backup[16]);
2681 b43_phy_write(dev, 0x0478, backup[17]);
2682 }
2683 b43_nrssi_mem_update(dev);
2684 b43_calc_nrssi_threshold(dev);
2685 break;
2686 default:
2687 B43_WARN_ON(1);
2688 }
2689}
2690
2691void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2692{
2693 struct b43_phy *phy = &dev->phy;
2694 s32 threshold;
2695 s32 a, b;
2696 s16 tmp16;
2697 u16 tmp_u16;
2698
2699 switch (phy->type) {
2700 case B43_PHYTYPE_B:{
2701 if (phy->radio_ver != 0x2050)
2702 return;
2703 if (!
2704 (dev->dev->bus->sprom.
2705 boardflags_lo & B43_BFL_RSSI))
2706 return;
2707
2708 if (phy->radio_rev >= 6) {
2709 threshold =
2710 (phy->nrssi[1] - phy->nrssi[0]) * 32;
2711 threshold += 20 * (phy->nrssi[0] + 1);
2712 threshold /= 40;
2713 } else
2714 threshold = phy->nrssi[1] - 5;
2715
2716 threshold = clamp_val(threshold, 0, 0x3E);
2717 b43_phy_read(dev, 0x0020); /* dummy read */
2718 b43_phy_write(dev, 0x0020,
2719 (((u16) threshold) << 8) | 0x001C);
2720
2721 if (phy->radio_rev >= 6) {
2722 b43_phy_write(dev, 0x0087, 0x0E0D);
2723 b43_phy_write(dev, 0x0086, 0x0C0B);
2724 b43_phy_write(dev, 0x0085, 0x0A09);
2725 b43_phy_write(dev, 0x0084, 0x0808);
2726 b43_phy_write(dev, 0x0083, 0x0808);
2727 b43_phy_write(dev, 0x0082, 0x0604);
2728 b43_phy_write(dev, 0x0081, 0x0302);
2729 b43_phy_write(dev, 0x0080, 0x0100);
2730 }
2731 break;
2732 }
2733 case B43_PHYTYPE_G:
2734 if (!phy->gmode ||
2735 !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2736 tmp16 = b43_nrssi_hw_read(dev, 0x20);
2737 if (tmp16 >= 0x20)
2738 tmp16 -= 0x40;
2739 if (tmp16 < 3) {
2740 b43_phy_write(dev, 0x048A,
2741 (b43_phy_read(dev, 0x048A)
2742 & 0xF000) | 0x09EB);
2743 } else {
2744 b43_phy_write(dev, 0x048A,
2745 (b43_phy_read(dev, 0x048A)
2746 & 0xF000) | 0x0AED);
2747 }
2748 } else {
2749 if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
2750 a = 0xE;
2751 b = 0xA;
2752 } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
2753 a = 0x13;
2754 b = 0x12;
2755 } else {
2756 a = 0xE;
2757 b = 0x11;
2758 }
2759
2760 a = a * (phy->nrssi[1] - phy->nrssi[0]);
2761 a += (phy->nrssi[0] << 6);
2762 if (a < 32)
2763 a += 31;
2764 else
2765 a += 32;
2766 a = a >> 6;
2767 a = clamp_val(a, -31, 31);
2768
2769 b = b * (phy->nrssi[1] - phy->nrssi[0]);
2770 b += (phy->nrssi[0] << 6);
2771 if (b < 32)
2772 b += 31;
2773 else
2774 b += 32;
2775 b = b >> 6;
2776 b = clamp_val(b, -31, 31);
2777
2778 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
2779 tmp_u16 |= ((u32) b & 0x0000003F);
2780 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
2781 b43_phy_write(dev, 0x048A, tmp_u16);
2782 }
2783 break;
2784 default:
2785 B43_WARN_ON(1);
2786 }
2787}
2788
2789/* Stack implementation to save/restore values from the
2790 * interference mitigation code.
2791 * It is save to restore values in random order.
2792 */
2793static void _stack_save(u32 * _stackptr, size_t * stackidx,
2794 u8 id, u16 offset, u16 value)
2795{
2796 u32 *stackptr = &(_stackptr[*stackidx]);
2797
2798 B43_WARN_ON(offset & 0xF000);
2799 B43_WARN_ON(id & 0xF0);
2800 *stackptr = offset;
2801 *stackptr |= ((u32) id) << 12;
2802 *stackptr |= ((u32) value) << 16;
2803 (*stackidx)++;
2804 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
2805}
2806
2807static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
2808{
2809 size_t i;
2810
2811 B43_WARN_ON(offset & 0xF000);
2812 B43_WARN_ON(id & 0xF0);
2813 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
2814 if ((*stackptr & 0x00000FFF) != offset)
2815 continue;
2816 if (((*stackptr & 0x0000F000) >> 12) != id)
2817 continue;
2818 return ((*stackptr & 0xFFFF0000) >> 16);
2819 }
2820 B43_WARN_ON(1);
2821
2822 return 0;
2823}
2824
2825#define phy_stacksave(offset) \
2826 do { \
2827 _stack_save(stack, &stackidx, 0x1, (offset), \
2828 b43_phy_read(dev, (offset))); \
2829 } while (0)
2830#define phy_stackrestore(offset) \
2831 do { \
2832 b43_phy_write(dev, (offset), \
2833 _stack_restore(stack, 0x1, \
2834 (offset))); \
2835 } while (0)
2836#define radio_stacksave(offset) \
2837 do { \
2838 _stack_save(stack, &stackidx, 0x2, (offset), \
2839 b43_radio_read16(dev, (offset))); \
2840 } while (0)
2841#define radio_stackrestore(offset) \
2842 do { \
2843 b43_radio_write16(dev, (offset), \
2844 _stack_restore(stack, 0x2, \
2845 (offset))); \
2846 } while (0)
2847#define ofdmtab_stacksave(table, offset) \
2848 do { \
2849 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
2850 b43_ofdmtab_read16(dev, (table), (offset))); \
2851 } while (0)
2852#define ofdmtab_stackrestore(table, offset) \
2853 do { \
2854 b43_ofdmtab_write16(dev, (table), (offset), \
2855 _stack_restore(stack, 0x3, \
2856 (offset)|(table))); \
2857 } while (0)
2858
2859static void
2860b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
2861{
2862 struct b43_phy *phy = &dev->phy;
2863 u16 tmp, flipped;
2864 size_t stackidx = 0;
2865 u32 *stack = phy->interfstack;
2866
2867 switch (mode) {
2868 case B43_INTERFMODE_NONWLAN:
2869 if (phy->rev != 1) {
2870 b43_phy_write(dev, 0x042B,
2871 b43_phy_read(dev, 0x042B) | 0x0800);
2872 b43_phy_write(dev, B43_PHY_G_CRS,
2873 b43_phy_read(dev,
2874 B43_PHY_G_CRS) & ~0x4000);
2875 break;
2876 }
2877 radio_stacksave(0x0078);
2878 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
2879 B43_WARN_ON(tmp > 15);
2880 flipped = bitrev4(tmp);
2881 if (flipped < 10 && flipped >= 8)
2882 flipped = 7;
2883 else if (flipped >= 10)
2884 flipped -= 3;
2885 flipped = (bitrev4(flipped) << 1) | 0x0020;
2886 b43_radio_write16(dev, 0x0078, flipped);
2887
2888 b43_calc_nrssi_threshold(dev);
2889
2890 phy_stacksave(0x0406);
2891 b43_phy_write(dev, 0x0406, 0x7E28);
2892
2893 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
2894 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
2895 b43_phy_read(dev,
2896 B43_PHY_RADIO_BITFIELD) | 0x1000);
2897
2898 phy_stacksave(0x04A0);
2899 b43_phy_write(dev, 0x04A0,
2900 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
2901 phy_stacksave(0x04A1);
2902 b43_phy_write(dev, 0x04A1,
2903 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
2904 phy_stacksave(0x04A2);
2905 b43_phy_write(dev, 0x04A2,
2906 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
2907 phy_stacksave(0x04A8);
2908 b43_phy_write(dev, 0x04A8,
2909 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
2910 phy_stacksave(0x04AB);
2911 b43_phy_write(dev, 0x04AB,
2912 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
2913
2914 phy_stacksave(0x04A7);
2915 b43_phy_write(dev, 0x04A7, 0x0002);
2916 phy_stacksave(0x04A3);
2917 b43_phy_write(dev, 0x04A3, 0x287A);
2918 phy_stacksave(0x04A9);
2919 b43_phy_write(dev, 0x04A9, 0x2027);
2920 phy_stacksave(0x0493);
2921 b43_phy_write(dev, 0x0493, 0x32F5);
2922 phy_stacksave(0x04AA);
2923 b43_phy_write(dev, 0x04AA, 0x2027);
2924 phy_stacksave(0x04AC);
2925 b43_phy_write(dev, 0x04AC, 0x32F5);
2926 break;
2927 case B43_INTERFMODE_MANUALWLAN:
2928 if (b43_phy_read(dev, 0x0033) & 0x0800)
2929 break;
2930
2931 phy->aci_enable = 1;
2932
2933 phy_stacksave(B43_PHY_RADIO_BITFIELD);
2934 phy_stacksave(B43_PHY_G_CRS);
2935 if (phy->rev < 2) {
2936 phy_stacksave(0x0406);
2937 } else {
2938 phy_stacksave(0x04C0);
2939 phy_stacksave(0x04C1);
2940 }
2941 phy_stacksave(0x0033);
2942 phy_stacksave(0x04A7);
2943 phy_stacksave(0x04A3);
2944 phy_stacksave(0x04A9);
2945 phy_stacksave(0x04AA);
2946 phy_stacksave(0x04AC);
2947 phy_stacksave(0x0493);
2948 phy_stacksave(0x04A1);
2949 phy_stacksave(0x04A0);
2950 phy_stacksave(0x04A2);
2951 phy_stacksave(0x048A);
2952 phy_stacksave(0x04A8);
2953 phy_stacksave(0x04AB);
2954 if (phy->rev == 2) {
2955 phy_stacksave(0x04AD);
2956 phy_stacksave(0x04AE);
2957 } else if (phy->rev >= 3) {
2958 phy_stacksave(0x04AD);
2959 phy_stacksave(0x0415);
2960 phy_stacksave(0x0416);
2961 phy_stacksave(0x0417);
2962 ofdmtab_stacksave(0x1A00, 0x2);
2963 ofdmtab_stacksave(0x1A00, 0x3);
2964 }
2965 phy_stacksave(0x042B);
2966 phy_stacksave(0x048C);
2967
2968 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
2969 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
2970 & ~0x1000);
2971 b43_phy_write(dev, B43_PHY_G_CRS,
2972 (b43_phy_read(dev, B43_PHY_G_CRS)
2973 & 0xFFFC) | 0x0002);
2974
2975 b43_phy_write(dev, 0x0033, 0x0800);
2976 b43_phy_write(dev, 0x04A3, 0x2027);
2977 b43_phy_write(dev, 0x04A9, 0x1CA8);
2978 b43_phy_write(dev, 0x0493, 0x287A);
2979 b43_phy_write(dev, 0x04AA, 0x1CA8);
2980 b43_phy_write(dev, 0x04AC, 0x287A);
2981
2982 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
2983 & 0xFFC0) | 0x001A);
2984 b43_phy_write(dev, 0x04A7, 0x000D);
2985
2986 if (phy->rev < 2) {
2987 b43_phy_write(dev, 0x0406, 0xFF0D);
2988 } else if (phy->rev == 2) {
2989 b43_phy_write(dev, 0x04C0, 0xFFFF);
2990 b43_phy_write(dev, 0x04C1, 0x00A9);
2991 } else {
2992 b43_phy_write(dev, 0x04C0, 0x00C1);
2993 b43_phy_write(dev, 0x04C1, 0x0059);
2994 }
2995
2996 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
2997 & 0xC0FF) | 0x1800);
2998 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
2999 & 0xFFC0) | 0x0015);
3000 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3001 & 0xCFFF) | 0x1000);
3002 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3003 & 0xF0FF) | 0x0A00);
3004 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3005 & 0xCFFF) | 0x1000);
3006 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3007 & 0xF0FF) | 0x0800);
3008 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3009 & 0xFFCF) | 0x0010);
3010 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3011 & 0xFFF0) | 0x0005);
3012 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3013 & 0xFFCF) | 0x0010);
3014 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3015 & 0xFFF0) | 0x0006);
3016 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3017 & 0xF0FF) | 0x0800);
3018 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3019 & 0xF0FF) | 0x0500);
3020 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3021 & 0xFFF0) | 0x000B);
3022
3023 if (phy->rev >= 3) {
3024 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3025 & ~0x8000);
3026 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3027 & 0x8000) | 0x36D8);
3028 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3029 & 0x8000) | 0x36D8);
3030 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3031 & 0xFE00) | 0x016D);
3032 } else {
3033 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3034 | 0x1000);
3035 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3036 & 0x9FFF) | 0x2000);
3037 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3038 }
3039 if (phy->rev >= 2) {
3040 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3041 | 0x0800);
3042 }
3043 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3044 & 0xF0FF) | 0x0200);
3045 if (phy->rev == 2) {
3046 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3047 & 0xFF00) | 0x007F);
3048 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3049 & 0x00FF) | 0x1300);
3050 } else if (phy->rev >= 6) {
3051 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3052 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3053 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3054 & 0x00FF);
3055 }
3056 b43_calc_nrssi_slope(dev);
3057 break;
3058 default:
3059 B43_WARN_ON(1);
3060 }
3061}
3062
3063static void
3064b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3065{
3066 struct b43_phy *phy = &dev->phy;
3067 u32 *stack = phy->interfstack;
3068
3069 switch (mode) {
3070 case B43_INTERFMODE_NONWLAN:
3071 if (phy->rev != 1) {
3072 b43_phy_write(dev, 0x042B,
3073 b43_phy_read(dev, 0x042B) & ~0x0800);
3074 b43_phy_write(dev, B43_PHY_G_CRS,
3075 b43_phy_read(dev,
3076 B43_PHY_G_CRS) | 0x4000);
3077 break;
3078 }
3079 radio_stackrestore(0x0078);
3080 b43_calc_nrssi_threshold(dev);
3081 phy_stackrestore(0x0406);
3082 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3083 if (!dev->bad_frames_preempt) {
3084 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3085 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3086 & ~(1 << 11));
3087 }
3088 b43_phy_write(dev, B43_PHY_G_CRS,
3089 b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3090 phy_stackrestore(0x04A0);
3091 phy_stackrestore(0x04A1);
3092 phy_stackrestore(0x04A2);
3093 phy_stackrestore(0x04A8);
3094 phy_stackrestore(0x04AB);
3095 phy_stackrestore(0x04A7);
3096 phy_stackrestore(0x04A3);
3097 phy_stackrestore(0x04A9);
3098 phy_stackrestore(0x0493);
3099 phy_stackrestore(0x04AA);
3100 phy_stackrestore(0x04AC);
3101 break;
3102 case B43_INTERFMODE_MANUALWLAN:
3103 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3104 break;
3105
3106 phy->aci_enable = 0;
3107
3108 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3109 phy_stackrestore(B43_PHY_G_CRS);
3110 phy_stackrestore(0x0033);
3111 phy_stackrestore(0x04A3);
3112 phy_stackrestore(0x04A9);
3113 phy_stackrestore(0x0493);
3114 phy_stackrestore(0x04AA);
3115 phy_stackrestore(0x04AC);
3116 phy_stackrestore(0x04A0);
3117 phy_stackrestore(0x04A7);
3118 if (phy->rev >= 2) {
3119 phy_stackrestore(0x04C0);
3120 phy_stackrestore(0x04C1);
3121 } else
3122 phy_stackrestore(0x0406);
3123 phy_stackrestore(0x04A1);
3124 phy_stackrestore(0x04AB);
3125 phy_stackrestore(0x04A8);
3126 if (phy->rev == 2) {
3127 phy_stackrestore(0x04AD);
3128 phy_stackrestore(0x04AE);
3129 } else if (phy->rev >= 3) {
3130 phy_stackrestore(0x04AD);
3131 phy_stackrestore(0x0415);
3132 phy_stackrestore(0x0416);
3133 phy_stackrestore(0x0417);
3134 ofdmtab_stackrestore(0x1A00, 0x2);
3135 ofdmtab_stackrestore(0x1A00, 0x3);
3136 }
3137 phy_stackrestore(0x04A2);
3138 phy_stackrestore(0x048A);
3139 phy_stackrestore(0x042B);
3140 phy_stackrestore(0x048C);
3141 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3142 b43_calc_nrssi_slope(dev);
3143 break;
3144 default:
3145 B43_WARN_ON(1);
3146 }
3147}
3148
3149#undef phy_stacksave
3150#undef phy_stackrestore
3151#undef radio_stacksave
3152#undef radio_stackrestore
3153#undef ofdmtab_stacksave
3154#undef ofdmtab_stackrestore
3155
3156int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3157{
3158 struct b43_phy *phy = &dev->phy;
3159 int currentmode;
3160
3161 if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3162 return -ENODEV;
3163
3164 phy->aci_wlan_automatic = 0;
3165 switch (mode) {
3166 case B43_INTERFMODE_AUTOWLAN:
3167 phy->aci_wlan_automatic = 1;
3168 if (phy->aci_enable)
3169 mode = B43_INTERFMODE_MANUALWLAN;
3170 else
3171 mode = B43_INTERFMODE_NONE;
3172 break;
3173 case B43_INTERFMODE_NONE:
3174 case B43_INTERFMODE_NONWLAN:
3175 case B43_INTERFMODE_MANUALWLAN:
3176 break;
3177 default:
3178 return -EINVAL;
3179 }
3180
3181 currentmode = phy->interfmode;
3182 if (currentmode == mode)
3183 return 0;
3184 if (currentmode != B43_INTERFMODE_NONE)
3185 b43_radio_interference_mitigation_disable(dev, currentmode);
3186
3187 if (mode == B43_INTERFMODE_NONE) {
3188 phy->aci_enable = 0;
3189 phy->aci_hw_rssi = 0;
3190 } else
3191 b43_radio_interference_mitigation_enable(dev, mode);
3192 phy->interfmode = mode;
3193
3194 return 0;
3195}
3196
3197static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3198{
3199 u16 reg, index, ret;
3200
3201 static const u8 rcc_table[] = {
3202 0x02, 0x03, 0x01, 0x0F,
3203 0x06, 0x07, 0x05, 0x0F,
3204 0x0A, 0x0B, 0x09, 0x0F,
3205 0x0E, 0x0F, 0x0D, 0x0F,
3206 };
3207
3208 reg = b43_radio_read16(dev, 0x60);
3209 index = (reg & 0x001E) >> 1;
3210 ret = rcc_table[index] << 1;
3211 ret |= (reg & 0x0001);
3212 ret |= 0x0020;
3213
3214 return ret;
3215}
3216
3217#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
3218static u16 radio2050_rfover_val(struct b43_wldev *dev,
3219 u16 phy_register, unsigned int lpd)
3220{
3221 struct b43_phy *phy = &dev->phy;
3222 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3223
3224 if (!phy->gmode)
3225 return 0;
3226
3227 if (has_loopback_gain(phy)) {
3228 int max_lb_gain = phy->max_lb_gain;
3229 u16 extlna;
3230 u16 i;
3231
3232 if (phy->radio_rev == 8)
3233 max_lb_gain += 0x3E;
3234 else
3235 max_lb_gain += 0x26;
3236 if (max_lb_gain >= 0x46) {
3237 extlna = 0x3000;
3238 max_lb_gain -= 0x46;
3239 } else if (max_lb_gain >= 0x3A) {
3240 extlna = 0x1000;
3241 max_lb_gain -= 0x3A;
3242 } else if (max_lb_gain >= 0x2E) {
3243 extlna = 0x2000;
3244 max_lb_gain -= 0x2E;
3245 } else {
3246 extlna = 0;
3247 max_lb_gain -= 0x10;
3248 }
3249
3250 for (i = 0; i < 16; i++) {
3251 max_lb_gain -= (i * 6);
3252 if (max_lb_gain < 6)
3253 break;
3254 }
3255
3256 if ((phy->rev < 7) ||
3257 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
3258 if (phy_register == B43_PHY_RFOVER) {
3259 return 0x1B3;
3260 } else if (phy_register == B43_PHY_RFOVERVAL) {
3261 extlna |= (i << 8);
3262 switch (lpd) {
3263 case LPD(0, 1, 1):
3264 return 0x0F92;
3265 case LPD(0, 0, 1):
3266 case LPD(1, 0, 1):
3267 return (0x0092 | extlna);
3268 case LPD(1, 0, 0):
3269 return (0x0093 | extlna);
3270 }
3271 B43_WARN_ON(1);
3272 }
3273 B43_WARN_ON(1);
3274 } else {
3275 if (phy_register == B43_PHY_RFOVER) {
3276 return 0x9B3;
3277 } else if (phy_register == B43_PHY_RFOVERVAL) {
3278 if (extlna)
3279 extlna |= 0x8000;
3280 extlna |= (i << 8);
3281 switch (lpd) {
3282 case LPD(0, 1, 1):
3283 return 0x8F92;
3284 case LPD(0, 0, 1):
3285 return (0x8092 | extlna);
3286 case LPD(1, 0, 1):
3287 return (0x2092 | extlna);
3288 case LPD(1, 0, 0):
3289 return (0x2093 | extlna);
3290 }
3291 B43_WARN_ON(1);
3292 }
3293 B43_WARN_ON(1);
3294 }
3295 } else {
3296 if ((phy->rev < 7) ||
3297 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
3298 if (phy_register == B43_PHY_RFOVER) {
3299 return 0x1B3;
3300 } else if (phy_register == B43_PHY_RFOVERVAL) {
3301 switch (lpd) {
3302 case LPD(0, 1, 1):
3303 return 0x0FB2;
3304 case LPD(0, 0, 1):
3305 return 0x00B2;
3306 case LPD(1, 0, 1):
3307 return 0x30B2;
3308 case LPD(1, 0, 0):
3309 return 0x30B3;
3310 }
3311 B43_WARN_ON(1);
3312 }
3313 B43_WARN_ON(1);
3314 } else {
3315 if (phy_register == B43_PHY_RFOVER) {
3316 return 0x9B3;
3317 } else if (phy_register == B43_PHY_RFOVERVAL) {
3318 switch (lpd) {
3319 case LPD(0, 1, 1):
3320 return 0x8FB2;
3321 case LPD(0, 0, 1):
3322 return 0x80B2;
3323 case LPD(1, 0, 1):
3324 return 0x20B2;
3325 case LPD(1, 0, 0):
3326 return 0x20B3;
3327 }
3328 B43_WARN_ON(1);
3329 }
3330 B43_WARN_ON(1);
3331 }
3332 }
3333 return 0;
3334}
3335
3336struct init2050_saved_values {
3337 /* Core registers */
3338 u16 reg_3EC;
3339 u16 reg_3E6;
3340 u16 reg_3F4;
3341 /* Radio registers */
3342 u16 radio_43;
3343 u16 radio_51;
3344 u16 radio_52;
3345 /* PHY registers */
3346 u16 phy_pgactl;
3347 u16 phy_cck_5A;
3348 u16 phy_cck_59;
3349 u16 phy_cck_58;
3350 u16 phy_cck_30;
3351 u16 phy_rfover;
3352 u16 phy_rfoverval;
3353 u16 phy_analogover;
3354 u16 phy_analogoverval;
3355 u16 phy_crs0;
3356 u16 phy_classctl;
3357 u16 phy_lo_mask;
3358 u16 phy_lo_ctl;
3359 u16 phy_syncctl;
3360};
3361
3362u16 b43_radio_init2050(struct b43_wldev *dev)
3363{
3364 struct b43_phy *phy = &dev->phy;
3365 struct init2050_saved_values sav;
3366 u16 rcc;
3367 u16 radio78;
3368 u16 ret;
3369 u16 i, j;
3370 u32 tmp1 = 0, tmp2 = 0;
3371
3372 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
3373
3374 sav.radio_43 = b43_radio_read16(dev, 0x43);
3375 sav.radio_51 = b43_radio_read16(dev, 0x51);
3376 sav.radio_52 = b43_radio_read16(dev, 0x52);
3377 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3378 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
3379 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
3380 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
3381
3382 if (phy->type == B43_PHYTYPE_B) {
3383 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
3384 sav.reg_3EC = b43_read16(dev, 0x3EC);
3385
3386 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
3387 b43_write16(dev, 0x3EC, 0x3F3F);
3388 } else if (phy->gmode || phy->rev >= 2) {
3389 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3390 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3391 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3392 sav.phy_analogoverval =
3393 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3394 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3395 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3396
3397 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3398 b43_phy_read(dev, B43_PHY_ANALOGOVER)
3399 | 0x0003);
3400 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3401 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3402 & 0xFFFC);
3403 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3404 & 0x7FFF);
3405 b43_phy_write(dev, B43_PHY_CLASSCTL,
3406 b43_phy_read(dev, B43_PHY_CLASSCTL)
3407 & 0xFFFC);
3408 if (has_loopback_gain(phy)) {
3409 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3410 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3411
3412 if (phy->rev >= 3)
3413 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3414 else
3415 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3416 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3417 }
3418
3419 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3420 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3421 LPD(0, 1, 1)));
3422 b43_phy_write(dev, B43_PHY_RFOVER,
3423 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3424 }
3425 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3426
3427 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3428 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3429 & 0xFF7F);
3430 sav.reg_3E6 = b43_read16(dev, 0x3E6);
3431 sav.reg_3F4 = b43_read16(dev, 0x3F4);
3432
3433 if (phy->analog == 0) {
3434 b43_write16(dev, 0x03E6, 0x0122);
3435 } else {
3436 if (phy->analog >= 2) {
3437 b43_phy_write(dev, B43_PHY_CCK(0x03),
3438 (b43_phy_read(dev, B43_PHY_CCK(0x03))
3439 & 0xFFBF) | 0x40);
3440 }
3441 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3442 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3443 }
3444
3445 rcc = b43_radio_core_calibration_value(dev);
3446
3447 if (phy->type == B43_PHYTYPE_B)
3448 b43_radio_write16(dev, 0x78, 0x26);
3449 if (phy->gmode || phy->rev >= 2) {
3450 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3451 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3452 LPD(0, 1, 1)));
3453 }
3454 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3455 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
3456 if (phy->gmode || phy->rev >= 2) {
3457 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3458 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3459 LPD(0, 0, 1)));
3460 }
3461 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3462 b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3463 | 0x0004);
3464 if (phy->radio_rev == 8) {
3465 b43_radio_write16(dev, 0x43, 0x1F);
3466 } else {
3467 b43_radio_write16(dev, 0x52, 0);
3468 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3469 & 0xFFF0) | 0x0009);
3470 }
3471 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3472
3473 for (i = 0; i < 16; i++) {
3474 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
3475 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3476 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3477 if (phy->gmode || phy->rev >= 2) {
3478 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3479 radio2050_rfover_val(dev,
3480 B43_PHY_RFOVERVAL,
3481 LPD(1, 0, 1)));
3482 }
3483 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3484 udelay(10);
3485 if (phy->gmode || phy->rev >= 2) {
3486 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3487 radio2050_rfover_val(dev,
3488 B43_PHY_RFOVERVAL,
3489 LPD(1, 0, 1)));
3490 }
3491 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3492 udelay(10);
3493 if (phy->gmode || phy->rev >= 2) {
3494 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3495 radio2050_rfover_val(dev,
3496 B43_PHY_RFOVERVAL,
3497 LPD(1, 0, 0)));
3498 }
3499 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3500 udelay(20);
3501 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3502 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3503 if (phy->gmode || phy->rev >= 2) {
3504 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3505 radio2050_rfover_val(dev,
3506 B43_PHY_RFOVERVAL,
3507 LPD(1, 0, 1)));
3508 }
3509 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3510 }
3511 udelay(10);
3512
3513 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3514 tmp1++;
3515 tmp1 >>= 9;
3516
3517 for (i = 0; i < 16; i++) {
3518 radio78 = (bitrev4(i) << 1) | 0x0020;
3519 b43_radio_write16(dev, 0x78, radio78);
3520 udelay(10);
3521 for (j = 0; j < 16; j++) {
3522 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
3523 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3524 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3525 if (phy->gmode || phy->rev >= 2) {
3526 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3527 radio2050_rfover_val(dev,
3528 B43_PHY_RFOVERVAL,
3529 LPD(1, 0,
3530 1)));
3531 }
3532 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3533 udelay(10);
3534 if (phy->gmode || phy->rev >= 2) {
3535 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3536 radio2050_rfover_val(dev,
3537 B43_PHY_RFOVERVAL,
3538 LPD(1, 0,
3539 1)));
3540 }
3541 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3542 udelay(10);
3543 if (phy->gmode || phy->rev >= 2) {
3544 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3545 radio2050_rfover_val(dev,
3546 B43_PHY_RFOVERVAL,
3547 LPD(1, 0,
3548 0)));
3549 }
3550 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3551 udelay(10);
3552 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3553 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3554 if (phy->gmode || phy->rev >= 2) {
3555 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3556 radio2050_rfover_val(dev,
3557 B43_PHY_RFOVERVAL,
3558 LPD(1, 0,
3559 1)));
3560 }
3561 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3562 }
3563 tmp2++;
3564 tmp2 >>= 8;
3565 if (tmp1 < tmp2)
3566 break;
3567 }
3568
3569 /* Restore the registers */
3570 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3571 b43_radio_write16(dev, 0x51, sav.radio_51);
3572 b43_radio_write16(dev, 0x52, sav.radio_52);
3573 b43_radio_write16(dev, 0x43, sav.radio_43);
3574 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
3575 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
3576 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
3577 b43_write16(dev, 0x3E6, sav.reg_3E6);
3578 if (phy->analog != 0)
3579 b43_write16(dev, 0x3F4, sav.reg_3F4);
3580 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3581 b43_synth_pu_workaround(dev, phy->channel);
3582 if (phy->type == B43_PHYTYPE_B) {
3583 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
3584 b43_write16(dev, 0x3EC, sav.reg_3EC);
3585 } else if (phy->gmode) {
3586 b43_write16(dev, B43_MMIO_PHY_RADIO,
3587 b43_read16(dev, B43_MMIO_PHY_RADIO)
3588 & 0x7FFF);
3589 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
3590 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
3591 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
3592 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3593 sav.phy_analogoverval);
3594 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
3595 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
3596 if (has_loopback_gain(phy)) {
3597 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
3598 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
3599 }
3600 }
3601 if (i > 15)
3602 ret = radio78;
3603 else
3604 ret = rcc;
3605
3606 return ret;
3607}
3608
3609void b43_radio_init2060(struct b43_wldev *dev)
3610{
3611 int err;
3612
3613 b43_radio_write16(dev, 0x0004, 0x00C0);
3614 b43_radio_write16(dev, 0x0005, 0x0008);
3615 b43_radio_write16(dev, 0x0009, 0x0040);
3616 b43_radio_write16(dev, 0x0005, 0x00AA);
3617 b43_radio_write16(dev, 0x0032, 0x008F);
3618 b43_radio_write16(dev, 0x0006, 0x008F);
3619 b43_radio_write16(dev, 0x0034, 0x008F);
3620 b43_radio_write16(dev, 0x002C, 0x0007);
3621 b43_radio_write16(dev, 0x0082, 0x0080);
3622 b43_radio_write16(dev, 0x0080, 0x0000);
3623 b43_radio_write16(dev, 0x003F, 0x00DA);
3624 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3625 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
3626 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3627 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3628 msleep(1); /* delay 400usec */
3629
3630 b43_radio_write16(dev, 0x0081,
3631 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
3632 msleep(1); /* delay 400usec */
3633
3634 b43_radio_write16(dev, 0x0005,
3635 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
3636 b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
3637 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3638 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
3639 b43_radio_write16(dev, 0x0081,
3640 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
3641 b43_radio_write16(dev, 0x0005,
3642 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
3643 b43_phy_write(dev, 0x0063, 0xDDC6);
3644 b43_phy_write(dev, 0x0069, 0x07BE);
3645 b43_phy_write(dev, 0x006A, 0x0000);
3646
3647 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
3648 B43_WARN_ON(err);
3649
3650 msleep(1);
3651}
3652
3653static inline u16 freq_r3A_value(u16 frequency)
3654{
3655 u16 value;
3656
3657 if (frequency < 5091)
3658 value = 0x0040;
3659 else if (frequency < 5321)
3660 value = 0x0000;
3661 else if (frequency < 5806)
3662 value = 0x0080;
3663 else
3664 value = 0x0040;
3665
3666 return value;
3667}
3668
3669void b43_radio_set_tx_iq(struct b43_wldev *dev)
3670{
3671 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
3672 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
3673 u16 tmp = b43_radio_read16(dev, 0x001E);
3674 int i, j;
3675
3676 for (i = 0; i < 5; i++) {
3677 for (j = 0; j < 5; j++) {
3678 if (tmp == (data_high[i] << 4 | data_low[j])) {
3679 b43_phy_write(dev, 0x0069,
3680 (i - j) << 8 | 0x00C0);
3681 return;
3682 }
3683 }
3684 }
3685}
3686
3687int b43_radio_selectchannel(struct b43_wldev *dev,
3688 u8 channel, int synthetic_pu_workaround)
3689{
3690 struct b43_phy *phy = &dev->phy;
3691 u16 r8, tmp;
3692 u16 freq;
3693 u16 channelcookie, savedcookie;
3694 int err = 0;
3695
3696 if (channel == 0xFF) {
3697 switch (phy->type) {
3698 case B43_PHYTYPE_A:
3699 channel = B43_DEFAULT_CHANNEL_A;
3700 break;
3701 case B43_PHYTYPE_B:
3702 case B43_PHYTYPE_G:
3703 channel = B43_DEFAULT_CHANNEL_BG;
3704 break;
3705 case B43_PHYTYPE_N:
3706 //FIXME check if we are on 2.4GHz or 5GHz and set a default channel.
3707 channel = 1;
3708 break;
3709 default:
3710 B43_WARN_ON(1);
3711 }
3712 }
3713
3714 /* First we set the channel radio code to prevent the
3715 * firmware from sending ghost packets.
3716 */
3717 channelcookie = channel;
3718 if (0 /*FIXME on 5Ghz */)
3719 channelcookie |= 0x100;
3720 //FIXME set 40Mhz flag if required
3721 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
3722 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
3723
3724 switch (phy->type) {
3725 case B43_PHYTYPE_A:
3726 if (channel > 200) {
3727 err = -EINVAL;
3728 goto out;
3729 }
3730 freq = channel2freq_a(channel);
3731
3732 r8 = b43_radio_read16(dev, 0x0008);
3733 b43_write16(dev, 0x03F0, freq);
3734 b43_radio_write16(dev, 0x0008, r8);
3735
3736 //TODO: write max channel TX power? to Radio 0x2D
3737 tmp = b43_radio_read16(dev, 0x002E);
3738 tmp &= 0x0080;
3739 //TODO: OR tmp with the Power out estimation for this channel?
3740 b43_radio_write16(dev, 0x002E, tmp);
3741
3742 if (freq >= 4920 && freq <= 5500) {
3743 /*
3744 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
3745 * = (freq * 0.025862069
3746 */
3747 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
3748 }
3749 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
3750 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
3751 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
3752 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
3753 & 0x000F) | (r8 << 4));
3754 b43_radio_write16(dev, 0x002A, (r8 << 4));
3755 b43_radio_write16(dev, 0x002B, (r8 << 4));
3756 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
3757 & 0x00F0) | (r8 << 4));
3758 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
3759 & 0xFF0F) | 0x00B0);
3760 b43_radio_write16(dev, 0x0035, 0x00AA);
3761 b43_radio_write16(dev, 0x0036, 0x0085);
3762 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
3763 & 0xFF20) |
3764 freq_r3A_value(freq));
3765 b43_radio_write16(dev, 0x003D,
3766 b43_radio_read16(dev, 0x003D) & 0x00FF);
3767 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
3768 & 0xFF7F) | 0x0080);
3769 b43_radio_write16(dev, 0x0035,
3770 b43_radio_read16(dev, 0x0035) & 0xFFEF);
3771 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
3772 & 0xFFEF) | 0x0010);
3773 b43_radio_set_tx_iq(dev);
3774 //TODO: TSSI2dbm workaround
3775 b43_phy_xmitpower(dev); //FIXME correct?
3776 break;
3777 case B43_PHYTYPE_G:
3778 if ((channel < 1) || (channel > 14)) {
3779 err = -EINVAL;
3780 goto out;
3781 }
3782
3783 if (synthetic_pu_workaround)
3784 b43_synth_pu_workaround(dev, channel);
3785
3786 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
3787
3788 if (channel == 14) {
3789 if (dev->dev->bus->sprom.country_code ==
3790 SSB_SPROM1CCODE_JAPAN)
3791 b43_hf_write(dev,
3792 b43_hf_read(dev) & ~B43_HF_ACPR);
3793 else
3794 b43_hf_write(dev,
3795 b43_hf_read(dev) | B43_HF_ACPR);
3796 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3797 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3798 | (1 << 11));
3799 } else {
3800 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3801 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3802 & 0xF7BF);
3803 }
3804 break;
3805 case B43_PHYTYPE_N:
3806 err = b43_nphy_selectchannel(dev, channel);
3807 if (err)
3808 goto out;
3809 break;
3810 default:
3811 B43_WARN_ON(1);
3812 }
3813
3814 phy->channel = channel;
3815 /* Wait for the radio to tune to the channel and stabilize. */
3816 msleep(8);
3817out:
3818 if (err) {
3819 b43_shm_write16(dev, B43_SHM_SHARED,
3820 B43_SHM_SH_CHAN, savedcookie);
3821 }
3822 return err;
3823}
3824
3825void b43_radio_turn_on(struct b43_wldev *dev) 432void b43_radio_turn_on(struct b43_wldev *dev)
3826{ 433{
3827 struct b43_phy *phy = &dev->phy; 434 struct b43_phy *phy = &dev->phy;
@@ -3843,21 +450,7 @@ void b43_radio_turn_on(struct b43_wldev *dev)
3843 break; 450 break;
3844 case B43_PHYTYPE_B: 451 case B43_PHYTYPE_B:
3845 case B43_PHYTYPE_G: 452 case B43_PHYTYPE_G:
3846 b43_phy_write(dev, 0x0015, 0x8000); 453 //XXX
3847 b43_phy_write(dev, 0x0015, 0xCC00);
3848 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
3849 if (phy->radio_off_context.valid) {
3850 /* Restore the RFover values. */
3851 b43_phy_write(dev, B43_PHY_RFOVER,
3852 phy->radio_off_context.rfover);
3853 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3854 phy->radio_off_context.rfoverval);
3855 phy->radio_off_context.valid = 0;
3856 }
3857 channel = phy->channel;
3858 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
3859 err |= b43_radio_selectchannel(dev, channel, 0);
3860 B43_WARN_ON(err);
3861 break; 454 break;
3862 case B43_PHYTYPE_N: 455 case B43_PHYTYPE_N:
3863 b43_nphy_radio_turn_on(dev); 456 b43_nphy_radio_turn_on(dev);
@@ -3886,17 +479,7 @@ void b43_radio_turn_off(struct b43_wldev *dev, bool force)
3886 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008); 479 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
3887 break; 480 break;
3888 case B43_PHYTYPE_G: { 481 case B43_PHYTYPE_G: {
3889 u16 rfover, rfoverval; 482 //XXX
3890
3891 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3892 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3893 if (!force) {
3894 phy->radio_off_context.rfover = rfover;
3895 phy->radio_off_context.rfoverval = rfoverval;
3896 phy->radio_off_context.valid = 1;
3897 }
3898 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
3899 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
3900 break; 483 break;
3901 } 484 }
3902 default: 485 default:
diff --git a/drivers/net/wireless/b43/phy.h b/drivers/net/wireless/b43/phy.h
deleted file mode 100644
index 4aab10903529..000000000000
--- a/drivers/net/wireless/b43/phy.h
+++ /dev/null
@@ -1,340 +0,0 @@
1#ifndef B43_PHY_H_
2#define B43_PHY_H_
3
4#include <linux/types.h>
5
6struct b43_wldev;
7struct b43_phy;
8
9/*** PHY Registers ***/
10
11/* Routing */
12#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
13#define B43_PHYROUTE_BASE 0x0000 /* Base registers */
14#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
15#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
16#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
17
18/* CCK (B-PHY) registers. */
19#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
20/* N-PHY registers. */
21#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
22/* N-PHY BMODE registers. */
23#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
24/* OFDM (A-PHY) registers. */
25#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
26/* Extended G-PHY registers. */
27#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
28
29/* OFDM (A) PHY Registers */
30#define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
31#define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
32#define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
33#define B43_PHY_BBANDCFG_RXANT_SHIFT 7
34#define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
35#define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
36#define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
37#define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
38#define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
39#define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
40#define B43_PHY_CRS0_EN 0x4000
41#define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
42#define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
43#define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
44#define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
45#define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */
46#define B43_PHY_LMS B43_PHY_OFDM(0x55)
47#define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
48#define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */
49#define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
50#define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
51#define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
52#define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
53#define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
54#define B43_PHY_OTABLENR_SHIFT 10
55#define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
56#define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
57#define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
58#define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
59#define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
60#define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
61#define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
62#define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
63#define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
64#define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
65#define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */
66#define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0)
67#define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1)
68#define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
69#define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
70#define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
71#define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
72#define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
73#define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
74#define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
75#define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
76#define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB)
77#define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
78#define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
79#define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
80#define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
81#define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */
82#define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */
83#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
84
85/* CCK (B) PHY Registers */
86#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
87#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
88#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
89#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
90#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
91#define B43_PHY_PGACTL_UNKNOWN 0xEFA0
92#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
93#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
94#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
95#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
96#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
97#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
98#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
99#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
100
101/* Extended G-PHY Registers */
102#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
103#define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */
104#define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
105#define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
106#define B43_PHY_GTABNR_SHIFT 10
107#define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */
108#define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */
109#define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */
110#define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */
111#define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */
112#define B43_PHY_RFOVERVAL_EXTLNA 0x8000
113#define B43_PHY_RFOVERVAL_LNA 0x7000
114#define B43_PHY_RFOVERVAL_LNA_SHIFT 12
115#define B43_PHY_RFOVERVAL_PGA 0x0F00
116#define B43_PHY_RFOVERVAL_PGA_SHIFT 8
117#define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */
118#define B43_PHY_RFOVERVAL_TRSWRX 0x00E0
119#define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */
120#define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */
121#define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */
122#define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */
123#define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */
124
125/*** OFDM table numbers ***/
126#define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
127#define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0)
128#define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0)
129#define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename
130#define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4)
131#define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0)
132#define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3)
133#define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0)
134#define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0)
135#define B43_OFDMTAB_LNAHPFGAIN2 B43_OFDMTAB(0x04, 0)
136#define B43_OFDMTAB_NOISESCALE B43_OFDMTAB(0x05, 0)
137#define B43_OFDMTAB_AGC2 B43_OFDMTAB(0x06, 0)
138#define B43_OFDMTAB_ROTOR B43_OFDMTAB(0x08, 0)
139#define B43_OFDMTAB_ADVRETARD B43_OFDMTAB(0x09, 0)
140#define B43_OFDMTAB_DAC B43_OFDMTAB(0x0C, 0)
141#define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7)
142#define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12)
143#define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13)
144#define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename
145#define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename
146#define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12)
147#define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0)
148#define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename
149#define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0)
150#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove!
151#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0)
152#define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0)
153#define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4)
154#define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0)
155#define B43_OFDMTAB_DACRFPABB B43_OFDMTAB(0x16, 0)
156#define B43_OFDMTAB_DACOFF B43_OFDMTAB(0x17, 0)
157#define B43_OFDMTAB_DCBIAS B43_OFDMTAB(0x18, 0)
158
159u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
160void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
161 u16 offset, u16 value);
162u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
163void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
164 u16 offset, u32 value);
165
166/*** G-PHY table numbers */
167#define B43_GTAB(number, offset) (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
168#define B43_GTAB_NRSSI B43_GTAB(0x00, 0)
169#define B43_GTAB_TRFEMW B43_GTAB(0x0C, 0x120)
170#define B43_GTAB_ORIGTR B43_GTAB(0x2E, 0x298)
171
172u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset); //TODO implement
173void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value); //TODO implement
174
175#define B43_DEFAULT_CHANNEL_A 36
176#define B43_DEFAULT_CHANNEL_BG 6
177
178enum {
179 B43_ANTENNA0, /* Antenna 0 */
180 B43_ANTENNA1, /* Antenna 0 */
181 B43_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
182 B43_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
183 B43_ANTENNA2,
184 B43_ANTENNA3 = 8,
185
186 B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
187 B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
188};
189
190enum {
191 B43_INTERFMODE_NONE,
192 B43_INTERFMODE_NONWLAN,
193 B43_INTERFMODE_MANUALWLAN,
194 B43_INTERFMODE_AUTOWLAN,
195};
196
197/* Masks for the different PHY versioning registers. */
198#define B43_PHYVER_ANALOG 0xF000
199#define B43_PHYVER_ANALOG_SHIFT 12
200#define B43_PHYVER_TYPE 0x0F00
201#define B43_PHYVER_TYPE_SHIFT 8
202#define B43_PHYVER_VERSION 0x00FF
203
204void b43_phy_lock(struct b43_wldev *dev);
205void b43_phy_unlock(struct b43_wldev *dev);
206
207
208/* Read a value from a PHY register */
209u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
210/* Write a value to a PHY register */
211void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
212/* Mask a PHY register with a mask */
213void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
214/* OR a PHY register with a bitmap */
215void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
216/* Mask and OR a PHY register with a mask and bitmap */
217void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
218
219
220int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
221
222void b43_phy_early_init(struct b43_wldev *dev);
223int b43_phy_init(struct b43_wldev *dev);
224
225void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
226
227void b43_phy_xmitpower(struct b43_wldev *dev);
228
229/* Returns the boolean whether the board has HardwarePowerControl */
230bool b43_has_hardware_pctl(struct b43_phy *phy);
231/* Returns the boolean whether "TX Magnification" is enabled. */
232#define has_tx_magnification(phy) \
233 (((phy)->rev >= 2) && \
234 ((phy)->radio_ver == 0x2050) && \
235 ((phy)->radio_rev == 8))
236/* Card uses the loopback gain stuff */
237#define has_loopback_gain(phy) \
238 (((phy)->rev > 1) || ((phy)->gmode))
239
240/* Radio Attenuation (RF Attenuation) */
241struct b43_rfatt {
242 u8 att; /* Attenuation value */
243 bool with_padmix; /* Flag, PAD Mixer enabled. */
244};
245struct b43_rfatt_list {
246 /* Attenuation values list */
247 const struct b43_rfatt *list;
248 u8 len;
249 /* Minimum/Maximum attenuation values */
250 u8 min_val;
251 u8 max_val;
252};
253
254/* Returns true, if the values are the same. */
255static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
256 const struct b43_rfatt *b)
257{
258 return ((a->att == b->att) &&
259 (a->with_padmix == b->with_padmix));
260}
261
262/* Baseband Attenuation */
263struct b43_bbatt {
264 u8 att; /* Attenuation value */
265};
266struct b43_bbatt_list {
267 /* Attenuation values list */
268 const struct b43_bbatt *list;
269 u8 len;
270 /* Minimum/Maximum attenuation values */
271 u8 min_val;
272 u8 max_val;
273};
274
275/* Returns true, if the values are the same. */
276static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
277 const struct b43_bbatt *b)
278{
279 return (a->att == b->att);
280}
281
282/* tx_control bits. */
283#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */
284#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */
285#define B43_TXCTL_TXMIX 0x10 /* TX Mixer Gain */
286
287/* Write BasebandAttenuation value to the device. */
288void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
289 u16 baseband_attenuation);
290
291extern const u8 b43_radio_channel_codes_bg[];
292
293void b43_radio_lock(struct b43_wldev *dev);
294void b43_radio_unlock(struct b43_wldev *dev);
295
296
297/* Read a value from a 16bit radio register */
298u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
299/* Write a value to a 16bit radio register */
300void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
301/* Mask a 16bit radio register with a mask */
302void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
303/* OR a 16bit radio register with a bitmap */
304void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
305/* Mask and OR a PHY register with a mask and bitmap */
306void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
307
308
309u16 b43_radio_init2050(struct b43_wldev *dev);
310void b43_radio_init2060(struct b43_wldev *dev);
311
312void b43_radio_turn_on(struct b43_wldev *dev);
313void b43_radio_turn_off(struct b43_wldev *dev, bool force);
314
315int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
316 int synthetic_pu_workaround);
317
318u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
319u8 b43_radio_aci_scan(struct b43_wldev *dev);
320
321int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
322
323void b43_calc_nrssi_slope(struct b43_wldev *dev);
324void b43_calc_nrssi_threshold(struct b43_wldev *dev);
325s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
326void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
327void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
328void b43_nrssi_mem_update(struct b43_wldev *dev);
329
330void b43_radio_set_tx_iq(struct b43_wldev *dev);
331u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
332
333void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
334 int *_bbatt, int *_rfatt);
335
336void b43_set_txpower_g(struct b43_wldev *dev,
337 const struct b43_bbatt *bbatt,
338 const struct b43_rfatt *rfatt, u8 tx_control);
339
340#endif /* B43_PHY_H_ */
diff --git a/drivers/net/wireless/b43/phy_a.c b/drivers/net/wireless/b43/phy_a.c
new file mode 100644
index 000000000000..dd347314b76c
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_a.c
@@ -0,0 +1,536 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11a PHY driver
5
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
26
27*/
28
29#include "b43.h"
30#include "phy_a.h"
31#include "phy_common.h"
32#include "wa.h"
33#include "tables.h"
34#include "main.h"
35
36
37/* Get the freq, as it has to be written to the device. */
38static inline u16 channel2freq_a(u8 channel)
39{
40 B43_WARN_ON(channel > 200);
41
42 return (5000 + 5 * channel);
43}
44
45static inline u16 freq_r3A_value(u16 frequency)
46{
47 u16 value;
48
49 if (frequency < 5091)
50 value = 0x0040;
51 else if (frequency < 5321)
52 value = 0x0000;
53 else if (frequency < 5806)
54 value = 0x0080;
55 else
56 value = 0x0040;
57
58 return value;
59}
60
61void b43_radio_set_tx_iq(struct b43_wldev *dev)
62{
63 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
64 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
65 u16 tmp = b43_radio_read16(dev, 0x001E);
66 int i, j;
67
68 for (i = 0; i < 5; i++) {
69 for (j = 0; j < 5; j++) {
70 if (tmp == (data_high[i] << 4 | data_low[j])) {
71 b43_phy_write(dev, 0x0069,
72 (i - j) << 8 | 0x00C0);
73 return;
74 }
75 }
76 }
77}
78
79static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
80{
81 u16 freq, r8, tmp;
82
83 freq = channel2freq_a(channel);
84
85 r8 = b43_radio_read16(dev, 0x0008);
86 b43_write16(dev, 0x03F0, freq);
87 b43_radio_write16(dev, 0x0008, r8);
88
89 //TODO: write max channel TX power? to Radio 0x2D
90 tmp = b43_radio_read16(dev, 0x002E);
91 tmp &= 0x0080;
92 //TODO: OR tmp with the Power out estimation for this channel?
93 b43_radio_write16(dev, 0x002E, tmp);
94
95 if (freq >= 4920 && freq <= 5500) {
96 /*
97 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
98 * = (freq * 0.025862069
99 */
100 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
101 }
102 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
103 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
104 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
105 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
106 & 0x000F) | (r8 << 4));
107 b43_radio_write16(dev, 0x002A, (r8 << 4));
108 b43_radio_write16(dev, 0x002B, (r8 << 4));
109 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
110 & 0x00F0) | (r8 << 4));
111 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
112 & 0xFF0F) | 0x00B0);
113 b43_radio_write16(dev, 0x0035, 0x00AA);
114 b43_radio_write16(dev, 0x0036, 0x0085);
115 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
116 & 0xFF20) |
117 freq_r3A_value(freq));
118 b43_radio_write16(dev, 0x003D,
119 b43_radio_read16(dev, 0x003D) & 0x00FF);
120 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
121 & 0xFF7F) | 0x0080);
122 b43_radio_write16(dev, 0x0035,
123 b43_radio_read16(dev, 0x0035) & 0xFFEF);
124 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
125 & 0xFFEF) | 0x0010);
126 b43_radio_set_tx_iq(dev);
127 //TODO: TSSI2dbm workaround
128//FIXME b43_phy_xmitpower(dev);
129}
130
131void b43_radio_init2060(struct b43_wldev *dev)
132{
133 b43_radio_write16(dev, 0x0004, 0x00C0);
134 b43_radio_write16(dev, 0x0005, 0x0008);
135 b43_radio_write16(dev, 0x0009, 0x0040);
136 b43_radio_write16(dev, 0x0005, 0x00AA);
137 b43_radio_write16(dev, 0x0032, 0x008F);
138 b43_radio_write16(dev, 0x0006, 0x008F);
139 b43_radio_write16(dev, 0x0034, 0x008F);
140 b43_radio_write16(dev, 0x002C, 0x0007);
141 b43_radio_write16(dev, 0x0082, 0x0080);
142 b43_radio_write16(dev, 0x0080, 0x0000);
143 b43_radio_write16(dev, 0x003F, 0x00DA);
144 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
145 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
146 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
147 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
148 msleep(1); /* delay 400usec */
149
150 b43_radio_write16(dev, 0x0081,
151 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
152 msleep(1); /* delay 400usec */
153
154 b43_radio_write16(dev, 0x0005,
155 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
156 b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
157 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
158 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
159 b43_radio_write16(dev, 0x0081,
160 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
161 b43_radio_write16(dev, 0x0005,
162 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
163 b43_phy_write(dev, 0x0063, 0xDDC6);
164 b43_phy_write(dev, 0x0069, 0x07BE);
165 b43_phy_write(dev, 0x006A, 0x0000);
166
167 aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
168
169 msleep(1);
170}
171
172static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
173{
174 int i;
175
176 if (dev->phy.rev < 3) {
177 if (enable)
178 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
179 b43_ofdmtab_write16(dev,
180 B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
181 b43_ofdmtab_write16(dev,
182 B43_OFDMTAB_WRSSI, i, 0xFFF8);
183 }
184 else
185 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
186 b43_ofdmtab_write16(dev,
187 B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
188 b43_ofdmtab_write16(dev,
189 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
190 }
191 } else {
192 if (enable)
193 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
194 b43_ofdmtab_write16(dev,
195 B43_OFDMTAB_WRSSI, i, 0x0820);
196 else
197 for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
198 b43_ofdmtab_write16(dev,
199 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
200 }
201}
202
203static void b43_phy_ww(struct b43_wldev *dev)
204{
205 u16 b, curr_s, best_s = 0xFFFF;
206 int i;
207
208 b43_phy_write(dev, B43_PHY_CRS0,
209 b43_phy_read(dev, B43_PHY_CRS0) & ~B43_PHY_CRS0_EN);
210 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
211 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) | 0x1000);
212 b43_phy_write(dev, B43_PHY_OFDM(0x82),
213 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
214 b43_radio_write16(dev, 0x0009,
215 b43_radio_read16(dev, 0x0009) | 0x0080);
216 b43_radio_write16(dev, 0x0012,
217 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
218 b43_wa_initgains(dev);
219 b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
220 b = b43_phy_read(dev, B43_PHY_PWRDOWN);
221 b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
222 b43_radio_write16(dev, 0x0004,
223 b43_radio_read16(dev, 0x0004) | 0x0004);
224 for (i = 0x10; i <= 0x20; i++) {
225 b43_radio_write16(dev, 0x0013, i);
226 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
227 if (!curr_s) {
228 best_s = 0x0000;
229 break;
230 } else if (curr_s >= 0x0080)
231 curr_s = 0x0100 - curr_s;
232 if (curr_s < best_s)
233 best_s = curr_s;
234 }
235 b43_phy_write(dev, B43_PHY_PWRDOWN, b);
236 b43_radio_write16(dev, 0x0004,
237 b43_radio_read16(dev, 0x0004) & 0xFFFB);
238 b43_radio_write16(dev, 0x0013, best_s);
239 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
240 b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
241 b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
242 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
243 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
244 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
245 b43_phy_write(dev, B43_PHY_OFDM(0xBB),
246 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
247 b43_phy_write(dev, B43_PHY_OFDM61,
248 (b43_phy_read(dev, B43_PHY_OFDM61) & 0xFE1F) | 0x0120);
249 b43_phy_write(dev, B43_PHY_OFDM(0x13),
250 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
251 b43_phy_write(dev, B43_PHY_OFDM(0x14),
252 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
253 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
254 for (i = 0; i < 6; i++)
255 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
256 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
257 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
258 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
259 b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
260 b43_phy_write(dev, B43_PHY_CRS0,
261 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
262}
263
264static void hardware_pctl_init_aphy(struct b43_wldev *dev)
265{
266 //TODO
267}
268
269void b43_phy_inita(struct b43_wldev *dev)
270{
271 struct ssb_bus *bus = dev->dev->bus;
272 struct b43_phy *phy = &dev->phy;
273
274 /* This lowlevel A-PHY init is also called from G-PHY init.
275 * So we must not access phy->a, if called from G-PHY code.
276 */
277 B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
278 (phy->type != B43_PHYTYPE_G));
279
280 might_sleep();
281
282 if (phy->rev >= 6) {
283 if (phy->type == B43_PHYTYPE_A)
284 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
285 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x1000);
286 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
287 b43_phy_write(dev, B43_PHY_ENCORE,
288 b43_phy_read(dev, B43_PHY_ENCORE) | 0x0010);
289 else
290 b43_phy_write(dev, B43_PHY_ENCORE,
291 b43_phy_read(dev, B43_PHY_ENCORE) & ~0x1010);
292 }
293
294 b43_wa_all(dev);
295
296 if (phy->type == B43_PHYTYPE_A) {
297 if (phy->gmode && (phy->rev < 3))
298 b43_phy_write(dev, 0x0034,
299 b43_phy_read(dev, 0x0034) | 0x0001);
300 b43_phy_rssiagc(dev, 0);
301
302 b43_phy_write(dev, B43_PHY_CRS0,
303 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
304
305 b43_radio_init2060(dev);
306
307 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
308 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
309 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
310 ; //TODO: A PHY LO
311 }
312
313 if (phy->rev >= 3)
314 b43_phy_ww(dev);
315
316 hardware_pctl_init_aphy(dev);
317
318 //TODO: radar detection
319 }
320
321 if ((phy->type == B43_PHYTYPE_G) &&
322 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
323 b43_phy_write(dev, B43_PHY_OFDM(0x6E),
324 (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
325 & 0xE000) | 0x3CF);
326 }
327}
328
329static int b43_aphy_op_allocate(struct b43_wldev *dev)
330{
331 struct b43_phy_a *aphy;
332
333 aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
334 if (!aphy)
335 return -ENOMEM;
336 dev->phy.a = aphy;
337
338 //TODO init struct b43_phy_a
339
340 return 0;
341}
342
343static int b43_aphy_op_init(struct b43_wldev *dev)
344{
345 struct b43_phy_a *aphy = dev->phy.a;
346
347 b43_phy_inita(dev);
348 aphy->initialised = 1;
349
350 return 0;
351}
352
353static void b43_aphy_op_exit(struct b43_wldev *dev)
354{
355 struct b43_phy_a *aphy = dev->phy.a;
356
357 if (aphy->initialised) {
358 //TODO
359 aphy->initialised = 0;
360 }
361 //TODO
362 kfree(aphy);
363 dev->phy.a = NULL;
364}
365
366static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
367{
368 /* OFDM registers are base-registers for the A-PHY. */
369 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
370 offset &= ~B43_PHYROUTE;
371 offset |= B43_PHYROUTE_BASE;
372 }
373
374#if B43_DEBUG
375 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
376 /* Ext-G registers are only available on G-PHYs */
377 b43err(dev->wl, "Invalid EXT-G PHY access at "
378 "0x%04X on A-PHY\n", offset);
379 dump_stack();
380 }
381 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
382 /* N-BMODE registers are only available on N-PHYs */
383 b43err(dev->wl, "Invalid N-BMODE PHY access at "
384 "0x%04X on A-PHY\n", offset);
385 dump_stack();
386 }
387#endif /* B43_DEBUG */
388
389 return offset;
390}
391
392static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
393{
394 reg = adjust_phyreg(dev, reg);
395 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
396 return b43_read16(dev, B43_MMIO_PHY_DATA);
397}
398
399static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
400{
401 reg = adjust_phyreg(dev, reg);
402 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
403 b43_write16(dev, B43_MMIO_PHY_DATA, value);
404}
405
406static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
407{
408 /* Register 1 is a 32-bit register. */
409 B43_WARN_ON(reg == 1);
410 /* A-PHY needs 0x40 for read access */
411 reg |= 0x40;
412
413 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
414 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
415}
416
417static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
418{
419 /* Register 1 is a 32-bit register. */
420 B43_WARN_ON(reg == 1);
421
422 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
423 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
424}
425
426static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
427{
428 return (dev->phy.rev >= 5);
429}
430
431static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
432 enum rfkill_state state)
433{//TODO
434}
435
436static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
437 unsigned int new_channel)
438{
439 if (new_channel > 200)
440 return -EINVAL;
441 aphy_channel_switch(dev, new_channel);
442
443 return 0;
444}
445
446static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
447{
448 return 36; /* Default to channel 36 */
449}
450
451static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
452{//TODO
453 struct b43_phy *phy = &dev->phy;
454 u64 hf;
455 u16 tmp;
456 int autodiv = 0;
457
458 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
459 autodiv = 1;
460
461 hf = b43_hf_read(dev);
462 hf &= ~B43_HF_ANTDIVHELP;
463 b43_hf_write(dev, hf);
464
465 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
466 tmp &= ~B43_PHY_BBANDCFG_RXANT;
467 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
468 << B43_PHY_BBANDCFG_RXANT_SHIFT;
469 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
470
471 if (autodiv) {
472 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
473 if (antenna == B43_ANTENNA_AUTO0)
474 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
475 else
476 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
477 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
478 }
479 if (phy->rev < 3) {
480 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
481 tmp = (tmp & 0xFF00) | 0x24;
482 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
483 } else {
484 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
485 tmp |= 0x10;
486 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
487 if (phy->analog == 3) {
488 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
489 0x1D);
490 b43_phy_write(dev, B43_PHY_ADIVRELATED,
491 8);
492 } else {
493 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
494 0x3A);
495 tmp =
496 b43_phy_read(dev,
497 B43_PHY_ADIVRELATED);
498 tmp = (tmp & 0xFF00) | 8;
499 b43_phy_write(dev, B43_PHY_ADIVRELATED,
500 tmp);
501 }
502 }
503
504 hf |= B43_HF_ANTDIVHELP;
505 b43_hf_write(dev, hf);
506}
507
508static void b43_aphy_op_xmitpower(struct b43_wldev *dev)
509{//TODO
510}
511
512static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
513{//TODO
514}
515
516static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
517{//TODO
518}
519
520const struct b43_phy_operations b43_phyops_a = {
521 .allocate = b43_aphy_op_allocate,
522 .init = b43_aphy_op_init,
523 .exit = b43_aphy_op_exit,
524 .phy_read = b43_aphy_op_read,
525 .phy_write = b43_aphy_op_write,
526 .radio_read = b43_aphy_op_radio_read,
527 .radio_write = b43_aphy_op_radio_write,
528 .supports_hwpctl = b43_aphy_op_supports_hwpctl,
529 .software_rfkill = b43_aphy_op_software_rfkill,
530 .switch_channel = b43_aphy_op_switch_channel,
531 .get_default_chan = b43_aphy_op_get_default_chan,
532 .set_rx_antenna = b43_aphy_op_set_rx_antenna,
533 .xmitpower = b43_aphy_op_xmitpower,
534 .pwork_15sec = b43_aphy_op_pwork_15sec,
535 .pwork_60sec = b43_aphy_op_pwork_60sec,
536};
diff --git a/drivers/net/wireless/b43/phy_a.h b/drivers/net/wireless/b43/phy_a.h
new file mode 100644
index 000000000000..e8640f7312bf
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_a.h
@@ -0,0 +1,124 @@
1#ifndef LINUX_B43_PHY_A_H_
2#define LINUX_B43_PHY_A_H_
3
4#include "phy_common.h"
5
6
7/* OFDM (A) PHY Registers */
8#define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
9#define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
10#define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
11#define B43_PHY_BBANDCFG_RXANT_SHIFT 7
12#define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
13#define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
14#define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
15#define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
16#define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
17#define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
18#define B43_PHY_CRS0_EN 0x4000
19#define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
20#define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
21#define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
22#define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
23#define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */
24#define B43_PHY_LMS B43_PHY_OFDM(0x55)
25#define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
26#define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */
27#define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
28#define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
29#define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
30#define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
31#define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
32#define B43_PHY_OTABLENR_SHIFT 10
33#define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
34#define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
35#define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
36#define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
37#define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
38#define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
39#define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
40#define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
41#define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
42#define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
43#define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */
44#define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0)
45#define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1)
46#define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
47#define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
48#define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
49#define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
50#define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
51#define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
52#define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
53#define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
54#define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB)
55#define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
56#define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
57#define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
58#define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
59#define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */
60#define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */
61#define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
62
63/*** OFDM table numbers ***/
64#define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
65#define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0)
66#define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0)
67#define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename
68#define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4)
69#define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0)
70#define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3)
71#define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0)
72#define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0)
73#define B43_OFDMTAB_LNAHPFGAIN2 B43_OFDMTAB(0x04, 0)
74#define B43_OFDMTAB_NOISESCALE B43_OFDMTAB(0x05, 0)
75#define B43_OFDMTAB_AGC2 B43_OFDMTAB(0x06, 0)
76#define B43_OFDMTAB_ROTOR B43_OFDMTAB(0x08, 0)
77#define B43_OFDMTAB_ADVRETARD B43_OFDMTAB(0x09, 0)
78#define B43_OFDMTAB_DAC B43_OFDMTAB(0x0C, 0)
79#define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7)
80#define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12)
81#define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13)
82#define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename
83#define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename
84#define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12)
85#define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0)
86#define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename
87#define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0)
88#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove!
89#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0)
90#define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0)
91#define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4)
92#define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0)
93#define B43_OFDMTAB_DACRFPABB B43_OFDMTAB(0x16, 0)
94#define B43_OFDMTAB_DACOFF B43_OFDMTAB(0x17, 0)
95#define B43_OFDMTAB_DCBIAS B43_OFDMTAB(0x18, 0)
96
97u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
98void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
99 u16 offset, u16 value);
100u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
101void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
102 u16 offset, u32 value);
103
104
105struct b43_phy_a {
106 bool initialised;
107
108 /* A-PHY TX Power control value. */
109 u16 txpwr_offset;
110
111 //TODO lots of missing stuff
112};
113
114/**
115 * b43_phy_inita - Lowlevel A-PHY init routine.
116 * This is _only_ used by the G-PHY code.
117 */
118void b43_phy_inita(struct b43_wldev *dev);
119
120
121struct b43_phy_operations;
122extern const struct b43_phy_operations b43_phyops_a;
123
124#endif /* LINUX_B43_PHY_A_H_ */
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
new file mode 100644
index 000000000000..45074c05d51d
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -0,0 +1,276 @@
1/*
2
3 Broadcom B43 wireless driver
4 Common PHY routines
5
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
26
27*/
28
29#include "phy_common.h"
30#include "phy_g.h"
31#include "phy_a.h"
32#include "nphy.h"
33#include "b43.h"
34#include "main.h"
35
36
37int b43_phy_operations_setup(struct b43_wldev *dev)
38{
39 struct b43_phy *phy = &(dev->phy);
40 int err;
41
42 phy->ops = NULL;
43
44 switch (phy->type) {
45 case B43_PHYTYPE_A:
46 phy->ops = &b43_phyops_a;
47 break;
48 case B43_PHYTYPE_G:
49 phy->ops = &b43_phyops_g;
50 break;
51 case B43_PHYTYPE_N:
52#ifdef CONFIG_B43_NPHY
53 phy->ops = &b43_phyops_n;
54#endif
55 break;
56 case B43_PHYTYPE_LP:
57 /* FIXME: Not yet */
58 break;
59 }
60 if (B43_WARN_ON(!phy->ops))
61 return -ENODEV;
62
63 err = phy->ops->allocate(dev);
64 if (err)
65 phy->ops = NULL;
66
67 return err;
68}
69
70int b43_phy_init(struct b43_wldev *dev)
71{
72 struct b43_phy *phy = &dev->phy;
73 const struct b43_phy_operations *ops = phy->ops;
74 int err;
75
76 phy->channel = ops->get_default_chan(dev);
77
78 ops->software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
79 err = ops->init(dev);
80 if (err) {
81 b43err(dev->wl, "PHY init failed\n");
82 goto err_block_rf;
83 }
84 /* Make sure to switch hardware and firmware (SHM) to
85 * the default channel. */
86 err = b43_switch_channel(dev, ops->get_default_chan(dev));
87 if (err) {
88 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
89 goto err_phy_exit;
90 }
91
92 return 0;
93
94err_phy_exit:
95 if (ops->exit)
96 ops->exit(dev);
97err_block_rf:
98 ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
99
100 return err;
101}
102
103void b43_phy_exit(struct b43_wldev *dev)
104{
105 const struct b43_phy_operations *ops = dev->phy.ops;
106
107 ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
108 if (ops->exit)
109 ops->exit(dev);
110}
111
112bool b43_has_hardware_pctl(struct b43_wldev *dev)
113{
114 if (!dev->phy.hardware_power_control)
115 return 0;
116 if (!dev->phy.ops->supports_hwpctl)
117 return 0;
118 return dev->phy.ops->supports_hwpctl(dev);
119}
120
121void b43_radio_lock(struct b43_wldev *dev)
122{
123 u32 macctl;
124
125 macctl = b43_read32(dev, B43_MMIO_MACCTL);
126 B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
127 macctl |= B43_MACCTL_RADIOLOCK;
128 b43_write32(dev, B43_MMIO_MACCTL, macctl);
129 /* Commit the write and wait for the device
130 * to exit any radio register access. */
131 b43_read32(dev, B43_MMIO_MACCTL);
132 udelay(10);
133}
134
135void b43_radio_unlock(struct b43_wldev *dev)
136{
137 u32 macctl;
138
139 /* Commit any write */
140 b43_read16(dev, B43_MMIO_PHY_VER);
141 /* unlock */
142 macctl = b43_read32(dev, B43_MMIO_MACCTL);
143 B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
144 macctl &= ~B43_MACCTL_RADIOLOCK;
145 b43_write32(dev, B43_MMIO_MACCTL, macctl);
146}
147
148void b43_phy_lock(struct b43_wldev *dev)
149{
150#if B43_DEBUG
151 B43_WARN_ON(dev->phy.phy_locked);
152 dev->phy.phy_locked = 1;
153#endif
154 B43_WARN_ON(dev->dev->id.revision < 3);
155
156 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
157 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
158}
159
160void b43_phy_unlock(struct b43_wldev *dev)
161{
162#if B43_DEBUG
163 B43_WARN_ON(!dev->phy.phy_locked);
164 dev->phy.phy_locked = 0;
165#endif
166 B43_WARN_ON(dev->dev->id.revision < 3);
167
168 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
169 b43_power_saving_ctl_bits(dev, 0);
170}
171
172u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
173{
174 return dev->phy.ops->radio_read(dev, reg);
175}
176
177void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
178{
179 dev->phy.ops->radio_write(dev, reg, value);
180}
181
182void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
183{
184 b43_radio_write16(dev, offset,
185 b43_radio_read16(dev, offset) & mask);
186}
187
188void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
189{
190 b43_radio_write16(dev, offset,
191 b43_radio_read16(dev, offset) | set);
192}
193
194void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
195{
196 b43_radio_write16(dev, offset,
197 (b43_radio_read16(dev, offset) & mask) | set);
198}
199
200u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
201{
202 return dev->phy.ops->phy_read(dev, reg);
203}
204
205void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
206{
207 dev->phy.ops->phy_write(dev, reg, value);
208}
209
210void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
211{
212 b43_phy_write(dev, offset,
213 b43_phy_read(dev, offset) & mask);
214}
215
216void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
217{
218 b43_phy_write(dev, offset,
219 b43_phy_read(dev, offset) | set);
220}
221
222void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
223{
224 b43_phy_write(dev, offset,
225 (b43_phy_read(dev, offset) & mask) | set);
226}
227
228int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
229{
230 struct b43_phy *phy = &(dev->phy);
231 u16 channelcookie, savedcookie;
232 int err;
233
234 if (new_channel == B43_DEFAULT_CHANNEL)
235 new_channel = phy->ops->get_default_chan(dev);
236
237 /* First we set the channel radio code to prevent the
238 * firmware from sending ghost packets.
239 */
240 channelcookie = new_channel;
241 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
242 channelcookie |= 0x100;
243 //FIXME set 40Mhz flag if required
244 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
245 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
246
247 /* Now try to switch the PHY hardware channel. */
248 err = phy->ops->switch_channel(dev, new_channel);
249 if (err)
250 goto err_restore_cookie;
251
252 dev->phy.channel = new_channel;
253 /* Wait for the radio to tune to the channel and stabilize. */
254 msleep(8);
255
256 return 0;
257
258err_restore_cookie:
259 b43_shm_write16(dev, B43_SHM_SHARED,
260 B43_SHM_SH_CHAN, savedcookie);
261
262 return err;
263}
264
265void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state)
266{
267 struct b43_phy *phy = &dev->phy;
268
269 if (state == RFKILL_STATE_HARD_BLOCKED) {
270 /* We cannot hardware-block the device */
271 state = RFKILL_STATE_SOFT_BLOCKED;
272 }
273
274 phy->ops->software_rfkill(dev, state);
275 phy->radio_on = (state == RFKILL_STATE_UNBLOCKED);
276}
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
new file mode 100644
index 000000000000..9b9635eda9c4
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -0,0 +1,312 @@
1#ifndef LINUX_B43_PHY_COMMON_H_
2#define LINUX_B43_PHY_COMMON_H_
3
4#include <linux/rfkill.h>
5
6struct b43_wldev;
7
8
9/* PHY register routing bits */
10#define B43_PHYROUTE 0x0C00 /* PHY register routing bits mask */
11#define B43_PHYROUTE_BASE 0x0000 /* Base registers */
12#define B43_PHYROUTE_OFDM_GPHY 0x0400 /* OFDM register routing for G-PHYs */
13#define B43_PHYROUTE_EXT_GPHY 0x0800 /* Extended G-PHY registers */
14#define B43_PHYROUTE_N_BMODE 0x0C00 /* N-PHY BMODE registers */
15
16/* CCK (B-PHY) registers. */
17#define B43_PHY_CCK(reg) ((reg) | B43_PHYROUTE_BASE)
18/* N-PHY registers. */
19#define B43_PHY_N(reg) ((reg) | B43_PHYROUTE_BASE)
20/* N-PHY BMODE registers. */
21#define B43_PHY_N_BMODE(reg) ((reg) | B43_PHYROUTE_N_BMODE)
22/* OFDM (A-PHY) registers. */
23#define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
24/* Extended G-PHY registers. */
25#define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
26
27
28/* Masks for the PHY versioning registers. */
29#define B43_PHYVER_ANALOG 0xF000
30#define B43_PHYVER_ANALOG_SHIFT 12
31#define B43_PHYVER_TYPE 0x0F00
32#define B43_PHYVER_TYPE_SHIFT 8
33#define B43_PHYVER_VERSION 0x00FF
34
35/**
36 * enum b43_interference_mitigation - Interference Mitigation mode
37 *
38 * @B43_INTERFMODE_NONE: Disabled
39 * @B43_INTERFMODE_NONWLAN: Non-WLAN Interference Mitigation
40 * @B43_INTERFMODE_MANUALWLAN: WLAN Interference Mitigation
41 * @B43_INTERFMODE_AUTOWLAN: Automatic WLAN Interference Mitigation
42 */
43enum b43_interference_mitigation {
44 B43_INTERFMODE_NONE,
45 B43_INTERFMODE_NONWLAN,
46 B43_INTERFMODE_MANUALWLAN,
47 B43_INTERFMODE_AUTOWLAN,
48};
49
50/* Antenna identifiers */
51enum {
52 B43_ANTENNA0, /* Antenna 0 */
53 B43_ANTENNA1, /* Antenna 0 */
54 B43_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
55 B43_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
56 B43_ANTENNA2,
57 B43_ANTENNA3 = 8,
58
59 B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
60 B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
61};
62
63/**
64 * struct b43_phy_operations - Function pointers for PHY ops.
65 *
66 * @prepare: Prepare the PHY. This is called before @init.
67 * Can be NULL, if not required.
68 * @init: Initialize the PHY.
69 * Must not be NULL.
70 * @exit: Shutdown the PHY and free all data structures.
71 * Can be NULL, if not required.
72 *
73 * @phy_read: Read from a PHY register.
74 * Must not be NULL.
75 * @phy_write: Write to a PHY register.
76 * Must not be NULL.
77 * @radio_read: Read from a Radio register.
78 * Must not be NULL.
79 * @radio_write: Write to a Radio register.
80 * Must not be NULL.
81 *
82 * @supports_hwpctl: Returns a boolean whether Hardware Power Control
83 * is supported or not.
84 * If NULL, hwpctl is assumed to be never supported.
85 * @software_rfkill: Turn the radio ON or OFF.
86 * Possible state values are
87 * RFKILL_STATE_SOFT_BLOCKED or
88 * RFKILL_STATE_UNBLOCKED
89 * Must not be NULL.
90 * @switch_channel: Switch the radio to another channel.
91 * Must not be NULL.
92 * @get_default_chan: Just returns the default channel number.
93 * Must not be NULL.
94 * @set_rx_antenna: Set the antenna used for RX.
95 * Can be NULL, if not supported.
96 * @interf_mitigation: Switch the Interference Mitigation mode.
97 * Can be NULL, if not supported.
98 *
99 * @xmitpower: FIXME REMOVEME
100 * Must not be NULL.
101 *
102 * @pwork_15sec: Periodic work. Called every 15 seconds.
103 * Can be NULL, if not required.
104 * @pwork_60sec: Periodic work. Called every 60 seconds.
105 * Can be NULL, if not required.
106 */
107struct b43_phy_operations {
108 /* Initialisation */
109 int (*allocate)(struct b43_wldev *dev);
110 int (*prepare)(struct b43_wldev *dev);
111 int (*init)(struct b43_wldev *dev);
112 void (*exit)(struct b43_wldev *dev);
113
114 /* Register access */
115 u16 (*phy_read)(struct b43_wldev *dev, u16 reg);
116 void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value);
117 u16 (*radio_read)(struct b43_wldev *dev, u16 reg);
118 void (*radio_write)(struct b43_wldev *dev, u16 reg, u16 value);
119
120 /* Radio */
121 bool (*supports_hwpctl)(struct b43_wldev *dev);
122 void (*software_rfkill)(struct b43_wldev *dev, enum rfkill_state state);
123 int (*switch_channel)(struct b43_wldev *dev, unsigned int new_channel);
124 unsigned int (*get_default_chan)(struct b43_wldev *dev);
125 void (*set_rx_antenna)(struct b43_wldev *dev, int antenna);
126 int (*interf_mitigation)(struct b43_wldev *dev,
127 enum b43_interference_mitigation new_mode);
128
129 /* Transmission power adjustment */
130 void (*xmitpower)(struct b43_wldev *dev);
131
132 /* Misc */
133 void (*pwork_15sec)(struct b43_wldev *dev);
134 void (*pwork_60sec)(struct b43_wldev *dev);
135};
136
137struct b43_phy_a;
138struct b43_phy_g;
139struct b43_phy_n;
140
141struct b43_phy {
142 /* Hardware operation callbacks. */
143 const struct b43_phy_operations *ops;
144
145 /* Most hardware context information is stored in the standard-
146 * specific data structures pointed to by the pointers below.
147 * Only one of them is valid (the currently enabled PHY). */
148#ifdef CONFIG_B43_DEBUG
149 /* No union for debug build to force NULL derefs in buggy code. */
150 struct {
151#else
152 union {
153#endif
154 /* A-PHY specific information */
155 struct b43_phy_a *a;
156 /* G-PHY specific information */
157 struct b43_phy_g *g;
158 /* N-PHY specific information */
159 struct b43_phy_n *n;
160 };
161
162 /* Band support flags. */
163 bool supports_2ghz;
164 bool supports_5ghz;
165
166 /* GMODE bit enabled? */
167 bool gmode;
168
169 /* Analog Type */
170 u8 analog;
171 /* B43_PHYTYPE_ */
172 u8 type;
173 /* PHY revision number. */
174 u8 rev;
175
176 /* Radio versioning */
177 u16 radio_manuf; /* Radio manufacturer */
178 u16 radio_ver; /* Radio version */
179 u8 radio_rev; /* Radio revision */
180
181 /* Software state of the radio */
182 bool radio_on;
183
184 /* Desired TX power level (in dBm).
185 * This is set by the user and adjusted in b43_phy_xmitpower(). */
186 u8 power_level;
187
188 /* Hardware Power Control enabled? */
189 bool hardware_power_control;
190
191 /* current channel */
192 unsigned int channel;
193
194 /* PHY TX errors counter. */
195 atomic_t txerr_cnt;
196
197#ifdef CONFIG_B43_DEBUG
198 /* PHY registers locked by b43_phy_lock()? */
199 bool phy_locked;
200#endif /* B43_DEBUG */
201};
202
203
204/**
205 * b43_phy_operations_setup - Initialize the PHY operations datastructure
206 * based on the current PHY type.
207 */
208int b43_phy_operations_setup(struct b43_wldev *dev);
209
210/**
211 * b43_phy_init - Initialise the PHY
212 */
213int b43_phy_init(struct b43_wldev *dev);
214
215/**
216 * b43_phy_exit - Cleanup PHY
217 */
218void b43_phy_exit(struct b43_wldev *dev);
219
220/**
221 * b43_has_hardware_pctl - Hardware Power Control supported?
222 * Returns a boolean, whether hardware power control is supported.
223 */
224bool b43_has_hardware_pctl(struct b43_wldev *dev);
225
226/**
227 * b43_phy_read - 16bit PHY register read access
228 */
229u16 b43_phy_read(struct b43_wldev *dev, u16 reg);
230
231/**
232 * b43_phy_write - 16bit PHY register write access
233 */
234void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value);
235
236/**
237 * b43_phy_mask - Mask a PHY register with a mask
238 */
239void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
240
241/**
242 * b43_phy_set - OR a PHY register with a bitmap
243 */
244void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set);
245
246/**
247 * b43_phy_maskset - Mask and OR a PHY register with a mask and bitmap
248 */
249void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
250
251/**
252 * b43_radio_read - 16bit Radio register read access
253 */
254u16 b43_radio_read(struct b43_wldev *dev, u16 reg);
255#define b43_radio_read16 b43_radio_read /* DEPRECATED */
256
257/**
258 * b43_radio_write - 16bit Radio register write access
259 */
260void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value);
261#define b43_radio_write16 b43_radio_write /* DEPRECATED */
262
263/**
264 * b43_radio_mask - Mask a 16bit radio register with a mask
265 */
266void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask);
267
268/**
269 * b43_radio_set - OR a 16bit radio register with a bitmap
270 */
271void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set);
272
273/**
274 * b43_radio_maskset - Mask and OR a radio register with a mask and bitmap
275 */
276void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set);
277
278/**
279 * b43_radio_lock - Lock firmware radio register access
280 */
281void b43_radio_lock(struct b43_wldev *dev);
282
283/**
284 * b43_radio_unlock - Unlock firmware radio register access
285 */
286void b43_radio_unlock(struct b43_wldev *dev);
287
288/**
289 * b43_phy_lock - Lock firmware PHY register access
290 */
291void b43_phy_lock(struct b43_wldev *dev);
292
293/**
294 * b43_phy_unlock - Unlock firmware PHY register access
295 */
296void b43_phy_unlock(struct b43_wldev *dev);
297
298/**
299 * b43_switch_channel - Switch to another channel
300 */
301int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel);
302/**
303 * B43_DEFAULT_CHANNEL - Switch to the default channel.
304 */
305#define B43_DEFAULT_CHANNEL UINT_MAX
306
307/**
308 * b43_software_rfkill - Turn the radio ON or OFF in software.
309 */
310void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state);
311
312#endif /* LINUX_B43_PHY_COMMON_H_ */
diff --git a/drivers/net/wireless/b43/phy_g.c b/drivers/net/wireless/b43/phy_g.c
new file mode 100644
index 000000000000..bb95c54cd43d
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_g.c
@@ -0,0 +1,3229 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g PHY driver
5
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
26
27*/
28
29#include "b43.h"
30#include "phy_g.h"
31#include "phy_common.h"
32#include "lo.h"
33#include "main.h"
34
35#include <linux/bitrev.h>
36
37
38static const s8 b43_tssi2dbm_g_table[] = {
39 77, 77, 77, 76,
40 76, 76, 75, 75,
41 74, 74, 73, 73,
42 73, 72, 72, 71,
43 71, 70, 70, 69,
44 68, 68, 67, 67,
45 66, 65, 65, 64,
46 63, 63, 62, 61,
47 60, 59, 58, 57,
48 56, 55, 54, 53,
49 52, 50, 49, 47,
50 45, 43, 40, 37,
51 33, 28, 22, 14,
52 5, -7, -20, -20,
53 -20, -20, -20, -20,
54 -20, -20, -20, -20,
55};
56
57const u8 b43_radio_channel_codes_bg[] = {
58 12, 17, 22, 27,
59 32, 37, 42, 47,
60 52, 57, 62, 67,
61 72, 84,
62};
63
64
65static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
66
67
68#define bitrev4(tmp) (bitrev8(tmp) >> 4)
69
70
71/* Get the freq, as it has to be written to the device. */
72static inline u16 channel2freq_bg(u8 channel)
73{
74 B43_WARN_ON(!(channel >= 1 && channel <= 14));
75
76 return b43_radio_channel_codes_bg[channel - 1];
77}
78
79static void generate_rfatt_list(struct b43_wldev *dev,
80 struct b43_rfatt_list *list)
81{
82 struct b43_phy *phy = &dev->phy;
83
84 /* APHY.rev < 5 || GPHY.rev < 6 */
85 static const struct b43_rfatt rfatt_0[] = {
86 {.att = 3,.with_padmix = 0,},
87 {.att = 1,.with_padmix = 0,},
88 {.att = 5,.with_padmix = 0,},
89 {.att = 7,.with_padmix = 0,},
90 {.att = 9,.with_padmix = 0,},
91 {.att = 2,.with_padmix = 0,},
92 {.att = 0,.with_padmix = 0,},
93 {.att = 4,.with_padmix = 0,},
94 {.att = 6,.with_padmix = 0,},
95 {.att = 8,.with_padmix = 0,},
96 {.att = 1,.with_padmix = 1,},
97 {.att = 2,.with_padmix = 1,},
98 {.att = 3,.with_padmix = 1,},
99 {.att = 4,.with_padmix = 1,},
100 };
101 /* Radio.rev == 8 && Radio.version == 0x2050 */
102 static const struct b43_rfatt rfatt_1[] = {
103 {.att = 2,.with_padmix = 1,},
104 {.att = 4,.with_padmix = 1,},
105 {.att = 6,.with_padmix = 1,},
106 {.att = 8,.with_padmix = 1,},
107 {.att = 10,.with_padmix = 1,},
108 {.att = 12,.with_padmix = 1,},
109 {.att = 14,.with_padmix = 1,},
110 };
111 /* Otherwise */
112 static const struct b43_rfatt rfatt_2[] = {
113 {.att = 0,.with_padmix = 1,},
114 {.att = 2,.with_padmix = 1,},
115 {.att = 4,.with_padmix = 1,},
116 {.att = 6,.with_padmix = 1,},
117 {.att = 8,.with_padmix = 1,},
118 {.att = 9,.with_padmix = 1,},
119 {.att = 9,.with_padmix = 1,},
120 };
121
122 if (!b43_has_hardware_pctl(dev)) {
123 /* Software pctl */
124 list->list = rfatt_0;
125 list->len = ARRAY_SIZE(rfatt_0);
126 list->min_val = 0;
127 list->max_val = 9;
128 return;
129 }
130 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
131 /* Hardware pctl */
132 list->list = rfatt_1;
133 list->len = ARRAY_SIZE(rfatt_1);
134 list->min_val = 0;
135 list->max_val = 14;
136 return;
137 }
138 /* Hardware pctl */
139 list->list = rfatt_2;
140 list->len = ARRAY_SIZE(rfatt_2);
141 list->min_val = 0;
142 list->max_val = 9;
143}
144
145static void generate_bbatt_list(struct b43_wldev *dev,
146 struct b43_bbatt_list *list)
147{
148 static const struct b43_bbatt bbatt_0[] = {
149 {.att = 0,},
150 {.att = 1,},
151 {.att = 2,},
152 {.att = 3,},
153 {.att = 4,},
154 {.att = 5,},
155 {.att = 6,},
156 {.att = 7,},
157 {.att = 8,},
158 };
159
160 list->list = bbatt_0;
161 list->len = ARRAY_SIZE(bbatt_0);
162 list->min_val = 0;
163 list->max_val = 8;
164}
165
166static void b43_shm_clear_tssi(struct b43_wldev *dev)
167{
168 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
169 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
170 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
171 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
172}
173
174/* Synthetic PU workaround */
175static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
176{
177 struct b43_phy *phy = &dev->phy;
178
179 might_sleep();
180
181 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
182 /* We do not need the workaround. */
183 return;
184 }
185
186 if (channel <= 10) {
187 b43_write16(dev, B43_MMIO_CHANNEL,
188 channel2freq_bg(channel + 4));
189 } else {
190 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
191 }
192 msleep(1);
193 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
194}
195
196/* Set the baseband attenuation value on chip. */
197void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
198 u16 baseband_attenuation)
199{
200 struct b43_phy *phy = &dev->phy;
201
202 if (phy->analog == 0) {
203 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
204 & 0xFFF0) |
205 baseband_attenuation);
206 } else if (phy->analog > 1) {
207 b43_phy_write(dev, B43_PHY_DACCTL,
208 (b43_phy_read(dev, B43_PHY_DACCTL)
209 & 0xFFC3) | (baseband_attenuation << 2));
210 } else {
211 b43_phy_write(dev, B43_PHY_DACCTL,
212 (b43_phy_read(dev, B43_PHY_DACCTL)
213 & 0xFF87) | (baseband_attenuation << 3));
214 }
215}
216
217/* Adjust the transmission power output (G-PHY) */
218void b43_set_txpower_g(struct b43_wldev *dev,
219 const struct b43_bbatt *bbatt,
220 const struct b43_rfatt *rfatt, u8 tx_control)
221{
222 struct b43_phy *phy = &dev->phy;
223 struct b43_phy_g *gphy = phy->g;
224 struct b43_txpower_lo_control *lo = gphy->lo_control;
225 u16 bb, rf;
226 u16 tx_bias, tx_magn;
227
228 bb = bbatt->att;
229 rf = rfatt->att;
230 tx_bias = lo->tx_bias;
231 tx_magn = lo->tx_magn;
232 if (unlikely(tx_bias == 0xFF))
233 tx_bias = 0;
234
235 /* Save the values for later */
236 gphy->tx_control = tx_control;
237 memcpy(&gphy->rfatt, rfatt, sizeof(*rfatt));
238 gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
239 memcpy(&gphy->bbatt, bbatt, sizeof(*bbatt));
240
241 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
242 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
243 "rfatt(%u), tx_control(0x%02X), "
244 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
245 bb, rf, tx_control, tx_bias, tx_magn);
246 }
247
248 b43_gphy_set_baseband_attenuation(dev, bb);
249 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
250 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
251 b43_radio_write16(dev, 0x43,
252 (rf & 0x000F) | (tx_control & 0x0070));
253 } else {
254 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
255 & 0xFFF0) | (rf & 0x000F));
256 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
257 & ~0x0070) | (tx_control &
258 0x0070));
259 }
260 if (has_tx_magnification(phy)) {
261 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
262 } else {
263 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
264 & 0xFFF0) | (tx_bias & 0x000F));
265 }
266 b43_lo_g_adjust(dev);
267}
268
269/* GPHY_TSSI_Power_Lookup_Table_Init */
270static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
271{
272 struct b43_phy_g *gphy = dev->phy.g;
273 int i;
274 u16 value;
275
276 for (i = 0; i < 32; i++)
277 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
278 for (i = 32; i < 64; i++)
279 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
280 for (i = 0; i < 64; i += 2) {
281 value = (u16) gphy->tssi2dbm[i];
282 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
283 b43_phy_write(dev, 0x380 + (i / 2), value);
284 }
285}
286
287/* GPHY_Gain_Lookup_Table_Init */
288static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
289{
290 struct b43_phy *phy = &dev->phy;
291 struct b43_phy_g *gphy = phy->g;
292 struct b43_txpower_lo_control *lo = gphy->lo_control;
293 u16 nr_written = 0;
294 u16 tmp;
295 u8 rf, bb;
296
297 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
298 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
299 if (nr_written >= 0x40)
300 return;
301 tmp = lo->bbatt_list.list[bb].att;
302 tmp <<= 8;
303 if (phy->radio_rev == 8)
304 tmp |= 0x50;
305 else
306 tmp |= 0x40;
307 tmp |= lo->rfatt_list.list[rf].att;
308 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
309 nr_written++;
310 }
311 }
312}
313
314static void b43_set_all_gains(struct b43_wldev *dev,
315 s16 first, s16 second, s16 third)
316{
317 struct b43_phy *phy = &dev->phy;
318 u16 i;
319 u16 start = 0x08, end = 0x18;
320 u16 tmp;
321 u16 table;
322
323 if (phy->rev <= 1) {
324 start = 0x10;
325 end = 0x20;
326 }
327
328 table = B43_OFDMTAB_GAINX;
329 if (phy->rev <= 1)
330 table = B43_OFDMTAB_GAINX_R1;
331 for (i = 0; i < 4; i++)
332 b43_ofdmtab_write16(dev, table, i, first);
333
334 for (i = start; i < end; i++)
335 b43_ofdmtab_write16(dev, table, i, second);
336
337 if (third != -1) {
338 tmp = ((u16) third << 14) | ((u16) third << 6);
339 b43_phy_write(dev, 0x04A0,
340 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
341 b43_phy_write(dev, 0x04A1,
342 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
343 b43_phy_write(dev, 0x04A2,
344 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
345 }
346 b43_dummy_transmission(dev);
347}
348
349static void b43_set_original_gains(struct b43_wldev *dev)
350{
351 struct b43_phy *phy = &dev->phy;
352 u16 i, tmp;
353 u16 table;
354 u16 start = 0x0008, end = 0x0018;
355
356 if (phy->rev <= 1) {
357 start = 0x0010;
358 end = 0x0020;
359 }
360
361 table = B43_OFDMTAB_GAINX;
362 if (phy->rev <= 1)
363 table = B43_OFDMTAB_GAINX_R1;
364 for (i = 0; i < 4; i++) {
365 tmp = (i & 0xFFFC);
366 tmp |= (i & 0x0001) << 1;
367 tmp |= (i & 0x0002) >> 1;
368
369 b43_ofdmtab_write16(dev, table, i, tmp);
370 }
371
372 for (i = start; i < end; i++)
373 b43_ofdmtab_write16(dev, table, i, i - start);
374
375 b43_phy_write(dev, 0x04A0,
376 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
377 b43_phy_write(dev, 0x04A1,
378 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
379 b43_phy_write(dev, 0x04A2,
380 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
381 b43_dummy_transmission(dev);
382}
383
384/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
385void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
386{
387 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
388 mmiowb();
389 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
390}
391
392/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
393s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
394{
395 u16 val;
396
397 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
398 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
399
400 return (s16) val;
401}
402
403/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
404void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
405{
406 u16 i;
407 s16 tmp;
408
409 for (i = 0; i < 64; i++) {
410 tmp = b43_nrssi_hw_read(dev, i);
411 tmp -= val;
412 tmp = clamp_val(tmp, -32, 31);
413 b43_nrssi_hw_write(dev, i, tmp);
414 }
415}
416
417/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
418void b43_nrssi_mem_update(struct b43_wldev *dev)
419{
420 struct b43_phy_g *gphy = dev->phy.g;
421 s16 i, delta;
422 s32 tmp;
423
424 delta = 0x1F - gphy->nrssi[0];
425 for (i = 0; i < 64; i++) {
426 tmp = (i - delta) * gphy->nrssislope;
427 tmp /= 0x10000;
428 tmp += 0x3A;
429 tmp = clamp_val(tmp, 0, 0x3F);
430 gphy->nrssi_lt[i] = tmp;
431 }
432}
433
434static void b43_calc_nrssi_offset(struct b43_wldev *dev)
435{
436 struct b43_phy *phy = &dev->phy;
437 u16 backup[20] = { 0 };
438 s16 v47F;
439 u16 i;
440 u16 saved = 0xFFFF;
441
442 backup[0] = b43_phy_read(dev, 0x0001);
443 backup[1] = b43_phy_read(dev, 0x0811);
444 backup[2] = b43_phy_read(dev, 0x0812);
445 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
446 backup[3] = b43_phy_read(dev, 0x0814);
447 backup[4] = b43_phy_read(dev, 0x0815);
448 }
449 backup[5] = b43_phy_read(dev, 0x005A);
450 backup[6] = b43_phy_read(dev, 0x0059);
451 backup[7] = b43_phy_read(dev, 0x0058);
452 backup[8] = b43_phy_read(dev, 0x000A);
453 backup[9] = b43_phy_read(dev, 0x0003);
454 backup[10] = b43_radio_read16(dev, 0x007A);
455 backup[11] = b43_radio_read16(dev, 0x0043);
456
457 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
458 b43_phy_write(dev, 0x0001,
459 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
460 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
461 b43_phy_write(dev, 0x0812,
462 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
463 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
464 if (phy->rev >= 6) {
465 backup[12] = b43_phy_read(dev, 0x002E);
466 backup[13] = b43_phy_read(dev, 0x002F);
467 backup[14] = b43_phy_read(dev, 0x080F);
468 backup[15] = b43_phy_read(dev, 0x0810);
469 backup[16] = b43_phy_read(dev, 0x0801);
470 backup[17] = b43_phy_read(dev, 0x0060);
471 backup[18] = b43_phy_read(dev, 0x0014);
472 backup[19] = b43_phy_read(dev, 0x0478);
473
474 b43_phy_write(dev, 0x002E, 0);
475 b43_phy_write(dev, 0x002F, 0);
476 b43_phy_write(dev, 0x080F, 0);
477 b43_phy_write(dev, 0x0810, 0);
478 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
479 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
480 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
481 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
482 }
483 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
484 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
485 udelay(30);
486
487 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
488 if (v47F >= 0x20)
489 v47F -= 0x40;
490 if (v47F == 31) {
491 for (i = 7; i >= 4; i--) {
492 b43_radio_write16(dev, 0x007B, i);
493 udelay(20);
494 v47F =
495 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
496 if (v47F >= 0x20)
497 v47F -= 0x40;
498 if (v47F < 31 && saved == 0xFFFF)
499 saved = i;
500 }
501 if (saved == 0xFFFF)
502 saved = 4;
503 } else {
504 b43_radio_write16(dev, 0x007A,
505 b43_radio_read16(dev, 0x007A) & 0x007F);
506 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
507 b43_phy_write(dev, 0x0814,
508 b43_phy_read(dev, 0x0814) | 0x0001);
509 b43_phy_write(dev, 0x0815,
510 b43_phy_read(dev, 0x0815) & 0xFFFE);
511 }
512 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
513 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
514 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
515 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
516 b43_phy_write(dev, 0x005A, 0x0480);
517 b43_phy_write(dev, 0x0059, 0x0810);
518 b43_phy_write(dev, 0x0058, 0x000D);
519 if (phy->rev == 0) {
520 b43_phy_write(dev, 0x0003, 0x0122);
521 } else {
522 b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
523 | 0x2000);
524 }
525 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
526 b43_phy_write(dev, 0x0814,
527 b43_phy_read(dev, 0x0814) | 0x0004);
528 b43_phy_write(dev, 0x0815,
529 b43_phy_read(dev, 0x0815) & 0xFFFB);
530 }
531 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
532 | 0x0040);
533 b43_radio_write16(dev, 0x007A,
534 b43_radio_read16(dev, 0x007A) | 0x000F);
535 b43_set_all_gains(dev, 3, 0, 1);
536 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
537 & 0x00F0) | 0x000F);
538 udelay(30);
539 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
540 if (v47F >= 0x20)
541 v47F -= 0x40;
542 if (v47F == -32) {
543 for (i = 0; i < 4; i++) {
544 b43_radio_write16(dev, 0x007B, i);
545 udelay(20);
546 v47F =
547 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
548 0x003F);
549 if (v47F >= 0x20)
550 v47F -= 0x40;
551 if (v47F > -31 && saved == 0xFFFF)
552 saved = i;
553 }
554 if (saved == 0xFFFF)
555 saved = 3;
556 } else
557 saved = 0;
558 }
559 b43_radio_write16(dev, 0x007B, saved);
560
561 if (phy->rev >= 6) {
562 b43_phy_write(dev, 0x002E, backup[12]);
563 b43_phy_write(dev, 0x002F, backup[13]);
564 b43_phy_write(dev, 0x080F, backup[14]);
565 b43_phy_write(dev, 0x0810, backup[15]);
566 }
567 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
568 b43_phy_write(dev, 0x0814, backup[3]);
569 b43_phy_write(dev, 0x0815, backup[4]);
570 }
571 b43_phy_write(dev, 0x005A, backup[5]);
572 b43_phy_write(dev, 0x0059, backup[6]);
573 b43_phy_write(dev, 0x0058, backup[7]);
574 b43_phy_write(dev, 0x000A, backup[8]);
575 b43_phy_write(dev, 0x0003, backup[9]);
576 b43_radio_write16(dev, 0x0043, backup[11]);
577 b43_radio_write16(dev, 0x007A, backup[10]);
578 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
579 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
580 b43_set_original_gains(dev);
581 if (phy->rev >= 6) {
582 b43_phy_write(dev, 0x0801, backup[16]);
583 b43_phy_write(dev, 0x0060, backup[17]);
584 b43_phy_write(dev, 0x0014, backup[18]);
585 b43_phy_write(dev, 0x0478, backup[19]);
586 }
587 b43_phy_write(dev, 0x0001, backup[0]);
588 b43_phy_write(dev, 0x0812, backup[2]);
589 b43_phy_write(dev, 0x0811, backup[1]);
590}
591
592void b43_calc_nrssi_slope(struct b43_wldev *dev)
593{
594 struct b43_phy *phy = &dev->phy;
595 struct b43_phy_g *gphy = phy->g;
596 u16 backup[18] = { 0 };
597 u16 tmp;
598 s16 nrssi0, nrssi1;
599
600 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
601
602 if (phy->radio_rev >= 9)
603 return;
604 if (phy->radio_rev == 8)
605 b43_calc_nrssi_offset(dev);
606
607 b43_phy_write(dev, B43_PHY_G_CRS,
608 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
609 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
610 backup[7] = b43_read16(dev, 0x03E2);
611 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
612 backup[0] = b43_radio_read16(dev, 0x007A);
613 backup[1] = b43_radio_read16(dev, 0x0052);
614 backup[2] = b43_radio_read16(dev, 0x0043);
615 backup[3] = b43_phy_read(dev, 0x0015);
616 backup[4] = b43_phy_read(dev, 0x005A);
617 backup[5] = b43_phy_read(dev, 0x0059);
618 backup[6] = b43_phy_read(dev, 0x0058);
619 backup[8] = b43_read16(dev, 0x03E6);
620 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
621 if (phy->rev >= 3) {
622 backup[10] = b43_phy_read(dev, 0x002E);
623 backup[11] = b43_phy_read(dev, 0x002F);
624 backup[12] = b43_phy_read(dev, 0x080F);
625 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
626 backup[14] = b43_phy_read(dev, 0x0801);
627 backup[15] = b43_phy_read(dev, 0x0060);
628 backup[16] = b43_phy_read(dev, 0x0014);
629 backup[17] = b43_phy_read(dev, 0x0478);
630 b43_phy_write(dev, 0x002E, 0);
631 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
632 switch (phy->rev) {
633 case 4:
634 case 6:
635 case 7:
636 b43_phy_write(dev, 0x0478,
637 b43_phy_read(dev, 0x0478)
638 | 0x0100);
639 b43_phy_write(dev, 0x0801,
640 b43_phy_read(dev, 0x0801)
641 | 0x0040);
642 break;
643 case 3:
644 case 5:
645 b43_phy_write(dev, 0x0801,
646 b43_phy_read(dev, 0x0801)
647 & 0xFFBF);
648 break;
649 }
650 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
651 | 0x0040);
652 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
653 | 0x0200);
654 }
655 b43_radio_write16(dev, 0x007A,
656 b43_radio_read16(dev, 0x007A) | 0x0070);
657 b43_set_all_gains(dev, 0, 8, 0);
658 b43_radio_write16(dev, 0x007A,
659 b43_radio_read16(dev, 0x007A) & 0x00F7);
660 if (phy->rev >= 2) {
661 b43_phy_write(dev, 0x0811,
662 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
663 0x0030);
664 b43_phy_write(dev, 0x0812,
665 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
666 0x0010);
667 }
668 b43_radio_write16(dev, 0x007A,
669 b43_radio_read16(dev, 0x007A) | 0x0080);
670 udelay(20);
671
672 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
673 if (nrssi0 >= 0x0020)
674 nrssi0 -= 0x0040;
675
676 b43_radio_write16(dev, 0x007A,
677 b43_radio_read16(dev, 0x007A) & 0x007F);
678 if (phy->rev >= 2) {
679 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
680 & 0xFF9F) | 0x0040);
681 }
682
683 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
684 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
685 | 0x2000);
686 b43_radio_write16(dev, 0x007A,
687 b43_radio_read16(dev, 0x007A) | 0x000F);
688 b43_phy_write(dev, 0x0015, 0xF330);
689 if (phy->rev >= 2) {
690 b43_phy_write(dev, 0x0812,
691 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
692 0x0020);
693 b43_phy_write(dev, 0x0811,
694 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
695 0x0020);
696 }
697
698 b43_set_all_gains(dev, 3, 0, 1);
699 if (phy->radio_rev == 8) {
700 b43_radio_write16(dev, 0x0043, 0x001F);
701 } else {
702 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
703 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
704 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
705 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
706 }
707 b43_phy_write(dev, 0x005A, 0x0480);
708 b43_phy_write(dev, 0x0059, 0x0810);
709 b43_phy_write(dev, 0x0058, 0x000D);
710 udelay(20);
711 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
712 if (nrssi1 >= 0x0020)
713 nrssi1 -= 0x0040;
714 if (nrssi0 == nrssi1)
715 gphy->nrssislope = 0x00010000;
716 else
717 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
718 if (nrssi0 >= -4) {
719 gphy->nrssi[0] = nrssi1;
720 gphy->nrssi[1] = nrssi0;
721 }
722 if (phy->rev >= 3) {
723 b43_phy_write(dev, 0x002E, backup[10]);
724 b43_phy_write(dev, 0x002F, backup[11]);
725 b43_phy_write(dev, 0x080F, backup[12]);
726 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
727 }
728 if (phy->rev >= 2) {
729 b43_phy_write(dev, 0x0812,
730 b43_phy_read(dev, 0x0812) & 0xFFCF);
731 b43_phy_write(dev, 0x0811,
732 b43_phy_read(dev, 0x0811) & 0xFFCF);
733 }
734
735 b43_radio_write16(dev, 0x007A, backup[0]);
736 b43_radio_write16(dev, 0x0052, backup[1]);
737 b43_radio_write16(dev, 0x0043, backup[2]);
738 b43_write16(dev, 0x03E2, backup[7]);
739 b43_write16(dev, 0x03E6, backup[8]);
740 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
741 b43_phy_write(dev, 0x0015, backup[3]);
742 b43_phy_write(dev, 0x005A, backup[4]);
743 b43_phy_write(dev, 0x0059, backup[5]);
744 b43_phy_write(dev, 0x0058, backup[6]);
745 b43_synth_pu_workaround(dev, phy->channel);
746 b43_phy_write(dev, 0x0802,
747 b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
748 b43_set_original_gains(dev);
749 b43_phy_write(dev, B43_PHY_G_CRS,
750 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
751 if (phy->rev >= 3) {
752 b43_phy_write(dev, 0x0801, backup[14]);
753 b43_phy_write(dev, 0x0060, backup[15]);
754 b43_phy_write(dev, 0x0014, backup[16]);
755 b43_phy_write(dev, 0x0478, backup[17]);
756 }
757 b43_nrssi_mem_update(dev);
758 b43_calc_nrssi_threshold(dev);
759}
760
761static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
762{
763 struct b43_phy *phy = &dev->phy;
764 struct b43_phy_g *gphy = phy->g;
765 s32 a, b;
766 s16 tmp16;
767 u16 tmp_u16;
768
769 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
770
771 if (!phy->gmode ||
772 !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
773 tmp16 = b43_nrssi_hw_read(dev, 0x20);
774 if (tmp16 >= 0x20)
775 tmp16 -= 0x40;
776 if (tmp16 < 3) {
777 b43_phy_write(dev, 0x048A,
778 (b43_phy_read(dev, 0x048A)
779 & 0xF000) | 0x09EB);
780 } else {
781 b43_phy_write(dev, 0x048A,
782 (b43_phy_read(dev, 0x048A)
783 & 0xF000) | 0x0AED);
784 }
785 } else {
786 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
787 a = 0xE;
788 b = 0xA;
789 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
790 a = 0x13;
791 b = 0x12;
792 } else {
793 a = 0xE;
794 b = 0x11;
795 }
796
797 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
798 a += (gphy->nrssi[0] << 6);
799 if (a < 32)
800 a += 31;
801 else
802 a += 32;
803 a = a >> 6;
804 a = clamp_val(a, -31, 31);
805
806 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
807 b += (gphy->nrssi[0] << 6);
808 if (b < 32)
809 b += 31;
810 else
811 b += 32;
812 b = b >> 6;
813 b = clamp_val(b, -31, 31);
814
815 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
816 tmp_u16 |= ((u32) b & 0x0000003F);
817 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
818 b43_phy_write(dev, 0x048A, tmp_u16);
819 }
820}
821
822/* Stack implementation to save/restore values from the
823 * interference mitigation code.
824 * It is save to restore values in random order.
825 */
826static void _stack_save(u32 * _stackptr, size_t * stackidx,
827 u8 id, u16 offset, u16 value)
828{
829 u32 *stackptr = &(_stackptr[*stackidx]);
830
831 B43_WARN_ON(offset & 0xF000);
832 B43_WARN_ON(id & 0xF0);
833 *stackptr = offset;
834 *stackptr |= ((u32) id) << 12;
835 *stackptr |= ((u32) value) << 16;
836 (*stackidx)++;
837 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
838}
839
840static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
841{
842 size_t i;
843
844 B43_WARN_ON(offset & 0xF000);
845 B43_WARN_ON(id & 0xF0);
846 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
847 if ((*stackptr & 0x00000FFF) != offset)
848 continue;
849 if (((*stackptr & 0x0000F000) >> 12) != id)
850 continue;
851 return ((*stackptr & 0xFFFF0000) >> 16);
852 }
853 B43_WARN_ON(1);
854
855 return 0;
856}
857
858#define phy_stacksave(offset) \
859 do { \
860 _stack_save(stack, &stackidx, 0x1, (offset), \
861 b43_phy_read(dev, (offset))); \
862 } while (0)
863#define phy_stackrestore(offset) \
864 do { \
865 b43_phy_write(dev, (offset), \
866 _stack_restore(stack, 0x1, \
867 (offset))); \
868 } while (0)
869#define radio_stacksave(offset) \
870 do { \
871 _stack_save(stack, &stackidx, 0x2, (offset), \
872 b43_radio_read16(dev, (offset))); \
873 } while (0)
874#define radio_stackrestore(offset) \
875 do { \
876 b43_radio_write16(dev, (offset), \
877 _stack_restore(stack, 0x2, \
878 (offset))); \
879 } while (0)
880#define ofdmtab_stacksave(table, offset) \
881 do { \
882 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
883 b43_ofdmtab_read16(dev, (table), (offset))); \
884 } while (0)
885#define ofdmtab_stackrestore(table, offset) \
886 do { \
887 b43_ofdmtab_write16(dev, (table), (offset), \
888 _stack_restore(stack, 0x3, \
889 (offset)|(table))); \
890 } while (0)
891
892static void
893b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
894{
895 struct b43_phy *phy = &dev->phy;
896 struct b43_phy_g *gphy = phy->g;
897 u16 tmp, flipped;
898 size_t stackidx = 0;
899 u32 *stack = gphy->interfstack;
900
901 switch (mode) {
902 case B43_INTERFMODE_NONWLAN:
903 if (phy->rev != 1) {
904 b43_phy_write(dev, 0x042B,
905 b43_phy_read(dev, 0x042B) | 0x0800);
906 b43_phy_write(dev, B43_PHY_G_CRS,
907 b43_phy_read(dev,
908 B43_PHY_G_CRS) & ~0x4000);
909 break;
910 }
911 radio_stacksave(0x0078);
912 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
913 B43_WARN_ON(tmp > 15);
914 flipped = bitrev4(tmp);
915 if (flipped < 10 && flipped >= 8)
916 flipped = 7;
917 else if (flipped >= 10)
918 flipped -= 3;
919 flipped = (bitrev4(flipped) << 1) | 0x0020;
920 b43_radio_write16(dev, 0x0078, flipped);
921
922 b43_calc_nrssi_threshold(dev);
923
924 phy_stacksave(0x0406);
925 b43_phy_write(dev, 0x0406, 0x7E28);
926
927 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
928 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
929 b43_phy_read(dev,
930 B43_PHY_RADIO_BITFIELD) | 0x1000);
931
932 phy_stacksave(0x04A0);
933 b43_phy_write(dev, 0x04A0,
934 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
935 phy_stacksave(0x04A1);
936 b43_phy_write(dev, 0x04A1,
937 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
938 phy_stacksave(0x04A2);
939 b43_phy_write(dev, 0x04A2,
940 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
941 phy_stacksave(0x04A8);
942 b43_phy_write(dev, 0x04A8,
943 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
944 phy_stacksave(0x04AB);
945 b43_phy_write(dev, 0x04AB,
946 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
947
948 phy_stacksave(0x04A7);
949 b43_phy_write(dev, 0x04A7, 0x0002);
950 phy_stacksave(0x04A3);
951 b43_phy_write(dev, 0x04A3, 0x287A);
952 phy_stacksave(0x04A9);
953 b43_phy_write(dev, 0x04A9, 0x2027);
954 phy_stacksave(0x0493);
955 b43_phy_write(dev, 0x0493, 0x32F5);
956 phy_stacksave(0x04AA);
957 b43_phy_write(dev, 0x04AA, 0x2027);
958 phy_stacksave(0x04AC);
959 b43_phy_write(dev, 0x04AC, 0x32F5);
960 break;
961 case B43_INTERFMODE_MANUALWLAN:
962 if (b43_phy_read(dev, 0x0033) & 0x0800)
963 break;
964
965 gphy->aci_enable = 1;
966
967 phy_stacksave(B43_PHY_RADIO_BITFIELD);
968 phy_stacksave(B43_PHY_G_CRS);
969 if (phy->rev < 2) {
970 phy_stacksave(0x0406);
971 } else {
972 phy_stacksave(0x04C0);
973 phy_stacksave(0x04C1);
974 }
975 phy_stacksave(0x0033);
976 phy_stacksave(0x04A7);
977 phy_stacksave(0x04A3);
978 phy_stacksave(0x04A9);
979 phy_stacksave(0x04AA);
980 phy_stacksave(0x04AC);
981 phy_stacksave(0x0493);
982 phy_stacksave(0x04A1);
983 phy_stacksave(0x04A0);
984 phy_stacksave(0x04A2);
985 phy_stacksave(0x048A);
986 phy_stacksave(0x04A8);
987 phy_stacksave(0x04AB);
988 if (phy->rev == 2) {
989 phy_stacksave(0x04AD);
990 phy_stacksave(0x04AE);
991 } else if (phy->rev >= 3) {
992 phy_stacksave(0x04AD);
993 phy_stacksave(0x0415);
994 phy_stacksave(0x0416);
995 phy_stacksave(0x0417);
996 ofdmtab_stacksave(0x1A00, 0x2);
997 ofdmtab_stacksave(0x1A00, 0x3);
998 }
999 phy_stacksave(0x042B);
1000 phy_stacksave(0x048C);
1001
1002 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1003 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
1004 & ~0x1000);
1005 b43_phy_write(dev, B43_PHY_G_CRS,
1006 (b43_phy_read(dev, B43_PHY_G_CRS)
1007 & 0xFFFC) | 0x0002);
1008
1009 b43_phy_write(dev, 0x0033, 0x0800);
1010 b43_phy_write(dev, 0x04A3, 0x2027);
1011 b43_phy_write(dev, 0x04A9, 0x1CA8);
1012 b43_phy_write(dev, 0x0493, 0x287A);
1013 b43_phy_write(dev, 0x04AA, 0x1CA8);
1014 b43_phy_write(dev, 0x04AC, 0x287A);
1015
1016 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
1017 & 0xFFC0) | 0x001A);
1018 b43_phy_write(dev, 0x04A7, 0x000D);
1019
1020 if (phy->rev < 2) {
1021 b43_phy_write(dev, 0x0406, 0xFF0D);
1022 } else if (phy->rev == 2) {
1023 b43_phy_write(dev, 0x04C0, 0xFFFF);
1024 b43_phy_write(dev, 0x04C1, 0x00A9);
1025 } else {
1026 b43_phy_write(dev, 0x04C0, 0x00C1);
1027 b43_phy_write(dev, 0x04C1, 0x0059);
1028 }
1029
1030 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
1031 & 0xC0FF) | 0x1800);
1032 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
1033 & 0xFFC0) | 0x0015);
1034 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1035 & 0xCFFF) | 0x1000);
1036 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1037 & 0xF0FF) | 0x0A00);
1038 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1039 & 0xCFFF) | 0x1000);
1040 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1041 & 0xF0FF) | 0x0800);
1042 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1043 & 0xFFCF) | 0x0010);
1044 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1045 & 0xFFF0) | 0x0005);
1046 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1047 & 0xFFCF) | 0x0010);
1048 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1049 & 0xFFF0) | 0x0006);
1050 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1051 & 0xF0FF) | 0x0800);
1052 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
1053 & 0xF0FF) | 0x0500);
1054 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1055 & 0xFFF0) | 0x000B);
1056
1057 if (phy->rev >= 3) {
1058 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
1059 & ~0x8000);
1060 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
1061 & 0x8000) | 0x36D8);
1062 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
1063 & 0x8000) | 0x36D8);
1064 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
1065 & 0xFE00) | 0x016D);
1066 } else {
1067 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
1068 | 0x1000);
1069 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
1070 & 0x9FFF) | 0x2000);
1071 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
1072 }
1073 if (phy->rev >= 2) {
1074 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
1075 | 0x0800);
1076 }
1077 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
1078 & 0xF0FF) | 0x0200);
1079 if (phy->rev == 2) {
1080 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
1081 & 0xFF00) | 0x007F);
1082 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
1083 & 0x00FF) | 0x1300);
1084 } else if (phy->rev >= 6) {
1085 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1086 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
1087 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
1088 & 0x00FF);
1089 }
1090 b43_calc_nrssi_slope(dev);
1091 break;
1092 default:
1093 B43_WARN_ON(1);
1094 }
1095}
1096
1097static void
1098b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1099{
1100 struct b43_phy *phy = &dev->phy;
1101 struct b43_phy_g *gphy = phy->g;
1102 u32 *stack = gphy->interfstack;
1103
1104 switch (mode) {
1105 case B43_INTERFMODE_NONWLAN:
1106 if (phy->rev != 1) {
1107 b43_phy_write(dev, 0x042B,
1108 b43_phy_read(dev, 0x042B) & ~0x0800);
1109 b43_phy_write(dev, B43_PHY_G_CRS,
1110 b43_phy_read(dev,
1111 B43_PHY_G_CRS) | 0x4000);
1112 break;
1113 }
1114 radio_stackrestore(0x0078);
1115 b43_calc_nrssi_threshold(dev);
1116 phy_stackrestore(0x0406);
1117 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
1118 if (!dev->bad_frames_preempt) {
1119 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1120 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
1121 & ~(1 << 11));
1122 }
1123 b43_phy_write(dev, B43_PHY_G_CRS,
1124 b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
1125 phy_stackrestore(0x04A0);
1126 phy_stackrestore(0x04A1);
1127 phy_stackrestore(0x04A2);
1128 phy_stackrestore(0x04A8);
1129 phy_stackrestore(0x04AB);
1130 phy_stackrestore(0x04A7);
1131 phy_stackrestore(0x04A3);
1132 phy_stackrestore(0x04A9);
1133 phy_stackrestore(0x0493);
1134 phy_stackrestore(0x04AA);
1135 phy_stackrestore(0x04AC);
1136 break;
1137 case B43_INTERFMODE_MANUALWLAN:
1138 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1139 break;
1140
1141 gphy->aci_enable = 0;
1142
1143 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1144 phy_stackrestore(B43_PHY_G_CRS);
1145 phy_stackrestore(0x0033);
1146 phy_stackrestore(0x04A3);
1147 phy_stackrestore(0x04A9);
1148 phy_stackrestore(0x0493);
1149 phy_stackrestore(0x04AA);
1150 phy_stackrestore(0x04AC);
1151 phy_stackrestore(0x04A0);
1152 phy_stackrestore(0x04A7);
1153 if (phy->rev >= 2) {
1154 phy_stackrestore(0x04C0);
1155 phy_stackrestore(0x04C1);
1156 } else
1157 phy_stackrestore(0x0406);
1158 phy_stackrestore(0x04A1);
1159 phy_stackrestore(0x04AB);
1160 phy_stackrestore(0x04A8);
1161 if (phy->rev == 2) {
1162 phy_stackrestore(0x04AD);
1163 phy_stackrestore(0x04AE);
1164 } else if (phy->rev >= 3) {
1165 phy_stackrestore(0x04AD);
1166 phy_stackrestore(0x0415);
1167 phy_stackrestore(0x0416);
1168 phy_stackrestore(0x0417);
1169 ofdmtab_stackrestore(0x1A00, 0x2);
1170 ofdmtab_stackrestore(0x1A00, 0x3);
1171 }
1172 phy_stackrestore(0x04A2);
1173 phy_stackrestore(0x048A);
1174 phy_stackrestore(0x042B);
1175 phy_stackrestore(0x048C);
1176 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1177 b43_calc_nrssi_slope(dev);
1178 break;
1179 default:
1180 B43_WARN_ON(1);
1181 }
1182}
1183
1184#undef phy_stacksave
1185#undef phy_stackrestore
1186#undef radio_stacksave
1187#undef radio_stackrestore
1188#undef ofdmtab_stacksave
1189#undef ofdmtab_stackrestore
1190
1191static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1192{
1193 u16 reg, index, ret;
1194
1195 static const u8 rcc_table[] = {
1196 0x02, 0x03, 0x01, 0x0F,
1197 0x06, 0x07, 0x05, 0x0F,
1198 0x0A, 0x0B, 0x09, 0x0F,
1199 0x0E, 0x0F, 0x0D, 0x0F,
1200 };
1201
1202 reg = b43_radio_read16(dev, 0x60);
1203 index = (reg & 0x001E) >> 1;
1204 ret = rcc_table[index] << 1;
1205 ret |= (reg & 0x0001);
1206 ret |= 0x0020;
1207
1208 return ret;
1209}
1210
1211#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1212static u16 radio2050_rfover_val(struct b43_wldev *dev,
1213 u16 phy_register, unsigned int lpd)
1214{
1215 struct b43_phy *phy = &dev->phy;
1216 struct b43_phy_g *gphy = phy->g;
1217 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1218
1219 if (!phy->gmode)
1220 return 0;
1221
1222 if (has_loopback_gain(phy)) {
1223 int max_lb_gain = gphy->max_lb_gain;
1224 u16 extlna;
1225 u16 i;
1226
1227 if (phy->radio_rev == 8)
1228 max_lb_gain += 0x3E;
1229 else
1230 max_lb_gain += 0x26;
1231 if (max_lb_gain >= 0x46) {
1232 extlna = 0x3000;
1233 max_lb_gain -= 0x46;
1234 } else if (max_lb_gain >= 0x3A) {
1235 extlna = 0x1000;
1236 max_lb_gain -= 0x3A;
1237 } else if (max_lb_gain >= 0x2E) {
1238 extlna = 0x2000;
1239 max_lb_gain -= 0x2E;
1240 } else {
1241 extlna = 0;
1242 max_lb_gain -= 0x10;
1243 }
1244
1245 for (i = 0; i < 16; i++) {
1246 max_lb_gain -= (i * 6);
1247 if (max_lb_gain < 6)
1248 break;
1249 }
1250
1251 if ((phy->rev < 7) ||
1252 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1253 if (phy_register == B43_PHY_RFOVER) {
1254 return 0x1B3;
1255 } else if (phy_register == B43_PHY_RFOVERVAL) {
1256 extlna |= (i << 8);
1257 switch (lpd) {
1258 case LPD(0, 1, 1):
1259 return 0x0F92;
1260 case LPD(0, 0, 1):
1261 case LPD(1, 0, 1):
1262 return (0x0092 | extlna);
1263 case LPD(1, 0, 0):
1264 return (0x0093 | extlna);
1265 }
1266 B43_WARN_ON(1);
1267 }
1268 B43_WARN_ON(1);
1269 } else {
1270 if (phy_register == B43_PHY_RFOVER) {
1271 return 0x9B3;
1272 } else if (phy_register == B43_PHY_RFOVERVAL) {
1273 if (extlna)
1274 extlna |= 0x8000;
1275 extlna |= (i << 8);
1276 switch (lpd) {
1277 case LPD(0, 1, 1):
1278 return 0x8F92;
1279 case LPD(0, 0, 1):
1280 return (0x8092 | extlna);
1281 case LPD(1, 0, 1):
1282 return (0x2092 | extlna);
1283 case LPD(1, 0, 0):
1284 return (0x2093 | extlna);
1285 }
1286 B43_WARN_ON(1);
1287 }
1288 B43_WARN_ON(1);
1289 }
1290 } else {
1291 if ((phy->rev < 7) ||
1292 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1293 if (phy_register == B43_PHY_RFOVER) {
1294 return 0x1B3;
1295 } else if (phy_register == B43_PHY_RFOVERVAL) {
1296 switch (lpd) {
1297 case LPD(0, 1, 1):
1298 return 0x0FB2;
1299 case LPD(0, 0, 1):
1300 return 0x00B2;
1301 case LPD(1, 0, 1):
1302 return 0x30B2;
1303 case LPD(1, 0, 0):
1304 return 0x30B3;
1305 }
1306 B43_WARN_ON(1);
1307 }
1308 B43_WARN_ON(1);
1309 } else {
1310 if (phy_register == B43_PHY_RFOVER) {
1311 return 0x9B3;
1312 } else if (phy_register == B43_PHY_RFOVERVAL) {
1313 switch (lpd) {
1314 case LPD(0, 1, 1):
1315 return 0x8FB2;
1316 case LPD(0, 0, 1):
1317 return 0x80B2;
1318 case LPD(1, 0, 1):
1319 return 0x20B2;
1320 case LPD(1, 0, 0):
1321 return 0x20B3;
1322 }
1323 B43_WARN_ON(1);
1324 }
1325 B43_WARN_ON(1);
1326 }
1327 }
1328 return 0;
1329}
1330
1331struct init2050_saved_values {
1332 /* Core registers */
1333 u16 reg_3EC;
1334 u16 reg_3E6;
1335 u16 reg_3F4;
1336 /* Radio registers */
1337 u16 radio_43;
1338 u16 radio_51;
1339 u16 radio_52;
1340 /* PHY registers */
1341 u16 phy_pgactl;
1342 u16 phy_cck_5A;
1343 u16 phy_cck_59;
1344 u16 phy_cck_58;
1345 u16 phy_cck_30;
1346 u16 phy_rfover;
1347 u16 phy_rfoverval;
1348 u16 phy_analogover;
1349 u16 phy_analogoverval;
1350 u16 phy_crs0;
1351 u16 phy_classctl;
1352 u16 phy_lo_mask;
1353 u16 phy_lo_ctl;
1354 u16 phy_syncctl;
1355};
1356
1357u16 b43_radio_init2050(struct b43_wldev *dev)
1358{
1359 struct b43_phy *phy = &dev->phy;
1360 struct init2050_saved_values sav;
1361 u16 rcc;
1362 u16 radio78;
1363 u16 ret;
1364 u16 i, j;
1365 u32 tmp1 = 0, tmp2 = 0;
1366
1367 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
1368
1369 sav.radio_43 = b43_radio_read16(dev, 0x43);
1370 sav.radio_51 = b43_radio_read16(dev, 0x51);
1371 sav.radio_52 = b43_radio_read16(dev, 0x52);
1372 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1373 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1374 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1375 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1376
1377 if (phy->type == B43_PHYTYPE_B) {
1378 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1379 sav.reg_3EC = b43_read16(dev, 0x3EC);
1380
1381 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1382 b43_write16(dev, 0x3EC, 0x3F3F);
1383 } else if (phy->gmode || phy->rev >= 2) {
1384 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1385 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1386 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1387 sav.phy_analogoverval =
1388 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1389 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1390 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1391
1392 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1393 b43_phy_read(dev, B43_PHY_ANALOGOVER)
1394 | 0x0003);
1395 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1396 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
1397 & 0xFFFC);
1398 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1399 & 0x7FFF);
1400 b43_phy_write(dev, B43_PHY_CLASSCTL,
1401 b43_phy_read(dev, B43_PHY_CLASSCTL)
1402 & 0xFFFC);
1403 if (has_loopback_gain(phy)) {
1404 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1405 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1406
1407 if (phy->rev >= 3)
1408 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1409 else
1410 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1411 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1412 }
1413
1414 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1415 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1416 LPD(0, 1, 1)));
1417 b43_phy_write(dev, B43_PHY_RFOVER,
1418 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1419 }
1420 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1421
1422 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1423 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
1424 & 0xFF7F);
1425 sav.reg_3E6 = b43_read16(dev, 0x3E6);
1426 sav.reg_3F4 = b43_read16(dev, 0x3F4);
1427
1428 if (phy->analog == 0) {
1429 b43_write16(dev, 0x03E6, 0x0122);
1430 } else {
1431 if (phy->analog >= 2) {
1432 b43_phy_write(dev, B43_PHY_CCK(0x03),
1433 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1434 & 0xFFBF) | 0x40);
1435 }
1436 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1437 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1438 }
1439
1440 rcc = b43_radio_core_calibration_value(dev);
1441
1442 if (phy->type == B43_PHYTYPE_B)
1443 b43_radio_write16(dev, 0x78, 0x26);
1444 if (phy->gmode || phy->rev >= 2) {
1445 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1446 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1447 LPD(0, 1, 1)));
1448 }
1449 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1450 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1451 if (phy->gmode || phy->rev >= 2) {
1452 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1453 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1454 LPD(0, 0, 1)));
1455 }
1456 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1457 b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
1458 | 0x0004);
1459 if (phy->radio_rev == 8) {
1460 b43_radio_write16(dev, 0x43, 0x1F);
1461 } else {
1462 b43_radio_write16(dev, 0x52, 0);
1463 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1464 & 0xFFF0) | 0x0009);
1465 }
1466 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1467
1468 for (i = 0; i < 16; i++) {
1469 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1470 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1471 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1472 if (phy->gmode || phy->rev >= 2) {
1473 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1474 radio2050_rfover_val(dev,
1475 B43_PHY_RFOVERVAL,
1476 LPD(1, 0, 1)));
1477 }
1478 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1479 udelay(10);
1480 if (phy->gmode || phy->rev >= 2) {
1481 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1482 radio2050_rfover_val(dev,
1483 B43_PHY_RFOVERVAL,
1484 LPD(1, 0, 1)));
1485 }
1486 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1487 udelay(10);
1488 if (phy->gmode || phy->rev >= 2) {
1489 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1490 radio2050_rfover_val(dev,
1491 B43_PHY_RFOVERVAL,
1492 LPD(1, 0, 0)));
1493 }
1494 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1495 udelay(20);
1496 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1497 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1498 if (phy->gmode || phy->rev >= 2) {
1499 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1500 radio2050_rfover_val(dev,
1501 B43_PHY_RFOVERVAL,
1502 LPD(1, 0, 1)));
1503 }
1504 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1505 }
1506 udelay(10);
1507
1508 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1509 tmp1++;
1510 tmp1 >>= 9;
1511
1512 for (i = 0; i < 16; i++) {
1513 radio78 = (bitrev4(i) << 1) | 0x0020;
1514 b43_radio_write16(dev, 0x78, radio78);
1515 udelay(10);
1516 for (j = 0; j < 16; j++) {
1517 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1518 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1519 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1520 if (phy->gmode || phy->rev >= 2) {
1521 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1522 radio2050_rfover_val(dev,
1523 B43_PHY_RFOVERVAL,
1524 LPD(1, 0,
1525 1)));
1526 }
1527 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1528 udelay(10);
1529 if (phy->gmode || phy->rev >= 2) {
1530 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1531 radio2050_rfover_val(dev,
1532 B43_PHY_RFOVERVAL,
1533 LPD(1, 0,
1534 1)));
1535 }
1536 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1537 udelay(10);
1538 if (phy->gmode || phy->rev >= 2) {
1539 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1540 radio2050_rfover_val(dev,
1541 B43_PHY_RFOVERVAL,
1542 LPD(1, 0,
1543 0)));
1544 }
1545 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1546 udelay(10);
1547 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1548 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1549 if (phy->gmode || phy->rev >= 2) {
1550 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1551 radio2050_rfover_val(dev,
1552 B43_PHY_RFOVERVAL,
1553 LPD(1, 0,
1554 1)));
1555 }
1556 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1557 }
1558 tmp2++;
1559 tmp2 >>= 8;
1560 if (tmp1 < tmp2)
1561 break;
1562 }
1563
1564 /* Restore the registers */
1565 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1566 b43_radio_write16(dev, 0x51, sav.radio_51);
1567 b43_radio_write16(dev, 0x52, sav.radio_52);
1568 b43_radio_write16(dev, 0x43, sav.radio_43);
1569 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1570 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1571 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1572 b43_write16(dev, 0x3E6, sav.reg_3E6);
1573 if (phy->analog != 0)
1574 b43_write16(dev, 0x3F4, sav.reg_3F4);
1575 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1576 b43_synth_pu_workaround(dev, phy->channel);
1577 if (phy->type == B43_PHYTYPE_B) {
1578 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1579 b43_write16(dev, 0x3EC, sav.reg_3EC);
1580 } else if (phy->gmode) {
1581 b43_write16(dev, B43_MMIO_PHY_RADIO,
1582 b43_read16(dev, B43_MMIO_PHY_RADIO)
1583 & 0x7FFF);
1584 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1585 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1586 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1587 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1588 sav.phy_analogoverval);
1589 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1590 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1591 if (has_loopback_gain(phy)) {
1592 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1593 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1594 }
1595 }
1596 if (i > 15)
1597 ret = radio78;
1598 else
1599 ret = rcc;
1600
1601 return ret;
1602}
1603
1604static void b43_phy_initb5(struct b43_wldev *dev)
1605{
1606 struct ssb_bus *bus = dev->dev->bus;
1607 struct b43_phy *phy = &dev->phy;
1608 struct b43_phy_g *gphy = phy->g;
1609 u16 offset, value;
1610 u8 old_channel;
1611
1612 if (phy->analog == 1) {
1613 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1614 | 0x0050);
1615 }
1616 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1617 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1618 value = 0x2120;
1619 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1620 b43_phy_write(dev, offset, value);
1621 value += 0x202;
1622 }
1623 }
1624 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1625 | 0x0700);
1626 if (phy->radio_ver == 0x2050)
1627 b43_phy_write(dev, 0x0038, 0x0667);
1628
1629 if (phy->gmode || phy->rev >= 2) {
1630 if (phy->radio_ver == 0x2050) {
1631 b43_radio_write16(dev, 0x007A,
1632 b43_radio_read16(dev, 0x007A)
1633 | 0x0020);
1634 b43_radio_write16(dev, 0x0051,
1635 b43_radio_read16(dev, 0x0051)
1636 | 0x0004);
1637 }
1638 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1639
1640 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1641 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1642
1643 b43_phy_write(dev, 0x001C, 0x186A);
1644
1645 b43_phy_write(dev, 0x0013,
1646 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1647 b43_phy_write(dev, 0x0035,
1648 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1649 b43_phy_write(dev, 0x005D,
1650 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1651 }
1652
1653 if (dev->bad_frames_preempt) {
1654 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1655 b43_phy_read(dev,
1656 B43_PHY_RADIO_BITFIELD) | (1 << 11));
1657 }
1658
1659 if (phy->analog == 1) {
1660 b43_phy_write(dev, 0x0026, 0xCE00);
1661 b43_phy_write(dev, 0x0021, 0x3763);
1662 b43_phy_write(dev, 0x0022, 0x1BC3);
1663 b43_phy_write(dev, 0x0023, 0x06F9);
1664 b43_phy_write(dev, 0x0024, 0x037E);
1665 } else
1666 b43_phy_write(dev, 0x0026, 0xCC00);
1667 b43_phy_write(dev, 0x0030, 0x00C6);
1668 b43_write16(dev, 0x03EC, 0x3F22);
1669
1670 if (phy->analog == 1)
1671 b43_phy_write(dev, 0x0020, 0x3E1C);
1672 else
1673 b43_phy_write(dev, 0x0020, 0x301C);
1674
1675 if (phy->analog == 0)
1676 b43_write16(dev, 0x03E4, 0x3000);
1677
1678 old_channel = phy->channel;
1679 /* Force to channel 7, even if not supported. */
1680 b43_gphy_channel_switch(dev, 7, 0);
1681
1682 if (phy->radio_ver != 0x2050) {
1683 b43_radio_write16(dev, 0x0075, 0x0080);
1684 b43_radio_write16(dev, 0x0079, 0x0081);
1685 }
1686
1687 b43_radio_write16(dev, 0x0050, 0x0020);
1688 b43_radio_write16(dev, 0x0050, 0x0023);
1689
1690 if (phy->radio_ver == 0x2050) {
1691 b43_radio_write16(dev, 0x0050, 0x0020);
1692 b43_radio_write16(dev, 0x005A, 0x0070);
1693 }
1694
1695 b43_radio_write16(dev, 0x005B, 0x007B);
1696 b43_radio_write16(dev, 0x005C, 0x00B0);
1697
1698 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1699
1700 b43_gphy_channel_switch(dev, old_channel, 0);
1701
1702 b43_phy_write(dev, 0x0014, 0x0080);
1703 b43_phy_write(dev, 0x0032, 0x00CA);
1704 b43_phy_write(dev, 0x002A, 0x88A3);
1705
1706 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1707
1708 if (phy->radio_ver == 0x2050)
1709 b43_radio_write16(dev, 0x005D, 0x000D);
1710
1711 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1712}
1713
1714static void b43_phy_initb6(struct b43_wldev *dev)
1715{
1716 struct b43_phy *phy = &dev->phy;
1717 struct b43_phy_g *gphy = phy->g;
1718 u16 offset, val;
1719 u8 old_channel;
1720
1721 b43_phy_write(dev, 0x003E, 0x817A);
1722 b43_radio_write16(dev, 0x007A,
1723 (b43_radio_read16(dev, 0x007A) | 0x0058));
1724 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1725 b43_radio_write16(dev, 0x51, 0x37);
1726 b43_radio_write16(dev, 0x52, 0x70);
1727 b43_radio_write16(dev, 0x53, 0xB3);
1728 b43_radio_write16(dev, 0x54, 0x9B);
1729 b43_radio_write16(dev, 0x5A, 0x88);
1730 b43_radio_write16(dev, 0x5B, 0x88);
1731 b43_radio_write16(dev, 0x5D, 0x88);
1732 b43_radio_write16(dev, 0x5E, 0x88);
1733 b43_radio_write16(dev, 0x7D, 0x88);
1734 b43_hf_write(dev, b43_hf_read(dev)
1735 | B43_HF_TSSIRPSMW);
1736 }
1737 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1738 if (phy->radio_rev == 8) {
1739 b43_radio_write16(dev, 0x51, 0);
1740 b43_radio_write16(dev, 0x52, 0x40);
1741 b43_radio_write16(dev, 0x53, 0xB7);
1742 b43_radio_write16(dev, 0x54, 0x98);
1743 b43_radio_write16(dev, 0x5A, 0x88);
1744 b43_radio_write16(dev, 0x5B, 0x6B);
1745 b43_radio_write16(dev, 0x5C, 0x0F);
1746 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1747 b43_radio_write16(dev, 0x5D, 0xFA);
1748 b43_radio_write16(dev, 0x5E, 0xD8);
1749 } else {
1750 b43_radio_write16(dev, 0x5D, 0xF5);
1751 b43_radio_write16(dev, 0x5E, 0xB8);
1752 }
1753 b43_radio_write16(dev, 0x0073, 0x0003);
1754 b43_radio_write16(dev, 0x007D, 0x00A8);
1755 b43_radio_write16(dev, 0x007C, 0x0001);
1756 b43_radio_write16(dev, 0x007E, 0x0008);
1757 }
1758 val = 0x1E1F;
1759 for (offset = 0x0088; offset < 0x0098; offset++) {
1760 b43_phy_write(dev, offset, val);
1761 val -= 0x0202;
1762 }
1763 val = 0x3E3F;
1764 for (offset = 0x0098; offset < 0x00A8; offset++) {
1765 b43_phy_write(dev, offset, val);
1766 val -= 0x0202;
1767 }
1768 val = 0x2120;
1769 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1770 b43_phy_write(dev, offset, (val & 0x3F3F));
1771 val += 0x0202;
1772 }
1773 if (phy->type == B43_PHYTYPE_G) {
1774 b43_radio_write16(dev, 0x007A,
1775 b43_radio_read16(dev, 0x007A) | 0x0020);
1776 b43_radio_write16(dev, 0x0051,
1777 b43_radio_read16(dev, 0x0051) | 0x0004);
1778 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1779 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1780 b43_phy_write(dev, 0x5B, 0);
1781 b43_phy_write(dev, 0x5C, 0);
1782 }
1783
1784 old_channel = phy->channel;
1785 if (old_channel >= 8)
1786 b43_gphy_channel_switch(dev, 1, 0);
1787 else
1788 b43_gphy_channel_switch(dev, 13, 0);
1789
1790 b43_radio_write16(dev, 0x0050, 0x0020);
1791 b43_radio_write16(dev, 0x0050, 0x0023);
1792 udelay(40);
1793 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1794 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1795 | 0x0002));
1796 b43_radio_write16(dev, 0x50, 0x20);
1797 }
1798 if (phy->radio_rev <= 2) {
1799 b43_radio_write16(dev, 0x7C, 0x20);
1800 b43_radio_write16(dev, 0x5A, 0x70);
1801 b43_radio_write16(dev, 0x5B, 0x7B);
1802 b43_radio_write16(dev, 0x5C, 0xB0);
1803 }
1804 b43_radio_write16(dev, 0x007A,
1805 (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1806
1807 b43_gphy_channel_switch(dev, old_channel, 0);
1808
1809 b43_phy_write(dev, 0x0014, 0x0200);
1810 if (phy->radio_rev >= 6)
1811 b43_phy_write(dev, 0x2A, 0x88C2);
1812 else
1813 b43_phy_write(dev, 0x2A, 0x8AC0);
1814 b43_phy_write(dev, 0x0038, 0x0668);
1815 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1816 if (phy->radio_rev <= 5) {
1817 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1818 & 0xFF80) | 0x0003);
1819 }
1820 if (phy->radio_rev <= 2)
1821 b43_radio_write16(dev, 0x005D, 0x000D);
1822
1823 if (phy->analog == 4) {
1824 b43_write16(dev, 0x3E4, 9);
1825 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1826 & 0x0FFF);
1827 } else {
1828 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1829 | 0x0004);
1830 }
1831 if (phy->type == B43_PHYTYPE_B)
1832 B43_WARN_ON(1);
1833 else if (phy->type == B43_PHYTYPE_G)
1834 b43_write16(dev, 0x03E6, 0x0);
1835}
1836
1837static void b43_calc_loopback_gain(struct b43_wldev *dev)
1838{
1839 struct b43_phy *phy = &dev->phy;
1840 struct b43_phy_g *gphy = phy->g;
1841 u16 backup_phy[16] = { 0 };
1842 u16 backup_radio[3];
1843 u16 backup_bband;
1844 u16 i, j, loop_i_max;
1845 u16 trsw_rx;
1846 u16 loop1_outer_done, loop1_inner_done;
1847
1848 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1849 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1850 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1851 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1852 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1853 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1854 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1855 }
1856 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1857 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1858 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1859 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1860 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1861 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1862 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1863 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1864 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1865 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1866 backup_bband = gphy->bbatt.att;
1867 backup_radio[0] = b43_radio_read16(dev, 0x52);
1868 backup_radio[1] = b43_radio_read16(dev, 0x43);
1869 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1870
1871 b43_phy_write(dev, B43_PHY_CRS0,
1872 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1873 b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1874 b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1875 b43_phy_write(dev, B43_PHY_RFOVER,
1876 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1877 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1878 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1879 b43_phy_write(dev, B43_PHY_RFOVER,
1880 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1881 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1882 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1883 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1884 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1885 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1886 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1887 b43_phy_read(dev,
1888 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1889 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1890 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1891 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1892 b43_phy_read(dev,
1893 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1894 }
1895 b43_phy_write(dev, B43_PHY_RFOVER,
1896 b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1897 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1898 b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1899 b43_phy_write(dev, B43_PHY_RFOVER,
1900 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1901 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1902 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1903 & 0xFFCF) | 0x10);
1904
1905 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1906 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1907 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1908
1909 b43_phy_write(dev, B43_PHY_CCK(0x0A),
1910 b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
1911 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1912 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1913 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1914 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1915 b43_phy_read(dev,
1916 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1917 }
1918 b43_phy_write(dev, B43_PHY_CCK(0x03),
1919 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1920 & 0xFF9F) | 0x40);
1921
1922 if (phy->radio_rev == 8) {
1923 b43_radio_write16(dev, 0x43, 0x000F);
1924 } else {
1925 b43_radio_write16(dev, 0x52, 0);
1926 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1927 & 0xFFF0) | 0x9);
1928 }
1929 b43_gphy_set_baseband_attenuation(dev, 11);
1930
1931 if (phy->rev >= 3)
1932 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1933 else
1934 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1935 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1936
1937 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1938 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1939 & 0xFFC0) | 0x01);
1940 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1941 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1942 & 0xC0FF) | 0x800);
1943
1944 b43_phy_write(dev, B43_PHY_RFOVER,
1945 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1946 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1947 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1948
1949 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1950 if (phy->rev >= 7) {
1951 b43_phy_write(dev, B43_PHY_RFOVER,
1952 b43_phy_read(dev, B43_PHY_RFOVER)
1953 | 0x0800);
1954 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1955 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1956 | 0x8000);
1957 }
1958 }
1959 b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1960 & 0x00F7);
1961
1962 j = 0;
1963 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1964 for (i = 0; i < loop_i_max; i++) {
1965 for (j = 0; j < 16; j++) {
1966 b43_radio_write16(dev, 0x43, i);
1967 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1968 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1969 & 0xF0FF) | (j << 8));
1970 b43_phy_write(dev, B43_PHY_PGACTL,
1971 (b43_phy_read(dev, B43_PHY_PGACTL)
1972 & 0x0FFF) | 0xA000);
1973 b43_phy_write(dev, B43_PHY_PGACTL,
1974 b43_phy_read(dev, B43_PHY_PGACTL)
1975 | 0xF000);
1976 udelay(20);
1977 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1978 goto exit_loop1;
1979 }
1980 }
1981 exit_loop1:
1982 loop1_outer_done = i;
1983 loop1_inner_done = j;
1984 if (j >= 8) {
1985 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1986 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1987 | 0x30);
1988 trsw_rx = 0x1B;
1989 for (j = j - 8; j < 16; j++) {
1990 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1991 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1992 & 0xF0FF) | (j << 8));
1993 b43_phy_write(dev, B43_PHY_PGACTL,
1994 (b43_phy_read(dev, B43_PHY_PGACTL)
1995 & 0x0FFF) | 0xA000);
1996 b43_phy_write(dev, B43_PHY_PGACTL,
1997 b43_phy_read(dev, B43_PHY_PGACTL)
1998 | 0xF000);
1999 udelay(20);
2000 trsw_rx -= 3;
2001 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
2002 goto exit_loop2;
2003 }
2004 } else
2005 trsw_rx = 0x18;
2006 exit_loop2:
2007
2008 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2009 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
2010 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
2011 }
2012 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
2013 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
2014 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
2015 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
2016 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
2017 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
2018 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
2019 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
2020 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
2021
2022 b43_gphy_set_baseband_attenuation(dev, backup_bband);
2023
2024 b43_radio_write16(dev, 0x52, backup_radio[0]);
2025 b43_radio_write16(dev, 0x43, backup_radio[1]);
2026 b43_radio_write16(dev, 0x7A, backup_radio[2]);
2027
2028 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
2029 udelay(10);
2030 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
2031 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
2032 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
2033 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
2034
2035 gphy->max_lb_gain =
2036 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
2037 gphy->trsw_rx_gain = trsw_rx * 2;
2038}
2039
2040static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
2041{
2042 struct b43_phy *phy = &dev->phy;
2043
2044 if (!b43_has_hardware_pctl(dev)) {
2045 b43_phy_write(dev, 0x047A, 0xC111);
2046 return;
2047 }
2048
2049 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
2050 b43_phy_write(dev, 0x002F, 0x0202);
2051 b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
2052 b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
2053 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
2054 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
2055 & 0xFF0F) | 0x0010);
2056 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
2057 | 0x8000);
2058 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
2059 & 0xFFC0) | 0x0010);
2060 b43_phy_write(dev, 0x002E, 0xC07F);
2061 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
2062 | 0x0400);
2063 } else {
2064 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
2065 | 0x0200);
2066 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
2067 | 0x0400);
2068 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
2069 & 0x7FFF);
2070 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
2071 & 0xFFFE);
2072 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
2073 & 0xFFC0) | 0x0010);
2074 b43_phy_write(dev, 0x002E, 0xC07F);
2075 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
2076 & 0xFF0F) | 0x0010);
2077 }
2078}
2079
2080/* Hardware power control for G-PHY */
2081static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
2082{
2083 struct b43_phy *phy = &dev->phy;
2084 struct b43_phy_g *gphy = phy->g;
2085
2086 if (!b43_has_hardware_pctl(dev)) {
2087 /* No hardware power control */
2088 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
2089 return;
2090 }
2091
2092 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
2093 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2094 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
2095 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2096 b43_gphy_tssi_power_lt_init(dev);
2097 b43_gphy_gain_lt_init(dev);
2098 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
2099 b43_phy_write(dev, 0x0014, 0x0000);
2100
2101 B43_WARN_ON(phy->rev < 6);
2102 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
2103 | 0x0800);
2104 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
2105 & 0xFEFF);
2106 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
2107 & 0xFFBF);
2108
2109 b43_gphy_dc_lt_init(dev, 1);
2110
2111 /* Enable hardware pctl in firmware. */
2112 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
2113}
2114
2115/* Intialize B/G PHY power control */
2116static void b43_phy_init_pctl(struct b43_wldev *dev)
2117{
2118 struct ssb_bus *bus = dev->dev->bus;
2119 struct b43_phy *phy = &dev->phy;
2120 struct b43_phy_g *gphy = phy->g;
2121 struct b43_rfatt old_rfatt;
2122 struct b43_bbatt old_bbatt;
2123 u8 old_tx_control = 0;
2124
2125 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2126
2127 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
2128 (bus->boardinfo.type == SSB_BOARD_BU4306))
2129 return;
2130
2131 b43_phy_write(dev, 0x0028, 0x8018);
2132
2133 /* This does something with the Analog... */
2134 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
2135 & 0xFFDF);
2136
2137 if (!phy->gmode)
2138 return;
2139 b43_hardware_pctl_early_init(dev);
2140 if (gphy->cur_idle_tssi == 0) {
2141 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2142 b43_radio_write16(dev, 0x0076,
2143 (b43_radio_read16(dev, 0x0076)
2144 & 0x00F7) | 0x0084);
2145 } else {
2146 struct b43_rfatt rfatt;
2147 struct b43_bbatt bbatt;
2148
2149 memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
2150 memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
2151 old_tx_control = gphy->tx_control;
2152
2153 bbatt.att = 11;
2154 if (phy->radio_rev == 8) {
2155 rfatt.att = 15;
2156 rfatt.with_padmix = 1;
2157 } else {
2158 rfatt.att = 9;
2159 rfatt.with_padmix = 0;
2160 }
2161 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
2162 }
2163 b43_dummy_transmission(dev);
2164 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
2165 if (B43_DEBUG) {
2166 /* Current-Idle-TSSI sanity check. */
2167 if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
2168 b43dbg(dev->wl,
2169 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
2170 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
2171 "adjustment.\n", gphy->cur_idle_tssi,
2172 gphy->tgt_idle_tssi);
2173 gphy->cur_idle_tssi = 0;
2174 }
2175 }
2176 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2177 b43_radio_write16(dev, 0x0076,
2178 b43_radio_read16(dev, 0x0076)
2179 & 0xFF7B);
2180 } else {
2181 b43_set_txpower_g(dev, &old_bbatt,
2182 &old_rfatt, old_tx_control);
2183 }
2184 }
2185 b43_hardware_pctl_init_gphy(dev);
2186 b43_shm_clear_tssi(dev);
2187}
2188
2189static void b43_phy_initg(struct b43_wldev *dev)
2190{
2191 struct b43_phy *phy = &dev->phy;
2192 struct b43_phy_g *gphy = phy->g;
2193 u16 tmp;
2194
2195 if (phy->rev == 1)
2196 b43_phy_initb5(dev);
2197 else
2198 b43_phy_initb6(dev);
2199
2200 if (phy->rev >= 2 || phy->gmode)
2201 b43_phy_inita(dev);
2202
2203 if (phy->rev >= 2) {
2204 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2205 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2206 }
2207 if (phy->rev == 2) {
2208 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2209 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2210 }
2211 if (phy->rev > 5) {
2212 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2213 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2214 }
2215 if (phy->gmode || phy->rev >= 2) {
2216 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2217 tmp &= B43_PHYVER_VERSION;
2218 if (tmp == 3 || tmp == 5) {
2219 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2220 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2221 }
2222 if (tmp == 5) {
2223 b43_phy_write(dev, B43_PHY_OFDM(0xCC),
2224 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
2225 & 0x00FF) | 0x1F00);
2226 }
2227 }
2228 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2229 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2230 if (phy->radio_rev == 8) {
2231 b43_phy_write(dev, B43_PHY_EXTG(0x01),
2232 b43_phy_read(dev, B43_PHY_EXTG(0x01))
2233 | 0x80);
2234 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
2235 b43_phy_read(dev, B43_PHY_OFDM(0x3E))
2236 | 0x4);
2237 }
2238 if (has_loopback_gain(phy))
2239 b43_calc_loopback_gain(dev);
2240
2241 if (phy->radio_rev != 8) {
2242 if (gphy->initval == 0xFFFF)
2243 gphy->initval = b43_radio_init2050(dev);
2244 else
2245 b43_radio_write16(dev, 0x0078, gphy->initval);
2246 }
2247 b43_lo_g_init(dev);
2248 if (has_tx_magnification(phy)) {
2249 b43_radio_write16(dev, 0x52,
2250 (b43_radio_read16(dev, 0x52) & 0xFF00)
2251 | gphy->lo_control->tx_bias | gphy->
2252 lo_control->tx_magn);
2253 } else {
2254 b43_radio_write16(dev, 0x52,
2255 (b43_radio_read16(dev, 0x52) & 0xFFF0)
2256 | gphy->lo_control->tx_bias);
2257 }
2258 if (phy->rev >= 6) {
2259 b43_phy_write(dev, B43_PHY_CCK(0x36),
2260 (b43_phy_read(dev, B43_PHY_CCK(0x36))
2261 & 0x0FFF) | (gphy->lo_control->
2262 tx_bias << 12));
2263 }
2264 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2265 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2266 else
2267 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2268 if (phy->rev < 2)
2269 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2270 else
2271 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2272 if (phy->gmode || phy->rev >= 2) {
2273 b43_lo_g_adjust(dev);
2274 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2275 }
2276
2277 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2278 /* The specs state to update the NRSSI LT with
2279 * the value 0x7FFFFFFF here. I think that is some weird
2280 * compiler optimization in the original driver.
2281 * Essentially, what we do here is resetting all NRSSI LT
2282 * entries to -32 (see the clamp_val() in nrssi_hw_update())
2283 */
2284 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
2285 b43_calc_nrssi_threshold(dev);
2286 } else if (phy->gmode || phy->rev >= 2) {
2287 if (gphy->nrssi[0] == -1000) {
2288 B43_WARN_ON(gphy->nrssi[1] != -1000);
2289 b43_calc_nrssi_slope(dev);
2290 } else
2291 b43_calc_nrssi_threshold(dev);
2292 }
2293 if (phy->radio_rev == 8)
2294 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2295 b43_phy_init_pctl(dev);
2296 /* FIXME: The spec says in the following if, the 0 should be replaced
2297 'if OFDM may not be used in the current locale'
2298 but OFDM is legal everywhere */
2299 if ((dev->dev->bus->chip_id == 0x4306
2300 && dev->dev->bus->chip_package == 2) || 0) {
2301 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
2302 & 0xBFFF);
2303 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
2304 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
2305 & 0x7FFF);
2306 }
2307}
2308
2309void b43_gphy_channel_switch(struct b43_wldev *dev,
2310 unsigned int channel,
2311 bool synthetic_pu_workaround)
2312{
2313 if (synthetic_pu_workaround)
2314 b43_synth_pu_workaround(dev, channel);
2315
2316 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2317
2318 if (channel == 14) {
2319 if (dev->dev->bus->sprom.country_code ==
2320 SSB_SPROM1CCODE_JAPAN)
2321 b43_hf_write(dev,
2322 b43_hf_read(dev) & ~B43_HF_ACPR);
2323 else
2324 b43_hf_write(dev,
2325 b43_hf_read(dev) | B43_HF_ACPR);
2326 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2327 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2328 | (1 << 11));
2329 } else {
2330 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2331 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2332 & 0xF7BF);
2333 }
2334}
2335
2336static void default_baseband_attenuation(struct b43_wldev *dev,
2337 struct b43_bbatt *bb)
2338{
2339 struct b43_phy *phy = &dev->phy;
2340
2341 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2342 bb->att = 0;
2343 else
2344 bb->att = 2;
2345}
2346
2347static void default_radio_attenuation(struct b43_wldev *dev,
2348 struct b43_rfatt *rf)
2349{
2350 struct ssb_bus *bus = dev->dev->bus;
2351 struct b43_phy *phy = &dev->phy;
2352
2353 rf->with_padmix = 0;
2354
2355 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2356 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2357 if (bus->boardinfo.rev < 0x43) {
2358 rf->att = 2;
2359 return;
2360 } else if (bus->boardinfo.rev < 0x51) {
2361 rf->att = 3;
2362 return;
2363 }
2364 }
2365
2366 if (phy->type == B43_PHYTYPE_A) {
2367 rf->att = 0x60;
2368 return;
2369 }
2370
2371 switch (phy->radio_ver) {
2372 case 0x2053:
2373 switch (phy->radio_rev) {
2374 case 1:
2375 rf->att = 6;
2376 return;
2377 }
2378 break;
2379 case 0x2050:
2380 switch (phy->radio_rev) {
2381 case 0:
2382 rf->att = 5;
2383 return;
2384 case 1:
2385 if (phy->type == B43_PHYTYPE_G) {
2386 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2387 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2388 && bus->boardinfo.rev >= 30)
2389 rf->att = 3;
2390 else if (bus->boardinfo.vendor ==
2391 SSB_BOARDVENDOR_BCM
2392 && bus->boardinfo.type ==
2393 SSB_BOARD_BU4306)
2394 rf->att = 3;
2395 else
2396 rf->att = 1;
2397 } else {
2398 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2399 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2400 && bus->boardinfo.rev >= 30)
2401 rf->att = 7;
2402 else
2403 rf->att = 6;
2404 }
2405 return;
2406 case 2:
2407 if (phy->type == B43_PHYTYPE_G) {
2408 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2409 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2410 && bus->boardinfo.rev >= 30)
2411 rf->att = 3;
2412 else if (bus->boardinfo.vendor ==
2413 SSB_BOARDVENDOR_BCM
2414 && bus->boardinfo.type ==
2415 SSB_BOARD_BU4306)
2416 rf->att = 5;
2417 else if (bus->chip_id == 0x4320)
2418 rf->att = 4;
2419 else
2420 rf->att = 3;
2421 } else
2422 rf->att = 6;
2423 return;
2424 case 3:
2425 rf->att = 5;
2426 return;
2427 case 4:
2428 case 5:
2429 rf->att = 1;
2430 return;
2431 case 6:
2432 case 7:
2433 rf->att = 5;
2434 return;
2435 case 8:
2436 rf->att = 0xA;
2437 rf->with_padmix = 1;
2438 return;
2439 case 9:
2440 default:
2441 rf->att = 5;
2442 return;
2443 }
2444 }
2445 rf->att = 5;
2446}
2447
2448static u16 default_tx_control(struct b43_wldev *dev)
2449{
2450 struct b43_phy *phy = &dev->phy;
2451
2452 if (phy->radio_ver != 0x2050)
2453 return 0;
2454 if (phy->radio_rev == 1)
2455 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2456 if (phy->radio_rev < 6)
2457 return B43_TXCTL_PA2DB;
2458 if (phy->radio_rev == 8)
2459 return B43_TXCTL_TXMIX;
2460 return 0;
2461}
2462
2463static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2464{
2465 struct b43_phy *phy = &dev->phy;
2466 struct b43_phy_g *gphy = phy->g;
2467 u8 ret = 0;
2468 u16 saved, rssi, temp;
2469 int i, j = 0;
2470
2471 saved = b43_phy_read(dev, 0x0403);
2472 b43_switch_channel(dev, channel);
2473 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2474 if (gphy->aci_hw_rssi)
2475 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2476 else
2477 rssi = saved & 0x3F;
2478 /* clamp temp to signed 5bit */
2479 if (rssi > 32)
2480 rssi -= 64;
2481 for (i = 0; i < 100; i++) {
2482 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2483 if (temp > 32)
2484 temp -= 64;
2485 if (temp < rssi)
2486 j++;
2487 if (j >= 20)
2488 ret = 1;
2489 }
2490 b43_phy_write(dev, 0x0403, saved);
2491
2492 return ret;
2493}
2494
2495static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2496{
2497 struct b43_phy *phy = &dev->phy;
2498 u8 ret[13];
2499 unsigned int channel = phy->channel;
2500 unsigned int i, j, start, end;
2501
2502 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2503 return 0;
2504
2505 b43_phy_lock(dev);
2506 b43_radio_lock(dev);
2507 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2508 b43_phy_write(dev, B43_PHY_G_CRS,
2509 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2510 b43_set_all_gains(dev, 3, 8, 1);
2511
2512 start = (channel - 5 > 0) ? channel - 5 : 1;
2513 end = (channel + 5 < 14) ? channel + 5 : 13;
2514
2515 for (i = start; i <= end; i++) {
2516 if (abs(channel - i) > 2)
2517 ret[i - 1] = b43_gphy_aci_detect(dev, i);
2518 }
2519 b43_switch_channel(dev, channel);
2520 b43_phy_write(dev, 0x0802,
2521 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2522 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2523 b43_phy_write(dev, B43_PHY_G_CRS,
2524 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2525 b43_set_original_gains(dev);
2526 for (i = 0; i < 13; i++) {
2527 if (!ret[i])
2528 continue;
2529 end = (i + 5 < 13) ? i + 5 : 13;
2530 for (j = i; j < end; j++)
2531 ret[j] = 1;
2532 }
2533 b43_radio_unlock(dev);
2534 b43_phy_unlock(dev);
2535
2536 return ret[channel - 1];
2537}
2538
2539static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2540{
2541 if (num < 0)
2542 return num / den;
2543 else
2544 return (num + den / 2) / den;
2545}
2546
2547static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2548 s16 pab0, s16 pab1, s16 pab2)
2549{
2550 s32 m1, m2, f = 256, q, delta;
2551 s8 i = 0;
2552
2553 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2554 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2555 do {
2556 if (i > 15)
2557 return -EINVAL;
2558 q = b43_tssi2dbm_ad(f * 4096 -
2559 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2560 delta = abs(q - f);
2561 f = q;
2562 i++;
2563 } while (delta >= 2);
2564 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2565 return 0;
2566}
2567
2568u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2569 s16 pab0, s16 pab1, s16 pab2)
2570{
2571 unsigned int i;
2572 u8 *tab;
2573 int err;
2574
2575 tab = kmalloc(64, GFP_KERNEL);
2576 if (!tab) {
2577 b43err(dev->wl, "Could not allocate memory "
2578 "for tssi2dbm table\n");
2579 return NULL;
2580 }
2581 for (i = 0; i < 64; i++) {
2582 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2583 if (err) {
2584 b43err(dev->wl, "Could not generate "
2585 "tssi2dBm table\n");
2586 kfree(tab);
2587 return NULL;
2588 }
2589 }
2590
2591 return tab;
2592}
2593
2594/* Initialise the TSSI->dBm lookup table */
2595static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2596{
2597 struct b43_phy *phy = &dev->phy;
2598 struct b43_phy_g *gphy = phy->g;
2599 s16 pab0, pab1, pab2;
2600
2601 pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
2602 pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
2603 pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
2604
2605 B43_WARN_ON((dev->dev->bus->chip_id == 0x4301) &&
2606 (phy->radio_ver != 0x2050)); /* Not supported anymore */
2607
2608 gphy->dyn_tssi_tbl = 0;
2609
2610 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2611 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2612 /* The pabX values are set in SPROM. Use them. */
2613 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
2614 (s8) dev->dev->bus->sprom.itssi_bg != -1) {
2615 gphy->tgt_idle_tssi =
2616 (s8) (dev->dev->bus->sprom.itssi_bg);
2617 } else
2618 gphy->tgt_idle_tssi = 62;
2619 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2620 pab1, pab2);
2621 if (!gphy->tssi2dbm)
2622 return -ENOMEM;
2623 gphy->dyn_tssi_tbl = 1;
2624 } else {
2625 /* pabX values not set in SPROM. */
2626 gphy->tgt_idle_tssi = 52;
2627 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2628 }
2629
2630 return 0;
2631}
2632
2633static int b43_gphy_op_allocate(struct b43_wldev *dev)
2634{
2635 struct b43_phy_g *gphy;
2636 struct b43_txpower_lo_control *lo;
2637 int err, i;
2638
2639 gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2640 if (!gphy) {
2641 err = -ENOMEM;
2642 goto error;
2643 }
2644 dev->phy.g = gphy;
2645
2646 memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2647
2648 /* NRSSI */
2649 for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2650 gphy->nrssi[i] = -1000;
2651 for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2652 gphy->nrssi_lt[i] = i;
2653
2654 gphy->lofcal = 0xFFFF;
2655 gphy->initval = 0xFFFF;
2656
2657 gphy->interfmode = B43_INTERFMODE_NONE;
2658
2659 /* OFDM-table address caching. */
2660 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2661
2662
2663 lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2664 if (!lo) {
2665 err = -ENOMEM;
2666 goto err_free_gphy;
2667 }
2668 gphy->lo_control = lo;
2669
2670 lo->tx_bias = 0xFF;
2671 INIT_LIST_HEAD(&lo->calib_list);
2672
2673 err = b43_gphy_init_tssi2dbm_table(dev);
2674 if (err)
2675 goto err_free_lo;
2676
2677 return 0;
2678
2679err_free_lo:
2680 kfree(lo);
2681err_free_gphy:
2682 kfree(gphy);
2683error:
2684 return err;
2685}
2686
2687static int b43_gphy_op_prepare(struct b43_wldev *dev)
2688{
2689 struct b43_phy *phy = &dev->phy;
2690 struct b43_phy_g *gphy = phy->g;
2691 struct b43_txpower_lo_control *lo = gphy->lo_control;
2692
2693 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2694
2695 default_baseband_attenuation(dev, &gphy->bbatt);
2696 default_radio_attenuation(dev, &gphy->rfatt);
2697 gphy->tx_control = (default_tx_control(dev) << 4);
2698 generate_rfatt_list(dev, &lo->rfatt_list);
2699 generate_bbatt_list(dev, &lo->bbatt_list);
2700
2701 /* Commit previous writes */
2702 b43_read32(dev, B43_MMIO_MACCTL);
2703
2704 if (phy->rev == 1) {
2705 /* Workaround: Temporarly disable gmode through the early init
2706 * phase, as the gmode stuff is not needed for phy rev 1 */
2707 phy->gmode = 0;
2708 b43_wireless_core_reset(dev, 0);
2709 b43_phy_initg(dev);
2710 phy->gmode = 1;
2711 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2712 }
2713
2714 return 0;
2715}
2716
2717static int b43_gphy_op_init(struct b43_wldev *dev)
2718{
2719 struct b43_phy_g *gphy = dev->phy.g;
2720
2721 b43_phy_initg(dev);
2722 gphy->initialised = 1;
2723
2724 return 0;
2725}
2726
2727static void b43_gphy_op_exit(struct b43_wldev *dev)
2728{
2729 struct b43_phy_g *gphy = dev->phy.g;
2730
2731 if (gphy->initialised) {
2732 //TODO
2733 gphy->initialised = 0;
2734 }
2735 b43_lo_g_cleanup(dev);
2736 kfree(gphy->lo_control);
2737 if (gphy->dyn_tssi_tbl)
2738 kfree(gphy->tssi2dbm);
2739 kfree(gphy);
2740 dev->phy.g = NULL;
2741}
2742
2743static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2744{
2745 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2746 return b43_read16(dev, B43_MMIO_PHY_DATA);
2747}
2748
2749static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2750{
2751 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2752 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2753}
2754
2755static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2756{
2757 /* Register 1 is a 32-bit register. */
2758 B43_WARN_ON(reg == 1);
2759 /* G-PHY needs 0x80 for read access. */
2760 reg |= 0x80;
2761
2762 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2763 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2764}
2765
2766static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2767{
2768 /* Register 1 is a 32-bit register. */
2769 B43_WARN_ON(reg == 1);
2770
2771 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2772 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2773}
2774
2775static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2776{
2777 return (dev->phy.rev >= 6);
2778}
2779
2780static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2781 enum rfkill_state state)
2782{
2783 struct b43_phy *phy = &dev->phy;
2784 struct b43_phy_g *gphy = phy->g;
2785 unsigned int channel;
2786
2787 might_sleep();
2788
2789 if (state == RFKILL_STATE_UNBLOCKED) {
2790 /* Turn radio ON */
2791 if (phy->radio_on)
2792 return;
2793
2794 b43_phy_write(dev, 0x0015, 0x8000);
2795 b43_phy_write(dev, 0x0015, 0xCC00);
2796 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2797 if (gphy->radio_off_context.valid) {
2798 /* Restore the RFover values. */
2799 b43_phy_write(dev, B43_PHY_RFOVER,
2800 gphy->radio_off_context.rfover);
2801 b43_phy_write(dev, B43_PHY_RFOVERVAL,
2802 gphy->radio_off_context.rfoverval);
2803 gphy->radio_off_context.valid = 0;
2804 }
2805 channel = phy->channel;
2806 b43_gphy_channel_switch(dev, 6, 1);
2807 b43_gphy_channel_switch(dev, channel, 0);
2808 } else {
2809 /* Turn radio OFF */
2810 u16 rfover, rfoverval;
2811
2812 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2813 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2814 gphy->radio_off_context.rfover = rfover;
2815 gphy->radio_off_context.rfoverval = rfoverval;
2816 gphy->radio_off_context.valid = 1;
2817 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2818 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2819 }
2820}
2821
2822static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2823 unsigned int new_channel)
2824{
2825 if ((new_channel < 1) || (new_channel > 14))
2826 return -EINVAL;
2827 b43_gphy_channel_switch(dev, new_channel, 0);
2828
2829 return 0;
2830}
2831
2832static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2833{
2834 return 1; /* Default to channel 1 */
2835}
2836
2837static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2838{
2839 struct b43_phy *phy = &dev->phy;
2840 u64 hf;
2841 u16 tmp;
2842 int autodiv = 0;
2843
2844 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2845 autodiv = 1;
2846
2847 hf = b43_hf_read(dev);
2848 hf &= ~B43_HF_ANTDIVHELP;
2849 b43_hf_write(dev, hf);
2850
2851 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2852 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2853 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2854 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2855 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2856
2857 if (autodiv) {
2858 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2859 if (antenna == B43_ANTENNA_AUTO0)
2860 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2861 else
2862 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2863 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2864 }
2865 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2866 if (autodiv)
2867 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2868 else
2869 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2870 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2871 if (phy->rev >= 2) {
2872 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2873 tmp |= B43_PHY_OFDM61_10;
2874 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2875
2876 tmp =
2877 b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2878 tmp = (tmp & 0xFF00) | 0x15;
2879 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2880 tmp);
2881
2882 if (phy->rev == 2) {
2883 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2884 8);
2885 } else {
2886 tmp =
2887 b43_phy_read(dev,
2888 B43_PHY_ADIVRELATED);
2889 tmp = (tmp & 0xFF00) | 8;
2890 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2891 tmp);
2892 }
2893 }
2894 if (phy->rev >= 6)
2895 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2896
2897 hf |= B43_HF_ANTDIVHELP;
2898 b43_hf_write(dev, hf);
2899}
2900
2901static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2902 enum b43_interference_mitigation mode)
2903{
2904 struct b43_phy *phy = &dev->phy;
2905 struct b43_phy_g *gphy = phy->g;
2906 int currentmode;
2907
2908 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2909 if ((phy->rev == 0) || (!phy->gmode))
2910 return -ENODEV;
2911
2912 gphy->aci_wlan_automatic = 0;
2913 switch (mode) {
2914 case B43_INTERFMODE_AUTOWLAN:
2915 gphy->aci_wlan_automatic = 1;
2916 if (gphy->aci_enable)
2917 mode = B43_INTERFMODE_MANUALWLAN;
2918 else
2919 mode = B43_INTERFMODE_NONE;
2920 break;
2921 case B43_INTERFMODE_NONE:
2922 case B43_INTERFMODE_NONWLAN:
2923 case B43_INTERFMODE_MANUALWLAN:
2924 break;
2925 default:
2926 return -EINVAL;
2927 }
2928
2929 currentmode = gphy->interfmode;
2930 if (currentmode == mode)
2931 return 0;
2932 if (currentmode != B43_INTERFMODE_NONE)
2933 b43_radio_interference_mitigation_disable(dev, currentmode);
2934
2935 if (mode == B43_INTERFMODE_NONE) {
2936 gphy->aci_enable = 0;
2937 gphy->aci_hw_rssi = 0;
2938 } else
2939 b43_radio_interference_mitigation_enable(dev, mode);
2940 gphy->interfmode = mode;
2941
2942 return 0;
2943}
2944
2945/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2946 * This function converts a TSSI value to dBm in Q5.2
2947 */
2948static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2949{
2950 struct b43_phy_g *gphy = dev->phy.g;
2951 s8 dbm;
2952 s32 tmp;
2953
2954 tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2955 tmp = clamp_val(tmp, 0x00, 0x3F);
2956 dbm = gphy->tssi2dbm[tmp];
2957
2958 return dbm;
2959}
2960
2961static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2962 int *_bbatt, int *_rfatt)
2963{
2964 int rfatt = *_rfatt;
2965 int bbatt = *_bbatt;
2966 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2967
2968 /* Get baseband and radio attenuation values into their permitted ranges.
2969 * Radio attenuation affects power level 4 times as much as baseband. */
2970
2971 /* Range constants */
2972 const int rf_min = lo->rfatt_list.min_val;
2973 const int rf_max = lo->rfatt_list.max_val;
2974 const int bb_min = lo->bbatt_list.min_val;
2975 const int bb_max = lo->bbatt_list.max_val;
2976
2977 while (1) {
2978 if (rfatt > rf_max && bbatt > bb_max - 4)
2979 break; /* Can not get it into ranges */
2980 if (rfatt < rf_min && bbatt < bb_min + 4)
2981 break; /* Can not get it into ranges */
2982 if (bbatt > bb_max && rfatt > rf_max - 1)
2983 break; /* Can not get it into ranges */
2984 if (bbatt < bb_min && rfatt < rf_min + 1)
2985 break; /* Can not get it into ranges */
2986
2987 if (bbatt > bb_max) {
2988 bbatt -= 4;
2989 rfatt += 1;
2990 continue;
2991 }
2992 if (bbatt < bb_min) {
2993 bbatt += 4;
2994 rfatt -= 1;
2995 continue;
2996 }
2997 if (rfatt > rf_max) {
2998 rfatt -= 1;
2999 bbatt += 4;
3000 continue;
3001 }
3002 if (rfatt < rf_min) {
3003 rfatt += 1;
3004 bbatt -= 4;
3005 continue;
3006 }
3007 break;
3008 }
3009
3010 *_rfatt = clamp_val(rfatt, rf_min, rf_max);
3011 *_bbatt = clamp_val(bbatt, bb_min, bb_max);
3012}
3013
3014static void b43_gphy_op_xmitpower(struct b43_wldev *dev)
3015{
3016 struct ssb_bus *bus = dev->dev->bus;
3017 struct b43_phy *phy = &dev->phy;
3018 struct b43_phy_g *gphy = phy->g;
3019 u16 tmp;
3020 s8 v0, v1, v2, v3;
3021 s8 average;
3022 int max_pwr;
3023 int desired_pwr, estimated_pwr, pwr_adjust;
3024 int rfatt_delta, bbatt_delta;
3025 int rfatt, bbatt;
3026 u8 tx_control;
3027
3028 if (gphy->cur_idle_tssi == 0)
3029 return;
3030 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
3031 (bus->boardinfo.type == SSB_BOARD_BU4306))
3032 return;
3033
3034 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
3035 v0 = (s8) (tmp & 0x00FF);
3036 v1 = (s8) ((tmp & 0xFF00) >> 8);
3037 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
3038 v2 = (s8) (tmp & 0x00FF);
3039 v3 = (s8) ((tmp & 0xFF00) >> 8);
3040 tmp = 0;
3041
3042 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
3043 || v3 == 0x7F) {
3044 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
3045 v0 = (s8) (tmp & 0x00FF);
3046 v1 = (s8) ((tmp & 0xFF00) >> 8);
3047 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
3048 v2 = (s8) (tmp & 0x00FF);
3049 v3 = (s8) ((tmp & 0xFF00) >> 8);
3050 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
3051 || v3 == 0x7F)
3052 return;
3053 v0 = (v0 + 0x20) & 0x3F;
3054 v1 = (v1 + 0x20) & 0x3F;
3055 v2 = (v2 + 0x20) & 0x3F;
3056 v3 = (v3 + 0x20) & 0x3F;
3057 tmp = 1;
3058 }
3059 b43_shm_clear_tssi(dev);
3060
3061 average = (v0 + v1 + v2 + v3 + 2) / 4;
3062
3063 if (tmp && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) & 0x8))
3064 average -= 13;
3065
3066 estimated_pwr = b43_gphy_estimate_power_out(dev, average);
3067
3068 max_pwr = dev->dev->bus->sprom.maxpwr_bg;
3069 if ((dev->dev->bus->sprom.boardflags_lo
3070 & B43_BFL_PACTRL) && (phy->type == B43_PHYTYPE_G))
3071 max_pwr -= 0x3;
3072 if (unlikely(max_pwr <= 0)) {
3073 b43warn(dev->wl,
3074 "Invalid max-TX-power value in SPROM.\n");
3075 max_pwr = 60; /* fake it */
3076 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
3077 }
3078
3079 /*TODO:
3080 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
3081 where REG is the max power as per the regulatory domain
3082 */
3083
3084 /* Get desired power (in Q5.2) */
3085 desired_pwr = INT_TO_Q52(phy->power_level);
3086 /* And limit it. max_pwr already is Q5.2 */
3087 desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
3088 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
3089 b43dbg(dev->wl,
3090 "Current TX power output: " Q52_FMT
3091 " dBm, " "Desired TX power output: "
3092 Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
3093 Q52_ARG(desired_pwr));
3094 }
3095
3096 /* Calculate the adjustment delta. */
3097 pwr_adjust = desired_pwr - estimated_pwr;
3098
3099 /* RF attenuation delta. */
3100 rfatt_delta = ((pwr_adjust + 7) / 8);
3101 /* Lower attenuation => Bigger power output. Negate it. */
3102 rfatt_delta = -rfatt_delta;
3103
3104 /* Baseband attenuation delta. */
3105 bbatt_delta = pwr_adjust / 2;
3106 /* Lower attenuation => Bigger power output. Negate it. */
3107 bbatt_delta = -bbatt_delta;
3108 /* RF att affects power level 4 times as much as
3109 * Baseband attennuation. Subtract it. */
3110 bbatt_delta -= 4 * rfatt_delta;
3111
3112 /* So do we finally need to adjust something? */
3113 if ((rfatt_delta == 0) && (bbatt_delta == 0))
3114 return;
3115
3116 /* Calculate the new attenuation values. */
3117 bbatt = gphy->bbatt.att;
3118 bbatt += bbatt_delta;
3119 rfatt = gphy->rfatt.att;
3120 rfatt += rfatt_delta;
3121
3122 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
3123 tx_control = gphy->tx_control;
3124 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
3125 if (rfatt <= 1) {
3126 if (tx_control == 0) {
3127 tx_control =
3128 B43_TXCTL_PA2DB |
3129 B43_TXCTL_TXMIX;
3130 rfatt += 2;
3131 bbatt += 2;
3132 } else if (dev->dev->bus->sprom.
3133 boardflags_lo &
3134 B43_BFL_PACTRL) {
3135 bbatt += 4 * (rfatt - 2);
3136 rfatt = 2;
3137 }
3138 } else if (rfatt > 4 && tx_control) {
3139 tx_control = 0;
3140 if (bbatt < 3) {
3141 rfatt -= 3;
3142 bbatt += 2;
3143 } else {
3144 rfatt -= 2;
3145 bbatt -= 2;
3146 }
3147 }
3148 }
3149 /* Save the control values */
3150 gphy->tx_control = tx_control;
3151 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
3152 gphy->rfatt.att = rfatt;
3153 gphy->bbatt.att = bbatt;
3154
3155 /* Adjust the hardware */
3156 b43_phy_lock(dev);
3157 b43_radio_lock(dev);
3158 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
3159 gphy->tx_control);
3160 b43_radio_unlock(dev);
3161 b43_phy_unlock(dev);
3162}
3163
3164static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
3165{
3166 struct b43_phy *phy = &dev->phy;
3167 struct b43_phy_g *gphy = phy->g;
3168
3169 //TODO: update_aci_moving_average
3170 if (gphy->aci_enable && gphy->aci_wlan_automatic) {
3171 b43_mac_suspend(dev);
3172 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) {
3173 if (0 /*TODO: bunch of conditions */ ) {
3174 phy->ops->interf_mitigation(dev,
3175 B43_INTERFMODE_MANUALWLAN);
3176 }
3177 } else if (0 /*TODO*/) {
3178 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3179 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3180 }
3181 b43_mac_enable(dev);
3182 } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3183 phy->rev == 1) {
3184 //TODO: implement rev1 workaround
3185 }
3186 b43_lo_g_maintanance_work(dev);
3187}
3188
3189static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3190{
3191 struct b43_phy *phy = &dev->phy;
3192
3193 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI))
3194 return;
3195
3196 b43_mac_suspend(dev);
3197 b43_calc_nrssi_slope(dev);
3198 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3199 u8 old_chan = phy->channel;
3200
3201 /* VCO Calibration */
3202 if (old_chan >= 8)
3203 b43_switch_channel(dev, 1);
3204 else
3205 b43_switch_channel(dev, 13);
3206 b43_switch_channel(dev, old_chan);
3207 }
3208 b43_mac_enable(dev);
3209}
3210
3211const struct b43_phy_operations b43_phyops_g = {
3212 .allocate = b43_gphy_op_allocate,
3213 .prepare = b43_gphy_op_prepare,
3214 .init = b43_gphy_op_init,
3215 .exit = b43_gphy_op_exit,
3216 .phy_read = b43_gphy_op_read,
3217 .phy_write = b43_gphy_op_write,
3218 .radio_read = b43_gphy_op_radio_read,
3219 .radio_write = b43_gphy_op_radio_write,
3220 .supports_hwpctl = b43_gphy_op_supports_hwpctl,
3221 .software_rfkill = b43_gphy_op_software_rfkill,
3222 .switch_channel = b43_gphy_op_switch_channel,
3223 .get_default_chan = b43_gphy_op_get_default_chan,
3224 .set_rx_antenna = b43_gphy_op_set_rx_antenna,
3225 .interf_mitigation = b43_gphy_op_interf_mitigation,
3226 .xmitpower = b43_gphy_op_xmitpower,
3227 .pwork_15sec = b43_gphy_op_pwork_15sec,
3228 .pwork_60sec = b43_gphy_op_pwork_60sec,
3229};
diff --git a/drivers/net/wireless/b43/phy_g.h b/drivers/net/wireless/b43/phy_g.h
new file mode 100644
index 000000000000..1f0daebd6eb6
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_g.h
@@ -0,0 +1,201 @@
1#ifndef LINUX_B43_PHY_G_H_
2#define LINUX_B43_PHY_G_H_
3
4/* OFDM PHY registers are defined in the A-PHY header. */
5#include "phy_a.h"
6
7/* CCK (B) PHY Registers */
8#define B43_PHY_VERSION_CCK B43_PHY_CCK(0x00) /* Versioning register for B-PHY */
9#define B43_PHY_CCKBBANDCFG B43_PHY_CCK(0x01) /* Contains antenna 0/1 control bit */
10#define B43_PHY_PGACTL B43_PHY_CCK(0x15) /* PGA control */
11#define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
12#define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
13#define B43_PHY_PGACTL_UNKNOWN 0xEFA0
14#define B43_PHY_FBCTL1 B43_PHY_CCK(0x18) /* Frequency bandwidth control 1 */
15#define B43_PHY_ITSSI B43_PHY_CCK(0x29) /* Idle TSSI */
16#define B43_PHY_LO_LEAKAGE B43_PHY_CCK(0x2D) /* Measured LO leakage */
17#define B43_PHY_ENERGY B43_PHY_CCK(0x33) /* Energy */
18#define B43_PHY_SYNCCTL B43_PHY_CCK(0x35)
19#define B43_PHY_FBCTL2 B43_PHY_CCK(0x38) /* Frequency bandwidth control 2 */
20#define B43_PHY_DACCTL B43_PHY_CCK(0x60) /* DAC control */
21#define B43_PHY_RCCALOVER B43_PHY_CCK(0x78) /* RC calibration override */
22
23/* Extended G-PHY Registers */
24#define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
25#define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */
26#define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
27#define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
28#define B43_PHY_GTABNR_SHIFT 10
29#define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */
30#define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */
31#define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */
32#define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */
33#define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */
34#define B43_PHY_RFOVERVAL_EXTLNA 0x8000
35#define B43_PHY_RFOVERVAL_LNA 0x7000
36#define B43_PHY_RFOVERVAL_LNA_SHIFT 12
37#define B43_PHY_RFOVERVAL_PGA 0x0F00
38#define B43_PHY_RFOVERVAL_PGA_SHIFT 8
39#define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */
40#define B43_PHY_RFOVERVAL_TRSWRX 0x00E0
41#define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */
42#define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */
43#define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */
44#define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */
45#define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */
46
47
48/*** G-PHY table numbers */
49#define B43_GTAB(number, offset) (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
50#define B43_GTAB_NRSSI B43_GTAB(0x00, 0)
51#define B43_GTAB_TRFEMW B43_GTAB(0x0C, 0x120)
52#define B43_GTAB_ORIGTR B43_GTAB(0x2E, 0x298)
53
54u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);
55void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);
56
57
58/* Returns the boolean whether "TX Magnification" is enabled. */
59#define has_tx_magnification(phy) \
60 (((phy)->rev >= 2) && \
61 ((phy)->radio_ver == 0x2050) && \
62 ((phy)->radio_rev == 8))
63/* Card uses the loopback gain stuff */
64#define has_loopback_gain(phy) \
65 (((phy)->rev > 1) || ((phy)->gmode))
66
67/* Radio Attenuation (RF Attenuation) */
68struct b43_rfatt {
69 u8 att; /* Attenuation value */
70 bool with_padmix; /* Flag, PAD Mixer enabled. */
71};
72struct b43_rfatt_list {
73 /* Attenuation values list */
74 const struct b43_rfatt *list;
75 u8 len;
76 /* Minimum/Maximum attenuation values */
77 u8 min_val;
78 u8 max_val;
79};
80
81/* Returns true, if the values are the same. */
82static inline bool b43_compare_rfatt(const struct b43_rfatt *a,
83 const struct b43_rfatt *b)
84{
85 return ((a->att == b->att) &&
86 (a->with_padmix == b->with_padmix));
87}
88
89/* Baseband Attenuation */
90struct b43_bbatt {
91 u8 att; /* Attenuation value */
92};
93struct b43_bbatt_list {
94 /* Attenuation values list */
95 const struct b43_bbatt *list;
96 u8 len;
97 /* Minimum/Maximum attenuation values */
98 u8 min_val;
99 u8 max_val;
100};
101
102/* Returns true, if the values are the same. */
103static inline bool b43_compare_bbatt(const struct b43_bbatt *a,
104 const struct b43_bbatt *b)
105{
106 return (a->att == b->att);
107}
108
109/* tx_control bits. */
110#define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */
111#define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */
112#define B43_TXCTL_TXMIX 0x10 /* TX Mixer Gain */
113
114struct b43_txpower_lo_control;
115
116struct b43_phy_g {
117 bool initialised;
118 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
119
120 /* ACI (adjacent channel interference) flags. */
121 bool aci_enable;
122 bool aci_wlan_automatic;
123 bool aci_hw_rssi;
124
125 /* Radio switched on/off */
126 bool radio_on;
127 struct {
128 /* Values saved when turning the radio off.
129 * They are needed when turning it on again. */
130 bool valid;
131 u16 rfover;
132 u16 rfoverval;
133 } radio_off_context;
134
135 u16 minlowsig[2];
136 u16 minlowsigpos[2];
137
138 /* TSSI to dBm table in use */
139 const s8 *tssi2dbm;
140 /* Target idle TSSI */
141 int tgt_idle_tssi;
142 /* Current idle TSSI */
143 int cur_idle_tssi;
144
145 /* LocalOscillator control values. */
146 struct b43_txpower_lo_control *lo_control;
147 /* Values from b43_calc_loopback_gain() */
148 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
149 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
150 s16 lna_lod_gain; /* LNA lod */
151 s16 lna_gain; /* LNA */
152 s16 pga_gain; /* PGA */
153
154 /* Current TX power level attenuation control values */
155 struct b43_bbatt bbatt;
156 struct b43_rfatt rfatt;
157 u8 tx_control; /* B43_TXCTL_XXX */
158
159 /* Current Interference Mitigation mode */
160 int interfmode;
161 /* Stack of saved values from the Interference Mitigation code.
162 * Each value in the stack is layed out as follows:
163 * bit 0-11: offset
164 * bit 12-15: register ID
165 * bit 16-32: value
166 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
167 */
168#define B43_INTERFSTACK_SIZE 26
169 u32 interfstack[B43_INTERFSTACK_SIZE]; //FIXME: use a data structure
170
171 /* Saved values from the NRSSI Slope calculation */
172 s16 nrssi[2];
173 s32 nrssislope;
174 /* In memory nrssi lookup table. */
175 s8 nrssi_lt[64];
176
177 u16 lofcal;
178
179 u16 initval; //FIXME rename?
180
181 /* The device does address auto increment for the OFDM tables.
182 * We cache the previously used address here and omit the address
183 * write on the next table access, if possible. */
184 u16 ofdmtab_addr; /* The address currently set in hardware. */
185 enum { /* The last data flow direction. */
186 B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
187 B43_OFDMTAB_DIRECTION_READ,
188 B43_OFDMTAB_DIRECTION_WRITE,
189 } ofdmtab_addr_direction;
190};
191
192void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
193 u16 baseband_attenuation);
194void b43_gphy_channel_switch(struct b43_wldev *dev,
195 unsigned int channel,
196 bool synthetic_pu_workaround);
197
198struct b43_phy_operations;
199extern const struct b43_phy_operations b43_phyops_g;
200
201#endif /* LINUX_B43_PHY_G_H_ */
diff --git a/drivers/net/wireless/b43/rfkill.c b/drivers/net/wireless/b43/rfkill.c
index fec5645944a4..7b9e99adb8c3 100644
--- a/drivers/net/wireless/b43/rfkill.c
+++ b/drivers/net/wireless/b43/rfkill.c
@@ -24,6 +24,7 @@
24 24
25#include "rfkill.h" 25#include "rfkill.h"
26#include "b43.h" 26#include "b43.h"
27#include "phy_common.h"
27 28
28#include <linux/kmod.h> 29#include <linux/kmod.h>
29 30
@@ -114,11 +115,11 @@ static int b43_rfkill_soft_toggle(void *data, enum rfkill_state state)
114 goto out_unlock; 115 goto out_unlock;
115 } 116 }
116 if (!dev->phy.radio_on) 117 if (!dev->phy.radio_on)
117 b43_radio_turn_on(dev); 118 b43_software_rfkill(dev, state);
118 break; 119 break;
119 case RFKILL_STATE_SOFT_BLOCKED: 120 case RFKILL_STATE_SOFT_BLOCKED:
120 if (dev->phy.radio_on) 121 if (dev->phy.radio_on)
121 b43_radio_turn_off(dev, 0); 122 b43_software_rfkill(dev, state);
122 break; 123 break;
123 default: 124 default:
124 b43warn(wl, "Received unexpected rfkill state %d.\n", state); 125 b43warn(wl, "Received unexpected rfkill state %d.\n", state);
diff --git a/drivers/net/wireless/b43/sysfs.c b/drivers/net/wireless/b43/sysfs.c
index 275095b8cbe7..5adaa3692d75 100644
--- a/drivers/net/wireless/b43/sysfs.c
+++ b/drivers/net/wireless/b43/sysfs.c
@@ -29,7 +29,7 @@
29#include "b43.h" 29#include "b43.h"
30#include "sysfs.h" 30#include "sysfs.h"
31#include "main.h" 31#include "main.h"
32#include "phy.h" 32#include "phy_common.h"
33 33
34#define GENERIC_FILESIZE 64 34#define GENERIC_FILESIZE 64
35 35
@@ -59,7 +59,12 @@ static ssize_t b43_attr_interfmode_show(struct device *dev,
59 59
60 mutex_lock(&wldev->wl->mutex); 60 mutex_lock(&wldev->wl->mutex);
61 61
62 switch (wldev->phy.interfmode) { 62 if (wldev->phy.type != B43_PHYTYPE_G) {
63 mutex_unlock(&wldev->wl->mutex);
64 return -ENOSYS;
65 }
66
67 switch (wldev->phy.g->interfmode) {
63 case B43_INTERFMODE_NONE: 68 case B43_INTERFMODE_NONE:
64 count = 69 count =
65 snprintf(buf, PAGE_SIZE, 70 snprintf(buf, PAGE_SIZE,
@@ -117,11 +122,15 @@ static ssize_t b43_attr_interfmode_store(struct device *dev,
117 mutex_lock(&wldev->wl->mutex); 122 mutex_lock(&wldev->wl->mutex);
118 spin_lock_irqsave(&wldev->wl->irq_lock, flags); 123 spin_lock_irqsave(&wldev->wl->irq_lock, flags);
119 124
120 err = b43_radio_set_interference_mitigation(wldev, mode); 125 if (wldev->phy.ops->interf_mitigation) {
121 if (err) { 126 err = wldev->phy.ops->interf_mitigation(wldev, mode);
122 b43err(wldev->wl, "Interference Mitigation not " 127 if (err) {
123 "supported by device\n"); 128 b43err(wldev->wl, "Interference Mitigation not "
124 } 129 "supported by device\n");
130 }
131 } else
132 err = -ENOSYS;
133
125 mmiowb(); 134 mmiowb();
126 spin_unlock_irqrestore(&wldev->wl->irq_lock, flags); 135 spin_unlock_irqrestore(&wldev->wl->irq_lock, flags);
127 mutex_unlock(&wldev->wl->mutex); 136 mutex_unlock(&wldev->wl->mutex);
diff --git a/drivers/net/wireless/b43/tables.c b/drivers/net/wireless/b43/tables.c
index 3f5ea06bf13c..1ef9a6463ec6 100644
--- a/drivers/net/wireless/b43/tables.c
+++ b/drivers/net/wireless/b43/tables.c
@@ -27,7 +27,8 @@
27 27
28#include "b43.h" 28#include "b43.h"
29#include "tables.h" 29#include "tables.h"
30#include "phy.h" 30#include "phy_g.h"
31
31 32
32const u32 b43_tab_rotor[] = { 33const u32 b43_tab_rotor[] = {
33 0xFEB93FFD, 0xFEC63FFD, /* 0 */ 34 0xFEB93FFD, 0xFEC63FFD, /* 0 */
@@ -377,17 +378,17 @@ static inline void assert_sizes(void)
377 378
378u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset) 379u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset)
379{ 380{
380 struct b43_phy *phy = &dev->phy; 381 struct b43_phy_g *gphy = dev->phy.g;
381 u16 addr; 382 u16 addr;
382 383
383 addr = table + offset; 384 addr = table + offset;
384 if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) || 385 if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) ||
385 (addr - 1 != phy->ofdmtab_addr)) { 386 (addr - 1 != gphy->ofdmtab_addr)) {
386 /* The hardware has a different address in memory. Update it. */ 387 /* The hardware has a different address in memory. Update it. */
387 b43_phy_write(dev, B43_PHY_OTABLECTL, addr); 388 b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
388 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ; 389 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ;
389 } 390 }
390 phy->ofdmtab_addr = addr; 391 gphy->ofdmtab_addr = addr;
391 392
392 return b43_phy_read(dev, B43_PHY_OTABLEI); 393 return b43_phy_read(dev, B43_PHY_OTABLEI);
393 394
@@ -398,34 +399,34 @@ u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset)
398void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table, 399void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
399 u16 offset, u16 value) 400 u16 offset, u16 value)
400{ 401{
401 struct b43_phy *phy = &dev->phy; 402 struct b43_phy_g *gphy = dev->phy.g;
402 u16 addr; 403 u16 addr;
403 404
404 addr = table + offset; 405 addr = table + offset;
405 if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) || 406 if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) ||
406 (addr - 1 != phy->ofdmtab_addr)) { 407 (addr - 1 != gphy->ofdmtab_addr)) {
407 /* The hardware has a different address in memory. Update it. */ 408 /* The hardware has a different address in memory. Update it. */
408 b43_phy_write(dev, B43_PHY_OTABLECTL, addr); 409 b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
409 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE; 410 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE;
410 } 411 }
411 phy->ofdmtab_addr = addr; 412 gphy->ofdmtab_addr = addr;
412 b43_phy_write(dev, B43_PHY_OTABLEI, value); 413 b43_phy_write(dev, B43_PHY_OTABLEI, value);
413} 414}
414 415
415u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset) 416u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
416{ 417{
417 struct b43_phy *phy = &dev->phy; 418 struct b43_phy_g *gphy = dev->phy.g;
418 u32 ret; 419 u32 ret;
419 u16 addr; 420 u16 addr;
420 421
421 addr = table + offset; 422 addr = table + offset;
422 if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) || 423 if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_READ) ||
423 (addr - 1 != phy->ofdmtab_addr)) { 424 (addr - 1 != gphy->ofdmtab_addr)) {
424 /* The hardware has a different address in memory. Update it. */ 425 /* The hardware has a different address in memory. Update it. */
425 b43_phy_write(dev, B43_PHY_OTABLECTL, addr); 426 b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
426 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ; 427 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_READ;
427 } 428 }
428 phy->ofdmtab_addr = addr; 429 gphy->ofdmtab_addr = addr;
429 ret = b43_phy_read(dev, B43_PHY_OTABLEQ); 430 ret = b43_phy_read(dev, B43_PHY_OTABLEQ);
430 ret <<= 16; 431 ret <<= 16;
431 ret |= b43_phy_read(dev, B43_PHY_OTABLEI); 432 ret |= b43_phy_read(dev, B43_PHY_OTABLEI);
@@ -436,17 +437,17 @@ u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
436void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table, 437void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
437 u16 offset, u32 value) 438 u16 offset, u32 value)
438{ 439{
439 struct b43_phy *phy = &dev->phy; 440 struct b43_phy_g *gphy = dev->phy.g;
440 u16 addr; 441 u16 addr;
441 442
442 addr = table + offset; 443 addr = table + offset;
443 if ((phy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) || 444 if ((gphy->ofdmtab_addr_direction != B43_OFDMTAB_DIRECTION_WRITE) ||
444 (addr - 1 != phy->ofdmtab_addr)) { 445 (addr - 1 != gphy->ofdmtab_addr)) {
445 /* The hardware has a different address in memory. Update it. */ 446 /* The hardware has a different address in memory. Update it. */
446 b43_phy_write(dev, B43_PHY_OTABLECTL, addr); 447 b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
447 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE; 448 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_WRITE;
448 } 449 }
449 phy->ofdmtab_addr = addr; 450 gphy->ofdmtab_addr = addr;
450 451
451 b43_phy_write(dev, B43_PHY_OTABLEI, value); 452 b43_phy_write(dev, B43_PHY_OTABLEI, value);
452 b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16)); 453 b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16));
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c
index 2aa57551786a..1de2c2e2e14c 100644
--- a/drivers/net/wireless/b43/tables_nphy.c
+++ b/drivers/net/wireless/b43/tables_nphy.c
@@ -24,7 +24,7 @@
24 24
25#include "b43.h" 25#include "b43.h"
26#include "tables_nphy.h" 26#include "tables_nphy.h"
27#include "phy.h" 27#include "phy_common.h"
28#include "nphy.h" 28#include "nphy.h"
29 29
30 30
diff --git a/drivers/net/wireless/b43/wa.c b/drivers/net/wireless/b43/wa.c
index daa94211f838..0c0fb15abb9f 100644
--- a/drivers/net/wireless/b43/wa.c
+++ b/drivers/net/wireless/b43/wa.c
@@ -27,7 +27,7 @@
27#include "b43.h" 27#include "b43.h"
28#include "main.h" 28#include "main.h"
29#include "tables.h" 29#include "tables.h"
30#include "phy.h" 30#include "phy_common.h"
31#include "wa.h" 31#include "wa.h"
32 32
33static void b43_wa_papd(struct b43_wldev *dev) 33static void b43_wa_papd(struct b43_wldev *dev)
diff --git a/drivers/net/wireless/b43/xmit.c b/drivers/net/wireless/b43/xmit.c
index 9dda8169f7cc..c8a831234e4a 100644
--- a/drivers/net/wireless/b43/xmit.c
+++ b/drivers/net/wireless/b43/xmit.c
@@ -28,7 +28,7 @@
28*/ 28*/
29 29
30#include "xmit.h" 30#include "xmit.h"
31#include "phy.h" 31#include "phy_common.h"
32#include "dma.h" 32#include "dma.h"
33#include "pio.h" 33#include "pio.h"
34 34
@@ -431,6 +431,7 @@ static s8 b43_rssi_postprocess(struct b43_wldev *dev,
431 int adjust_2053, int adjust_2050) 431 int adjust_2053, int adjust_2050)
432{ 432{
433 struct b43_phy *phy = &dev->phy; 433 struct b43_phy *phy = &dev->phy;
434 struct b43_phy_g *gphy = phy->g;
434 s32 tmp; 435 s32 tmp;
435 436
436 switch (phy->radio_ver) { 437 switch (phy->radio_ver) {
@@ -450,7 +451,8 @@ static s8 b43_rssi_postprocess(struct b43_wldev *dev,
450 boardflags_lo & B43_BFL_RSSI) { 451 boardflags_lo & B43_BFL_RSSI) {
451 if (in_rssi > 63) 452 if (in_rssi > 63)
452 in_rssi = 63; 453 in_rssi = 63;
453 tmp = phy->nrssi_lt[in_rssi]; 454 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
455 tmp = gphy->nrssi_lt[in_rssi];
454 tmp = 31 - tmp; 456 tmp = 31 - tmp;
455 tmp *= -131; 457 tmp *= -131;
456 tmp /= 128; 458 tmp /= 128;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 20:06:08 -0500