aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/b43
diff options
context:
space:
mode:
authorRafał Miłecki <zajec5@gmail.com>2013-03-20 11:57:04 -0400
committerRafał Miłecki <zajec5@gmail.com>2013-04-23 06:27:56 -0400
commite5ab1fd7a5932d2e863935abe52d5aa0c4139c87 (patch)
tree4b344ef41d4ef0e1ba6c753f8b72b327b7957c45 /drivers/net/wireless/b43
parent6aa38725a5768bd01f1076aeda97efec409e16fa (diff)
b43: N-PHY: simplify conditions in RSSI offset scale function
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r--drivers/net/wireless/b43/phy_n.c120
1 files changed, 65 insertions, 55 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index f331f2ba7906..ebbb50bd6241 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -1214,7 +1214,7 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1214static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1214static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1215 s8 offset, u8 core, 1215 s8 offset, u8 core,
1216 enum n_rail_type rail, 1216 enum n_rail_type rail,
1217 enum b43_nphy_rssi_type type) 1217 enum b43_nphy_rssi_type rssi_type)
1218{ 1218{
1219 u16 tmp; 1219 u16 tmp;
1220 bool core1or5 = (core == 1) || (core == 5); 1220 bool core1or5 = (core == 1) || (core == 5);
@@ -1223,60 +1223,70 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1223 offset = clamp_val(offset, -32, 31); 1223 offset = clamp_val(offset, -32, 31);
1224 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1224 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1225 1225
1226 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1226 switch (rssi_type) {
1227 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1227 case B43_NPHY_RSSI_Z:
1228 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1228 if (core1or5 && rail == N_RAIL_I)
1229 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1229 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1230 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1230 if (core1or5 && rail == N_RAIL_Q)
1231 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1231 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1232 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1232 if (core2or5 && rail == N_RAIL_I)
1233 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1233 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1234 1234 if (core2or5 && rail == N_RAIL_Q)
1235 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1235 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1236 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1236 break;
1237 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1237 case B43_NPHY_RSSI_X:
1238 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1238 if (core1or5 && rail == N_RAIL_I)
1239 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1240 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1240 if (core1or5 && rail == N_RAIL_Q)
1241 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1241 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1242 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1242 if (core2or5 && rail == N_RAIL_I)
1243 1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1244 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1244 if (core2or5 && rail == N_RAIL_Q)
1245 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1245 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1246 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1246 break;
1247 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1247 case B43_NPHY_RSSI_Y:
1248 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1248 if (core1or5 && rail == N_RAIL_I)
1249 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1250 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1250 if (core1or5 && rail == N_RAIL_Q)
1251 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1251 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1252 1252 if (core2or5 && rail == N_RAIL_I)
1253 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1254 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1254 if (core2or5 && rail == N_RAIL_Q)
1255 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1255 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1256 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1256 break;
1257 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1257 case B43_NPHY_RSSI_TBD:
1258 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1258 if (core1or5 && rail == N_RAIL_I)
1259 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1260 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1260 if (core1or5 && rail == N_RAIL_Q)
1261 1261 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1262 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1262 if (core2or5 && rail == N_RAIL_I)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1264 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1264 if (core2or5 && rail == N_RAIL_Q)
1265 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1265 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1266 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1266 break;
1267 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1267 case B43_NPHY_RSSI_PWRDET:
1268 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1268 if (core1or5 && rail == N_RAIL_I)
1269 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1270 1270 if (core1or5 && rail == N_RAIL_Q)
1271 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1271 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1272 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1272 if (core2or5 && rail == N_RAIL_I)
1273 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1274 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1274 if (core2or5 && rail == N_RAIL_Q)
1275 1275 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1276 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1276 break;
1277 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1277 case B43_NPHY_RSSI_TSSI_I:
1278 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1278 if (core1or5)
1279 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1280 if (core2or5)
1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1282 break;
1283 case B43_NPHY_RSSI_TSSI_Q:
1284 if (core1or5)
1285 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1286 if (core2or5)
1287 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1288 break;
1289 }
1280} 1290}
1281 1291
1282static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1292static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)