diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2013-03-20 12:30:38 -0400 |
---|---|---|
committer | Rafał Miłecki <zajec5@gmail.com> | 2013-04-23 06:27:56 -0400 |
commit | 2a2d0589446c3808858410639719642712af59c1 (patch) | |
tree | 3430f0a66643fb7e03d916b92e00c6225f8351cf /drivers/net/wireless/b43 | |
parent | 37859a75cc52cfe845a587ce96f6d27b7418b1fb (diff) |
b43: N-PHY: rename RSSI types to be shorter and more accurate
Thanks to Broadcom releasing some code we can use better names.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Diffstat (limited to 'drivers/net/wireless/b43')
-rw-r--r-- | drivers/net/wireless/b43/phy_n.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c index 1063fe428c75..60ac7c131e0a 100644 --- a/drivers/net/wireless/b43/phy_n.c +++ b/drivers/net/wireless/b43/phy_n.c | |||
@@ -69,14 +69,14 @@ enum b43_nphy_rf_sequence { | |||
69 | B43_RFSEQ_UPDATE_GAINU, | 69 | B43_RFSEQ_UPDATE_GAINU, |
70 | }; | 70 | }; |
71 | 71 | ||
72 | enum b43_nphy_rssi_type { | 72 | enum n_rssi_type { |
73 | B43_NPHY_RSSI_X = 0, | 73 | N_RSSI_W1 = 0, |
74 | B43_NPHY_RSSI_Y, | 74 | N_RSSI_W2, |
75 | B43_NPHY_RSSI_Z, | 75 | N_RSSI_NB, |
76 | B43_NPHY_RSSI_PWRDET, | 76 | N_RSSI_IQ, |
77 | B43_NPHY_RSSI_TSSI_I, | 77 | N_RSSI_TSSI_2G, |
78 | B43_NPHY_RSSI_TSSI_Q, | 78 | N_RSSI_TSSI_5G, |
79 | B43_NPHY_RSSI_TBD, | 79 | N_RSSI_TBD, |
80 | }; | 80 | }; |
81 | 81 | ||
82 | enum n_rail_type { | 82 | enum n_rail_type { |
@@ -1214,7 +1214,7 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, | |||
1214 | static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | 1214 | static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, |
1215 | s8 offset, u8 core, | 1215 | s8 offset, u8 core, |
1216 | enum n_rail_type rail, | 1216 | enum n_rail_type rail, |
1217 | enum b43_nphy_rssi_type rssi_type) | 1217 | enum n_rssi_type rssi_type) |
1218 | { | 1218 | { |
1219 | u16 tmp; | 1219 | u16 tmp; |
1220 | bool core1or5 = (core == 1) || (core == 5); | 1220 | bool core1or5 = (core == 1) || (core == 5); |
@@ -1224,7 +1224,7 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |||
1224 | tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); | 1224 | tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); |
1225 | 1225 | ||
1226 | switch (rssi_type) { | 1226 | switch (rssi_type) { |
1227 | case B43_NPHY_RSSI_Z: | 1227 | case N_RSSI_NB: |
1228 | if (core1or5 && rail == N_RAIL_I) | 1228 | if (core1or5 && rail == N_RAIL_I) |
1229 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); | 1229 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); |
1230 | if (core1or5 && rail == N_RAIL_Q) | 1230 | if (core1or5 && rail == N_RAIL_Q) |
@@ -1234,7 +1234,7 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |||
1234 | if (core2or5 && rail == N_RAIL_Q) | 1234 | if (core2or5 && rail == N_RAIL_Q) |
1235 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); | 1235 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); |
1236 | break; | 1236 | break; |
1237 | case B43_NPHY_RSSI_X: | 1237 | case N_RSSI_W1: |
1238 | if (core1or5 && rail == N_RAIL_I) | 1238 | if (core1or5 && rail == N_RAIL_I) |
1239 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); | 1239 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); |
1240 | if (core1or5 && rail == N_RAIL_Q) | 1240 | if (core1or5 && rail == N_RAIL_Q) |
@@ -1244,7 +1244,7 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |||
1244 | if (core2or5 && rail == N_RAIL_Q) | 1244 | if (core2or5 && rail == N_RAIL_Q) |
1245 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); | 1245 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); |
1246 | break; | 1246 | break; |
1247 | case B43_NPHY_RSSI_Y: | 1247 | case N_RSSI_W2: |
1248 | if (core1or5 && rail == N_RAIL_I) | 1248 | if (core1or5 && rail == N_RAIL_I) |
1249 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); | 1249 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); |
1250 | if (core1or5 && rail == N_RAIL_Q) | 1250 | if (core1or5 && rail == N_RAIL_Q) |
@@ -1254,7 +1254,7 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |||
1254 | if (core2or5 && rail == N_RAIL_Q) | 1254 | if (core2or5 && rail == N_RAIL_Q) |
1255 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); | 1255 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); |
1256 | break; | 1256 | break; |
1257 | case B43_NPHY_RSSI_TBD: | 1257 | case N_RSSI_TBD: |
1258 | if (core1or5 && rail == N_RAIL_I) | 1258 | if (core1or5 && rail == N_RAIL_I) |
1259 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); | 1259 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); |
1260 | if (core1or5 && rail == N_RAIL_Q) | 1260 | if (core1or5 && rail == N_RAIL_Q) |
@@ -1264,7 +1264,7 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |||
1264 | if (core2or5 && rail == N_RAIL_Q) | 1264 | if (core2or5 && rail == N_RAIL_Q) |
1265 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); | 1265 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); |
1266 | break; | 1266 | break; |
1267 | case B43_NPHY_RSSI_PWRDET: | 1267 | case N_RSSI_IQ: |
1268 | if (core1or5 && rail == N_RAIL_I) | 1268 | if (core1or5 && rail == N_RAIL_I) |
1269 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); | 1269 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); |
1270 | if (core1or5 && rail == N_RAIL_Q) | 1270 | if (core1or5 && rail == N_RAIL_Q) |
@@ -1274,13 +1274,13 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |||
1274 | if (core2or5 && rail == N_RAIL_Q) | 1274 | if (core2or5 && rail == N_RAIL_Q) |
1275 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); | 1275 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); |
1276 | break; | 1276 | break; |
1277 | case B43_NPHY_RSSI_TSSI_I: | 1277 | case N_RSSI_TSSI_2G: |
1278 | if (core1or5) | 1278 | if (core1or5) |
1279 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); | 1279 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); |
1280 | if (core2or5) | 1280 | if (core2or5) |
1281 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); | 1281 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); |
1282 | break; | 1282 | break; |
1283 | case B43_NPHY_RSSI_TSSI_Q: | 1283 | case N_RSSI_TSSI_5G: |
1284 | if (core1or5) | 1284 | if (core1or5) |
1285 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); | 1285 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); |
1286 | if (core2or5) | 1286 | if (core2or5) |
@@ -1921,9 +1921,9 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev) | |||
1921 | if (dev->phy.rev >= 3) { | 1921 | if (dev->phy.rev >= 3) { |
1922 | b43_nphy_rev3_rssi_cal(dev); | 1922 | b43_nphy_rev3_rssi_cal(dev); |
1923 | } else { | 1923 | } else { |
1924 | b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z); | 1924 | b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); |
1925 | b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X); | 1925 | b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); |
1926 | b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y); | 1926 | b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); |
1927 | } | 1927 | } |
1928 | } | 1928 | } |
1929 | 1929 | ||