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authorMichael Buesch <mb@bu3sch.de>2008-01-28 17:47:41 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:09:50 -0500
commiteb189d8bc9824bcb2187ffdab27d77ab469264c3 (patch)
tree612c6549f0d0261087b55b157dd5ca016386ddee /drivers/net/wireless/b43/xmit.h
parent243dcfcc1d4b33aa610f1bf3ec610dafdf4d7ff7 (diff)
b43: Add support for new firmware
This patch adds support for new firmware. Old firmware is still supported until July 2008. To get new firmware, go to ftp://ftp.linksys.com/opensourcecode/wrt150nv11/1.51.3/ and download the tarball. We don't have a smaller tarball, yet. That will be fixed later. You can extract firmware out of the "wl_ap.o" file contained in this tarball using latest fwcutter. You must pass the option --unsupported to fwcutter. Fwcutter-010 with official support for a new firmware image will be released soon. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wireless/b43/xmit.h')
-rw-r--r--drivers/net/wireless/b43/xmit.h200
1 files changed, 146 insertions, 54 deletions
diff --git a/drivers/net/wireless/b43/xmit.h b/drivers/net/wireless/b43/xmit.h
index 6dc079382f7f..ca2a2ab8654c 100644
--- a/drivers/net/wireless/b43/xmit.h
+++ b/drivers/net/wireless/b43/xmit.h
@@ -19,68 +19,160 @@ _b43_declare_plcp_hdr(6);
19#undef _b43_declare_plcp_hdr 19#undef _b43_declare_plcp_hdr
20 20
21/* TX header for v4 firmware */ 21/* TX header for v4 firmware */
22struct b43_txhdr_fw4 { 22struct b43_txhdr {
23 __le32 mac_ctl; /* MAC TX control */ 23 __le32 mac_ctl; /* MAC TX control */
24 __le16 mac_frame_ctl; /* Copy of the FrameControl field */ 24 __le16 mac_frame_ctl; /* Copy of the FrameControl field */
25 __le16 tx_fes_time_norm; /* TX FES Time Normal */ 25 __le16 tx_fes_time_norm; /* TX FES Time Normal */
26 __le16 phy_ctl; /* PHY TX control */ 26 __le16 phy_ctl; /* PHY TX control */
27 __le16 phy_ctl_0; /* Unused */ 27 __le16 phy_ctl1; /* PHY TX control word 1 */
28 __le16 phy_ctl_1; /* Unused */ 28 __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */
29 __le16 phy_ctl_rts_0; /* Unused */ 29 __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */
30 __le16 phy_ctl_rts_1; /* Unused */ 30 __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */
31 __u8 phy_rate; /* PHY rate */ 31 __u8 phy_rate; /* PHY rate */
32 __u8 phy_rate_rts; /* PHY rate for RTS/CTS */ 32 __u8 phy_rate_rts; /* PHY rate for RTS/CTS */
33 __u8 extra_ft; /* Extra Frame Types */ 33 __u8 extra_ft; /* Extra Frame Types */
34 __u8 chan_radio_code; /* Channel Radio Code */ 34 __u8 chan_radio_code; /* Channel Radio Code */
35 __u8 iv[16]; /* Encryption IV */ 35 __u8 iv[16]; /* Encryption IV */
36 __u8 tx_receiver[6]; /* TX Frame Receiver address */ 36 __u8 tx_receiver[6]; /* TX Frame Receiver address */
37 __le16 tx_fes_time_fb; /* TX FES Time Fallback */ 37 __le16 tx_fes_time_fb; /* TX FES Time Fallback */
38 struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP */ 38 struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
39 __le16 rts_dur_fb; /* RTS fallback duration */ 39 __le16 rts_dur_fb; /* RTS fallback duration */
40 struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP */ 40 struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */
41 __le16 dur_fb; /* Fallback duration */ 41 __le16 dur_fb; /* Fallback duration */
42 __le16 mm_dur_time; /* Unused */ 42 __le16 mimo_modelen; /* MIMO mode length */
43 __le16 mm_dur_time_fb; /* Unused */ 43 __le16 mimo_ratelen_fb; /* MIMO fallback rate length */
44 __le32 time_stamp; /* Timestamp */ 44 __le32 timeout; /* Timeout */
45 PAD_BYTES(2); 45
46 __le16 cookie; /* TX frame cookie */ 46 union {
47 __le16 tx_status; /* TX status */ 47 /* The new r410 format. */
48 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP */ 48 struct {
49 __u8 rts_frame[16]; /* The RTS frame (if used) */ 49 __le16 mimo_antenna; /* MIMO antenna select */
50 PAD_BYTES(2); 50 __le16 preload_size; /* Preload size */
51 struct b43_plcp_hdr6 plcp; /* Main PLCP */ 51 PAD_BYTES(2);
52 __le16 cookie; /* TX frame cookie */
53 __le16 tx_status; /* TX status */
54 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
55 __u8 rts_frame[16]; /* The RTS frame (if used) */
56 PAD_BYTES(2);
57 struct b43_plcp_hdr6 plcp; /* Main PLCP header */
58 } new_format __attribute__ ((__packed__));
59
60 /* The old r351 format. */
61 struct {
62 PAD_BYTES(2);
63 __le16 cookie; /* TX frame cookie */
64 __le16 tx_status; /* TX status */
65 struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
66 __u8 rts_frame[16]; /* The RTS frame (if used) */
67 PAD_BYTES(2);
68 struct b43_plcp_hdr6 plcp; /* Main PLCP header */
69 } old_format __attribute__ ((__packed__));
70
71 } __attribute__ ((__packed__));
52} __attribute__ ((__packed__)); 72} __attribute__ ((__packed__));
53 73
54/* MAC TX control */ 74/* MAC TX control */
55#define B43_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */ 75#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
56#define B43_TX4_MAC_KEYIDX_SHIFT 20 76#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
57#define B43_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */ 77#define B43_TXH_MAC_KEYIDX_SHIFT 20
58#define B43_TX4_MAC_KEYALG_SHIFT 16 78#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
59#define B43_TX4_MAC_LIFETIME 0x00001000 79#define B43_TXH_MAC_KEYALG_SHIFT 16
60#define B43_TX4_MAC_FRAMEBURST 0x00000800 80#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
61#define B43_TX4_MAC_SENDCTS 0x00000400 81#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
62#define B43_TX4_MAC_AMPDU 0x00000300 82#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
63#define B43_TX4_MAC_AMPDU_SHIFT 8 83#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
64#define B43_TX4_MAC_5GHZ 0x00000080 84#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
65#define B43_TX4_MAC_IGNPMQ 0x00000020 85#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
66#define B43_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */ 86#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
67#define B43_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */ 87#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
68#define B43_TX4_MAC_SENDRTS 0x00000004 88#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
69#define B43_TX4_MAC_LONGFRAME 0x00000002 89#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
70#define B43_TX4_MAC_ACK 0x00000001 90#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
91#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
92#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
93#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
94#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
95#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
96#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
97#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
98#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
71 99
72/* Extra Frame Types */ 100/* Extra Frame Types */
73#define B43_TX4_EFT_FBOFDM 0x0001 /* Data frame fallback rate type */ 101#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
74#define B43_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */ 102#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
75#define B43_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */ 103#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
104#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
105#define B43_TXH_EFT_FB_N 0x03 /* N */
106#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
107#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
108#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
109#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
110#define B43_TXH_EFT_RTS_N 0x0C /* N */
111#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
112#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
113#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
114#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
115#define B43_TXH_EFT_RTSFB_N 0x30 /* N */
76 116
77/* PHY TX control word */ 117/* PHY TX control word */
78#define B43_TX4_PHY_OFDM 0x0001 /* Data frame rate type */ 118#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
79#define B43_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */ 119#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
80#define B43_TX4_PHY_ANT 0x03C0 /* Antenna selection */ 120#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
81#define B43_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */ 121#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
82#define B43_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */ 122#define B43_TXH_PHY_ENC_N 0x0003 /* N */
83#define B43_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */ 123#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
124#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
125#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
126#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
127#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
128#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
129#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
130#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
131#define B43_TXH_PHY_TXPWR_SHIFT 10
132
133/* PHY TX control word 1 */
134#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
135#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
136#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
137#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
138#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
139#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
140#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
141#define B43_TXH_PHY1_MODE 0x0038 /* Mode */
142#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
143#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
144#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
145#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
146#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
147#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
148#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
149#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
150#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
151#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
152#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
153#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
154#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
155#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
156#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
157#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
158#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
159
160
161/* r351 firmware compatibility stuff. */
162static inline
163bool b43_is_old_txhdr_format(struct b43_wldev *dev)
164{
165 return (dev->fw.rev <= 351);
166}
167
168static inline
169size_t b43_txhdr_size(struct b43_wldev *dev)
170{
171 if (b43_is_old_txhdr_format(dev))
172 return 100 + sizeof(struct b43_plcp_hdr6);
173 return 104 + sizeof(struct b43_plcp_hdr6);
174}
175
84 176
85void b43_generate_txhdr(struct b43_wldev *dev, 177void b43_generate_txhdr(struct b43_wldev *dev,
86 u8 * txhdr, 178 u8 * txhdr,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 14:01:30 -0500