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authorGábor Stefanik <netrolller.3d@gmail.com>2009-08-02 19:28:12 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-04 16:44:24 -0400
commit738f0f4301587ad09b58651390b122205086b484 (patch)
tree6d5f51d1980db2ef37537b0bc6c1a5a694324e40 /drivers/net/wireless/b43/b43.h
parentd8cc8926e9b4dc2ce513ee3325bf16b4ea6d94e8 (diff)
b43: implement baseband init for LP-PHY <= rev1
Implement baseband init for rev.0 and rev.1 LP PHYs. Convert boardflags_hi values to defines. Implement b43_phy_copy for easier copying between registers, as needed by LP-PHY init. Signed-off-by: Gábor Stefanik<netrolller.3d@gmail.com> Cc: Michael Buesch<mb@bu3sch.de> Cc: Larry Finger<larry.finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/b43/b43.h')
-rw-r--r--drivers/net/wireless/b43/b43.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 40448067e4cc..b6811cff18ba 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -142,6 +142,17 @@
142#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ 142#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
143#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ 143#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
144 144
145/* SPROM boardflags_hi values */
146#define B43_BFH_NOPA 0x0001 /* has no PA */
147#define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
148#define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */
149#define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared
150 * with bluetooth */
151#define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
152#define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */
153#define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna
154 * with bluetooth */
155
145/* GPIO register offset, in both ChipCommon and PCI core. */ 156/* GPIO register offset, in both ChipCommon and PCI core. */
146#define B43_GPIO_CONTROL 0x6c 157#define B43_GPIO_CONTROL 0x6c
147 158