diff options
author | Joe Perches <joe@perches.com> | 2011-12-15 17:55:53 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-12-19 14:35:31 -0500 |
commit | d2182b69dcb6a68b1ef6070b2efd094e13dea3f1 (patch) | |
tree | 92da8da22d48540d9f28b1e91ba0d1befbac5fe9 /drivers/net/wireless/ath | |
parent | a85e1d55974646a442d95911e3f7d7a891ea9ac5 (diff) |
ath: Convert ath_dbg(bar, ATH_DBG_<FOO>, to ath_dbg(bar, FOO
Add ATH_DBG_ to macros to shorten the uses and
reduce the line count.
Coalesce ath_dbg formats.
Add missing spaces to coalesced formats.
Add missing newline terminations to ath_dbg formats.
Align ath_dbg arguments where appropriate.
Standardize ath_dbg formats without periods.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath')
34 files changed, 647 insertions, 799 deletions
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h index c1d699fd5717..efc01110dc34 100644 --- a/drivers/net/wireless/ath/ath.h +++ b/drivers/net/wireless/ath/ath.h | |||
@@ -255,7 +255,7 @@ enum ATH_DEBUG { | |||
255 | 255 | ||
256 | #define ath_dbg(common, dbg_mask, fmt, ...) \ | 256 | #define ath_dbg(common, dbg_mask, fmt, ...) \ |
257 | do { \ | 257 | do { \ |
258 | if ((common)->debug_mask & dbg_mask) \ | 258 | if ((common)->debug_mask & ATH_DBG_##dbg_mask) \ |
259 | _ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ | 259 | _ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \ |
260 | } while (0) | 260 | } while (0) |
261 | 261 | ||
@@ -265,10 +265,13 @@ do { \ | |||
265 | #else | 265 | #else |
266 | 266 | ||
267 | static inline __attribute__ ((format (printf, 3, 4))) | 267 | static inline __attribute__ ((format (printf, 3, 4))) |
268 | void ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, | 268 | void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask, |
269 | const char *fmt, ...) | 269 | const char *fmt, ...) |
270 | { | 270 | { |
271 | } | 271 | } |
272 | #define ath_dbg(common, dbg_mask, fmt, ...) \ | ||
273 | _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__) | ||
274 | |||
272 | #define ATH_DBG_WARN(foo, arg...) do {} while (0) | 275 | #define ATH_DBG_WARN(foo, arg...) do {} while (0) |
273 | #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ | 276 | #define ATH_DBG_WARN_ON_ONCE(foo) ({ \ |
274 | int __ret_warn_once = !!(foo); \ | 277 | int __ret_warn_once = !!(foo); \ |
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c index a639b94f7643..bc56f57b393b 100644 --- a/drivers/net/wireless/ath/ath9k/ani.c +++ b/drivers/net/wireless/ath/ath9k/ani.c | |||
@@ -136,8 +136,8 @@ static void ath9k_ani_restart(struct ath_hw *ah) | |||
136 | cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; | 136 | cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high; |
137 | } | 137 | } |
138 | 138 | ||
139 | ath_dbg(common, ATH_DBG_ANI, | 139 | ath_dbg(common, ANI, "Writing ofdmbase=%u cckbase=%u\n", |
140 | "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base); | 140 | ofdm_base, cck_base); |
141 | 141 | ||
142 | ENABLE_REGWRITE_BUFFER(ah); | 142 | ENABLE_REGWRITE_BUFFER(ah); |
143 | 143 | ||
@@ -268,8 +268,7 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel) | |||
268 | 268 | ||
269 | aniState->noiseFloor = BEACON_RSSI(ah); | 269 | aniState->noiseFloor = BEACON_RSSI(ah); |
270 | 270 | ||
271 | ath_dbg(common, ATH_DBG_ANI, | 271 | ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", |
272 | "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", | ||
273 | aniState->ofdmNoiseImmunityLevel, | 272 | aniState->ofdmNoiseImmunityLevel, |
274 | immunityLevel, aniState->noiseFloor, | 273 | immunityLevel, aniState->noiseFloor, |
275 | aniState->rssiThrLow, aniState->rssiThrHigh); | 274 | aniState->rssiThrLow, aniState->rssiThrHigh); |
@@ -336,8 +335,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel) | |||
336 | const struct ani_cck_level_entry *entry_cck; | 335 | const struct ani_cck_level_entry *entry_cck; |
337 | 336 | ||
338 | aniState->noiseFloor = BEACON_RSSI(ah); | 337 | aniState->noiseFloor = BEACON_RSSI(ah); |
339 | ath_dbg(common, ATH_DBG_ANI, | 338 | ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", |
340 | "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", | ||
341 | aniState->cckNoiseImmunityLevel, immunityLevel, | 339 | aniState->cckNoiseImmunityLevel, immunityLevel, |
342 | aniState->noiseFloor, aniState->rssiThrLow, | 340 | aniState->noiseFloor, aniState->rssiThrLow, |
343 | aniState->rssiThrHigh); | 341 | aniState->rssiThrHigh); |
@@ -481,8 +479,7 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning) | |||
481 | 479 | ||
482 | if (ah->opmode != NL80211_IFTYPE_STATION | 480 | if (ah->opmode != NL80211_IFTYPE_STATION |
483 | && ah->opmode != NL80211_IFTYPE_ADHOC) { | 481 | && ah->opmode != NL80211_IFTYPE_ADHOC) { |
484 | ath_dbg(common, ATH_DBG_ANI, | 482 | ath_dbg(common, ANI, "Reset ANI state opmode %u\n", ah->opmode); |
485 | "Reset ANI state opmode %u\n", ah->opmode); | ||
486 | ah->stats.ast_ani_reset++; | 483 | ah->stats.ast_ani_reset++; |
487 | 484 | ||
488 | if (ah->opmode == NL80211_IFTYPE_AP) { | 485 | if (ah->opmode == NL80211_IFTYPE_AP) { |
@@ -582,7 +579,7 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) | |||
582 | ATH9K_ANI_OFDM_DEF_LEVEL || | 579 | ATH9K_ANI_OFDM_DEF_LEVEL || |
583 | aniState->cckNoiseImmunityLevel != | 580 | aniState->cckNoiseImmunityLevel != |
584 | ATH9K_ANI_CCK_DEF_LEVEL) { | 581 | ATH9K_ANI_CCK_DEF_LEVEL) { |
585 | ath_dbg(common, ATH_DBG_ANI, | 582 | ath_dbg(common, ANI, |
586 | "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", | 583 | "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", |
587 | ah->opmode, | 584 | ah->opmode, |
588 | chan->channel, | 585 | chan->channel, |
@@ -599,7 +596,7 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) | |||
599 | /* | 596 | /* |
600 | * restore historical levels for this channel | 597 | * restore historical levels for this channel |
601 | */ | 598 | */ |
602 | ath_dbg(common, ATH_DBG_ANI, | 599 | ath_dbg(common, ANI, |
603 | "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", | 600 | "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n", |
604 | ah->opmode, | 601 | ah->opmode, |
605 | chan->channel, | 602 | chan->channel, |
@@ -662,7 +659,7 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) | |||
662 | 659 | ||
663 | if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { | 660 | if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) { |
664 | if (phyCnt1 < ofdm_base) { | 661 | if (phyCnt1 < ofdm_base) { |
665 | ath_dbg(common, ATH_DBG_ANI, | 662 | ath_dbg(common, ANI, |
666 | "phyCnt1 0x%x, resetting counter value to 0x%x\n", | 663 | "phyCnt1 0x%x, resetting counter value to 0x%x\n", |
667 | phyCnt1, ofdm_base); | 664 | phyCnt1, ofdm_base); |
668 | REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); | 665 | REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base); |
@@ -670,7 +667,7 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) | |||
670 | AR_PHY_ERR_OFDM_TIMING); | 667 | AR_PHY_ERR_OFDM_TIMING); |
671 | } | 668 | } |
672 | if (phyCnt2 < cck_base) { | 669 | if (phyCnt2 < cck_base) { |
673 | ath_dbg(common, ATH_DBG_ANI, | 670 | ath_dbg(common, ANI, |
674 | "phyCnt2 0x%x, resetting counter value to 0x%x\n", | 671 | "phyCnt2 0x%x, resetting counter value to 0x%x\n", |
675 | phyCnt2, cck_base); | 672 | phyCnt2, cck_base); |
676 | REG_WRITE(ah, AR_PHY_ERR_2, cck_base); | 673 | REG_WRITE(ah, AR_PHY_ERR_2, cck_base); |
@@ -713,7 +710,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) | |||
713 | cckPhyErrRate = aniState->cckPhyErrCount * 1000 / | 710 | cckPhyErrRate = aniState->cckPhyErrCount * 1000 / |
714 | aniState->listenTime; | 711 | aniState->listenTime; |
715 | 712 | ||
716 | ath_dbg(common, ATH_DBG_ANI, | 713 | ath_dbg(common, ANI, |
717 | "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", | 714 | "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", |
718 | aniState->listenTime, | 715 | aniState->listenTime, |
719 | aniState->ofdmNoiseImmunityLevel, | 716 | aniState->ofdmNoiseImmunityLevel, |
@@ -748,7 +745,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah) | |||
748 | { | 745 | { |
749 | struct ath_common *common = ath9k_hw_common(ah); | 746 | struct ath_common *common = ath9k_hw_common(ah); |
750 | 747 | ||
751 | ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n"); | 748 | ath_dbg(common, ANI, "Enable MIB counters\n"); |
752 | 749 | ||
753 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); | 750 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
754 | 751 | ||
@@ -770,7 +767,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah) | |||
770 | { | 767 | { |
771 | struct ath_common *common = ath9k_hw_common(ah); | 768 | struct ath_common *common = ath9k_hw_common(ah); |
772 | 769 | ||
773 | ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n"); | 770 | ath_dbg(common, ANI, "Disable MIB counters\n"); |
774 | 771 | ||
775 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); | 772 | REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); |
776 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); | 773 | ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
@@ -845,7 +842,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah) | |||
845 | struct ath_common *common = ath9k_hw_common(ah); | 842 | struct ath_common *common = ath9k_hw_common(ah); |
846 | int i; | 843 | int i; |
847 | 844 | ||
848 | ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n"); | 845 | ath_dbg(common, ANI, "Initialize ANI\n"); |
849 | 846 | ||
850 | if (use_new_ani(ah)) { | 847 | if (use_new_ani(ah)) { |
851 | ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; | 848 | ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW; |
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c index f199e9e25149..f901a17f76ba 100644 --- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c | |||
@@ -158,7 +158,7 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) | |||
158 | /* pre-reverse this field */ | 158 | /* pre-reverse this field */ |
159 | tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); | 159 | tmp_reg = ath9k_hw_reverse_bits(new_bias, 3); |
160 | 160 | ||
161 | ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", | 161 | ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n", |
162 | new_bias, synth_freq); | 162 | new_bias, synth_freq); |
163 | 163 | ||
164 | /* swizzle rf_pwd_icsyndiv */ | 164 | /* swizzle rf_pwd_icsyndiv */ |
@@ -1053,8 +1053,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1053 | u32 level = param; | 1053 | u32 level = param; |
1054 | 1054 | ||
1055 | if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { | 1055 | if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { |
1056 | ath_dbg(common, ATH_DBG_ANI, | 1056 | ath_dbg(common, ANI, "level out of range (%u > %zu)\n", |
1057 | "level out of range (%u > %zu)\n", | ||
1058 | level, ARRAY_SIZE(ah->totalSizeDesired)); | 1057 | level, ARRAY_SIZE(ah->totalSizeDesired)); |
1059 | return false; | 1058 | return false; |
1060 | } | 1059 | } |
@@ -1157,8 +1156,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1157 | u32 level = param; | 1156 | u32 level = param; |
1158 | 1157 | ||
1159 | if (level >= ARRAY_SIZE(firstep)) { | 1158 | if (level >= ARRAY_SIZE(firstep)) { |
1160 | ath_dbg(common, ATH_DBG_ANI, | 1159 | ath_dbg(common, ANI, "level out of range (%u > %zu)\n", |
1161 | "level out of range (%u > %zu)\n", | ||
1162 | level, ARRAY_SIZE(firstep)); | 1160 | level, ARRAY_SIZE(firstep)); |
1163 | return false; | 1161 | return false; |
1164 | } | 1162 | } |
@@ -1177,8 +1175,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1177 | u32 level = param; | 1175 | u32 level = param; |
1178 | 1176 | ||
1179 | if (level >= ARRAY_SIZE(cycpwrThr1)) { | 1177 | if (level >= ARRAY_SIZE(cycpwrThr1)) { |
1180 | ath_dbg(common, ATH_DBG_ANI, | 1178 | ath_dbg(common, ANI, "level out of range (%u > %zu)\n", |
1181 | "level out of range (%u > %zu)\n", | ||
1182 | level, ARRAY_SIZE(cycpwrThr1)); | 1179 | level, ARRAY_SIZE(cycpwrThr1)); |
1183 | return false; | 1180 | return false; |
1184 | } | 1181 | } |
@@ -1195,23 +1192,22 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah, | |||
1195 | case ATH9K_ANI_PRESENT: | 1192 | case ATH9K_ANI_PRESENT: |
1196 | break; | 1193 | break; |
1197 | default: | 1194 | default: |
1198 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); | 1195 | ath_dbg(common, ANI, "invalid cmd %u\n", cmd); |
1199 | return false; | 1196 | return false; |
1200 | } | 1197 | } |
1201 | 1198 | ||
1202 | ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n"); | 1199 | ath_dbg(common, ANI, "ANI parameters:\n"); |
1203 | ath_dbg(common, ATH_DBG_ANI, | 1200 | ath_dbg(common, ANI, |
1204 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n", | 1201 | "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n", |
1205 | aniState->noiseImmunityLevel, | 1202 | aniState->noiseImmunityLevel, |
1206 | aniState->spurImmunityLevel, | 1203 | aniState->spurImmunityLevel, |
1207 | !aniState->ofdmWeakSigDetectOff); | 1204 | !aniState->ofdmWeakSigDetectOff); |
1208 | ath_dbg(common, ATH_DBG_ANI, | 1205 | ath_dbg(common, ANI, |
1209 | "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n", | 1206 | "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n", |
1210 | aniState->cckWeakSigThreshold, | 1207 | aniState->cckWeakSigThreshold, |
1211 | aniState->firstepLevel, | 1208 | aniState->firstepLevel, |
1212 | aniState->listenTime); | 1209 | aniState->listenTime); |
1213 | ath_dbg(common, ATH_DBG_ANI, | 1210 | ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", |
1214 | "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", | ||
1215 | aniState->ofdmPhyErrCount, | 1211 | aniState->ofdmPhyErrCount, |
1216 | aniState->cckPhyErrCount); | 1212 | aniState->cckPhyErrCount); |
1217 | 1213 | ||
@@ -1295,7 +1291,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1295 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | 1291 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
1296 | 1292 | ||
1297 | if (!on != aniState->ofdmWeakSigDetectOff) { | 1293 | if (!on != aniState->ofdmWeakSigDetectOff) { |
1298 | ath_dbg(common, ATH_DBG_ANI, | 1294 | ath_dbg(common, ANI, |
1299 | "** ch %d: ofdm weak signal: %s=>%s\n", | 1295 | "** ch %d: ofdm weak signal: %s=>%s\n", |
1300 | chan->channel, | 1296 | chan->channel, |
1301 | !aniState->ofdmWeakSigDetectOff ? | 1297 | !aniState->ofdmWeakSigDetectOff ? |
@@ -1313,7 +1309,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1313 | u32 level = param; | 1309 | u32 level = param; |
1314 | 1310 | ||
1315 | if (level >= ARRAY_SIZE(firstep_table)) { | 1311 | if (level >= ARRAY_SIZE(firstep_table)) { |
1316 | ath_dbg(common, ATH_DBG_ANI, | 1312 | ath_dbg(common, ANI, |
1317 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", | 1313 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
1318 | level, ARRAY_SIZE(firstep_table)); | 1314 | level, ARRAY_SIZE(firstep_table)); |
1319 | return false; | 1315 | return false; |
@@ -1350,7 +1346,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1350 | AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); | 1346 | AR_PHY_FIND_SIG_FIRSTEP_LOW, value2); |
1351 | 1347 | ||
1352 | if (level != aniState->firstepLevel) { | 1348 | if (level != aniState->firstepLevel) { |
1353 | ath_dbg(common, ATH_DBG_ANI, | 1349 | ath_dbg(common, ANI, |
1354 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", | 1350 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
1355 | chan->channel, | 1351 | chan->channel, |
1356 | aniState->firstepLevel, | 1352 | aniState->firstepLevel, |
@@ -1358,7 +1354,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1358 | ATH9K_ANI_FIRSTEP_LVL_NEW, | 1354 | ATH9K_ANI_FIRSTEP_LVL_NEW, |
1359 | value, | 1355 | value, |
1360 | aniState->iniDef.firstep); | 1356 | aniState->iniDef.firstep); |
1361 | ath_dbg(common, ATH_DBG_ANI, | 1357 | ath_dbg(common, ANI, |
1362 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", | 1358 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
1363 | chan->channel, | 1359 | chan->channel, |
1364 | aniState->firstepLevel, | 1360 | aniState->firstepLevel, |
@@ -1378,7 +1374,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1378 | u32 level = param; | 1374 | u32 level = param; |
1379 | 1375 | ||
1380 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { | 1376 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { |
1381 | ath_dbg(common, ATH_DBG_ANI, | 1377 | ath_dbg(common, ANI, |
1382 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", | 1378 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
1383 | level, ARRAY_SIZE(cycpwrThr1_table)); | 1379 | level, ARRAY_SIZE(cycpwrThr1_table)); |
1384 | return false; | 1380 | return false; |
@@ -1414,7 +1410,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1414 | AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); | 1410 | AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2); |
1415 | 1411 | ||
1416 | if (level != aniState->spurImmunityLevel) { | 1412 | if (level != aniState->spurImmunityLevel) { |
1417 | ath_dbg(common, ATH_DBG_ANI, | 1413 | ath_dbg(common, ANI, |
1418 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", | 1414 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
1419 | chan->channel, | 1415 | chan->channel, |
1420 | aniState->spurImmunityLevel, | 1416 | aniState->spurImmunityLevel, |
@@ -1422,7 +1418,7 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1422 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | 1418 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, |
1423 | value, | 1419 | value, |
1424 | aniState->iniDef.cycpwrThr1); | 1420 | aniState->iniDef.cycpwrThr1); |
1425 | ath_dbg(common, ATH_DBG_ANI, | 1421 | ath_dbg(common, ANI, |
1426 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", | 1422 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
1427 | chan->channel, | 1423 | chan->channel, |
1428 | aniState->spurImmunityLevel, | 1424 | aniState->spurImmunityLevel, |
@@ -1448,11 +1444,11 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah, | |||
1448 | case ATH9K_ANI_PRESENT: | 1444 | case ATH9K_ANI_PRESENT: |
1449 | break; | 1445 | break; |
1450 | default: | 1446 | default: |
1451 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); | 1447 | ath_dbg(common, ANI, "invalid cmd %u\n", cmd); |
1452 | return false; | 1448 | return false; |
1453 | } | 1449 | } |
1454 | 1450 | ||
1455 | ath_dbg(common, ATH_DBG_ANI, | 1451 | ath_dbg(common, ANI, |
1456 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", | 1452 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
1457 | aniState->spurImmunityLevel, | 1453 | aniState->spurImmunityLevel, |
1458 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", | 1454 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", |
@@ -1506,7 +1502,7 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah) | |||
1506 | 1502 | ||
1507 | iniDef = &aniState->iniDef; | 1503 | iniDef = &aniState->iniDef; |
1508 | 1504 | ||
1509 | ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", | 1505 | ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", |
1510 | ah->hw_version.macVersion, | 1506 | ah->hw_version.macVersion, |
1511 | ah->hw_version.macRev, | 1507 | ah->hw_version.macRev, |
1512 | ah->opmode, | 1508 | ah->opmode, |
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c index 157337febc2b..c55e5bbafc46 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c | |||
@@ -61,18 +61,16 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah, | |||
61 | switch (currCal->calData->calType) { | 61 | switch (currCal->calData->calType) { |
62 | case IQ_MISMATCH_CAL: | 62 | case IQ_MISMATCH_CAL: |
63 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | 63 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); |
64 | ath_dbg(common, ATH_DBG_CALIBRATE, | 64 | ath_dbg(common, CALIBRATE, |
65 | "starting IQ Mismatch Calibration\n"); | 65 | "starting IQ Mismatch Calibration\n"); |
66 | break; | 66 | break; |
67 | case ADC_GAIN_CAL: | 67 | case ADC_GAIN_CAL: |
68 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); | 68 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); |
69 | ath_dbg(common, ATH_DBG_CALIBRATE, | 69 | ath_dbg(common, CALIBRATE, "starting ADC Gain Calibration\n"); |
70 | "starting ADC Gain Calibration\n"); | ||
71 | break; | 70 | break; |
72 | case ADC_DC_CAL: | 71 | case ADC_DC_CAL: |
73 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); | 72 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); |
74 | ath_dbg(common, ATH_DBG_CALIBRATE, | 73 | ath_dbg(common, CALIBRATE, "starting ADC DC Calibration\n"); |
75 | "starting ADC DC Calibration\n"); | ||
76 | break; | 74 | break; |
77 | } | 75 | } |
78 | 76 | ||
@@ -129,7 +127,7 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah) | |||
129 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | 127 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
130 | ah->totalIqCorrMeas[i] += | 128 | ah->totalIqCorrMeas[i] += |
131 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | 129 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
132 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 130 | ath_dbg(ath9k_hw_common(ah), CALIBRATE, |
133 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | 131 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", |
134 | ah->cal_samples, i, ah->totalPowerMeasI[i], | 132 | ah->cal_samples, i, ah->totalPowerMeasI[i], |
135 | ah->totalPowerMeasQ[i], | 133 | ah->totalPowerMeasQ[i], |
@@ -151,7 +149,7 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah) | |||
151 | ah->totalAdcQEvenPhase[i] += | 149 | ah->totalAdcQEvenPhase[i] += |
152 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | 150 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
153 | 151 | ||
154 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 152 | ath_dbg(ath9k_hw_common(ah), CALIBRATE, |
155 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", | 153 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", |
156 | ah->cal_samples, i, | 154 | ah->cal_samples, i, |
157 | ah->totalAdcIOddPhase[i], | 155 | ah->totalAdcIOddPhase[i], |
@@ -175,7 +173,7 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah) | |||
175 | ah->totalAdcDcOffsetQEvenPhase[i] += | 173 | ah->totalAdcDcOffsetQEvenPhase[i] += |
176 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); | 174 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
177 | 175 | ||
178 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 176 | ath_dbg(ath9k_hw_common(ah), CALIBRATE, |
179 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", | 177 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n", |
180 | ah->cal_samples, i, | 178 | ah->cal_samples, i, |
181 | ah->totalAdcDcOffsetIOddPhase[i], | 179 | ah->totalAdcDcOffsetIOddPhase[i], |
@@ -198,11 +196,11 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
198 | powerMeasQ = ah->totalPowerMeasQ[i]; | 196 | powerMeasQ = ah->totalPowerMeasQ[i]; |
199 | iqCorrMeas = ah->totalIqCorrMeas[i]; | 197 | iqCorrMeas = ah->totalIqCorrMeas[i]; |
200 | 198 | ||
201 | ath_dbg(common, ATH_DBG_CALIBRATE, | 199 | ath_dbg(common, CALIBRATE, |
202 | "Starting IQ Cal and Correction for Chain %d\n", | 200 | "Starting IQ Cal and Correction for Chain %d\n", |
203 | i); | 201 | i); |
204 | 202 | ||
205 | ath_dbg(common, ATH_DBG_CALIBRATE, | 203 | ath_dbg(common, CALIBRATE, |
206 | "Original: Chn %d iq_corr_meas = 0x%08x\n", | 204 | "Original: Chn %d iq_corr_meas = 0x%08x\n", |
207 | i, ah->totalIqCorrMeas[i]); | 205 | i, ah->totalIqCorrMeas[i]); |
208 | 206 | ||
@@ -213,12 +211,11 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
213 | iqCorrNeg = 1; | 211 | iqCorrNeg = 1; |
214 | } | 212 | } |
215 | 213 | ||
216 | ath_dbg(common, ATH_DBG_CALIBRATE, | 214 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n", |
217 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | 215 | i, powerMeasI); |
218 | ath_dbg(common, ATH_DBG_CALIBRATE, | 216 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n", |
219 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | 217 | i, powerMeasQ); |
220 | ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | 218 | ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg); |
221 | iqCorrNeg); | ||
222 | 219 | ||
223 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; | 220 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; |
224 | qCoffDenom = powerMeasQ / 64; | 221 | qCoffDenom = powerMeasQ / 64; |
@@ -227,13 +224,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
227 | (qCoffDenom != 0)) { | 224 | (qCoffDenom != 0)) { |
228 | iCoff = iqCorrMeas / iCoffDenom; | 225 | iCoff = iqCorrMeas / iCoffDenom; |
229 | qCoff = powerMeasI / qCoffDenom - 64; | 226 | qCoff = powerMeasI / qCoffDenom - 64; |
230 | ath_dbg(common, ATH_DBG_CALIBRATE, | 227 | ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n", |
231 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | 228 | i, iCoff); |
232 | ath_dbg(common, ATH_DBG_CALIBRATE, | 229 | ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n", |
233 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | 230 | i, qCoff); |
234 | 231 | ||
235 | iCoff = iCoff & 0x3f; | 232 | iCoff = iCoff & 0x3f; |
236 | ath_dbg(common, ATH_DBG_CALIBRATE, | 233 | ath_dbg(common, CALIBRATE, |
237 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); | 234 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); |
238 | if (iqCorrNeg == 0x0) | 235 | if (iqCorrNeg == 0x0) |
239 | iCoff = 0x40 - iCoff; | 236 | iCoff = 0x40 - iCoff; |
@@ -243,7 +240,7 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
243 | else if (qCoff <= -16) | 240 | else if (qCoff <= -16) |
244 | qCoff = -16; | 241 | qCoff = -16; |
245 | 242 | ||
246 | ath_dbg(common, ATH_DBG_CALIBRATE, | 243 | ath_dbg(common, CALIBRATE, |
247 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | 244 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", |
248 | i, iCoff, qCoff); | 245 | i, iCoff, qCoff); |
249 | 246 | ||
@@ -253,7 +250,7 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
253 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | 250 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), |
254 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, | 251 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, |
255 | qCoff); | 252 | qCoff); |
256 | ath_dbg(common, ATH_DBG_CALIBRATE, | 253 | ath_dbg(common, CALIBRATE, |
257 | "IQ Cal and Correction done for Chain %d\n", | 254 | "IQ Cal and Correction done for Chain %d\n", |
258 | i); | 255 | i); |
259 | } | 256 | } |
@@ -275,21 +272,17 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) | |||
275 | qOddMeasOffset = ah->totalAdcQOddPhase[i]; | 272 | qOddMeasOffset = ah->totalAdcQOddPhase[i]; |
276 | qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; | 273 | qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; |
277 | 274 | ||
278 | ath_dbg(common, ATH_DBG_CALIBRATE, | 275 | ath_dbg(common, CALIBRATE, |
279 | "Starting ADC Gain Cal for Chain %d\n", i); | 276 | "Starting ADC Gain Cal for Chain %d\n", i); |
280 | 277 | ||
281 | ath_dbg(common, ATH_DBG_CALIBRATE, | 278 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_i = 0x%08x\n", |
282 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, | 279 | i, iOddMeasOffset); |
283 | iOddMeasOffset); | 280 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_i = 0x%08x\n", |
284 | ath_dbg(common, ATH_DBG_CALIBRATE, | 281 | i, iEvenMeasOffset); |
285 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, | 282 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_q = 0x%08x\n", |
286 | iEvenMeasOffset); | 283 | i, qOddMeasOffset); |
287 | ath_dbg(common, ATH_DBG_CALIBRATE, | 284 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_q = 0x%08x\n", |
288 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, | 285 | i, qEvenMeasOffset); |
289 | qOddMeasOffset); | ||
290 | ath_dbg(common, ATH_DBG_CALIBRATE, | ||
291 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, | ||
292 | qEvenMeasOffset); | ||
293 | 286 | ||
294 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { | 287 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { |
295 | iGainMismatch = | 288 | iGainMismatch = |
@@ -299,19 +292,19 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) | |||
299 | ((qOddMeasOffset * 32) / | 292 | ((qOddMeasOffset * 32) / |
300 | qEvenMeasOffset) & 0x3f; | 293 | qEvenMeasOffset) & 0x3f; |
301 | 294 | ||
302 | ath_dbg(common, ATH_DBG_CALIBRATE, | 295 | ath_dbg(common, CALIBRATE, |
303 | "Chn %d gain_mismatch_i = 0x%08x\n", i, | 296 | "Chn %d gain_mismatch_i = 0x%08x\n", |
304 | iGainMismatch); | 297 | i, iGainMismatch); |
305 | ath_dbg(common, ATH_DBG_CALIBRATE, | 298 | ath_dbg(common, CALIBRATE, |
306 | "Chn %d gain_mismatch_q = 0x%08x\n", i, | 299 | "Chn %d gain_mismatch_q = 0x%08x\n", |
307 | qGainMismatch); | 300 | i, qGainMismatch); |
308 | 301 | ||
309 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | 302 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); |
310 | val &= 0xfffff000; | 303 | val &= 0xfffff000; |
311 | val |= (qGainMismatch) | (iGainMismatch << 6); | 304 | val |= (qGainMismatch) | (iGainMismatch << 6); |
312 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | 305 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); |
313 | 306 | ||
314 | ath_dbg(common, ATH_DBG_CALIBRATE, | 307 | ath_dbg(common, CALIBRATE, |
315 | "ADC Gain Cal done for Chain %d\n", i); | 308 | "ADC Gain Cal done for Chain %d\n", i); |
316 | } | 309 | } |
317 | } | 310 | } |
@@ -337,40 +330,36 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) | |||
337 | qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; | 330 | qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; |
338 | qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; | 331 | qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; |
339 | 332 | ||
340 | ath_dbg(common, ATH_DBG_CALIBRATE, | 333 | ath_dbg(common, CALIBRATE, |
341 | "Starting ADC DC Offset Cal for Chain %d\n", i); | 334 | "Starting ADC DC Offset Cal for Chain %d\n", i); |
342 | 335 | ||
343 | ath_dbg(common, ATH_DBG_CALIBRATE, | 336 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_i = %d\n", |
344 | "Chn %d pwr_meas_odd_i = %d\n", i, | 337 | i, iOddMeasOffset); |
345 | iOddMeasOffset); | 338 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_i = %d\n", |
346 | ath_dbg(common, ATH_DBG_CALIBRATE, | 339 | i, iEvenMeasOffset); |
347 | "Chn %d pwr_meas_even_i = %d\n", i, | 340 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_q = %d\n", |
348 | iEvenMeasOffset); | 341 | i, qOddMeasOffset); |
349 | ath_dbg(common, ATH_DBG_CALIBRATE, | 342 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_q = %d\n", |
350 | "Chn %d pwr_meas_odd_q = %d\n", i, | 343 | i, qEvenMeasOffset); |
351 | qOddMeasOffset); | ||
352 | ath_dbg(common, ATH_DBG_CALIBRATE, | ||
353 | "Chn %d pwr_meas_even_q = %d\n", i, | ||
354 | qEvenMeasOffset); | ||
355 | 344 | ||
356 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / | 345 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / |
357 | numSamples) & 0x1ff; | 346 | numSamples) & 0x1ff; |
358 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / | 347 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / |
359 | numSamples) & 0x1ff; | 348 | numSamples) & 0x1ff; |
360 | 349 | ||
361 | ath_dbg(common, ATH_DBG_CALIBRATE, | 350 | ath_dbg(common, CALIBRATE, |
362 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, | 351 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", |
363 | iDcMismatch); | 352 | i, iDcMismatch); |
364 | ath_dbg(common, ATH_DBG_CALIBRATE, | 353 | ath_dbg(common, CALIBRATE, |
365 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, | 354 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", |
366 | qDcMismatch); | 355 | i, qDcMismatch); |
367 | 356 | ||
368 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | 357 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); |
369 | val &= 0xc0000fff; | 358 | val &= 0xc0000fff; |
370 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); | 359 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); |
371 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | 360 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); |
372 | 361 | ||
373 | ath_dbg(common, ATH_DBG_CALIBRATE, | 362 | ath_dbg(common, CALIBRATE, |
374 | "ADC DC Offset Cal done for Chain %d\n", i); | 363 | "ADC DC Offset Cal done for Chain %d\n", i); |
375 | } | 364 | } |
376 | 365 | ||
@@ -560,7 +549,7 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) | |||
560 | { 0x7838, 0 }, | 549 | { 0x7838, 0 }, |
561 | }; | 550 | }; |
562 | 551 | ||
563 | ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); | 552 | ath_dbg(common, CALIBRATE, "Running PA Calibration\n"); |
564 | 553 | ||
565 | /* PA CAL is not needed for high power solution */ | 554 | /* PA CAL is not needed for high power solution */ |
566 | if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == | 555 | if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == |
@@ -741,7 +730,7 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
741 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); | 730 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
742 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, | 731 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, |
743 | AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { | 732 | AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { |
744 | ath_dbg(common, ATH_DBG_CALIBRATE, | 733 | ath_dbg(common, CALIBRATE, |
745 | "offset calibration failed to complete in 1ms; noisy environment?\n"); | 734 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
746 | return false; | 735 | return false; |
747 | } | 736 | } |
@@ -755,7 +744,7 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
755 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); | 744 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); |
756 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, | 745 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, |
757 | 0, AH_WAIT_TIMEOUT)) { | 746 | 0, AH_WAIT_TIMEOUT)) { |
758 | ath_dbg(common, ATH_DBG_CALIBRATE, | 747 | ath_dbg(common, CALIBRATE, |
759 | "offset calibration failed to complete in 1ms; noisy environment?\n"); | 748 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
760 | return false; | 749 | return false; |
761 | } | 750 | } |
@@ -851,7 +840,7 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
851 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, | 840 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, |
852 | AR_PHY_AGC_CONTROL_CAL, | 841 | AR_PHY_AGC_CONTROL_CAL, |
853 | 0, AH_WAIT_TIMEOUT)) { | 842 | 0, AH_WAIT_TIMEOUT)) { |
854 | ath_dbg(common, ATH_DBG_CALIBRATE, | 843 | ath_dbg(common, CALIBRATE, |
855 | "offset calibration failed to complete in 1ms; noisy environment?\n"); | 844 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
856 | return false; | 845 | return false; |
857 | } | 846 | } |
@@ -886,22 +875,21 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) | |||
886 | if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) { | 875 | if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) { |
887 | INIT_CAL(&ah->adcgain_caldata); | 876 | INIT_CAL(&ah->adcgain_caldata); |
888 | INSERT_CAL(ah, &ah->adcgain_caldata); | 877 | INSERT_CAL(ah, &ah->adcgain_caldata); |
889 | ath_dbg(common, ATH_DBG_CALIBRATE, | 878 | ath_dbg(common, CALIBRATE, |
890 | "enabling ADC Gain Calibration.\n"); | 879 | "enabling ADC Gain Calibration\n"); |
891 | } | 880 | } |
892 | 881 | ||
893 | if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) { | 882 | if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) { |
894 | INIT_CAL(&ah->adcdc_caldata); | 883 | INIT_CAL(&ah->adcdc_caldata); |
895 | INSERT_CAL(ah, &ah->adcdc_caldata); | 884 | INSERT_CAL(ah, &ah->adcdc_caldata); |
896 | ath_dbg(common, ATH_DBG_CALIBRATE, | 885 | ath_dbg(common, CALIBRATE, |
897 | "enabling ADC DC Calibration.\n"); | 886 | "enabling ADC DC Calibration\n"); |
898 | } | 887 | } |
899 | 888 | ||
900 | if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) { | 889 | if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) { |
901 | INIT_CAL(&ah->iq_caldata); | 890 | INIT_CAL(&ah->iq_caldata); |
902 | INSERT_CAL(ah, &ah->iq_caldata); | 891 | INSERT_CAL(ah, &ah->iq_caldata); |
903 | ath_dbg(common, ATH_DBG_CALIBRATE, | 892 | ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n"); |
904 | "enabling IQ Calibration.\n"); | ||
905 | } | 893 | } |
906 | 894 | ||
907 | ah->cal_list_curr = ah->cal_list; | 895 | ah->cal_list_curr = ah->cal_list; |
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c index b5920168606d..7b6417b5212e 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c | |||
@@ -107,7 +107,7 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
107 | } | 107 | } |
108 | 108 | ||
109 | if (isr & AR_ISR_RXORN) { | 109 | if (isr & AR_ISR_RXORN) { |
110 | ath_dbg(common, ATH_DBG_INTERRUPT, | 110 | ath_dbg(common, INTERRUPT, |
111 | "receive FIFO overrun interrupt\n"); | 111 | "receive FIFO overrun interrupt\n"); |
112 | } | 112 | } |
113 | 113 | ||
@@ -143,24 +143,24 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
143 | 143 | ||
144 | if (fatal_int) { | 144 | if (fatal_int) { |
145 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | 145 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { |
146 | ath_dbg(common, ATH_DBG_ANY, | 146 | ath_dbg(common, ANY, |
147 | "received PCI FATAL interrupt\n"); | 147 | "received PCI FATAL interrupt\n"); |
148 | } | 148 | } |
149 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | 149 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { |
150 | ath_dbg(common, ATH_DBG_ANY, | 150 | ath_dbg(common, ANY, |
151 | "received PCI PERR interrupt\n"); | 151 | "received PCI PERR interrupt\n"); |
152 | } | 152 | } |
153 | *masked |= ATH9K_INT_FATAL; | 153 | *masked |= ATH9K_INT_FATAL; |
154 | } | 154 | } |
155 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | 155 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
156 | ath_dbg(common, ATH_DBG_INTERRUPT, | 156 | ath_dbg(common, INTERRUPT, |
157 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); | 157 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); |
158 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); | 158 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
159 | REG_WRITE(ah, AR_RC, 0); | 159 | REG_WRITE(ah, AR_RC, 0); |
160 | *masked |= ATH9K_INT_FATAL; | 160 | *masked |= ATH9K_INT_FATAL; |
161 | } | 161 | } |
162 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | 162 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { |
163 | ath_dbg(common, ATH_DBG_INTERRUPT, | 163 | ath_dbg(common, INTERRUPT, |
164 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | 164 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
165 | } | 165 | } |
166 | 166 | ||
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c index 23b3a6c57800..8e70f0bc073e 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c | |||
@@ -52,7 +52,7 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah, | |||
52 | currCal->calData->calCountMax); | 52 | currCal->calData->calCountMax); |
53 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | 53 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); |
54 | 54 | ||
55 | ath_dbg(common, ATH_DBG_CALIBRATE, | 55 | ath_dbg(common, CALIBRATE, |
56 | "starting IQ Mismatch Calibration\n"); | 56 | "starting IQ Mismatch Calibration\n"); |
57 | 57 | ||
58 | /* Kick-off cal */ | 58 | /* Kick-off cal */ |
@@ -64,7 +64,7 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah, | |||
64 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, | 64 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, |
65 | AR_PHY_65NM_CH0_THERM_START, 1); | 65 | AR_PHY_65NM_CH0_THERM_START, 1); |
66 | 66 | ||
67 | ath_dbg(common, ATH_DBG_CALIBRATE, | 67 | ath_dbg(common, CALIBRATE, |
68 | "starting Temperature Compensation Calibration\n"); | 68 | "starting Temperature Compensation Calibration\n"); |
69 | break; | 69 | break; |
70 | } | 70 | } |
@@ -194,7 +194,7 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah) | |||
194 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); | 194 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
195 | ah->totalIqCorrMeas[i] += | 195 | ah->totalIqCorrMeas[i] += |
196 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); | 196 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
197 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 197 | ath_dbg(ath9k_hw_common(ah), CALIBRATE, |
198 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | 198 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", |
199 | ah->cal_samples, i, ah->totalPowerMeasI[i], | 199 | ah->cal_samples, i, ah->totalPowerMeasI[i], |
200 | ah->totalPowerMeasQ[i], | 200 | ah->totalPowerMeasQ[i], |
@@ -221,11 +221,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
221 | powerMeasQ = ah->totalPowerMeasQ[i]; | 221 | powerMeasQ = ah->totalPowerMeasQ[i]; |
222 | iqCorrMeas = ah->totalIqCorrMeas[i]; | 222 | iqCorrMeas = ah->totalIqCorrMeas[i]; |
223 | 223 | ||
224 | ath_dbg(common, ATH_DBG_CALIBRATE, | 224 | ath_dbg(common, CALIBRATE, |
225 | "Starting IQ Cal and Correction for Chain %d\n", | 225 | "Starting IQ Cal and Correction for Chain %d\n", i); |
226 | i); | ||
227 | 226 | ||
228 | ath_dbg(common, ATH_DBG_CALIBRATE, | 227 | ath_dbg(common, CALIBRATE, |
229 | "Original: Chn %d iq_corr_meas = 0x%08x\n", | 228 | "Original: Chn %d iq_corr_meas = 0x%08x\n", |
230 | i, ah->totalIqCorrMeas[i]); | 229 | i, ah->totalIqCorrMeas[i]); |
231 | 230 | ||
@@ -236,12 +235,11 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
236 | iqCorrNeg = 1; | 235 | iqCorrNeg = 1; |
237 | } | 236 | } |
238 | 237 | ||
239 | ath_dbg(common, ATH_DBG_CALIBRATE, | 238 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n", |
240 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | 239 | i, powerMeasI); |
241 | ath_dbg(common, ATH_DBG_CALIBRATE, | 240 | ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n", |
242 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | 241 | i, powerMeasQ); |
243 | ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | 242 | ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg); |
244 | iqCorrNeg); | ||
245 | 243 | ||
246 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256; | 244 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256; |
247 | qCoffDenom = powerMeasQ / 64; | 245 | qCoffDenom = powerMeasQ / 64; |
@@ -249,10 +247,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
249 | if ((iCoffDenom != 0) && (qCoffDenom != 0)) { | 247 | if ((iCoffDenom != 0) && (qCoffDenom != 0)) { |
250 | iCoff = iqCorrMeas / iCoffDenom; | 248 | iCoff = iqCorrMeas / iCoffDenom; |
251 | qCoff = powerMeasI / qCoffDenom - 64; | 249 | qCoff = powerMeasI / qCoffDenom - 64; |
252 | ath_dbg(common, ATH_DBG_CALIBRATE, | 250 | ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n", |
253 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | 251 | i, iCoff); |
254 | ath_dbg(common, ATH_DBG_CALIBRATE, | 252 | ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n", |
255 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | 253 | i, qCoff); |
256 | 254 | ||
257 | /* Force bounds on iCoff */ | 255 | /* Force bounds on iCoff */ |
258 | if (iCoff >= 63) | 256 | if (iCoff >= 63) |
@@ -273,10 +271,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
273 | iCoff = iCoff & 0x7f; | 271 | iCoff = iCoff & 0x7f; |
274 | qCoff = qCoff & 0x7f; | 272 | qCoff = qCoff & 0x7f; |
275 | 273 | ||
276 | ath_dbg(common, ATH_DBG_CALIBRATE, | 274 | ath_dbg(common, CALIBRATE, |
277 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | 275 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", |
278 | i, iCoff, qCoff); | 276 | i, iCoff, qCoff); |
279 | ath_dbg(common, ATH_DBG_CALIBRATE, | 277 | ath_dbg(common, CALIBRATE, |
280 | "Register offset (0x%04x) before update = 0x%x\n", | 278 | "Register offset (0x%04x) before update = 0x%x\n", |
281 | offset_array[i], | 279 | offset_array[i], |
282 | REG_READ(ah, offset_array[i])); | 280 | REG_READ(ah, offset_array[i])); |
@@ -287,25 +285,25 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) | |||
287 | REG_RMW_FIELD(ah, offset_array[i], | 285 | REG_RMW_FIELD(ah, offset_array[i], |
288 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, | 286 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, |
289 | qCoff); | 287 | qCoff); |
290 | ath_dbg(common, ATH_DBG_CALIBRATE, | 288 | ath_dbg(common, CALIBRATE, |
291 | "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n", | 289 | "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n", |
292 | offset_array[i], | 290 | offset_array[i], |
293 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, | 291 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, |
294 | REG_READ(ah, offset_array[i])); | 292 | REG_READ(ah, offset_array[i])); |
295 | ath_dbg(common, ATH_DBG_CALIBRATE, | 293 | ath_dbg(common, CALIBRATE, |
296 | "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n", | 294 | "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n", |
297 | offset_array[i], | 295 | offset_array[i], |
298 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, | 296 | AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, |
299 | REG_READ(ah, offset_array[i])); | 297 | REG_READ(ah, offset_array[i])); |
300 | 298 | ||
301 | ath_dbg(common, ATH_DBG_CALIBRATE, | 299 | ath_dbg(common, CALIBRATE, |
302 | "IQ Cal and Correction done for Chain %d\n", i); | 300 | "IQ Cal and Correction done for Chain %d\n", i); |
303 | } | 301 | } |
304 | } | 302 | } |
305 | 303 | ||
306 | REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, | 304 | REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, |
307 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); | 305 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); |
308 | ath_dbg(common, ATH_DBG_CALIBRATE, | 306 | ath_dbg(common, CALIBRATE, |
309 | "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n", | 307 | "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n", |
310 | (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), | 308 | (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), |
311 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, | 309 | AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, |
@@ -349,7 +347,7 @@ static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah, | |||
349 | f2 = (f1 * f1 + f3 * f3) / result_shift; | 347 | f2 = (f1 * f1 + f3 * f3) / result_shift; |
350 | 348 | ||
351 | if (!f2) { | 349 | if (!f2) { |
352 | ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n"); | 350 | ath_dbg(common, CALIBRATE, "Divide by 0\n"); |
353 | return false; | 351 | return false; |
354 | } | 352 | } |
355 | 353 | ||
@@ -470,7 +468,7 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
470 | 468 | ||
471 | if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) || | 469 | if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) || |
472 | (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) { | 470 | (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) { |
473 | ath_dbg(common, ATH_DBG_CALIBRATE, | 471 | ath_dbg(common, CALIBRATE, |
474 | "Divide by 0:\n" | 472 | "Divide by 0:\n" |
475 | "a0_d0=%d\n" | 473 | "a0_d0=%d\n" |
476 | "a0_d1=%d\n" | 474 | "a0_d1=%d\n" |
@@ -510,8 +508,7 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
510 | mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); | 508 | mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); |
511 | 509 | ||
512 | if ((mag1 == 0) || (mag2 == 0)) { | 510 | if ((mag1 == 0) || (mag2 == 0)) { |
513 | ath_dbg(common, ATH_DBG_CALIBRATE, | 511 | ath_dbg(common, CALIBRATE, "Divide by 0: mag1=%d, mag2=%d\n", |
514 | "Divide by 0: mag1=%d, mag2=%d\n", | ||
515 | mag1, mag2); | 512 | mag1, mag2); |
516 | return false; | 513 | return false; |
517 | } | 514 | } |
@@ -529,8 +526,8 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
529 | mag_a0_d0, phs_a0_d0, | 526 | mag_a0_d0, phs_a0_d0, |
530 | mag_a1_d0, | 527 | mag_a1_d0, |
531 | phs_a1_d0, solved_eq)) { | 528 | phs_a1_d0, solved_eq)) { |
532 | ath_dbg(common, ATH_DBG_CALIBRATE, | 529 | ath_dbg(common, CALIBRATE, |
533 | "Call to ar9003_hw_solve_iq_cal() failed.\n"); | 530 | "Call to ar9003_hw_solve_iq_cal() failed\n"); |
534 | return false; | 531 | return false; |
535 | } | 532 | } |
536 | 533 | ||
@@ -539,12 +536,12 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
539 | mag_rx = solved_eq[2]; | 536 | mag_rx = solved_eq[2]; |
540 | phs_rx = solved_eq[3]; | 537 | phs_rx = solved_eq[3]; |
541 | 538 | ||
542 | ath_dbg(common, ATH_DBG_CALIBRATE, | 539 | ath_dbg(common, CALIBRATE, |
543 | "chain %d: mag mismatch=%d phase mismatch=%d\n", | 540 | "chain %d: mag mismatch=%d phase mismatch=%d\n", |
544 | chain_idx, mag_tx/res_scale, phs_tx/res_scale); | 541 | chain_idx, mag_tx/res_scale, phs_tx/res_scale); |
545 | 542 | ||
546 | if (res_scale == mag_tx) { | 543 | if (res_scale == mag_tx) { |
547 | ath_dbg(common, ATH_DBG_CALIBRATE, | 544 | ath_dbg(common, CALIBRATE, |
548 | "Divide by 0: mag_tx=%d, res_scale=%d\n", | 545 | "Divide by 0: mag_tx=%d, res_scale=%d\n", |
549 | mag_tx, res_scale); | 546 | mag_tx, res_scale); |
550 | return false; | 547 | return false; |
@@ -557,8 +554,7 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
557 | q_q_coff = (mag_corr_tx * 128 / res_scale); | 554 | q_q_coff = (mag_corr_tx * 128 / res_scale); |
558 | q_i_coff = (phs_corr_tx * 256 / res_scale); | 555 | q_i_coff = (phs_corr_tx * 256 / res_scale); |
559 | 556 | ||
560 | ath_dbg(common, ATH_DBG_CALIBRATE, | 557 | ath_dbg(common, CALIBRATE, "tx chain %d: mag corr=%d phase corr=%d\n", |
561 | "tx chain %d: mag corr=%d phase corr=%d\n", | ||
562 | chain_idx, q_q_coff, q_i_coff); | 558 | chain_idx, q_q_coff, q_i_coff); |
563 | 559 | ||
564 | if (q_i_coff < -63) | 560 | if (q_i_coff < -63) |
@@ -572,12 +568,11 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
572 | 568 | ||
573 | iqc_coeff[0] = (q_q_coff * 128) + q_i_coff; | 569 | iqc_coeff[0] = (q_q_coff * 128) + q_i_coff; |
574 | 570 | ||
575 | ath_dbg(common, ATH_DBG_CALIBRATE, | 571 | ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n", |
576 | "tx chain %d: iq corr coeff=%x\n", | ||
577 | chain_idx, iqc_coeff[0]); | 572 | chain_idx, iqc_coeff[0]); |
578 | 573 | ||
579 | if (-mag_rx == res_scale) { | 574 | if (-mag_rx == res_scale) { |
580 | ath_dbg(common, ATH_DBG_CALIBRATE, | 575 | ath_dbg(common, CALIBRATE, |
581 | "Divide by 0: mag_rx=%d, res_scale=%d\n", | 576 | "Divide by 0: mag_rx=%d, res_scale=%d\n", |
582 | mag_rx, res_scale); | 577 | mag_rx, res_scale); |
583 | return false; | 578 | return false; |
@@ -590,8 +585,7 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
590 | q_q_coff = (mag_corr_rx * 128 / res_scale); | 585 | q_q_coff = (mag_corr_rx * 128 / res_scale); |
591 | q_i_coff = (phs_corr_rx * 256 / res_scale); | 586 | q_i_coff = (phs_corr_rx * 256 / res_scale); |
592 | 587 | ||
593 | ath_dbg(common, ATH_DBG_CALIBRATE, | 588 | ath_dbg(common, CALIBRATE, "rx chain %d: mag corr=%d phase corr=%d\n", |
594 | "rx chain %d: mag corr=%d phase corr=%d\n", | ||
595 | chain_idx, q_q_coff, q_i_coff); | 589 | chain_idx, q_q_coff, q_i_coff); |
596 | 590 | ||
597 | if (q_i_coff < -63) | 591 | if (q_i_coff < -63) |
@@ -605,8 +599,7 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, | |||
605 | 599 | ||
606 | iqc_coeff[1] = (q_q_coff * 128) + q_i_coff; | 600 | iqc_coeff[1] = (q_q_coff * 128) + q_i_coff; |
607 | 601 | ||
608 | ath_dbg(common, ATH_DBG_CALIBRATE, | 602 | ath_dbg(common, CALIBRATE, "rx chain %d: iq corr coeff=%x\n", |
609 | "rx chain %d: iq corr coeff=%x\n", | ||
610 | chain_idx, iqc_coeff[1]); | 603 | chain_idx, iqc_coeff[1]); |
611 | 604 | ||
612 | return true; | 605 | return true; |
@@ -753,8 +746,7 @@ static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah) | |||
753 | if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, | 746 | if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, |
754 | AR_PHY_TX_IQCAL_START_DO_CAL, 0, | 747 | AR_PHY_TX_IQCAL_START_DO_CAL, 0, |
755 | AH_WAIT_TIMEOUT)) { | 748 | AH_WAIT_TIMEOUT)) { |
756 | ath_dbg(common, ATH_DBG_CALIBRATE, | 749 | ath_dbg(common, CALIBRATE, "Tx IQ Cal is not completed\n"); |
757 | "Tx IQ Cal is not completed.\n"); | ||
758 | return false; | 750 | return false; |
759 | } | 751 | } |
760 | return true; | 752 | return true; |
@@ -792,13 +784,13 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable) | |||
792 | nmeasurement = MAX_MEASUREMENT; | 784 | nmeasurement = MAX_MEASUREMENT; |
793 | 785 | ||
794 | for (im = 0; im < nmeasurement; im++) { | 786 | for (im = 0; im < nmeasurement; im++) { |
795 | ath_dbg(common, ATH_DBG_CALIBRATE, | 787 | ath_dbg(common, CALIBRATE, |
796 | "Doing Tx IQ Cal for chain %d.\n", i); | 788 | "Doing Tx IQ Cal for chain %d\n", i); |
797 | 789 | ||
798 | if (REG_READ(ah, txiqcal_status[i]) & | 790 | if (REG_READ(ah, txiqcal_status[i]) & |
799 | AR_PHY_TX_IQCAL_STATUS_FAILED) { | 791 | AR_PHY_TX_IQCAL_STATUS_FAILED) { |
800 | ath_dbg(common, ATH_DBG_CALIBRATE, | 792 | ath_dbg(common, CALIBRATE, |
801 | "Tx IQ Cal failed for chain %d.\n", i); | 793 | "Tx IQ Cal failed for chain %d\n", i); |
802 | goto tx_iqcal_fail; | 794 | goto tx_iqcal_fail; |
803 | } | 795 | } |
804 | 796 | ||
@@ -824,18 +816,16 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable) | |||
824 | iq_res[idx + 1] = 0xffff & REG_READ(ah, | 816 | iq_res[idx + 1] = 0xffff & REG_READ(ah, |
825 | chan_info_tab[i] + offset); | 817 | chan_info_tab[i] + offset); |
826 | 818 | ||
827 | ath_dbg(common, ATH_DBG_CALIBRATE, | 819 | ath_dbg(common, CALIBRATE, |
828 | "IQ_RES[%d]=0x%x " | 820 | "IQ_RES[%d]=0x%x IQ_RES[%d]=0x%x\n", |
829 | "IQ_RES[%d]=0x%x\n", | ||
830 | idx, iq_res[idx], idx + 1, | 821 | idx, iq_res[idx], idx + 1, |
831 | iq_res[idx + 1]); | 822 | iq_res[idx + 1]); |
832 | } | 823 | } |
833 | 824 | ||
834 | if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, | 825 | if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, |
835 | coeff.iqc_coeff)) { | 826 | coeff.iqc_coeff)) { |
836 | ath_dbg(common, ATH_DBG_CALIBRATE, | 827 | ath_dbg(common, CALIBRATE, |
837 | "Failed in calculation of \ | 828 | "Failed in calculation of IQ correction\n"); |
838 | IQ correction.\n"); | ||
839 | goto tx_iqcal_fail; | 829 | goto tx_iqcal_fail; |
840 | } | 830 | } |
841 | 831 | ||
@@ -855,7 +845,7 @@ static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable) | |||
855 | return; | 845 | return; |
856 | 846 | ||
857 | tx_iqcal_fail: | 847 | tx_iqcal_fail: |
858 | ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); | 848 | ath_dbg(common, CALIBRATE, "Tx IQ Cal failed\n"); |
859 | return; | 849 | return; |
860 | } | 850 | } |
861 | 851 | ||
@@ -953,7 +943,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, | |||
953 | if (!ar9003_hw_rtt_restore(ah, chan)) | 943 | if (!ar9003_hw_rtt_restore(ah, chan)) |
954 | run_rtt_cal = true; | 944 | run_rtt_cal = true; |
955 | 945 | ||
956 | ath_dbg(common, ATH_DBG_CALIBRATE, "RTT restore %s\n", | 946 | ath_dbg(common, CALIBRATE, "RTT restore %s\n", |
957 | run_rtt_cal ? "failed" : "succeed"); | 947 | run_rtt_cal ? "failed" : "succeed"); |
958 | } | 948 | } |
959 | run_agc_cal = run_rtt_cal; | 949 | run_agc_cal = run_rtt_cal; |
@@ -1016,20 +1006,20 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, | |||
1016 | u32 pld[4] = {0, 0, 0, 0}; | 1006 | u32 pld[4] = {0, 0, 0, 0}; |
1017 | 1007 | ||
1018 | /* send CAL_REQ only when BT is AWAKE. */ | 1008 | /* send CAL_REQ only when BT is AWAKE. */ |
1019 | ath_dbg(common, ATH_DBG_MCI, "MCI send WLAN_CAL_REQ 0x%x\n", | 1009 | ath_dbg(common, MCI, "MCI send WLAN_CAL_REQ 0x%x\n", |
1020 | mci_hw->wlan_cal_seq); | 1010 | mci_hw->wlan_cal_seq); |
1021 | MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_REQ); | 1011 | MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_REQ); |
1022 | pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_seq++; | 1012 | pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_seq++; |
1023 | ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false); | 1013 | ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false); |
1024 | 1014 | ||
1025 | /* Wait BT_CAL_GRANT for 50ms */ | 1015 | /* Wait BT_CAL_GRANT for 50ms */ |
1026 | ath_dbg(common, ATH_DBG_MCI, "MCI wait for BT_CAL_GRANT"); | 1016 | ath_dbg(common, MCI, "MCI wait for BT_CAL_GRANT\n"); |
1027 | 1017 | ||
1028 | if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) | 1018 | if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000)) |
1029 | ath_dbg(common, ATH_DBG_MCI, "MCI got BT_CAL_GRANT"); | 1019 | ath_dbg(common, MCI, "MCI got BT_CAL_GRANT\n"); |
1030 | else { | 1020 | else { |
1031 | is_reusable = false; | 1021 | is_reusable = false; |
1032 | ath_dbg(common, ATH_DBG_MCI, "\nMCI BT is not responding"); | 1022 | ath_dbg(common, MCI, "\nMCI BT is not responding\n"); |
1033 | } | 1023 | } |
1034 | } | 1024 | } |
1035 | 1025 | ||
@@ -1058,7 +1048,7 @@ skip_tx_iqcal: | |||
1058 | 1048 | ||
1059 | u32 pld[4] = {0, 0, 0, 0}; | 1049 | u32 pld[4] = {0, 0, 0, 0}; |
1060 | 1050 | ||
1061 | ath_dbg(common, ATH_DBG_MCI, "MCI Send WLAN_CAL_DONE 0x%x\n", | 1051 | ath_dbg(common, MCI, "MCI Send WLAN_CAL_DONE 0x%x\n", |
1062 | mci_hw->wlan_cal_done); | 1052 | mci_hw->wlan_cal_done); |
1063 | MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_DONE); | 1053 | MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_DONE); |
1064 | pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_done++; | 1054 | pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_done++; |
@@ -1074,9 +1064,8 @@ skip_tx_iqcal: | |||
1074 | if (run_rtt_cal) | 1064 | if (run_rtt_cal) |
1075 | ar9003_hw_rtt_disable(ah); | 1065 | ar9003_hw_rtt_disable(ah); |
1076 | 1066 | ||
1077 | ath_dbg(common, ATH_DBG_CALIBRATE, | 1067 | ath_dbg(common, CALIBRATE, |
1078 | "offset calibration failed to complete in 1ms;" | 1068 | "offset calibration failed to complete in 1ms; noisy environment?\n"); |
1079 | "noisy environment?\n"); | ||
1080 | return false; | 1069 | return false; |
1081 | } | 1070 | } |
1082 | 1071 | ||
@@ -1135,15 +1124,14 @@ skip_tx_iqcal: | |||
1135 | if (ah->supp_cals & IQ_MISMATCH_CAL) { | 1124 | if (ah->supp_cals & IQ_MISMATCH_CAL) { |
1136 | INIT_CAL(&ah->iq_caldata); | 1125 | INIT_CAL(&ah->iq_caldata); |
1137 | INSERT_CAL(ah, &ah->iq_caldata); | 1126 | INSERT_CAL(ah, &ah->iq_caldata); |
1138 | ath_dbg(common, ATH_DBG_CALIBRATE, | 1127 | ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n"); |
1139 | "enabling IQ Calibration.\n"); | ||
1140 | } | 1128 | } |
1141 | 1129 | ||
1142 | if (ah->supp_cals & TEMP_COMP_CAL) { | 1130 | if (ah->supp_cals & TEMP_COMP_CAL) { |
1143 | INIT_CAL(&ah->tempCompCalData); | 1131 | INIT_CAL(&ah->tempCompCalData); |
1144 | INSERT_CAL(ah, &ah->tempCompCalData); | 1132 | INSERT_CAL(ah, &ah->tempCompCalData); |
1145 | ath_dbg(common, ATH_DBG_CALIBRATE, | 1133 | ath_dbg(common, CALIBRATE, |
1146 | "enabling Temperature Compensation Calibration.\n"); | 1134 | "enabling Temperature Compensation Calibration\n"); |
1147 | } | 1135 | } |
1148 | 1136 | ||
1149 | /* Initialize current pointer to first element in list */ | 1137 | /* Initialize current pointer to first element in list */ |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 4ba6f52943a8..391def99314c 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
@@ -3043,8 +3043,7 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, | |||
3043 | int i; | 3043 | int i; |
3044 | 3044 | ||
3045 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { | 3045 | if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { |
3046 | ath_dbg(common, ATH_DBG_EEPROM, | 3046 | ath_dbg(common, EEPROM, "eeprom address not in range\n"); |
3047 | "eeprom address not in range\n"); | ||
3048 | return false; | 3047 | return false; |
3049 | } | 3048 | } |
3050 | 3049 | ||
@@ -3075,8 +3074,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, | |||
3075 | return true; | 3074 | return true; |
3076 | 3075 | ||
3077 | error: | 3076 | error: |
3078 | ath_dbg(common, ATH_DBG_EEPROM, | 3077 | ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n", |
3079 | "unable to read eeprom region at offset %d\n", address); | 3078 | address); |
3080 | return false; | 3079 | return false; |
3081 | } | 3080 | } |
3082 | 3081 | ||
@@ -3160,13 +3159,13 @@ static bool ar9300_uncompress_block(struct ath_hw *ah, | |||
3160 | length &= 0xff; | 3159 | length &= 0xff; |
3161 | 3160 | ||
3162 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { | 3161 | if (length > 0 && spot >= 0 && spot+length <= mdataSize) { |
3163 | ath_dbg(common, ATH_DBG_EEPROM, | 3162 | ath_dbg(common, EEPROM, |
3164 | "Restore at %d: spot=%d offset=%d length=%d\n", | 3163 | "Restore at %d: spot=%d offset=%d length=%d\n", |
3165 | it, spot, offset, length); | 3164 | it, spot, offset, length); |
3166 | memcpy(&mptr[spot], &block[it+2], length); | 3165 | memcpy(&mptr[spot], &block[it+2], length); |
3167 | spot += length; | 3166 | spot += length; |
3168 | } else if (length > 0) { | 3167 | } else if (length > 0) { |
3169 | ath_dbg(common, ATH_DBG_EEPROM, | 3168 | ath_dbg(common, EEPROM, |
3170 | "Bad restore at %d: spot=%d offset=%d length=%d\n", | 3169 | "Bad restore at %d: spot=%d offset=%d length=%d\n", |
3171 | it, spot, offset, length); | 3170 | it, spot, offset, length); |
3172 | return false; | 3171 | return false; |
@@ -3188,13 +3187,13 @@ static int ar9300_compress_decision(struct ath_hw *ah, | |||
3188 | switch (code) { | 3187 | switch (code) { |
3189 | case _CompressNone: | 3188 | case _CompressNone: |
3190 | if (length != mdata_size) { | 3189 | if (length != mdata_size) { |
3191 | ath_dbg(common, ATH_DBG_EEPROM, | 3190 | ath_dbg(common, EEPROM, |
3192 | "EEPROM structure size mismatch memory=%d eeprom=%d\n", | 3191 | "EEPROM structure size mismatch memory=%d eeprom=%d\n", |
3193 | mdata_size, length); | 3192 | mdata_size, length); |
3194 | return -1; | 3193 | return -1; |
3195 | } | 3194 | } |
3196 | memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); | 3195 | memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length); |
3197 | ath_dbg(common, ATH_DBG_EEPROM, | 3196 | ath_dbg(common, EEPROM, |
3198 | "restored eeprom %d: uncompressed, length %d\n", | 3197 | "restored eeprom %d: uncompressed, length %d\n", |
3199 | it, length); | 3198 | it, length); |
3200 | break; | 3199 | break; |
@@ -3203,22 +3202,21 @@ static int ar9300_compress_decision(struct ath_hw *ah, | |||
3203 | } else { | 3202 | } else { |
3204 | eep = ar9003_eeprom_struct_find_by_id(reference); | 3203 | eep = ar9003_eeprom_struct_find_by_id(reference); |
3205 | if (eep == NULL) { | 3204 | if (eep == NULL) { |
3206 | ath_dbg(common, ATH_DBG_EEPROM, | 3205 | ath_dbg(common, EEPROM, |
3207 | "can't find reference eeprom struct %d\n", | 3206 | "can't find reference eeprom struct %d\n", |
3208 | reference); | 3207 | reference); |
3209 | return -1; | 3208 | return -1; |
3210 | } | 3209 | } |
3211 | memcpy(mptr, eep, mdata_size); | 3210 | memcpy(mptr, eep, mdata_size); |
3212 | } | 3211 | } |
3213 | ath_dbg(common, ATH_DBG_EEPROM, | 3212 | ath_dbg(common, EEPROM, |
3214 | "restore eeprom %d: block, reference %d, length %d\n", | 3213 | "restore eeprom %d: block, reference %d, length %d\n", |
3215 | it, reference, length); | 3214 | it, reference, length); |
3216 | ar9300_uncompress_block(ah, mptr, mdata_size, | 3215 | ar9300_uncompress_block(ah, mptr, mdata_size, |
3217 | (u8 *) (word + COMP_HDR_LEN), length); | 3216 | (u8 *) (word + COMP_HDR_LEN), length); |
3218 | break; | 3217 | break; |
3219 | default: | 3218 | default: |
3220 | ath_dbg(common, ATH_DBG_EEPROM, | 3219 | ath_dbg(common, EEPROM, "unknown compression code %d\n", code); |
3221 | "unknown compression code %d\n", code); | ||
3222 | return -1; | 3220 | return -1; |
3223 | } | 3221 | } |
3224 | return 0; | 3222 | return 0; |
@@ -3294,34 +3292,32 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, | |||
3294 | cptr = AR9300_BASE_ADDR_512; | 3292 | cptr = AR9300_BASE_ADDR_512; |
3295 | else | 3293 | else |
3296 | cptr = AR9300_BASE_ADDR; | 3294 | cptr = AR9300_BASE_ADDR; |
3297 | ath_dbg(common, ATH_DBG_EEPROM, | 3295 | ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n", |
3298 | "Trying EEPROM access at Address 0x%04x\n", cptr); | 3296 | cptr); |
3299 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3297 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3300 | goto found; | 3298 | goto found; |
3301 | 3299 | ||
3302 | cptr = AR9300_BASE_ADDR_512; | 3300 | cptr = AR9300_BASE_ADDR_512; |
3303 | ath_dbg(common, ATH_DBG_EEPROM, | 3301 | ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n", |
3304 | "Trying EEPROM access at Address 0x%04x\n", cptr); | 3302 | cptr); |
3305 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3303 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3306 | goto found; | 3304 | goto found; |
3307 | 3305 | ||
3308 | read = ar9300_read_otp; | 3306 | read = ar9300_read_otp; |
3309 | cptr = AR9300_BASE_ADDR; | 3307 | cptr = AR9300_BASE_ADDR; |
3310 | ath_dbg(common, ATH_DBG_EEPROM, | 3308 | ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr); |
3311 | "Trying OTP access at Address 0x%04x\n", cptr); | ||
3312 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3309 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3313 | goto found; | 3310 | goto found; |
3314 | 3311 | ||
3315 | cptr = AR9300_BASE_ADDR_512; | 3312 | cptr = AR9300_BASE_ADDR_512; |
3316 | ath_dbg(common, ATH_DBG_EEPROM, | 3313 | ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr); |
3317 | "Trying OTP access at Address 0x%04x\n", cptr); | ||
3318 | if (ar9300_check_eeprom_header(ah, read, cptr)) | 3314 | if (ar9300_check_eeprom_header(ah, read, cptr)) |
3319 | goto found; | 3315 | goto found; |
3320 | 3316 | ||
3321 | goto fail; | 3317 | goto fail; |
3322 | 3318 | ||
3323 | found: | 3319 | found: |
3324 | ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n"); | 3320 | ath_dbg(common, EEPROM, "Found valid EEPROM data\n"); |
3325 | 3321 | ||
3326 | for (it = 0; it < MSTATE; it++) { | 3322 | for (it = 0; it < MSTATE; it++) { |
3327 | if (!read(ah, cptr, word, COMP_HDR_LEN)) | 3323 | if (!read(ah, cptr, word, COMP_HDR_LEN)) |
@@ -3332,13 +3328,12 @@ found: | |||
3332 | 3328 | ||
3333 | ar9300_comp_hdr_unpack(word, &code, &reference, | 3329 | ar9300_comp_hdr_unpack(word, &code, &reference, |
3334 | &length, &major, &minor); | 3330 | &length, &major, &minor); |
3335 | ath_dbg(common, ATH_DBG_EEPROM, | 3331 | ath_dbg(common, EEPROM, |
3336 | "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", | 3332 | "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n", |
3337 | cptr, code, reference, length, major, minor); | 3333 | cptr, code, reference, length, major, minor); |
3338 | if ((!AR_SREV_9485(ah) && length >= 1024) || | 3334 | if ((!AR_SREV_9485(ah) && length >= 1024) || |
3339 | (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { | 3335 | (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { |
3340 | ath_dbg(common, ATH_DBG_EEPROM, | 3336 | ath_dbg(common, EEPROM, "Skipping bad header\n"); |
3341 | "Skipping bad header\n"); | ||
3342 | cptr -= COMP_HDR_LEN; | 3337 | cptr -= COMP_HDR_LEN; |
3343 | continue; | 3338 | continue; |
3344 | } | 3339 | } |
@@ -3347,13 +3342,13 @@ found: | |||
3347 | read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); | 3342 | read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
3348 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); | 3343 | checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); |
3349 | mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]); | 3344 | mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]); |
3350 | ath_dbg(common, ATH_DBG_EEPROM, | 3345 | ath_dbg(common, EEPROM, "checksum %x %x\n", |
3351 | "checksum %x %x\n", checksum, mchecksum); | 3346 | checksum, mchecksum); |
3352 | if (checksum == mchecksum) { | 3347 | if (checksum == mchecksum) { |
3353 | ar9300_compress_decision(ah, it, code, reference, mptr, | 3348 | ar9300_compress_decision(ah, it, code, reference, mptr, |
3354 | word, length, mdata_size); | 3349 | word, length, mdata_size); |
3355 | } else { | 3350 | } else { |
3356 | ath_dbg(common, ATH_DBG_EEPROM, | 3351 | ath_dbg(common, EEPROM, |
3357 | "skipping block with bad checksum\n"); | 3352 | "skipping block with bad checksum\n"); |
3358 | } | 3353 | } |
3359 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); | 3354 | cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); |
@@ -4424,8 +4419,8 @@ static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq, | |||
4424 | is2GHz) + ht40PowerIncForPdadc; | 4419 | is2GHz) + ht40PowerIncForPdadc; |
4425 | 4420 | ||
4426 | for (i = 0; i < ar9300RateSize; i++) { | 4421 | for (i = 0; i < ar9300RateSize; i++) { |
4427 | ath_dbg(common, ATH_DBG_EEPROM, | 4422 | ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n", |
4428 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); | 4423 | i, targetPowerValT2[i]); |
4429 | } | 4424 | } |
4430 | } | 4425 | } |
4431 | 4426 | ||
@@ -4444,7 +4439,7 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |||
4444 | struct ath_common *common = ath9k_hw_common(ah); | 4439 | struct ath_common *common = ath9k_hw_common(ah); |
4445 | 4440 | ||
4446 | if (ichain >= AR9300_MAX_CHAINS) { | 4441 | if (ichain >= AR9300_MAX_CHAINS) { |
4447 | ath_dbg(common, ATH_DBG_EEPROM, | 4442 | ath_dbg(common, EEPROM, |
4448 | "Invalid chain index, must be less than %d\n", | 4443 | "Invalid chain index, must be less than %d\n", |
4449 | AR9300_MAX_CHAINS); | 4444 | AR9300_MAX_CHAINS); |
4450 | return -1; | 4445 | return -1; |
@@ -4452,7 +4447,7 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |||
4452 | 4447 | ||
4453 | if (mode) { /* 5GHz */ | 4448 | if (mode) { /* 5GHz */ |
4454 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { | 4449 | if (ipier >= AR9300_NUM_5G_CAL_PIERS) { |
4455 | ath_dbg(common, ATH_DBG_EEPROM, | 4450 | ath_dbg(common, EEPROM, |
4456 | "Invalid 5GHz cal pier index, must be less than %d\n", | 4451 | "Invalid 5GHz cal pier index, must be less than %d\n", |
4457 | AR9300_NUM_5G_CAL_PIERS); | 4452 | AR9300_NUM_5G_CAL_PIERS); |
4458 | return -1; | 4453 | return -1; |
@@ -4462,7 +4457,7 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, | |||
4462 | is2GHz = 0; | 4457 | is2GHz = 0; |
4463 | } else { | 4458 | } else { |
4464 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { | 4459 | if (ipier >= AR9300_NUM_2G_CAL_PIERS) { |
4465 | ath_dbg(common, ATH_DBG_EEPROM, | 4460 | ath_dbg(common, EEPROM, |
4466 | "Invalid 2GHz cal pier index, must be less than %d\n", | 4461 | "Invalid 2GHz cal pier index, must be less than %d\n", |
4467 | AR9300_NUM_2G_CAL_PIERS); | 4462 | AR9300_NUM_2G_CAL_PIERS); |
4468 | return -1; | 4463 | return -1; |
@@ -4624,8 +4619,7 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) | |||
4624 | 4619 | ||
4625 | /* interpolate */ | 4620 | /* interpolate */ |
4626 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { | 4621 | for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) { |
4627 | ath_dbg(common, ATH_DBG_EEPROM, | 4622 | ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n", |
4628 | "ch=%d f=%d low=%d %d h=%d %d\n", | ||
4629 | ichain, frequency, lfrequency[ichain], | 4623 | ichain, frequency, lfrequency[ichain], |
4630 | lcorrection[ichain], hfrequency[ichain], | 4624 | lcorrection[ichain], hfrequency[ichain], |
4631 | hcorrection[ichain]); | 4625 | hcorrection[ichain]); |
@@ -4680,7 +4674,7 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) | |||
4680 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, | 4674 | ar9003_hw_power_control_override(ah, frequency, correction, voltage, |
4681 | temperature); | 4675 | temperature); |
4682 | 4676 | ||
4683 | ath_dbg(common, ATH_DBG_EEPROM, | 4677 | ath_dbg(common, EEPROM, |
4684 | "for frequency=%d, calibration correction = %d %d %d\n", | 4678 | "for frequency=%d, calibration correction = %d %d %d\n", |
4685 | frequency, correction[0], correction[1], correction[2]); | 4679 | frequency, correction[0], correction[1], correction[2]); |
4686 | 4680 | ||
@@ -4866,7 +4860,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4866 | else | 4860 | else |
4867 | freq = centers.ctl_center; | 4861 | freq = centers.ctl_center; |
4868 | 4862 | ||
4869 | ath_dbg(common, ATH_DBG_REGULATORY, | 4863 | ath_dbg(common, REGULATORY, |
4870 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", | 4864 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", |
4871 | ctlMode, numCtlModes, isHt40CtlMode, | 4865 | ctlMode, numCtlModes, isHt40CtlMode, |
4872 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | 4866 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); |
@@ -4882,7 +4876,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4882 | 4876 | ||
4883 | twiceMaxEdgePower = MAX_RATE_POWER; | 4877 | twiceMaxEdgePower = MAX_RATE_POWER; |
4884 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { | 4878 | for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { |
4885 | ath_dbg(common, ATH_DBG_REGULATORY, | 4879 | ath_dbg(common, REGULATORY, |
4886 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", | 4880 | "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", |
4887 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], | 4881 | i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], |
4888 | chan->channel); | 4882 | chan->channel); |
@@ -4924,7 +4918,7 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, | |||
4924 | 4918 | ||
4925 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | 4919 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); |
4926 | 4920 | ||
4927 | ath_dbg(common, ATH_DBG_REGULATORY, | 4921 | ath_dbg(common, REGULATORY, |
4928 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", | 4922 | "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", |
4929 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | 4923 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, |
4930 | scaledPower, minCtlPower); | 4924 | scaledPower, minCtlPower); |
@@ -5048,7 +5042,7 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, | |||
5048 | target_power_val_t2_eep[i]) > | 5042 | target_power_val_t2_eep[i]) > |
5049 | paprd_scale_factor)) { | 5043 | paprd_scale_factor)) { |
5050 | ah->paprd_ratemask &= ~(1 << i); | 5044 | ah->paprd_ratemask &= ~(1 << i); |
5051 | ath_dbg(common, ATH_DBG_EEPROM, | 5045 | ath_dbg(common, EEPROM, |
5052 | "paprd disabled for mcs %d\n", i); | 5046 | "paprd disabled for mcs %d\n", i); |
5053 | } | 5047 | } |
5054 | } | 5048 | } |
@@ -5066,8 +5060,8 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, | |||
5066 | return; | 5060 | return; |
5067 | 5061 | ||
5068 | for (i = 0; i < ar9300RateSize; i++) { | 5062 | for (i = 0; i < ar9300RateSize; i++) { |
5069 | ath_dbg(common, ATH_DBG_EEPROM, | 5063 | ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n", |
5070 | "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]); | 5064 | i, targetPowerValT2[i]); |
5071 | } | 5065 | } |
5072 | 5066 | ||
5073 | ah->txpower_limit = regulatory->max_power_level; | 5067 | ah->txpower_limit = regulatory->max_power_level; |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index 631fe4f2e495..4a315155d779 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c | |||
@@ -305,10 +305,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
305 | raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); | 305 | raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); |
306 | 306 | ||
307 | if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) | 307 | if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef)) |
308 | ath_dbg(common, ATH_DBG_MCI, | 308 | ath_dbg(common, MCI, |
309 | "MCI gets 0xdeadbeef during MCI int processing" | 309 | "MCI gets 0xdeadbeef during MCI int processing new raw_intr=0x%08x, new rx_msg_raw=0x%08x, raw_intr=0x%08x, rx_msg_raw=0x%08x\n", |
310 | "new raw_intr=0x%08x, new rx_msg_raw=0x%08x, " | ||
311 | "raw_intr=0x%08x, rx_msg_raw=0x%08x\n", | ||
312 | raw_intr, rx_msg_intr, mci->raw_intr, | 310 | raw_intr, rx_msg_intr, mci->raw_intr, |
313 | mci->rx_msg_intr); | 311 | mci->rx_msg_intr); |
314 | else { | 312 | else { |
@@ -322,7 +320,7 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
322 | 320 | ||
323 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); | 321 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr); |
324 | REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); | 322 | REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr); |
325 | ath_dbg(common, ATH_DBG_MCI, "AR_INTR_SYNC_MCI\n"); | 323 | ath_dbg(common, MCI, "AR_INTR_SYNC_MCI\n"); |
326 | 324 | ||
327 | } | 325 | } |
328 | } | 326 | } |
@@ -335,7 +333,7 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) | |||
335 | } | 333 | } |
336 | 334 | ||
337 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) | 335 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) |
338 | ath_dbg(common, ATH_DBG_INTERRUPT, | 336 | ath_dbg(common, INTERRUPT, |
339 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | 337 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
340 | 338 | ||
341 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | 339 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); |
@@ -366,7 +364,7 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, | |||
366 | 364 | ||
367 | if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || | 365 | if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || |
368 | (MS(ads->ds_info, AR_TxRxDesc) != 1)) { | 366 | (MS(ads->ds_info, AR_TxRxDesc) != 1)) { |
369 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, | 367 | ath_dbg(ath9k_hw_common(ah), XMIT, |
370 | "Tx Descriptor error %x\n", ads->ds_info); | 368 | "Tx Descriptor error %x\n", ads->ds_info); |
371 | memset(ads, 0, sizeof(*ads)); | 369 | memset(ads, 0, sizeof(*ads)); |
372 | return -EIO; | 370 | return -EIO; |
@@ -574,7 +572,7 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) | |||
574 | memset((void *) ah->ts_ring, 0, | 572 | memset((void *) ah->ts_ring, 0, |
575 | ah->ts_size * sizeof(struct ar9003_txs)); | 573 | ah->ts_size * sizeof(struct ar9003_txs)); |
576 | 574 | ||
577 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, | 575 | ath_dbg(ath9k_hw_common(ah), XMIT, |
578 | "TS Start 0x%x End 0x%x Virt %p, Size %d\n", | 576 | "TS Start 0x%x End 0x%x Virt %p, Size %d\n", |
579 | ah->ts_paddr_start, ah->ts_paddr_end, | 577 | ah->ts_paddr_start, ah->ts_paddr_end, |
580 | ah->ts_ring, ah->ts_size); | 578 | ah->ts_ring, ah->ts_size); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mci.c b/drivers/net/wireless/ath/ath9k/ar9003_mci.c index 8599822dc83f..fdd0f815cf83 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mci.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mci.c | |||
@@ -68,11 +68,11 @@ static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address, | |||
68 | } | 68 | } |
69 | 69 | ||
70 | if (time_out <= 0) { | 70 | if (time_out <= 0) { |
71 | ath_dbg(common, ATH_DBG_MCI, | 71 | ath_dbg(common, MCI, |
72 | "MCI Wait for Reg 0x%08x = 0x%08x timeout.\n", | 72 | "MCI Wait for Reg 0x%08x = 0x%08x timeout\n", |
73 | address, bit_position); | 73 | address, bit_position); |
74 | ath_dbg(common, ATH_DBG_MCI, | 74 | ath_dbg(common, MCI, |
75 | "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x", | 75 | "MCI INT_RAW = 0x%08x, RX_MSG_RAW = 0x%08x\n", |
76 | REG_READ(ah, AR_MCI_INTERRUPT_RAW), | 76 | REG_READ(ah, AR_MCI_INTERRUPT_RAW), |
77 | REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); | 77 | REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); |
78 | time_out = 0; | 78 | time_out = 0; |
@@ -135,7 +135,7 @@ static void ar9003_mci_send_coex_version_query(struct ath_hw *ah, | |||
135 | 135 | ||
136 | if (!mci->bt_version_known && | 136 | if (!mci->bt_version_known && |
137 | (mci->bt_state != MCI_BT_SLEEP)) { | 137 | (mci->bt_state != MCI_BT_SLEEP)) { |
138 | ath_dbg(common, ATH_DBG_MCI, "MCI Send Coex version query\n"); | 138 | ath_dbg(common, MCI, "MCI Send Coex version query\n"); |
139 | MCI_GPM_SET_TYPE_OPCODE(payload, | 139 | MCI_GPM_SET_TYPE_OPCODE(payload, |
140 | MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_QUERY); | 140 | MCI_GPM_COEX_AGENT, MCI_GPM_COEX_VERSION_QUERY); |
141 | ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, | 141 | ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, |
@@ -150,7 +150,7 @@ static void ar9003_mci_send_coex_version_response(struct ath_hw *ah, | |||
150 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; | 150 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; |
151 | u32 payload[4] = {0, 0, 0, 0}; | 151 | u32 payload[4] = {0, 0, 0, 0}; |
152 | 152 | ||
153 | ath_dbg(common, ATH_DBG_MCI, "MCI Send Coex version response\n"); | 153 | ath_dbg(common, MCI, "MCI Send Coex version response\n"); |
154 | MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT, | 154 | MCI_GPM_SET_TYPE_OPCODE(payload, MCI_GPM_COEX_AGENT, |
155 | MCI_GPM_COEX_VERSION_RESPONSE); | 155 | MCI_GPM_COEX_VERSION_RESPONSE); |
156 | *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) = | 156 | *(((u8 *)payload) + MCI_GPM_COEX_B_MAJOR_VERSION) = |
@@ -187,8 +187,8 @@ static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah, | |||
187 | 187 | ||
188 | if (mci->bt_state != MCI_BT_SLEEP) { | 188 | if (mci->bt_state != MCI_BT_SLEEP) { |
189 | 189 | ||
190 | ath_dbg(common, ATH_DBG_MCI, | 190 | ath_dbg(common, MCI, "MCI Send Coex BT Status Query 0x%02X\n", |
191 | "MCI Send Coex BT Status Query 0x%02X\n", query_type); | 191 | query_type); |
192 | 192 | ||
193 | MCI_GPM_SET_TYPE_OPCODE(payload, | 193 | MCI_GPM_SET_TYPE_OPCODE(payload, |
194 | MCI_GPM_COEX_AGENT, MCI_GPM_COEX_STATUS_QUERY); | 194 | MCI_GPM_COEX_AGENT, MCI_GPM_COEX_STATUS_QUERY); |
@@ -203,9 +203,8 @@ static void ar9003_mci_send_coex_bt_status_query(struct ath_hw *ah, | |||
203 | if (query_btinfo) { | 203 | if (query_btinfo) { |
204 | mci->need_flush_btinfo = true; | 204 | mci->need_flush_btinfo = true; |
205 | 205 | ||
206 | ath_dbg(common, ATH_DBG_MCI, | 206 | ath_dbg(common, MCI, |
207 | "MCI send bt_status_query fail, " | 207 | "MCI send bt_status_query fail, set flush flag again\n"); |
208 | "set flush flag again\n"); | ||
209 | } | 208 | } |
210 | } | 209 | } |
211 | 210 | ||
@@ -221,7 +220,7 @@ void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt, | |||
221 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; | 220 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; |
222 | u32 payload[4] = {0, 0, 0, 0}; | 221 | u32 payload[4] = {0, 0, 0, 0}; |
223 | 222 | ||
224 | ath_dbg(common, ATH_DBG_MCI, "MCI Send Coex %s BT GPM.\n", | 223 | ath_dbg(common, MCI, "MCI Send Coex %s BT GPM\n", |
225 | (halt) ? "halt" : "unhalt"); | 224 | (halt) ? "halt" : "unhalt"); |
226 | 225 | ||
227 | MCI_GPM_SET_TYPE_OPCODE(payload, | 226 | MCI_GPM_SET_TYPE_OPCODE(payload, |
@@ -259,8 +258,8 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) | |||
259 | REG_READ(ah, AR_MCI_INTERRUPT_RAW)); | 258 | REG_READ(ah, AR_MCI_INTERRUPT_RAW)); |
260 | 259 | ||
261 | /* Remote Reset */ | 260 | /* Remote Reset */ |
262 | ath_dbg(common, ATH_DBG_MCI, "MCI Reset sequence start\n"); | 261 | ath_dbg(common, MCI, "MCI Reset sequence start\n"); |
263 | ath_dbg(common, ATH_DBG_MCI, "MCI send REMOTE_RESET\n"); | 262 | ath_dbg(common, MCI, "MCI send REMOTE_RESET\n"); |
264 | ar9003_mci_remote_reset(ah, true); | 263 | ar9003_mci_remote_reset(ah, true); |
265 | 264 | ||
266 | /* | 265 | /* |
@@ -271,14 +270,13 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) | |||
271 | if (AR_SREV_9462_10(ah)) | 270 | if (AR_SREV_9462_10(ah)) |
272 | udelay(252); | 271 | udelay(252); |
273 | 272 | ||
274 | ath_dbg(common, ATH_DBG_MCI, "MCI Send REQ_WAKE to remoter(BT)\n"); | 273 | ath_dbg(common, MCI, "MCI Send REQ_WAKE to remoter(BT)\n"); |
275 | ar9003_mci_send_req_wake(ah, true); | 274 | ar9003_mci_send_req_wake(ah, true); |
276 | 275 | ||
277 | if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, | 276 | if (ar9003_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, |
278 | AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) { | 277 | AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING, 500)) { |
279 | 278 | ||
280 | ath_dbg(common, ATH_DBG_MCI, | 279 | ath_dbg(common, MCI, "MCI SYS_WAKING from remote(BT)\n"); |
281 | "MCI SYS_WAKING from remote(BT)\n"); | ||
282 | mci->bt_state = MCI_BT_AWAKE; | 280 | mci->bt_state = MCI_BT_AWAKE; |
283 | 281 | ||
284 | if (AR_SREV_9462_10(ah)) | 282 | if (AR_SREV_9462_10(ah)) |
@@ -302,8 +300,7 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) | |||
302 | 300 | ||
303 | /* Send SYS_WAKING to BT */ | 301 | /* Send SYS_WAKING to BT */ |
304 | 302 | ||
305 | ath_dbg(common, ATH_DBG_MCI, | 303 | ath_dbg(common, MCI, "MCI send SW SYS_WAKING to remote BT\n"); |
306 | "MCI send SW SYS_WAKING to remote BT\n"); | ||
307 | 304 | ||
308 | ar9003_mci_send_sys_waking(ah, true); | 305 | ar9003_mci_send_sys_waking(ah, true); |
309 | udelay(10); | 306 | udelay(10); |
@@ -332,8 +329,7 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) | |||
332 | 329 | ||
333 | if (AR_SREV_9462_10(ah) || mci->is_2g) { | 330 | if (AR_SREV_9462_10(ah) || mci->is_2g) { |
334 | /* Send LNA_TRANS */ | 331 | /* Send LNA_TRANS */ |
335 | ath_dbg(common, ATH_DBG_MCI, | 332 | ath_dbg(common, MCI, "MCI send LNA_TRANS to BT\n"); |
336 | "MCI send LNA_TRANS to BT\n"); | ||
337 | ar9003_mci_send_lna_transfer(ah, true); | 333 | ar9003_mci_send_lna_transfer(ah, true); |
338 | udelay(5); | 334 | udelay(5); |
339 | } | 335 | } |
@@ -344,20 +340,17 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah) | |||
344 | AR_MCI_INTERRUPT_RX_MSG_RAW, | 340 | AR_MCI_INTERRUPT_RX_MSG_RAW, |
345 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO, | 341 | AR_MCI_INTERRUPT_RX_MSG_LNA_INFO, |
346 | mci_timeout)) | 342 | mci_timeout)) |
347 | ath_dbg(common, ATH_DBG_MCI, | 343 | ath_dbg(common, MCI, |
348 | "MCI WLAN has control over the LNA & " | 344 | "MCI WLAN has control over the LNA & BT obeys it\n"); |
349 | "BT obeys it\n"); | ||
350 | else | 345 | else |
351 | ath_dbg(common, ATH_DBG_MCI, | 346 | ath_dbg(common, MCI, |
352 | "MCI BT didn't respond to" | 347 | "MCI BT didn't respond to LNA_TRANS\n"); |
353 | "LNA_TRANS\n"); | ||
354 | } | 348 | } |
355 | 349 | ||
356 | if (AR_SREV_9462_10(ah)) { | 350 | if (AR_SREV_9462_10(ah)) { |
357 | /* Send another remote_reset to deassert BT clk_req. */ | 351 | /* Send another remote_reset to deassert BT clk_req. */ |
358 | ath_dbg(common, ATH_DBG_MCI, | 352 | ath_dbg(common, MCI, |
359 | "MCI another remote_reset to " | 353 | "MCI another remote_reset to deassert clk_req\n"); |
360 | "deassert clk_req\n"); | ||
361 | ar9003_mci_remote_reset(ah, true); | 354 | ar9003_mci_remote_reset(ah, true); |
362 | udelay(252); | 355 | udelay(252); |
363 | } | 356 | } |
@@ -441,7 +434,7 @@ static bool ar9003_mci_is_gpm_valid(struct ath_hw *ah, u32 msg_index) | |||
441 | recv_type = MCI_GPM_TYPE(payload); | 434 | recv_type = MCI_GPM_TYPE(payload); |
442 | 435 | ||
443 | if (recv_type == MCI_GPM_RSVD_PATTERN) { | 436 | if (recv_type == MCI_GPM_RSVD_PATTERN) { |
444 | ath_dbg(common, ATH_DBG_MCI, "MCI Skip RSVD GPM\n"); | 437 | ath_dbg(common, MCI, "MCI Skip RSVD GPM\n"); |
445 | return false; | 438 | return false; |
446 | } | 439 | } |
447 | 440 | ||
@@ -514,11 +507,11 @@ static bool ar9003_mci_send_coex_bt_flags(struct ath_hw *ah, bool wait_done, | |||
514 | *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF; | 507 | *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 2) = (bt_flags >> 16) & 0xFF; |
515 | *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF; | 508 | *(((u8 *)pld) + MCI_GPM_COEX_W_BT_FLAGS + 3) = (bt_flags >> 24) & 0xFF; |
516 | 509 | ||
517 | ath_dbg(common, ATH_DBG_MCI, | 510 | ath_dbg(common, MCI, |
518 | "MCI BT_MCI_FLAGS: Send Coex BT Update Flags %s 0x%08x\n", | 511 | "MCI BT_MCI_FLAGS: Send Coex BT Update Flags %s 0x%08x\n", |
519 | (opcode == MCI_GPM_COEX_BT_FLAGS_READ) ? "READ" : | 512 | opcode == MCI_GPM_COEX_BT_FLAGS_READ ? "READ" : |
520 | ((opcode == MCI_GPM_COEX_BT_FLAGS_SET) ? "SET" : "CLEAR"), | 513 | opcode == MCI_GPM_COEX_BT_FLAGS_SET ? "SET" : "CLEAR", |
521 | bt_flags); | 514 | bt_flags); |
522 | 515 | ||
523 | return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, | 516 | return ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, |
524 | wait_done, true); | 517 | wait_done, true); |
@@ -531,7 +524,7 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, | |||
531 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; | 524 | struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci; |
532 | u32 regval, thresh; | 525 | u32 regval, thresh; |
533 | 526 | ||
534 | ath_dbg(common, ATH_DBG_MCI, "MCI full_sleep = %d, is_2g = %d\n", | 527 | ath_dbg(common, MCI, "MCI full_sleep = %d, is_2g = %d\n", |
535 | is_full_sleep, is_2g); | 528 | is_full_sleep, is_2g); |
536 | 529 | ||
537 | /* | 530 | /* |
@@ -539,14 +532,13 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, | |||
539 | */ | 532 | */ |
540 | 533 | ||
541 | if (!mci->gpm_addr && !mci->sched_addr) { | 534 | if (!mci->gpm_addr && !mci->sched_addr) { |
542 | ath_dbg(common, ATH_DBG_MCI, | 535 | ath_dbg(common, MCI, |
543 | "MCI GPM and schedule buffers are not allocated"); | 536 | "MCI GPM and schedule buffers are not allocated\n"); |
544 | return; | 537 | return; |
545 | } | 538 | } |
546 | 539 | ||
547 | if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { | 540 | if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { |
548 | ath_dbg(common, ATH_DBG_MCI, | 541 | ath_dbg(common, MCI, "MCI it's deadbeef, quit mci_reset\n"); |
549 | "MCI it's deadbeef, quit mci_reset\n"); | ||
550 | return; | 542 | return; |
551 | } | 543 | } |
552 | 544 | ||
@@ -574,8 +566,7 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, | |||
574 | !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) { | 566 | !(mci->config & ATH_MCI_CONFIG_DISABLE_OSLA)) { |
575 | 567 | ||
576 | regval |= SM(1, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); | 568 | regval |= SM(1, AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN); |
577 | ath_dbg(common, ATH_DBG_MCI, | 569 | ath_dbg(common, MCI, "MCI sched one step look ahead\n"); |
578 | "MCI sched one step look ahead\n"); | ||
579 | 570 | ||
580 | if (!(mci->config & | 571 | if (!(mci->config & |
581 | ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) { | 572 | ATH_MCI_CONFIG_DISABLE_AGGR_THRESH)) { |
@@ -593,11 +584,9 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, | |||
593 | AR_MCI_SCHD_TABLE_2_MEM_BASED, 1); | 584 | AR_MCI_SCHD_TABLE_2_MEM_BASED, 1); |
594 | 585 | ||
595 | } else | 586 | } else |
596 | ath_dbg(common, ATH_DBG_MCI, | 587 | ath_dbg(common, MCI, "MCI sched aggr thresh: off\n"); |
597 | "MCI sched aggr thresh: off\n"); | ||
598 | } else | 588 | } else |
599 | ath_dbg(common, ATH_DBG_MCI, | 589 | ath_dbg(common, MCI, "MCI SCHED one step look ahead off\n"); |
600 | "MCI SCHED one step look ahead off\n"); | ||
601 | 590 | ||
602 | if (AR_SREV_9462_10(ah)) | 591 | if (AR_SREV_9462_10(ah)) |
603 | regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10); | 592 | regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10); |
@@ -678,12 +667,12 @@ void ar9003_mci_mute_bt(struct ath_hw *ah) | |||
678 | * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment | 667 | * 2. before reset MCI RX, to quiet BT and avoid MCI RX misalignment |
679 | */ | 668 | */ |
680 | 669 | ||
681 | ath_dbg(common, ATH_DBG_MCI, "MCI Send LNA take\n"); | 670 | ath_dbg(common, MCI, "MCI Send LNA take\n"); |
682 | ar9003_mci_send_lna_take(ah, true); | 671 | ar9003_mci_send_lna_take(ah, true); |
683 | 672 | ||
684 | udelay(5); | 673 | udelay(5); |
685 | 674 | ||
686 | ath_dbg(common, ATH_DBG_MCI, "MCI Send sys sleeping\n"); | 675 | ath_dbg(common, MCI, "MCI Send sys sleeping\n"); |
687 | ar9003_mci_send_sys_sleeping(ah, true); | 676 | ar9003_mci_send_sys_sleeping(ah, true); |
688 | } | 677 | } |
689 | 678 | ||
@@ -696,7 +685,7 @@ void ar9003_mci_sync_bt_state(struct ath_hw *ah) | |||
696 | cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL); | 685 | cur_bt_state = ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL); |
697 | 686 | ||
698 | if (mci->bt_state != cur_bt_state) { | 687 | if (mci->bt_state != cur_bt_state) { |
699 | ath_dbg(common, ATH_DBG_MCI, | 688 | ath_dbg(common, MCI, |
700 | "MCI BT state mismatches. old: %d, new: %d\n", | 689 | "MCI BT state mismatches. old: %d, new: %d\n", |
701 | mci->bt_state, cur_bt_state); | 690 | mci->bt_state, cur_bt_state); |
702 | mci->bt_state = cur_bt_state; | 691 | mci->bt_state = cur_bt_state; |
@@ -708,7 +697,7 @@ void ar9003_mci_sync_bt_state(struct ath_hw *ah) | |||
708 | ar9003_mci_send_coex_wlan_channels(ah, true); | 697 | ar9003_mci_send_coex_wlan_channels(ah, true); |
709 | 698 | ||
710 | if (mci->unhalt_bt_gpm == true) { | 699 | if (mci->unhalt_bt_gpm == true) { |
711 | ath_dbg(common, ATH_DBG_MCI, "MCI unhalt BT GPM"); | 700 | ath_dbg(common, MCI, "MCI unhalt BT GPM\n"); |
712 | ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); | 701 | ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); |
713 | } | 702 | } |
714 | } | 703 | } |
@@ -734,7 +723,7 @@ static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done) | |||
734 | to_set = MCI_5G_FLAGS_SET_MASK; | 723 | to_set = MCI_5G_FLAGS_SET_MASK; |
735 | } | 724 | } |
736 | 725 | ||
737 | ath_dbg(common, ATH_DBG_MCI, | 726 | ath_dbg(common, MCI, |
738 | "MCI BT_MCI_FLAGS: %s 0x%08x clr=0x%08x, set=0x%08x\n", | 727 | "MCI BT_MCI_FLAGS: %s 0x%08x clr=0x%08x, set=0x%08x\n", |
739 | mci->is_2g ? "2G" : "5G", new_flags, to_clear, to_set); | 728 | mci->is_2g ? "2G" : "5G", new_flags, to_clear, to_set); |
740 | 729 | ||
@@ -761,15 +750,15 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, | |||
761 | if (queue) { | 750 | if (queue) { |
762 | 751 | ||
763 | if (payload) | 752 | if (payload) |
764 | ath_dbg(common, ATH_DBG_MCI, | 753 | ath_dbg(common, MCI, |
765 | "MCI ERROR: Send fail: %02x: %02x %02x %02x\n", | 754 | "MCI ERROR: Send fail: %02x: %02x %02x %02x\n", |
766 | header, | 755 | header, |
767 | *(((u8 *)payload) + 4), | 756 | *(((u8 *)payload) + 4), |
768 | *(((u8 *)payload) + 5), | 757 | *(((u8 *)payload) + 5), |
769 | *(((u8 *)payload) + 6)); | 758 | *(((u8 *)payload) + 6)); |
770 | else | 759 | else |
771 | ath_dbg(common, ATH_DBG_MCI, | 760 | ath_dbg(common, MCI, "MCI ERROR: Send fail: %02x\n", |
772 | "MCI ERROR: Send fail: %02x\n", header); | 761 | header); |
773 | } | 762 | } |
774 | 763 | ||
775 | /* check if the message is to be queued */ | 764 | /* check if the message is to be queued */ |
@@ -795,12 +784,12 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, | |||
795 | mci->update_2g5g = queue; | 784 | mci->update_2g5g = queue; |
796 | 785 | ||
797 | if (queue) | 786 | if (queue) |
798 | ath_dbg(common, ATH_DBG_MCI, | 787 | ath_dbg(common, MCI, |
799 | "MCI BT_MCI_FLAGS: 2G5G status <queued> %s.\n", | 788 | "MCI BT_MCI_FLAGS: 2G5G status <queued> %s\n", |
800 | mci->is_2g ? "2G" : "5G"); | 789 | mci->is_2g ? "2G" : "5G"); |
801 | else | 790 | else |
802 | ath_dbg(common, ATH_DBG_MCI, | 791 | ath_dbg(common, MCI, |
803 | "MCI BT_MCI_FLAGS: 2G5G status <sent> %s.\n", | 792 | "MCI BT_MCI_FLAGS: 2G5G status <sent> %s\n", |
804 | mci->is_2g ? "2G" : "5G"); | 793 | mci->is_2g ? "2G" : "5G"); |
805 | 794 | ||
806 | break; | 795 | break; |
@@ -809,11 +798,9 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, | |||
809 | 798 | ||
810 | mci->wlan_channels_update = queue; | 799 | mci->wlan_channels_update = queue; |
811 | if (queue) | 800 | if (queue) |
812 | ath_dbg(common, ATH_DBG_MCI, | 801 | ath_dbg(common, MCI, "MCI WLAN channel map <queued>\n"); |
813 | "MCI WLAN channel map <queued>\n"); | ||
814 | else | 802 | else |
815 | ath_dbg(common, ATH_DBG_MCI, | 803 | ath_dbg(common, MCI, "MCI WLAN channel map <sent>\n"); |
816 | "MCI WLAN channel map <sent>\n"); | ||
817 | break; | 804 | break; |
818 | 805 | ||
819 | case MCI_GPM_COEX_HALT_BT_GPM: | 806 | case MCI_GPM_COEX_HALT_BT_GPM: |
@@ -824,11 +811,11 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, | |||
824 | mci->unhalt_bt_gpm = queue; | 811 | mci->unhalt_bt_gpm = queue; |
825 | 812 | ||
826 | if (queue) | 813 | if (queue) |
827 | ath_dbg(common, ATH_DBG_MCI, | 814 | ath_dbg(common, MCI, |
828 | "MCI UNHALT BT GPM <queued>\n"); | 815 | "MCI UNHALT BT GPM <queued>\n"); |
829 | else { | 816 | else { |
830 | mci->halted_bt_gpm = false; | 817 | mci->halted_bt_gpm = false; |
831 | ath_dbg(common, ATH_DBG_MCI, | 818 | ath_dbg(common, MCI, |
832 | "MCI UNHALT BT GPM <sent>\n"); | 819 | "MCI UNHALT BT GPM <sent>\n"); |
833 | } | 820 | } |
834 | } | 821 | } |
@@ -839,10 +826,10 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header, | |||
839 | mci->halted_bt_gpm = !queue; | 826 | mci->halted_bt_gpm = !queue; |
840 | 827 | ||
841 | if (queue) | 828 | if (queue) |
842 | ath_dbg(common, ATH_DBG_MCI, | 829 | ath_dbg(common, MCI, |
843 | "MCI HALT BT GPM <not sent>\n"); | 830 | "MCI HALT BT GPM <not sent>\n"); |
844 | else | 831 | else |
845 | ath_dbg(common, ATH_DBG_MCI, | 832 | ath_dbg(common, MCI, |
846 | "MCI UNHALT BT GPM <sent>\n"); | 833 | "MCI UNHALT BT GPM <sent>\n"); |
847 | } | 834 | } |
848 | 835 | ||
@@ -861,7 +848,7 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) | |||
861 | if (mci->is_2g) { | 848 | if (mci->is_2g) { |
862 | 849 | ||
863 | ar9003_mci_send_2g5g_status(ah, true); | 850 | ar9003_mci_send_2g5g_status(ah, true); |
864 | ath_dbg(common, ATH_DBG_MCI, "MCI Send LNA trans\n"); | 851 | ath_dbg(common, MCI, "MCI Send LNA trans\n"); |
865 | ar9003_mci_send_lna_transfer(ah, true); | 852 | ar9003_mci_send_lna_transfer(ah, true); |
866 | udelay(5); | 853 | udelay(5); |
867 | 854 | ||
@@ -878,7 +865,7 @@ void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done) | |||
878 | } | 865 | } |
879 | } | 866 | } |
880 | } else { | 867 | } else { |
881 | ath_dbg(common, ATH_DBG_MCI, "MCI Send LNA take\n"); | 868 | ath_dbg(common, MCI, "MCI Send LNA take\n"); |
882 | ar9003_mci_send_lna_take(ah, true); | 869 | ar9003_mci_send_lna_take(ah, true); |
883 | udelay(5); | 870 | udelay(5); |
884 | 871 | ||
@@ -913,9 +900,9 @@ bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag, | |||
913 | 900 | ||
914 | if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) { | 901 | if ((regval == 0xdeadbeef) || !(regval & AR_BTCOEX_CTRL_MCI_MODE_EN)) { |
915 | 902 | ||
916 | ath_dbg(common, ATH_DBG_MCI, | 903 | ath_dbg(common, MCI, |
917 | "MCI Not sending 0x%x. MCI is not enabled. " | 904 | "MCI Not sending 0x%x. MCI is not enabled. full_sleep = %d\n", |
918 | "full_sleep = %d\n", header, | 905 | header, |
919 | (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0); | 906 | (ah->power_mode == ATH9K_PM_FULL_SLEEP) ? 1 : 0); |
920 | 907 | ||
921 | ar9003_mci_queue_unsent_gpm(ah, header, payload, true); | 908 | ar9003_mci_queue_unsent_gpm(ah, header, payload, true); |
@@ -923,8 +910,9 @@ bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag, | |||
923 | 910 | ||
924 | } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) { | 911 | } else if (check_bt && (mci->bt_state == MCI_BT_SLEEP)) { |
925 | 912 | ||
926 | ath_dbg(common, ATH_DBG_MCI, | 913 | ath_dbg(common, MCI, |
927 | "MCI Don't send message 0x%x. BT is in sleep state\n", header); | 914 | "MCI Don't send message 0x%x. BT is in sleep state\n", |
915 | header); | ||
928 | 916 | ||
929 | ar9003_mci_queue_unsent_gpm(ah, header, payload, true); | 917 | ar9003_mci_queue_unsent_gpm(ah, header, payload, true); |
930 | return false; | 918 | return false; |
@@ -989,7 +977,7 @@ void ar9003_mci_cleanup(struct ath_hw *ah) | |||
989 | 977 | ||
990 | /* Turn off MCI and Jupiter mode. */ | 978 | /* Turn off MCI and Jupiter mode. */ |
991 | REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00); | 979 | REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00); |
992 | ath_dbg(common, ATH_DBG_MCI, "MCI ar9003_mci_cleanup\n"); | 980 | ath_dbg(common, MCI, "MCI ar9003_mci_cleanup\n"); |
993 | ar9003_mci_disable_interrupt(ah); | 981 | ar9003_mci_disable_interrupt(ah); |
994 | } | 982 | } |
995 | EXPORT_SYMBOL(ar9003_mci_cleanup); | 983 | EXPORT_SYMBOL(ar9003_mci_cleanup); |
@@ -1006,40 +994,35 @@ static void ar9003_mci_process_gpm_extra(struct ath_hw *ah, u8 gpm_type, | |||
1006 | 994 | ||
1007 | switch (gpm_opcode) { | 995 | switch (gpm_opcode) { |
1008 | case MCI_GPM_COEX_VERSION_QUERY: | 996 | case MCI_GPM_COEX_VERSION_QUERY: |
1009 | ath_dbg(common, ATH_DBG_MCI, | 997 | ath_dbg(common, MCI, "MCI Recv GPM COEX Version Query\n"); |
1010 | "MCI Recv GPM COEX Version Query\n"); | ||
1011 | ar9003_mci_send_coex_version_response(ah, true); | 998 | ar9003_mci_send_coex_version_response(ah, true); |
1012 | break; | 999 | break; |
1013 | case MCI_GPM_COEX_VERSION_RESPONSE: | 1000 | case MCI_GPM_COEX_VERSION_RESPONSE: |
1014 | ath_dbg(common, ATH_DBG_MCI, | 1001 | ath_dbg(common, MCI, "MCI Recv GPM COEX Version Response\n"); |
1015 | "MCI Recv GPM COEX Version Response\n"); | ||
1016 | mci->bt_ver_major = | 1002 | mci->bt_ver_major = |
1017 | *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION); | 1003 | *(p_data + MCI_GPM_COEX_B_MAJOR_VERSION); |
1018 | mci->bt_ver_minor = | 1004 | mci->bt_ver_minor = |
1019 | *(p_data + MCI_GPM_COEX_B_MINOR_VERSION); | 1005 | *(p_data + MCI_GPM_COEX_B_MINOR_VERSION); |
1020 | mci->bt_version_known = true; | 1006 | mci->bt_version_known = true; |
1021 | ath_dbg(common, ATH_DBG_MCI, | 1007 | ath_dbg(common, MCI, "MCI BT Coex version: %d.%d\n", |
1022 | "MCI BT Coex version: %d.%d\n", | 1008 | mci->bt_ver_major, mci->bt_ver_minor); |
1023 | mci->bt_ver_major, | ||
1024 | mci->bt_ver_minor); | ||
1025 | break; | 1009 | break; |
1026 | case MCI_GPM_COEX_STATUS_QUERY: | 1010 | case MCI_GPM_COEX_STATUS_QUERY: |
1027 | ath_dbg(common, ATH_DBG_MCI, | 1011 | ath_dbg(common, MCI, |
1028 | "MCI Recv GPM COEX Status Query = 0x%02X.\n", | 1012 | "MCI Recv GPM COEX Status Query = 0x%02X\n", |
1029 | *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP)); | 1013 | *(p_data + MCI_GPM_COEX_B_WLAN_BITMAP)); |
1030 | mci->wlan_channels_update = true; | 1014 | mci->wlan_channels_update = true; |
1031 | ar9003_mci_send_coex_wlan_channels(ah, true); | 1015 | ar9003_mci_send_coex_wlan_channels(ah, true); |
1032 | break; | 1016 | break; |
1033 | case MCI_GPM_COEX_BT_PROFILE_INFO: | 1017 | case MCI_GPM_COEX_BT_PROFILE_INFO: |
1034 | mci->query_bt = true; | 1018 | mci->query_bt = true; |
1035 | ath_dbg(common, ATH_DBG_MCI, | 1019 | ath_dbg(common, MCI, "MCI Recv GPM COEX BT_Profile_Info\n"); |
1036 | "MCI Recv GPM COEX BT_Profile_Info\n"); | ||
1037 | break; | 1020 | break; |
1038 | case MCI_GPM_COEX_BT_STATUS_UPDATE: | 1021 | case MCI_GPM_COEX_BT_STATUS_UPDATE: |
1039 | mci->query_bt = true; | 1022 | mci->query_bt = true; |
1040 | ath_dbg(common, ATH_DBG_MCI, | 1023 | ath_dbg(common, MCI, |
1041 | "MCI Recv GPM COEX BT_Status_Update " | 1024 | "MCI Recv GPM COEX BT_Status_Update SEQ=%d (drop&query)\n", |
1042 | "SEQ=%d (drop&query)\n", *(p_gpm + 3)); | 1025 | *(p_gpm + 3)); |
1043 | break; | 1026 | break; |
1044 | default: | 1027 | default: |
1045 | break; | 1028 | break; |
@@ -1090,9 +1073,8 @@ u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, | |||
1090 | if ((gpm_type == MCI_GPM_BT_CAL_DONE) && | 1073 | if ((gpm_type == MCI_GPM_BT_CAL_DONE) && |
1091 | !b_is_bt_cal_done) { | 1074 | !b_is_bt_cal_done) { |
1092 | gpm_type = MCI_GPM_BT_CAL_GRANT; | 1075 | gpm_type = MCI_GPM_BT_CAL_GRANT; |
1093 | ath_dbg(common, ATH_DBG_MCI, | 1076 | ath_dbg(common, MCI, |
1094 | "MCI Recv BT_CAL_DONE" | 1077 | "MCI Recv BT_CAL_DONE wait BT_CAL_GRANT\n"); |
1095 | "wait BT_CAL_GRANT\n"); | ||
1096 | continue; | 1078 | continue; |
1097 | } | 1079 | } |
1098 | 1080 | ||
@@ -1123,7 +1105,7 @@ u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, | |||
1123 | u32 payload[4] = {0, 0, 0, 0}; | 1105 | u32 payload[4] = {0, 0, 0, 0}; |
1124 | 1106 | ||
1125 | gpm_type = MCI_GPM_BT_CAL_DONE; | 1107 | gpm_type = MCI_GPM_BT_CAL_DONE; |
1126 | ath_dbg(common, ATH_DBG_MCI, | 1108 | ath_dbg(common, MCI, |
1127 | "MCI Rcv BT_CAL_REQ, send WLAN_CAL_GRANT\n"); | 1109 | "MCI Rcv BT_CAL_REQ, send WLAN_CAL_GRANT\n"); |
1128 | 1110 | ||
1129 | MCI_GPM_SET_CAL_TYPE(payload, | 1111 | MCI_GPM_SET_CAL_TYPE(payload, |
@@ -1132,13 +1114,12 @@ u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, | |||
1132 | ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, | 1114 | ar9003_mci_send_message(ah, MCI_GPM, 0, payload, 16, |
1133 | false, false); | 1115 | false, false); |
1134 | 1116 | ||
1135 | ath_dbg(common, ATH_DBG_MCI, | 1117 | ath_dbg(common, MCI, "MCI now wait for BT_CAL_DONE\n"); |
1136 | "MCI now wait for BT_CAL_DONE\n"); | ||
1137 | 1118 | ||
1138 | continue; | 1119 | continue; |
1139 | } else { | 1120 | } else { |
1140 | ath_dbg(common, ATH_DBG_MCI, "MCI GPM subtype" | 1121 | ath_dbg(common, MCI, "MCI GPM subtype not match 0x%x\n", |
1141 | "not match 0x%x\n", *(p_gpm + 1)); | 1122 | *(p_gpm + 1)); |
1142 | mismatch++; | 1123 | mismatch++; |
1143 | ar9003_mci_process_gpm_extra(ah, recv_type, | 1124 | ar9003_mci_process_gpm_extra(ah, recv_type, |
1144 | recv_opcode, p_gpm); | 1125 | recv_opcode, p_gpm); |
@@ -1151,16 +1132,15 @@ u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, | |||
1151 | 1132 | ||
1152 | if (time_out <= 0) { | 1133 | if (time_out <= 0) { |
1153 | time_out = 0; | 1134 | time_out = 0; |
1154 | ath_dbg(common, ATH_DBG_MCI, | 1135 | ath_dbg(common, MCI, |
1155 | "MCI GPM received timeout, mismatch = %d\n", mismatch); | 1136 | "MCI GPM received timeout, mismatch = %d\n", mismatch); |
1156 | } else | 1137 | } else |
1157 | ath_dbg(common, ATH_DBG_MCI, | 1138 | ath_dbg(common, MCI, "MCI Receive GPM type=0x%x, code=0x%x\n", |
1158 | "MCI Receive GPM type=0x%x, code=0x%x\n", | ||
1159 | gpm_type, gpm_opcode); | 1139 | gpm_type, gpm_opcode); |
1160 | 1140 | ||
1161 | while (more_data == MCI_GPM_MORE) { | 1141 | while (more_data == MCI_GPM_MORE) { |
1162 | 1142 | ||
1163 | ath_dbg(common, ATH_DBG_MCI, "MCI discard remaining GPM\n"); | 1143 | ath_dbg(common, MCI, "MCI discard remaining GPM\n"); |
1164 | offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, | 1144 | offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET, |
1165 | &more_data); | 1145 | &more_data); |
1166 | 1146 | ||
@@ -1201,8 +1181,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1201 | break; | 1181 | break; |
1202 | case MCI_STATE_INIT_GPM_OFFSET: | 1182 | case MCI_STATE_INIT_GPM_OFFSET: |
1203 | value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); | 1183 | value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); |
1204 | ath_dbg(common, ATH_DBG_MCI, | 1184 | ath_dbg(common, MCI, "MCI GPM initial WRITE_PTR=%d\n", value); |
1205 | "MCI GPM initial WRITE_PTR=%d\n", value); | ||
1206 | mci->gpm_idx = value; | 1185 | mci->gpm_idx = value; |
1207 | break; | 1186 | break; |
1208 | case MCI_STATE_NEXT_GPM_OFFSET: | 1187 | case MCI_STATE_NEXT_GPM_OFFSET: |
@@ -1227,8 +1206,8 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1227 | else if (value >= mci->gpm_len) { | 1206 | else if (value >= mci->gpm_len) { |
1228 | if (value != 0xFFFF) { | 1207 | if (value != 0xFFFF) { |
1229 | value = 0; | 1208 | value = 0; |
1230 | ath_dbg(common, ATH_DBG_MCI, "MCI GPM offset" | 1209 | ath_dbg(common, MCI, |
1231 | "out of range\n"); | 1210 | "MCI GPM offset out of range\n"); |
1232 | } | 1211 | } |
1233 | } else | 1212 | } else |
1234 | value--; | 1213 | value--; |
@@ -1236,8 +1215,8 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1236 | if (value == 0xFFFF) { | 1215 | if (value == 0xFFFF) { |
1237 | value = MCI_GPM_INVALID; | 1216 | value = MCI_GPM_INVALID; |
1238 | more_gpm = MCI_GPM_NOMORE; | 1217 | more_gpm = MCI_GPM_NOMORE; |
1239 | ath_dbg(common, ATH_DBG_MCI, "MCI GPM ptr invalid" | 1218 | ath_dbg(common, MCI, |
1240 | "@ptr=%d, offset=%d, more=GPM_NOMORE\n", | 1219 | "MCI GPM ptr invalid @ptr=%d, offset=%d, more=GPM_NOMORE\n", |
1241 | gpm_ptr, value); | 1220 | gpm_ptr, value); |
1242 | } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) { | 1221 | } else if (state_type == MCI_STATE_NEXT_GPM_OFFSET) { |
1243 | 1222 | ||
@@ -1245,9 +1224,9 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1245 | value = MCI_GPM_INVALID; | 1224 | value = MCI_GPM_INVALID; |
1246 | more_gpm = MCI_GPM_NOMORE; | 1225 | more_gpm = MCI_GPM_NOMORE; |
1247 | 1226 | ||
1248 | ath_dbg(common, ATH_DBG_MCI, "MCI GPM message" | 1227 | ath_dbg(common, MCI, |
1249 | "not available @ptr=%d, @offset=%d," | 1228 | "MCI GPM message not available @ptr=%d, @offset=%d, more=GPM_NOMORE\n", |
1250 | "more=GPM_NOMORE\n", gpm_ptr, value); | 1229 | gpm_ptr, value); |
1251 | } else { | 1230 | } else { |
1252 | for (;;) { | 1231 | for (;;) { |
1253 | 1232 | ||
@@ -1267,9 +1246,8 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1267 | mci->gpm_len) | 1246 | mci->gpm_len) |
1268 | mci->gpm_idx = 0; | 1247 | mci->gpm_idx = 0; |
1269 | 1248 | ||
1270 | ath_dbg(common, ATH_DBG_MCI, | 1249 | ath_dbg(common, MCI, |
1271 | "MCI GPM message got ptr=%d," | 1250 | "MCI GPM message got ptr=%d, @offset=%d, more=%d\n", |
1272 | "@offset=%d, more=%d\n", | ||
1273 | gpm_ptr, temp_index, | 1251 | gpm_ptr, temp_index, |
1274 | (more_gpm == MCI_GPM_MORE)); | 1252 | (more_gpm == MCI_GPM_MORE)); |
1275 | 1253 | ||
@@ -1333,8 +1311,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1333 | 1311 | ||
1334 | if (mci->unhalt_bt_gpm) { | 1312 | if (mci->unhalt_bt_gpm) { |
1335 | 1313 | ||
1336 | ath_dbg(common, ATH_DBG_MCI, | 1314 | ath_dbg(common, MCI, "MCI unhalt BT GPM\n"); |
1337 | "MCI unhalt BT GPM\n"); | ||
1338 | ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); | 1315 | ar9003_mci_send_coex_halt_bt_gpm(ah, false, true); |
1339 | } | 1316 | } |
1340 | 1317 | ||
@@ -1360,8 +1337,8 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1360 | ATH_MCI_CONFIG_MCI_OBS_GPIO) != | 1337 | ATH_MCI_CONFIG_MCI_OBS_GPIO) != |
1361 | ATH_MCI_CONFIG_MCI_OBS_GPIO) { | 1338 | ATH_MCI_CONFIG_MCI_OBS_GPIO) { |
1362 | 1339 | ||
1363 | ath_dbg(common, ATH_DBG_MCI, | 1340 | ath_dbg(common, MCI, |
1364 | "MCI reconfigure observation"); | 1341 | "MCI reconfigure observation\n"); |
1365 | ar9003_mci_observation_set_up(ah); | 1342 | ar9003_mci_observation_set_up(ah); |
1366 | } | 1343 | } |
1367 | } | 1344 | } |
@@ -1374,16 +1351,14 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1374 | case MCI_STATE_SET_BT_COEX_VERSION: | 1351 | case MCI_STATE_SET_BT_COEX_VERSION: |
1375 | 1352 | ||
1376 | if (!p_data) | 1353 | if (!p_data) |
1377 | ath_dbg(common, ATH_DBG_MCI, | 1354 | ath_dbg(common, MCI, |
1378 | "MCI Set BT Coex version with NULL data!!\n"); | 1355 | "MCI Set BT Coex version with NULL data!!\n"); |
1379 | else { | 1356 | else { |
1380 | mci->bt_ver_major = (*p_data >> 8) & 0xff; | 1357 | mci->bt_ver_major = (*p_data >> 8) & 0xff; |
1381 | mci->bt_ver_minor = (*p_data) & 0xff; | 1358 | mci->bt_ver_minor = (*p_data) & 0xff; |
1382 | mci->bt_version_known = true; | 1359 | mci->bt_version_known = true; |
1383 | ath_dbg(common, ATH_DBG_MCI, | 1360 | ath_dbg(common, MCI, "MCI BT version set: %d.%d\n", |
1384 | "MCI BT version set: %d.%d\n", | 1361 | mci->bt_ver_major, mci->bt_ver_minor); |
1385 | mci->bt_ver_major, | ||
1386 | mci->bt_ver_minor); | ||
1387 | } | 1362 | } |
1388 | break; | 1363 | break; |
1389 | 1364 | ||
@@ -1438,7 +1413,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data) | |||
1438 | 1413 | ||
1439 | case MCI_STATE_RECOVER_RX: | 1414 | case MCI_STATE_RECOVER_RX: |
1440 | 1415 | ||
1441 | ath_dbg(common, ATH_DBG_MCI, "MCI hw RECOVER_RX\n"); | 1416 | ath_dbg(common, MCI, "MCI hw RECOVER_RX\n"); |
1442 | ar9003_mci_prep_interface(ah); | 1417 | ar9003_mci_prep_interface(ah); |
1443 | mci->query_bt = true; | 1418 | mci->query_bt = true; |
1444 | mci->need_flush_btinfo = true; | 1419 | mci->need_flush_btinfo = true; |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c index a4450cba0653..59647a3ceb7f 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c | |||
@@ -119,8 +119,8 @@ static int ar9003_get_training_power_5g(struct ath_hw *ah) | |||
119 | break; | 119 | break; |
120 | default: | 120 | default: |
121 | delta = 0; | 121 | delta = 0; |
122 | ath_dbg(common, ATH_DBG_CALIBRATE, | 122 | ath_dbg(common, CALIBRATE, "Invalid tx-chainmask: %u\n", |
123 | "Invalid tx-chainmask: %u\n", ah->txchainmask); | 123 | ah->txchainmask); |
124 | } | 124 | } |
125 | 125 | ||
126 | power += delta; | 126 | power += delta; |
@@ -148,13 +148,12 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah) | |||
148 | else | 148 | else |
149 | training_power = ar9003_get_training_power_5g(ah); | 149 | training_power = ar9003_get_training_power_5g(ah); |
150 | 150 | ||
151 | ath_dbg(common, ATH_DBG_CALIBRATE, | 151 | ath_dbg(common, CALIBRATE, "Training power: %d, Target power: %d\n", |
152 | "Training power: %d, Target power: %d\n", | ||
153 | training_power, ah->paprd_target_power); | 152 | training_power, ah->paprd_target_power); |
154 | 153 | ||
155 | if (training_power < 0) { | 154 | if (training_power < 0) { |
156 | ath_dbg(common, ATH_DBG_CALIBRATE, | 155 | ath_dbg(common, CALIBRATE, |
157 | "PAPRD target power delta out of range"); | 156 | "PAPRD target power delta out of range\n"); |
158 | return -ERANGE; | 157 | return -ERANGE; |
159 | } | 158 | } |
160 | ah->paprd_training_power = training_power; | 159 | ah->paprd_training_power = training_power; |
@@ -311,8 +310,8 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain, | |||
311 | reg_cl_gain = AR_PHY_CL_TAB_2; | 310 | reg_cl_gain = AR_PHY_CL_TAB_2; |
312 | break; | 311 | break; |
313 | default: | 312 | default: |
314 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 313 | ath_dbg(ath9k_hw_common(ah), CALIBRATE, |
315 | "Invalid chainmask: %d\n", chain); | 314 | "Invalid chainmask: %d\n", chain); |
316 | break; | 315 | break; |
317 | } | 316 | } |
318 | 317 | ||
@@ -850,7 +849,7 @@ bool ar9003_paprd_is_done(struct ath_hw *ah) | |||
850 | agc2_pwr = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1, | 849 | agc2_pwr = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1, |
851 | AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR); | 850 | AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR); |
852 | 851 | ||
853 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | 852 | ath_dbg(ath9k_hw_common(ah), CALIBRATE, |
854 | "AGC2_PWR = 0x%x training done = 0x%x\n", | 853 | "AGC2_PWR = 0x%x training done = 0x%x\n", |
855 | agc2_pwr, paprd_done); | 854 | agc2_pwr, paprd_done); |
856 | /* | 855 | /* |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index e41d26939ab8..2589b38b689a 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -882,7 +882,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
882 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | 882 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
883 | 883 | ||
884 | if (!on != aniState->ofdmWeakSigDetectOff) { | 884 | if (!on != aniState->ofdmWeakSigDetectOff) { |
885 | ath_dbg(common, ATH_DBG_ANI, | 885 | ath_dbg(common, ANI, |
886 | "** ch %d: ofdm weak signal: %s=>%s\n", | 886 | "** ch %d: ofdm weak signal: %s=>%s\n", |
887 | chan->channel, | 887 | chan->channel, |
888 | !aniState->ofdmWeakSigDetectOff ? | 888 | !aniState->ofdmWeakSigDetectOff ? |
@@ -900,7 +900,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
900 | u32 level = param; | 900 | u32 level = param; |
901 | 901 | ||
902 | if (level >= ARRAY_SIZE(firstep_table)) { | 902 | if (level >= ARRAY_SIZE(firstep_table)) { |
903 | ath_dbg(common, ATH_DBG_ANI, | 903 | ath_dbg(common, ANI, |
904 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", | 904 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
905 | level, ARRAY_SIZE(firstep_table)); | 905 | level, ARRAY_SIZE(firstep_table)); |
906 | return false; | 906 | return false; |
@@ -937,7 +937,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
937 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); | 937 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); |
938 | 938 | ||
939 | if (level != aniState->firstepLevel) { | 939 | if (level != aniState->firstepLevel) { |
940 | ath_dbg(common, ATH_DBG_ANI, | 940 | ath_dbg(common, ANI, |
941 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", | 941 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
942 | chan->channel, | 942 | chan->channel, |
943 | aniState->firstepLevel, | 943 | aniState->firstepLevel, |
@@ -945,7 +945,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
945 | ATH9K_ANI_FIRSTEP_LVL_NEW, | 945 | ATH9K_ANI_FIRSTEP_LVL_NEW, |
946 | value, | 946 | value, |
947 | aniState->iniDef.firstep); | 947 | aniState->iniDef.firstep); |
948 | ath_dbg(common, ATH_DBG_ANI, | 948 | ath_dbg(common, ANI, |
949 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", | 949 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
950 | chan->channel, | 950 | chan->channel, |
951 | aniState->firstepLevel, | 951 | aniState->firstepLevel, |
@@ -965,7 +965,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
965 | u32 level = param; | 965 | u32 level = param; |
966 | 966 | ||
967 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { | 967 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { |
968 | ath_dbg(common, ATH_DBG_ANI, | 968 | ath_dbg(common, ANI, |
969 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", | 969 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
970 | level, ARRAY_SIZE(cycpwrThr1_table)); | 970 | level, ARRAY_SIZE(cycpwrThr1_table)); |
971 | return false; | 971 | return false; |
@@ -1001,7 +1001,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
1001 | AR_PHY_EXT_CYCPWR_THR1, value2); | 1001 | AR_PHY_EXT_CYCPWR_THR1, value2); |
1002 | 1002 | ||
1003 | if (level != aniState->spurImmunityLevel) { | 1003 | if (level != aniState->spurImmunityLevel) { |
1004 | ath_dbg(common, ATH_DBG_ANI, | 1004 | ath_dbg(common, ANI, |
1005 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", | 1005 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
1006 | chan->channel, | 1006 | chan->channel, |
1007 | aniState->spurImmunityLevel, | 1007 | aniState->spurImmunityLevel, |
@@ -1009,7 +1009,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
1009 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | 1009 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, |
1010 | value, | 1010 | value, |
1011 | aniState->iniDef.cycpwrThr1); | 1011 | aniState->iniDef.cycpwrThr1); |
1012 | ath_dbg(common, ATH_DBG_ANI, | 1012 | ath_dbg(common, ANI, |
1013 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", | 1013 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
1014 | chan->channel, | 1014 | chan->channel, |
1015 | aniState->spurImmunityLevel, | 1015 | aniState->spurImmunityLevel, |
@@ -1036,8 +1036,7 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
1036 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, | 1036 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, |
1037 | AR_PHY_MRC_CCK_MUX_REG, is_on); | 1037 | AR_PHY_MRC_CCK_MUX_REG, is_on); |
1038 | if (!is_on != aniState->mrcCCKOff) { | 1038 | if (!is_on != aniState->mrcCCKOff) { |
1039 | ath_dbg(common, ATH_DBG_ANI, | 1039 | ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", |
1040 | "** ch %d: MRC CCK: %s=>%s\n", | ||
1041 | chan->channel, | 1040 | chan->channel, |
1042 | !aniState->mrcCCKOff ? "on" : "off", | 1041 | !aniState->mrcCCKOff ? "on" : "off", |
1043 | is_on ? "on" : "off"); | 1042 | is_on ? "on" : "off"); |
@@ -1052,11 +1051,11 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah, | |||
1052 | case ATH9K_ANI_PRESENT: | 1051 | case ATH9K_ANI_PRESENT: |
1053 | break; | 1052 | break; |
1054 | default: | 1053 | default: |
1055 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); | 1054 | ath_dbg(common, ANI, "invalid cmd %u\n", cmd); |
1056 | return false; | 1055 | return false; |
1057 | } | 1056 | } |
1058 | 1057 | ||
1059 | ath_dbg(common, ATH_DBG_ANI, | 1058 | ath_dbg(common, ANI, |
1060 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", | 1059 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
1061 | aniState->spurImmunityLevel, | 1060 | aniState->spurImmunityLevel, |
1062 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", | 1061 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", |
@@ -1125,8 +1124,7 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) | |||
1125 | aniState = &ah->curchan->ani; | 1124 | aniState = &ah->curchan->ani; |
1126 | iniDef = &aniState->iniDef; | 1125 | iniDef = &aniState->iniDef; |
1127 | 1126 | ||
1128 | ath_dbg(common, ATH_DBG_ANI, | 1127 | ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n", |
1129 | "ver %d.%d opmode %u chan %d Mhz/0x%x\n", | ||
1130 | ah->hw_version.macVersion, | 1128 | ah->hw_version.macVersion, |
1131 | ah->hw_version.macRev, | 1129 | ah->hw_version.macRev, |
1132 | ah->opmode, | 1130 | ah->opmode, |
@@ -1388,7 +1386,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) | |||
1388 | ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | | 1386 | ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | |
1389 | AR_PHY_WATCHDOG_IDLE_ENABLE)); | 1387 | AR_PHY_WATCHDOG_IDLE_ENABLE)); |
1390 | 1388 | ||
1391 | ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); | 1389 | ath_dbg(common, RESET, "Disabled BB Watchdog\n"); |
1392 | return; | 1390 | return; |
1393 | } | 1391 | } |
1394 | 1392 | ||
@@ -1424,8 +1422,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) | |||
1424 | AR_PHY_WATCHDOG_IDLE_MASK | | 1422 | AR_PHY_WATCHDOG_IDLE_MASK | |
1425 | (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); | 1423 | (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); |
1426 | 1424 | ||
1427 | ath_dbg(common, ATH_DBG_RESET, | 1425 | ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", |
1428 | "Enabled BB Watchdog timeout (%u ms)\n", | ||
1429 | idle_tmo_ms); | 1426 | idle_tmo_ms); |
1430 | } | 1427 | } |
1431 | 1428 | ||
@@ -1454,9 +1451,9 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) | |||
1454 | return; | 1451 | return; |
1455 | 1452 | ||
1456 | status = ah->bb_watchdog_last_status; | 1453 | status = ah->bb_watchdog_last_status; |
1457 | ath_dbg(common, ATH_DBG_RESET, | 1454 | ath_dbg(common, RESET, |
1458 | "\n==== BB update: BB status=0x%08x ====\n", status); | 1455 | "\n==== BB update: BB status=0x%08x ====\n", status); |
1459 | ath_dbg(common, ATH_DBG_RESET, | 1456 | ath_dbg(common, RESET, |
1460 | "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", | 1457 | "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", |
1461 | MS(status, AR_PHY_WATCHDOG_INFO), | 1458 | MS(status, AR_PHY_WATCHDOG_INFO), |
1462 | MS(status, AR_PHY_WATCHDOG_DET_HANG), | 1459 | MS(status, AR_PHY_WATCHDOG_DET_HANG), |
@@ -1468,22 +1465,19 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) | |||
1468 | MS(status, AR_PHY_WATCHDOG_AGC_SM), | 1465 | MS(status, AR_PHY_WATCHDOG_AGC_SM), |
1469 | MS(status, AR_PHY_WATCHDOG_SRCH_SM)); | 1466 | MS(status, AR_PHY_WATCHDOG_SRCH_SM)); |
1470 | 1467 | ||
1471 | ath_dbg(common, ATH_DBG_RESET, | 1468 | ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", |
1472 | "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", | ||
1473 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), | 1469 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), |
1474 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); | 1470 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); |
1475 | ath_dbg(common, ATH_DBG_RESET, | 1471 | ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", |
1476 | "** BB mode: BB_gen_controls=0x%08x **\n", | ||
1477 | REG_READ(ah, AR_PHY_GEN_CTRL)); | 1472 | REG_READ(ah, AR_PHY_GEN_CTRL)); |
1478 | 1473 | ||
1479 | #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) | 1474 | #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) |
1480 | if (common->cc_survey.cycles) | 1475 | if (common->cc_survey.cycles) |
1481 | ath_dbg(common, ATH_DBG_RESET, | 1476 | ath_dbg(common, RESET, |
1482 | "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", | 1477 | "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", |
1483 | PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); | 1478 | PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); |
1484 | 1479 | ||
1485 | ath_dbg(common, ATH_DBG_RESET, | 1480 | ath_dbg(common, RESET, "==== BB update: done ====\n\n"); |
1486 | "==== BB update: done ====\n\n"); | ||
1487 | } | 1481 | } |
1488 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); | 1482 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); |
1489 | 1483 | ||
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c index a13cabb95435..dc5fd569690f 100644 --- a/drivers/net/wireless/ath/ath9k/beacon.c +++ b/drivers/net/wireless/ath/ath9k/beacon.c | |||
@@ -117,11 +117,10 @@ static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
117 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | 117 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
118 | txctl.txq = sc->beacon.cabq; | 118 | txctl.txq = sc->beacon.cabq; |
119 | 119 | ||
120 | ath_dbg(common, ATH_DBG_XMIT, | 120 | ath_dbg(common, XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
121 | "transmitting CABQ packet, skb: %p\n", skb); | ||
122 | 121 | ||
123 | if (ath_tx_start(hw, skb, &txctl) != 0) { | 122 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
124 | ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n"); | 123 | ath_dbg(common, XMIT, "CABQ TX failed\n"); |
125 | dev_kfree_skb_any(skb); | 124 | dev_kfree_skb_any(skb); |
126 | } | 125 | } |
127 | } | 126 | } |
@@ -204,7 +203,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw, | |||
204 | 203 | ||
205 | if (skb && cabq_depth) { | 204 | if (skb && cabq_depth) { |
206 | if (sc->nvifs > 1) { | 205 | if (sc->nvifs > 1) { |
207 | ath_dbg(common, ATH_DBG_BEACON, | 206 | ath_dbg(common, BEACON, |
208 | "Flushing previous cabq traffic\n"); | 207 | "Flushing previous cabq traffic\n"); |
209 | ath_draintxq(sc, cabq, false); | 208 | ath_draintxq(sc, cabq, false); |
210 | } | 209 | } |
@@ -297,7 +296,7 @@ int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif) | |||
297 | tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF; | 296 | tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF; |
298 | avp->tsf_adjust = cpu_to_le64(tsfadjust); | 297 | avp->tsf_adjust = cpu_to_le64(tsfadjust); |
299 | 298 | ||
300 | ath_dbg(common, ATH_DBG_BEACON, | 299 | ath_dbg(common, BEACON, |
301 | "stagger beacons, bslot %d intval %u tsfadjust %llu\n", | 300 | "stagger beacons, bslot %d intval %u tsfadjust %llu\n", |
302 | avp->av_bslot, intval, (unsigned long long)tsfadjust); | 301 | avp->av_bslot, intval, (unsigned long long)tsfadjust); |
303 | 302 | ||
@@ -371,15 +370,14 @@ void ath_beacon_tasklet(unsigned long data) | |||
371 | sc->beacon.bmisscnt++; | 370 | sc->beacon.bmisscnt++; |
372 | 371 | ||
373 | if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) { | 372 | if (sc->beacon.bmisscnt < BSTUCK_THRESH * sc->nbcnvifs) { |
374 | ath_dbg(common, ATH_DBG_BSTUCK, | 373 | ath_dbg(common, BSTUCK, |
375 | "missed %u consecutive beacons\n", | 374 | "missed %u consecutive beacons\n", |
376 | sc->beacon.bmisscnt); | 375 | sc->beacon.bmisscnt); |
377 | ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq); | 376 | ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq); |
378 | if (sc->beacon.bmisscnt > 3) | 377 | if (sc->beacon.bmisscnt > 3) |
379 | ath9k_hw_bstuck_nfcal(ah); | 378 | ath9k_hw_bstuck_nfcal(ah); |
380 | } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { | 379 | } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { |
381 | ath_dbg(common, ATH_DBG_BSTUCK, | 380 | ath_dbg(common, BSTUCK, "beacon is officially stuck\n"); |
382 | "beacon is officially stuck\n"); | ||
383 | sc->sc_flags |= SC_OP_TSF_RESET; | 381 | sc->sc_flags |= SC_OP_TSF_RESET; |
384 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | 382 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
385 | } | 383 | } |
@@ -406,7 +404,7 @@ void ath_beacon_tasklet(unsigned long data) | |||
406 | slot = (tsftu % (intval * ATH_BCBUF)) / intval; | 404 | slot = (tsftu % (intval * ATH_BCBUF)) / intval; |
407 | vif = sc->beacon.bslot[slot]; | 405 | vif = sc->beacon.bslot[slot]; |
408 | 406 | ||
409 | ath_dbg(common, ATH_DBG_BEACON, | 407 | ath_dbg(common, BEACON, |
410 | "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", | 408 | "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", |
411 | slot, tsf, tsftu / ATH_BCBUF, intval, vif); | 409 | slot, tsf, tsftu / ATH_BCBUF, intval, vif); |
412 | } else { | 410 | } else { |
@@ -424,7 +422,7 @@ void ath_beacon_tasklet(unsigned long data) | |||
424 | } | 422 | } |
425 | 423 | ||
426 | if (sc->beacon.bmisscnt != 0) { | 424 | if (sc->beacon.bmisscnt != 0) { |
427 | ath_dbg(common, ATH_DBG_BSTUCK, | 425 | ath_dbg(common, BSTUCK, |
428 | "resume beacon xmit after %u misses\n", | 426 | "resume beacon xmit after %u misses\n", |
429 | sc->beacon.bmisscnt); | 427 | sc->beacon.bmisscnt); |
430 | sc->beacon.bmisscnt = 0; | 428 | sc->beacon.bmisscnt = 0; |
@@ -541,7 +539,7 @@ static void ath_beacon_config_sta(struct ath_softc *sc, | |||
541 | 539 | ||
542 | /* No need to configure beacon if we are not associated */ | 540 | /* No need to configure beacon if we are not associated */ |
543 | if (!common->curaid) { | 541 | if (!common->curaid) { |
544 | ath_dbg(common, ATH_DBG_BEACON, | 542 | ath_dbg(common, BEACON, |
545 | "STA is not yet associated..skipping beacon config\n"); | 543 | "STA is not yet associated..skipping beacon config\n"); |
546 | return; | 544 | return; |
547 | } | 545 | } |
@@ -631,8 +629,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc, | |||
631 | /* TSF out of range threshold fixed at 1 second */ | 629 | /* TSF out of range threshold fixed at 1 second */ |
632 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; | 630 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; |
633 | 631 | ||
634 | ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); | 632 | ath_dbg(common, BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); |
635 | ath_dbg(common, ATH_DBG_BEACON, | 633 | ath_dbg(common, BEACON, |
636 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", | 634 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", |
637 | bs.bs_bmissthreshold, bs.bs_sleepduration, | 635 | bs.bs_bmissthreshold, bs.bs_sleepduration, |
638 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); | 636 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); |
@@ -660,8 +658,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc, | |||
660 | tsf = roundup(ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE), intval); | 658 | tsf = roundup(ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE), intval); |
661 | nexttbtt = tsf + intval; | 659 | nexttbtt = tsf + intval; |
662 | 660 | ||
663 | ath_dbg(common, ATH_DBG_BEACON, | 661 | ath_dbg(common, BEACON, "IBSS nexttbtt %u intval %u (%u)\n", |
664 | "IBSS nexttbtt %u intval %u (%u)\n", | ||
665 | nexttbtt, intval, conf->beacon_interval); | 662 | nexttbtt, intval, conf->beacon_interval); |
666 | 663 | ||
667 | /* | 664 | /* |
@@ -699,9 +696,8 @@ static bool ath9k_allow_beacon_config(struct ath_softc *sc, | |||
699 | (sc->nbcnvifs > 1) && | 696 | (sc->nbcnvifs > 1) && |
700 | (vif->type == NL80211_IFTYPE_AP) && | 697 | (vif->type == NL80211_IFTYPE_AP) && |
701 | (cur_conf->beacon_interval != bss_conf->beacon_int)) { | 698 | (cur_conf->beacon_interval != bss_conf->beacon_int)) { |
702 | ath_dbg(common, ATH_DBG_CONFIG, | 699 | ath_dbg(common, CONFIG, |
703 | "Changing beacon interval of multiple \ | 700 | "Changing beacon interval of multiple AP interfaces !\n"); |
704 | AP interfaces !\n"); | ||
705 | return false; | 701 | return false; |
706 | } | 702 | } |
707 | /* | 703 | /* |
@@ -710,7 +706,7 @@ static bool ath9k_allow_beacon_config(struct ath_softc *sc, | |||
710 | */ | 706 | */ |
711 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) && | 707 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) && |
712 | (vif->type != NL80211_IFTYPE_AP)) { | 708 | (vif->type != NL80211_IFTYPE_AP)) { |
713 | ath_dbg(common, ATH_DBG_CONFIG, | 709 | ath_dbg(common, CONFIG, |
714 | "STA vif's beacon not allowed on AP mode\n"); | 710 | "STA vif's beacon not allowed on AP mode\n"); |
715 | return false; | 711 | return false; |
716 | } | 712 | } |
@@ -722,7 +718,7 @@ static bool ath9k_allow_beacon_config(struct ath_softc *sc, | |||
722 | (vif->type == NL80211_IFTYPE_STATION) && | 718 | (vif->type == NL80211_IFTYPE_STATION) && |
723 | (sc->sc_flags & SC_OP_BEACONS) && | 719 | (sc->sc_flags & SC_OP_BEACONS) && |
724 | !avp->primary_sta_vif) { | 720 | !avp->primary_sta_vif) { |
725 | ath_dbg(common, ATH_DBG_CONFIG, | 721 | ath_dbg(common, CONFIG, |
726 | "Beacon already configured for a station interface\n"); | 722 | "Beacon already configured for a station interface\n"); |
727 | return false; | 723 | return false; |
728 | } | 724 | } |
@@ -802,8 +798,7 @@ void ath_set_beacon(struct ath_softc *sc) | |||
802 | ath_beacon_config_sta(sc, cur_conf); | 798 | ath_beacon_config_sta(sc, cur_conf); |
803 | break; | 799 | break; |
804 | default: | 800 | default: |
805 | ath_dbg(common, ATH_DBG_CONFIG, | 801 | ath_dbg(common, CONFIG, "Unsupported beaconing mode\n"); |
806 | "Unsupported beaconing mode\n"); | ||
807 | return; | 802 | return; |
808 | } | 803 | } |
809 | 804 | ||
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c index bbb20810ec10..553d279cc5ee 100644 --- a/drivers/net/wireless/ath/ath9k/btcoex.c +++ b/drivers/net/wireless/ath/ath9k/btcoex.c | |||
@@ -313,8 +313,7 @@ void ath9k_hw_btcoex_bt_stomp(struct ath_hw *ah, | |||
313 | AR_STOMP_NONE_WLAN_WGHT); | 313 | AR_STOMP_NONE_WLAN_WGHT); |
314 | break; | 314 | break; |
315 | default: | 315 | default: |
316 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 316 | ath_dbg(ath9k_hw_common(ah), BTCOEX, "Invalid Stomptype\n"); |
317 | "Invalid Stomptype\n"); | ||
318 | break; | 317 | break; |
319 | } | 318 | } |
320 | } | 319 | } |
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c index 99538810a312..172e33db7f4c 100644 --- a/drivers/net/wireless/ath/ath9k/calib.c +++ b/drivers/net/wireless/ath/ath9k/calib.c | |||
@@ -116,7 +116,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah, | |||
116 | if (h[i].privNF > limit->max) { | 116 | if (h[i].privNF > limit->max) { |
117 | high_nf_mid = true; | 117 | high_nf_mid = true; |
118 | 118 | ||
119 | ath_dbg(common, ATH_DBG_CALIBRATE, | 119 | ath_dbg(common, CALIBRATE, |
120 | "NFmid[%d] (%d) > MAX (%d), %s\n", | 120 | "NFmid[%d] (%d) > MAX (%d), %s\n", |
121 | i, h[i].privNF, limit->max, | 121 | i, h[i].privNF, limit->max, |
122 | (cal->nfcal_interference ? | 122 | (cal->nfcal_interference ? |
@@ -199,8 +199,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) | |||
199 | return true; | 199 | return true; |
200 | 200 | ||
201 | if (currCal->calState != CAL_DONE) { | 201 | if (currCal->calState != CAL_DONE) { |
202 | ath_dbg(common, ATH_DBG_CALIBRATE, | 202 | ath_dbg(common, CALIBRATE, "Calibration state incorrect, %d\n", |
203 | "Calibration state incorrect, %d\n", | ||
204 | currCal->calState); | 203 | currCal->calState); |
205 | return true; | 204 | return true; |
206 | } | 205 | } |
@@ -208,8 +207,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) | |||
208 | if (!(ah->supp_cals & currCal->calData->calType)) | 207 | if (!(ah->supp_cals & currCal->calData->calType)) |
209 | return true; | 208 | return true; |
210 | 209 | ||
211 | ath_dbg(common, ATH_DBG_CALIBRATE, | 210 | ath_dbg(common, CALIBRATE, "Resetting Cal %d state for channel %u\n", |
212 | "Resetting Cal %d state for channel %u\n", | ||
213 | currCal->calData->calType, conf->channel->center_freq); | 211 | currCal->calData->calType, conf->channel->center_freq); |
214 | 212 | ||
215 | ah->caldata->CalValid &= ~currCal->calData->calType; | 213 | ah->caldata->CalValid &= ~currCal->calData->calType; |
@@ -302,7 +300,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) | |||
302 | * noisefloor until the next calibration timer. | 300 | * noisefloor until the next calibration timer. |
303 | */ | 301 | */ |
304 | if (j == 10000) { | 302 | if (j == 10000) { |
305 | ath_dbg(common, ATH_DBG_ANY, | 303 | ath_dbg(common, ANY, |
306 | "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n", | 304 | "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n", |
307 | REG_READ(ah, AR_PHY_AGC_CONTROL)); | 305 | REG_READ(ah, AR_PHY_AGC_CONTROL)); |
308 | return; | 306 | return; |
@@ -344,17 +342,17 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf) | |||
344 | if (!nf[i]) | 342 | if (!nf[i]) |
345 | continue; | 343 | continue; |
346 | 344 | ||
347 | ath_dbg(common, ATH_DBG_CALIBRATE, | 345 | ath_dbg(common, CALIBRATE, |
348 | "NF calibrated [%s] [chain %d] is %d\n", | 346 | "NF calibrated [%s] [chain %d] is %d\n", |
349 | (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]); | 347 | (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]); |
350 | 348 | ||
351 | if (nf[i] > ATH9K_NF_TOO_HIGH) { | 349 | if (nf[i] > ATH9K_NF_TOO_HIGH) { |
352 | ath_dbg(common, ATH_DBG_CALIBRATE, | 350 | ath_dbg(common, CALIBRATE, |
353 | "NF[%d] (%d) > MAX (%d), correcting to MAX\n", | 351 | "NF[%d] (%d) > MAX (%d), correcting to MAX\n", |
354 | i, nf[i], ATH9K_NF_TOO_HIGH); | 352 | i, nf[i], ATH9K_NF_TOO_HIGH); |
355 | nf[i] = limit->max; | 353 | nf[i] = limit->max; |
356 | } else if (nf[i] < limit->min) { | 354 | } else if (nf[i] < limit->min) { |
357 | ath_dbg(common, ATH_DBG_CALIBRATE, | 355 | ath_dbg(common, CALIBRATE, |
358 | "NF[%d] (%d) < MIN (%d), correcting to NOM\n", | 356 | "NF[%d] (%d) < MIN (%d), correcting to NOM\n", |
359 | i, nf[i], limit->min); | 357 | i, nf[i], limit->min); |
360 | nf[i] = limit->nominal; | 358 | nf[i] = limit->nominal; |
@@ -373,7 +371,7 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) | |||
373 | 371 | ||
374 | chan->channelFlags &= (~CHANNEL_CW_INT); | 372 | chan->channelFlags &= (~CHANNEL_CW_INT); |
375 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { | 373 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { |
376 | ath_dbg(common, ATH_DBG_CALIBRATE, | 374 | ath_dbg(common, CALIBRATE, |
377 | "NF did not complete in calibration window\n"); | 375 | "NF did not complete in calibration window\n"); |
378 | return false; | 376 | return false; |
379 | } | 377 | } |
@@ -383,7 +381,7 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) | |||
383 | nf = nfarray[0]; | 381 | nf = nfarray[0]; |
384 | if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) | 382 | if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh) |
385 | && nf > nfThresh) { | 383 | && nf > nfThresh) { |
386 | ath_dbg(common, ATH_DBG_CALIBRATE, | 384 | ath_dbg(common, CALIBRATE, |
387 | "noise floor failed detected; detected %d, threshold %d\n", | 385 | "noise floor failed detected; detected %d, threshold %d\n", |
388 | nf, nfThresh); | 386 | nf, nfThresh); |
389 | chan->channelFlags |= CHANNEL_CW_INT; | 387 | chan->channelFlags |= CHANNEL_CW_INT; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c index e46f751ab508..c43523233319 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.c +++ b/drivers/net/wireless/ath/ath9k/eeprom.c | |||
@@ -305,8 +305,7 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah) | |||
305 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | 305 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; |
306 | break; | 306 | break; |
307 | default: | 307 | default: |
308 | ath_dbg(common, ATH_DBG_EEPROM, | 308 | ath_dbg(common, EEPROM, "Invalid chainmask configuration\n"); |
309 | "Invalid chainmask configuration\n"); | ||
310 | break; | 309 | break; |
311 | } | 310 | } |
312 | } | 311 | } |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c index 61fcab0e2d76..4322ac80c203 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c | |||
@@ -38,7 +38,7 @@ static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |||
38 | 38 | ||
39 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { | 39 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { |
40 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { | 40 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) { |
41 | ath_dbg(common, ATH_DBG_EEPROM, | 41 | ath_dbg(common, EEPROM, |
42 | "Unable to read eeprom region\n"); | 42 | "Unable to read eeprom region\n"); |
43 | return false; | 43 | return false; |
44 | } | 44 | } |
@@ -62,8 +62,7 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |||
62 | struct ath_common *common = ath9k_hw_common(ah); | 62 | struct ath_common *common = ath9k_hw_common(ah); |
63 | 63 | ||
64 | if (!ath9k_hw_use_flash(ah)) { | 64 | if (!ath9k_hw_use_flash(ah)) { |
65 | ath_dbg(common, ATH_DBG_EEPROM, | 65 | ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n"); |
66 | "Reading from EEPROM, not flash\n"); | ||
67 | } | 66 | } |
68 | 67 | ||
69 | if (common->bus_ops->ath_bus_type == ATH_USB) | 68 | if (common->bus_ops->ath_bus_type == ATH_USB) |
@@ -204,8 +203,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
204 | return false; | 203 | return false; |
205 | } | 204 | } |
206 | 205 | ||
207 | ath_dbg(common, ATH_DBG_EEPROM, | 206 | ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic); |
208 | "Read Magic = 0x%04X\n", magic); | ||
209 | 207 | ||
210 | if (magic != AR5416_EEPROM_MAGIC) { | 208 | if (magic != AR5416_EEPROM_MAGIC) { |
211 | magic2 = swab16(magic); | 209 | magic2 = swab16(magic); |
@@ -227,7 +225,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
227 | } | 225 | } |
228 | } | 226 | } |
229 | 227 | ||
230 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", | 228 | ath_dbg(common, EEPROM, "need_swap = %s\n", |
231 | need_swap ? "True" : "False"); | 229 | need_swap ? "True" : "False"); |
232 | 230 | ||
233 | if (need_swap) | 231 | if (need_swap) |
@@ -249,7 +247,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) | |||
249 | u32 integer; | 247 | u32 integer; |
250 | u16 word; | 248 | u16 word; |
251 | 249 | ||
252 | ath_dbg(common, ATH_DBG_EEPROM, | 250 | ath_dbg(common, EEPROM, |
253 | "EEPROM Endianness is not native.. Changing\n"); | 251 | "EEPROM Endianness is not native.. Changing\n"); |
254 | 252 | ||
255 | word = swab16(eep->baseEepHeader.length); | 253 | word = swab16(eep->baseEepHeader.length); |
@@ -435,11 +433,11 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, | |||
435 | reg32 = get_unaligned_le32(&pdadcValues[4 * j]); | 433 | reg32 = get_unaligned_le32(&pdadcValues[4 * j]); |
436 | REG_WRITE(ah, regOffset, reg32); | 434 | REG_WRITE(ah, regOffset, reg32); |
437 | 435 | ||
438 | ath_dbg(common, ATH_DBG_EEPROM, | 436 | ath_dbg(common, EEPROM, |
439 | "PDADC (%d,%4x): %4.4x %8.8x\n", | 437 | "PDADC (%d,%4x): %4.4x %8.8x\n", |
440 | i, regChainOffset, regOffset, | 438 | i, regChainOffset, regOffset, |
441 | reg32); | 439 | reg32); |
442 | ath_dbg(common, ATH_DBG_EEPROM, | 440 | ath_dbg(common, EEPROM, |
443 | "PDADC: Chain %d | " | 441 | "PDADC: Chain %d | " |
444 | "PDADC %3d Value %3d | " | 442 | "PDADC %3d Value %3d | " |
445 | "PDADC %3d Value %3d | " | 443 | "PDADC %3d Value %3d | " |
@@ -1079,8 +1077,7 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |||
1079 | 1077 | ||
1080 | u16 spur_val = AR_NO_SPUR; | 1078 | u16 spur_val = AR_NO_SPUR; |
1081 | 1079 | ||
1082 | ath_dbg(common, ATH_DBG_ANI, | 1080 | ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", |
1083 | "Getting spur idx:%d is2Ghz:%d val:%x\n", | ||
1084 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | 1081 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
1085 | 1082 | ||
1086 | switch (ah->config.spurmode) { | 1083 | switch (ah->config.spurmode) { |
@@ -1088,8 +1085,8 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |||
1088 | break; | 1085 | break; |
1089 | case SPUR_ENABLE_IOCTL: | 1086 | case SPUR_ENABLE_IOCTL: |
1090 | spur_val = ah->config.spurchans[i][is2GHz]; | 1087 | spur_val = ah->config.spurchans[i][is2GHz]; |
1091 | ath_dbg(common, ATH_DBG_ANI, | 1088 | ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", |
1092 | "Getting spur val from new loc. %d\n", spur_val); | 1089 | spur_val); |
1093 | break; | 1090 | break; |
1094 | case SPUR_ENABLE_EEPROM: | 1091 | case SPUR_ENABLE_EEPROM: |
1095 | spur_val = EEP_MAP4K_SPURCHAN; | 1092 | spur_val = EEP_MAP4K_SPURCHAN; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c index 0981c073471d..f272236d8053 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c | |||
@@ -41,7 +41,7 @@ static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) | |||
41 | for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) { | 41 | for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) { |
42 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, | 42 | if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, |
43 | eep_data)) { | 43 | eep_data)) { |
44 | ath_dbg(common, ATH_DBG_EEPROM, | 44 | ath_dbg(common, EEPROM, |
45 | "Unable to read eeprom region\n"); | 45 | "Unable to read eeprom region\n"); |
46 | return false; | 46 | return false; |
47 | } | 47 | } |
@@ -66,8 +66,7 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah) | |||
66 | struct ath_common *common = ath9k_hw_common(ah); | 66 | struct ath_common *common = ath9k_hw_common(ah); |
67 | 67 | ||
68 | if (!ath9k_hw_use_flash(ah)) { | 68 | if (!ath9k_hw_use_flash(ah)) { |
69 | ath_dbg(common, ATH_DBG_EEPROM, | 69 | ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n"); |
70 | "Reading from EEPROM, not flash\n"); | ||
71 | } | 70 | } |
72 | 71 | ||
73 | if (common->bus_ops->ath_bus_type == ATH_USB) | 72 | if (common->bus_ops->ath_bus_type == ATH_USB) |
@@ -197,8 +196,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) | |||
197 | return false; | 196 | return false; |
198 | } | 197 | } |
199 | 198 | ||
200 | ath_dbg(common, ATH_DBG_EEPROM, | 199 | ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic); |
201 | "Read Magic = 0x%04X\n", magic); | ||
202 | 200 | ||
203 | if (magic != AR5416_EEPROM_MAGIC) { | 201 | if (magic != AR5416_EEPROM_MAGIC) { |
204 | magic2 = swab16(magic); | 202 | magic2 = swab16(magic); |
@@ -220,7 +218,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah) | |||
220 | } | 218 | } |
221 | } | 219 | } |
222 | 220 | ||
223 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", | 221 | ath_dbg(common, EEPROM, "need_swap = %s\n", |
224 | need_swap ? "True" : "False"); | 222 | need_swap ? "True" : "False"); |
225 | 223 | ||
226 | if (need_swap) | 224 | if (need_swap) |
@@ -1041,8 +1039,7 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, | |||
1041 | struct ath_common *common = ath9k_hw_common(ah); | 1039 | struct ath_common *common = ath9k_hw_common(ah); |
1042 | u16 spur_val = AR_NO_SPUR; | 1040 | u16 spur_val = AR_NO_SPUR; |
1043 | 1041 | ||
1044 | ath_dbg(common, ATH_DBG_ANI, | 1042 | ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", |
1045 | "Getting spur idx:%d is2Ghz:%d val:%x\n", | ||
1046 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | 1043 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
1047 | 1044 | ||
1048 | switch (ah->config.spurmode) { | 1045 | switch (ah->config.spurmode) { |
@@ -1050,8 +1047,8 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah, | |||
1050 | break; | 1047 | break; |
1051 | case SPUR_ENABLE_IOCTL: | 1048 | case SPUR_ENABLE_IOCTL: |
1052 | spur_val = ah->config.spurchans[i][is2GHz]; | 1049 | spur_val = ah->config.spurchans[i][is2GHz]; |
1053 | ath_dbg(common, ATH_DBG_ANI, | 1050 | ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", |
1054 | "Getting spur val from new loc. %d\n", spur_val); | 1051 | spur_val); |
1055 | break; | 1052 | break; |
1056 | case SPUR_ENABLE_EEPROM: | 1053 | case SPUR_ENABLE_EEPROM: |
1057 | spur_val = EEP_MAP9287_SPURCHAN; | 1054 | spur_val = EEP_MAP9287_SPURCHAN; |
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c index 55a21d39167c..f57084ec49e7 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom_def.c +++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c | |||
@@ -121,8 +121,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) | |||
121 | struct ath_common *common = ath9k_hw_common(ah); | 121 | struct ath_common *common = ath9k_hw_common(ah); |
122 | 122 | ||
123 | if (!ath9k_hw_use_flash(ah)) { | 123 | if (!ath9k_hw_use_flash(ah)) { |
124 | ath_dbg(common, ATH_DBG_EEPROM, | 124 | ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n"); |
125 | "Reading from EEPROM, not flash\n"); | ||
126 | } | 125 | } |
127 | 126 | ||
128 | if (common->bus_ops->ath_bus_type == ATH_USB) | 127 | if (common->bus_ops->ath_bus_type == ATH_USB) |
@@ -279,8 +278,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
279 | } | 278 | } |
280 | 279 | ||
281 | if (!ath9k_hw_use_flash(ah)) { | 280 | if (!ath9k_hw_use_flash(ah)) { |
282 | ath_dbg(common, ATH_DBG_EEPROM, | 281 | ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic); |
283 | "Read Magic = 0x%04X\n", magic); | ||
284 | 282 | ||
285 | if (magic != AR5416_EEPROM_MAGIC) { | 283 | if (magic != AR5416_EEPROM_MAGIC) { |
286 | magic2 = swab16(magic); | 284 | magic2 = swab16(magic); |
@@ -303,7 +301,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
303 | } | 301 | } |
304 | } | 302 | } |
305 | 303 | ||
306 | ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n", | 304 | ath_dbg(common, EEPROM, "need_swap = %s\n", |
307 | need_swap ? "True" : "False"); | 305 | need_swap ? "True" : "False"); |
308 | 306 | ||
309 | if (need_swap) | 307 | if (need_swap) |
@@ -325,7 +323,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) | |||
325 | u32 integer, j; | 323 | u32 integer, j; |
326 | u16 word; | 324 | u16 word; |
327 | 325 | ||
328 | ath_dbg(common, ATH_DBG_EEPROM, | 326 | ath_dbg(common, EEPROM, |
329 | "EEPROM Endianness is not native.. Changing.\n"); | 327 | "EEPROM Endianness is not native.. Changing.\n"); |
330 | 328 | ||
331 | word = swab16(eep->baseEepHeader.length); | 329 | word = swab16(eep->baseEepHeader.length); |
@@ -965,15 +963,12 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, | |||
965 | reg32 = get_unaligned_le32(&pdadcValues[4 * j]); | 963 | reg32 = get_unaligned_le32(&pdadcValues[4 * j]); |
966 | REG_WRITE(ah, regOffset, reg32); | 964 | REG_WRITE(ah, regOffset, reg32); |
967 | 965 | ||
968 | ath_dbg(common, ATH_DBG_EEPROM, | 966 | ath_dbg(common, EEPROM, |
969 | "PDADC (%d,%4x): %4.4x %8.8x\n", | 967 | "PDADC (%d,%4x): %4.4x %8.8x\n", |
970 | i, regChainOffset, regOffset, | 968 | i, regChainOffset, regOffset, |
971 | reg32); | 969 | reg32); |
972 | ath_dbg(common, ATH_DBG_EEPROM, | 970 | ath_dbg(common, EEPROM, |
973 | "PDADC: Chain %d | PDADC %3d " | 971 | "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n", |
974 | "Value %3d | PDADC %3d Value %3d | " | ||
975 | "PDADC %3d Value %3d | PDADC %3d " | ||
976 | "Value %3d |\n", | ||
977 | i, 4 * j, pdadcValues[4 * j], | 972 | i, 4 * j, pdadcValues[4 * j], |
978 | 4 * j + 1, pdadcValues[4 * j + 1], | 973 | 4 * j + 1, pdadcValues[4 * j + 1], |
979 | 4 * j + 2, pdadcValues[4 * j + 2], | 974 | 4 * j + 2, pdadcValues[4 * j + 2], |
@@ -1278,7 +1273,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah, | |||
1278 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; | 1273 | regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; |
1279 | break; | 1274 | break; |
1280 | default: | 1275 | default: |
1281 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM, | 1276 | ath_dbg(ath9k_hw_common(ah), EEPROM, |
1282 | "Invalid chainmask configuration\n"); | 1277 | "Invalid chainmask configuration\n"); |
1283 | break; | 1278 | break; |
1284 | } | 1279 | } |
@@ -1396,8 +1391,7 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |||
1396 | 1391 | ||
1397 | u16 spur_val = AR_NO_SPUR; | 1392 | u16 spur_val = AR_NO_SPUR; |
1398 | 1393 | ||
1399 | ath_dbg(common, ATH_DBG_ANI, | 1394 | ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", |
1400 | "Getting spur idx:%d is2Ghz:%d val:%x\n", | ||
1401 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | 1395 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
1402 | 1396 | ||
1403 | switch (ah->config.spurmode) { | 1397 | switch (ah->config.spurmode) { |
@@ -1405,8 +1399,8 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) | |||
1405 | break; | 1399 | break; |
1406 | case SPUR_ENABLE_IOCTL: | 1400 | case SPUR_ENABLE_IOCTL: |
1407 | spur_val = ah->config.spurchans[i][is2GHz]; | 1401 | spur_val = ah->config.spurchans[i][is2GHz]; |
1408 | ath_dbg(common, ATH_DBG_ANI, | 1402 | ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", |
1409 | "Getting spur val from new loc. %d\n", spur_val); | 1403 | spur_val); |
1410 | break; | 1404 | break; |
1411 | case SPUR_ENABLE_EEPROM: | 1405 | case SPUR_ENABLE_EEPROM: |
1412 | spur_val = EEP_DEF_SPURCHAN; | 1406 | spur_val = EEP_DEF_SPURCHAN; |
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c index e4ae08e07719..7834d70a190d 100644 --- a/drivers/net/wireless/ath/ath9k/gpio.c +++ b/drivers/net/wireless/ath/ath9k/gpio.c | |||
@@ -130,12 +130,12 @@ static void ath_detect_bt_priority(struct ath_softc *sc) | |||
130 | sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); | 130 | sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN); |
131 | /* Detect if colocated bt started scanning */ | 131 | /* Detect if colocated bt started scanning */ |
132 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { | 132 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { |
133 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, | 133 | ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX, |
134 | "BT scan detected\n"); | 134 | "BT scan detected\n"); |
135 | sc->sc_flags |= (SC_OP_BT_SCAN | | 135 | sc->sc_flags |= (SC_OP_BT_SCAN | |
136 | SC_OP_BT_PRIORITY_DETECTED); | 136 | SC_OP_BT_PRIORITY_DETECTED); |
137 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { | 137 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { |
138 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX, | 138 | ath_dbg(ath9k_hw_common(sc->sc_ah), BTCOEX, |
139 | "BT priority traffic detected\n"); | 139 | "BT priority traffic detected\n"); |
140 | sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; | 140 | sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; |
141 | } | 141 | } |
@@ -230,8 +230,7 @@ static void ath_btcoex_no_stomp_timer(void *arg) | |||
230 | struct ath_common *common = ath9k_hw_common(ah); | 230 | struct ath_common *common = ath9k_hw_common(ah); |
231 | bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN; | 231 | bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN; |
232 | 232 | ||
233 | ath_dbg(common, ATH_DBG_BTCOEX, | 233 | ath_dbg(common, BTCOEX, "no stomp timer running\n"); |
234 | "no stomp timer running\n"); | ||
235 | 234 | ||
236 | ath9k_ps_wakeup(sc); | 235 | ath9k_ps_wakeup(sc); |
237 | spin_lock_bh(&btcoex->btcoex_lock); | 236 | spin_lock_bh(&btcoex->btcoex_lock); |
@@ -280,8 +279,7 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc) | |||
280 | struct ath_btcoex *btcoex = &sc->btcoex; | 279 | struct ath_btcoex *btcoex = &sc->btcoex; |
281 | struct ath_hw *ah = sc->sc_ah; | 280 | struct ath_hw *ah = sc->sc_ah; |
282 | 281 | ||
283 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 282 | ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex timers\n"); |
284 | "Starting btcoex timers\n"); | ||
285 | 283 | ||
286 | /* make sure duty cycle timer is also stopped when resuming */ | 284 | /* make sure duty cycle timer is also stopped when resuming */ |
287 | if (btcoex->hw_timer_enabled) | 285 | if (btcoex->hw_timer_enabled) |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c index 57fe22b24247..2eadffb7971c 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c | |||
@@ -167,9 +167,9 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv, | |||
167 | /* TSF out of range threshold fixed at 1 second */ | 167 | /* TSF out of range threshold fixed at 1 second */ |
168 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; | 168 | bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; |
169 | 169 | ||
170 | ath_dbg(common, ATH_DBG_CONFIG, "intval: %u tsf: %llu tsftu: %u\n", | 170 | ath_dbg(common, CONFIG, "intval: %u tsf: %llu tsftu: %u\n", |
171 | intval, tsf, tsftu); | 171 | intval, tsf, tsftu); |
172 | ath_dbg(common, ATH_DBG_CONFIG, | 172 | ath_dbg(common, CONFIG, |
173 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", | 173 | "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", |
174 | bs.bs_bmissthreshold, bs.bs_sleepduration, | 174 | bs.bs_bmissthreshold, bs.bs_sleepduration, |
175 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); | 175 | bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); |
@@ -224,9 +224,8 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv, | |||
224 | if (priv->op_flags & OP_ENABLE_BEACON) | 224 | if (priv->op_flags & OP_ENABLE_BEACON) |
225 | imask |= ATH9K_INT_SWBA; | 225 | imask |= ATH9K_INT_SWBA; |
226 | 226 | ||
227 | ath_dbg(common, ATH_DBG_CONFIG, | 227 | ath_dbg(common, CONFIG, |
228 | "AP Beacon config, intval: %d, nexttbtt: %u, resp_time: %d " | 228 | "AP Beacon config, intval: %d, nexttbtt: %u, resp_time: %d imask: 0x%x\n", |
229 | "imask: 0x%x\n", | ||
230 | bss_conf->beacon_interval, nexttbtt, | 229 | bss_conf->beacon_interval, nexttbtt, |
231 | priv->ah->config.sw_beacon_response_time, imask); | 230 | priv->ah->config.sw_beacon_response_time, imask); |
232 | 231 | ||
@@ -273,9 +272,8 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv, | |||
273 | if (priv->op_flags & OP_ENABLE_BEACON) | 272 | if (priv->op_flags & OP_ENABLE_BEACON) |
274 | imask |= ATH9K_INT_SWBA; | 273 | imask |= ATH9K_INT_SWBA; |
275 | 274 | ||
276 | ath_dbg(common, ATH_DBG_CONFIG, | 275 | ath_dbg(common, CONFIG, |
277 | "IBSS Beacon config, intval: %d, nexttbtt: %u, " | 276 | "IBSS Beacon config, intval: %d, nexttbtt: %u, resp_time: %d, imask: 0x%x\n", |
278 | "resp_time: %d, imask: 0x%x\n", | ||
279 | bss_conf->beacon_interval, nexttbtt, | 277 | bss_conf->beacon_interval, nexttbtt, |
280 | priv->ah->config.sw_beacon_response_time, imask); | 278 | priv->ah->config.sw_beacon_response_time, imask); |
281 | 279 | ||
@@ -323,7 +321,7 @@ static void ath9k_htc_send_buffered(struct ath9k_htc_priv *priv, | |||
323 | 321 | ||
324 | tx_slot = ath9k_htc_tx_get_slot(priv); | 322 | tx_slot = ath9k_htc_tx_get_slot(priv); |
325 | if (tx_slot < 0) { | 323 | if (tx_slot < 0) { |
326 | ath_dbg(common, ATH_DBG_XMIT, "No free CAB slot\n"); | 324 | ath_dbg(common, XMIT, "No free CAB slot\n"); |
327 | dev_kfree_skb_any(skb); | 325 | dev_kfree_skb_any(skb); |
328 | goto next; | 326 | goto next; |
329 | } | 327 | } |
@@ -333,8 +331,7 @@ static void ath9k_htc_send_buffered(struct ath9k_htc_priv *priv, | |||
333 | ath9k_htc_tx_clear_slot(priv, tx_slot); | 331 | ath9k_htc_tx_clear_slot(priv, tx_slot); |
334 | dev_kfree_skb_any(skb); | 332 | dev_kfree_skb_any(skb); |
335 | 333 | ||
336 | ath_dbg(common, ATH_DBG_XMIT, | 334 | ath_dbg(common, XMIT, "Failed to send CAB frame\n"); |
337 | "Failed to send CAB frame\n"); | ||
338 | } else { | 335 | } else { |
339 | spin_lock_bh(&priv->tx.tx_lock); | 336 | spin_lock_bh(&priv->tx.tx_lock); |
340 | priv->tx.queued_cnt++; | 337 | priv->tx.queued_cnt++; |
@@ -409,7 +406,7 @@ static void ath9k_htc_send_beacon(struct ath9k_htc_priv *priv, | |||
409 | ret = htc_send(priv->htc, beacon); | 406 | ret = htc_send(priv->htc, beacon); |
410 | if (ret != 0) { | 407 | if (ret != 0) { |
411 | if (ret == -ENOMEM) { | 408 | if (ret == -ENOMEM) { |
412 | ath_dbg(common, ATH_DBG_BSTUCK, | 409 | ath_dbg(common, BSTUCK, |
413 | "Failed to send beacon, no free TX buffer\n"); | 410 | "Failed to send beacon, no free TX buffer\n"); |
414 | } | 411 | } |
415 | dev_kfree_skb_any(beacon); | 412 | dev_kfree_skb_any(beacon); |
@@ -434,7 +431,7 @@ static int ath9k_htc_choose_bslot(struct ath9k_htc_priv *priv, | |||
434 | slot = ((tsftu % intval) * ATH9K_HTC_MAX_BCN_VIF) / intval; | 431 | slot = ((tsftu % intval) * ATH9K_HTC_MAX_BCN_VIF) / intval; |
435 | slot = ATH9K_HTC_MAX_BCN_VIF - slot - 1; | 432 | slot = ATH9K_HTC_MAX_BCN_VIF - slot - 1; |
436 | 433 | ||
437 | ath_dbg(common, ATH_DBG_BEACON, | 434 | ath_dbg(common, BEACON, |
438 | "Choose slot: %d, tsf: %llu, tsftu: %u, intval: %u\n", | 435 | "Choose slot: %d, tsf: %llu, tsftu: %u, intval: %u\n", |
439 | slot, tsf, tsftu, intval); | 436 | slot, tsf, tsftu, intval); |
440 | 437 | ||
@@ -450,8 +447,7 @@ void ath9k_htc_swba(struct ath9k_htc_priv *priv, | |||
450 | if (swba->beacon_pending != 0) { | 447 | if (swba->beacon_pending != 0) { |
451 | priv->cur_beacon_conf.bmiss_cnt++; | 448 | priv->cur_beacon_conf.bmiss_cnt++; |
452 | if (priv->cur_beacon_conf.bmiss_cnt > BSTUCK_THRESHOLD) { | 449 | if (priv->cur_beacon_conf.bmiss_cnt > BSTUCK_THRESHOLD) { |
453 | ath_dbg(common, ATH_DBG_BSTUCK, | 450 | ath_dbg(common, BSTUCK, "Beacon stuck, HW reset\n"); |
454 | "Beacon stuck, HW reset\n"); | ||
455 | ieee80211_queue_work(priv->hw, | 451 | ieee80211_queue_work(priv->hw, |
456 | &priv->fatal_work); | 452 | &priv->fatal_work); |
457 | } | 453 | } |
@@ -459,7 +455,7 @@ void ath9k_htc_swba(struct ath9k_htc_priv *priv, | |||
459 | } | 455 | } |
460 | 456 | ||
461 | if (priv->cur_beacon_conf.bmiss_cnt) { | 457 | if (priv->cur_beacon_conf.bmiss_cnt) { |
462 | ath_dbg(common, ATH_DBG_BSTUCK, | 458 | ath_dbg(common, BSTUCK, |
463 | "Resuming beacon xmit after %u misses\n", | 459 | "Resuming beacon xmit after %u misses\n", |
464 | priv->cur_beacon_conf.bmiss_cnt); | 460 | priv->cur_beacon_conf.bmiss_cnt); |
465 | priv->cur_beacon_conf.bmiss_cnt = 0; | 461 | priv->cur_beacon_conf.bmiss_cnt = 0; |
@@ -495,8 +491,8 @@ void ath9k_htc_assign_bslot(struct ath9k_htc_priv *priv, | |||
495 | priv->cur_beacon_conf.bslot[avp->bslot] = vif; | 491 | priv->cur_beacon_conf.bslot[avp->bslot] = vif; |
496 | spin_unlock_bh(&priv->beacon_lock); | 492 | spin_unlock_bh(&priv->beacon_lock); |
497 | 493 | ||
498 | ath_dbg(common, ATH_DBG_CONFIG, | 494 | ath_dbg(common, CONFIG, "Added interface at beacon slot: %d\n", |
499 | "Added interface at beacon slot: %d\n", avp->bslot); | 495 | avp->bslot); |
500 | } | 496 | } |
501 | 497 | ||
502 | void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv, | 498 | void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv, |
@@ -509,8 +505,8 @@ void ath9k_htc_remove_bslot(struct ath9k_htc_priv *priv, | |||
509 | priv->cur_beacon_conf.bslot[avp->bslot] = NULL; | 505 | priv->cur_beacon_conf.bslot[avp->bslot] = NULL; |
510 | spin_unlock_bh(&priv->beacon_lock); | 506 | spin_unlock_bh(&priv->beacon_lock); |
511 | 507 | ||
512 | ath_dbg(common, ATH_DBG_CONFIG, | 508 | ath_dbg(common, CONFIG, "Removed interface at beacon slot: %d\n", |
513 | "Removed interface at beacon slot: %d\n", avp->bslot); | 509 | avp->bslot); |
514 | } | 510 | } |
515 | 511 | ||
516 | /* | 512 | /* |
@@ -536,8 +532,7 @@ void ath9k_htc_set_tsfadjust(struct ath9k_htc_priv *priv, | |||
536 | tsfadjust = cur_conf->beacon_interval * avp->bslot / ATH9K_HTC_MAX_BCN_VIF; | 532 | tsfadjust = cur_conf->beacon_interval * avp->bslot / ATH9K_HTC_MAX_BCN_VIF; |
537 | avp->tsfadjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); | 533 | avp->tsfadjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); |
538 | 534 | ||
539 | ath_dbg(common, ATH_DBG_CONFIG, | 535 | ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n", |
540 | "tsfadjust is: %llu for bslot: %d\n", | ||
541 | (unsigned long long)tsfadjust, avp->bslot); | 536 | (unsigned long long)tsfadjust, avp->bslot); |
542 | } | 537 | } |
543 | 538 | ||
@@ -568,7 +563,7 @@ static bool ath9k_htc_check_beacon_config(struct ath9k_htc_priv *priv, | |||
568 | (priv->num_ap_vif > 1) && | 563 | (priv->num_ap_vif > 1) && |
569 | (vif->type == NL80211_IFTYPE_AP) && | 564 | (vif->type == NL80211_IFTYPE_AP) && |
570 | (cur_conf->beacon_interval != bss_conf->beacon_int)) { | 565 | (cur_conf->beacon_interval != bss_conf->beacon_int)) { |
571 | ath_dbg(common, ATH_DBG_CONFIG, | 566 | ath_dbg(common, CONFIG, |
572 | "Changing beacon interval of multiple AP interfaces !\n"); | 567 | "Changing beacon interval of multiple AP interfaces !\n"); |
573 | return false; | 568 | return false; |
574 | } | 569 | } |
@@ -579,7 +574,7 @@ static bool ath9k_htc_check_beacon_config(struct ath9k_htc_priv *priv, | |||
579 | */ | 574 | */ |
580 | if (priv->num_ap_vif && | 575 | if (priv->num_ap_vif && |
581 | (vif->type != NL80211_IFTYPE_AP)) { | 576 | (vif->type != NL80211_IFTYPE_AP)) { |
582 | ath_dbg(common, ATH_DBG_CONFIG, | 577 | ath_dbg(common, CONFIG, |
583 | "HW in AP mode, cannot set STA beacon parameters\n"); | 578 | "HW in AP mode, cannot set STA beacon parameters\n"); |
584 | return false; | 579 | return false; |
585 | } | 580 | } |
@@ -597,7 +592,7 @@ static bool ath9k_htc_check_beacon_config(struct ath9k_htc_priv *priv, | |||
597 | &beacon_configured); | 592 | &beacon_configured); |
598 | 593 | ||
599 | if (beacon_configured) { | 594 | if (beacon_configured) { |
600 | ath_dbg(common, ATH_DBG_CONFIG, | 595 | ath_dbg(common, CONFIG, |
601 | "Beacon already configured for a station interface\n"); | 596 | "Beacon already configured for a station interface\n"); |
602 | return false; | 597 | return false; |
603 | } | 598 | } |
@@ -637,8 +632,7 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv, | |||
637 | ath9k_htc_beacon_config_ap(priv, cur_conf); | 632 | ath9k_htc_beacon_config_ap(priv, cur_conf); |
638 | break; | 633 | break; |
639 | default: | 634 | default: |
640 | ath_dbg(common, ATH_DBG_CONFIG, | 635 | ath_dbg(common, CONFIG, "Unsupported beaconing mode\n"); |
641 | "Unsupported beaconing mode\n"); | ||
642 | return; | 636 | return; |
643 | } | 637 | } |
644 | } | 638 | } |
@@ -659,8 +653,7 @@ void ath9k_htc_beacon_reconfig(struct ath9k_htc_priv *priv) | |||
659 | ath9k_htc_beacon_config_ap(priv, cur_conf); | 653 | ath9k_htc_beacon_config_ap(priv, cur_conf); |
660 | break; | 654 | break; |
661 | default: | 655 | default: |
662 | ath_dbg(common, ATH_DBG_CONFIG, | 656 | ath_dbg(common, CONFIG, "Unsupported beaconing mode\n"); |
663 | "Unsupported beaconing mode\n"); | ||
664 | return; | 657 | return; |
665 | } | 658 | } |
666 | } | 659 | } |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c index ce606b618e0b..b7c030018403 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c | |||
@@ -36,12 +36,12 @@ static void ath_detect_bt_priority(struct ath9k_htc_priv *priv) | |||
36 | priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); | 36 | priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN); |
37 | /* Detect if colocated bt started scanning */ | 37 | /* Detect if colocated bt started scanning */ |
38 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { | 38 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) { |
39 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 39 | ath_dbg(ath9k_hw_common(ah), BTCOEX, |
40 | "BT scan detected\n"); | 40 | "BT scan detected\n"); |
41 | priv->op_flags |= (OP_BT_SCAN | | 41 | priv->op_flags |= (OP_BT_SCAN | |
42 | OP_BT_PRIORITY_DETECTED); | 42 | OP_BT_PRIORITY_DETECTED); |
43 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { | 43 | } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { |
44 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, | 44 | ath_dbg(ath9k_hw_common(ah), BTCOEX, |
45 | "BT priority traffic detected\n"); | 45 | "BT priority traffic detected\n"); |
46 | priv->op_flags |= OP_BT_PRIORITY_DETECTED; | 46 | priv->op_flags |= OP_BT_PRIORITY_DETECTED; |
47 | } | 47 | } |
@@ -102,8 +102,7 @@ static void ath_btcoex_duty_cycle_work(struct work_struct *work) | |||
102 | struct ath_common *common = ath9k_hw_common(ah); | 102 | struct ath_common *common = ath9k_hw_common(ah); |
103 | bool is_btscan = priv->op_flags & OP_BT_SCAN; | 103 | bool is_btscan = priv->op_flags & OP_BT_SCAN; |
104 | 104 | ||
105 | ath_dbg(common, ATH_DBG_BTCOEX, | 105 | ath_dbg(common, BTCOEX, "time slice work for bt and wlan\n"); |
106 | "time slice work for bt and wlan\n"); | ||
107 | 106 | ||
108 | if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) | 107 | if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan) |
109 | ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); | 108 | ath9k_hw_btcoex_bt_stomp(ah, ATH_BTCOEX_STOMP_NONE); |
@@ -134,7 +133,7 @@ void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv) | |||
134 | struct ath_btcoex *btcoex = &priv->btcoex; | 133 | struct ath_btcoex *btcoex = &priv->btcoex; |
135 | struct ath_hw *ah = priv->ah; | 134 | struct ath_hw *ah = priv->ah; |
136 | 135 | ||
137 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, "Starting btcoex work\n"); | 136 | ath_dbg(ath9k_hw_common(ah), BTCOEX, "Starting btcoex work\n"); |
138 | 137 | ||
139 | btcoex->bt_priority_cnt = 0; | 138 | btcoex->bt_priority_cnt = 0; |
140 | btcoex->bt_priority_time = jiffies; | 139 | btcoex->bt_priority_time = jiffies; |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c index 966661c9e586..6cbad73f9f2a 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c | |||
@@ -299,8 +299,7 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) | |||
299 | (u8 *) &val, sizeof(val), | 299 | (u8 *) &val, sizeof(val), |
300 | 100); | 300 | 100); |
301 | if (unlikely(r)) { | 301 | if (unlikely(r)) { |
302 | ath_dbg(common, ATH_DBG_WMI, | 302 | ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n", |
303 | "REGISTER READ FAILED: (0x%04x, %d)\n", | ||
304 | reg_offset, r); | 303 | reg_offset, r); |
305 | return -EIO; | 304 | return -EIO; |
306 | } | 305 | } |
@@ -327,7 +326,7 @@ static void ath9k_multi_regread(void *hw_priv, u32 *addr, | |||
327 | (u8 *)tmpval, sizeof(u32) * count, | 326 | (u8 *)tmpval, sizeof(u32) * count, |
328 | 100); | 327 | 100); |
329 | if (unlikely(ret)) { | 328 | if (unlikely(ret)) { |
330 | ath_dbg(common, ATH_DBG_WMI, | 329 | ath_dbg(common, WMI, |
331 | "Multiple REGISTER READ FAILED (count: %d)\n", count); | 330 | "Multiple REGISTER READ FAILED (count: %d)\n", count); |
332 | } | 331 | } |
333 | 332 | ||
@@ -352,8 +351,7 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) | |||
352 | (u8 *) &val, sizeof(val), | 351 | (u8 *) &val, sizeof(val), |
353 | 100); | 352 | 100); |
354 | if (unlikely(r)) { | 353 | if (unlikely(r)) { |
355 | ath_dbg(common, ATH_DBG_WMI, | 354 | ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n", |
356 | "REGISTER WRITE FAILED:(0x%04x, %d)\n", | ||
357 | reg_offset, r); | 355 | reg_offset, r); |
358 | } | 356 | } |
359 | } | 357 | } |
@@ -384,7 +382,7 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) | |||
384 | (u8 *) &rsp_status, sizeof(rsp_status), | 382 | (u8 *) &rsp_status, sizeof(rsp_status), |
385 | 100); | 383 | 100); |
386 | if (unlikely(r)) { | 384 | if (unlikely(r)) { |
387 | ath_dbg(common, ATH_DBG_WMI, | 385 | ath_dbg(common, WMI, |
388 | "REGISTER WRITE FAILED, multi len: %d\n", | 386 | "REGISTER WRITE FAILED, multi len: %d\n", |
389 | priv->wmi->multi_write_idx); | 387 | priv->wmi->multi_write_idx); |
390 | } | 388 | } |
@@ -434,7 +432,7 @@ static void ath9k_regwrite_flush(void *hw_priv) | |||
434 | (u8 *) &rsp_status, sizeof(rsp_status), | 432 | (u8 *) &rsp_status, sizeof(rsp_status), |
435 | 100); | 433 | 100); |
436 | if (unlikely(r)) { | 434 | if (unlikely(r)) { |
437 | ath_dbg(common, ATH_DBG_WMI, | 435 | ath_dbg(common, WMI, |
438 | "REGISTER WRITE FAILED, multi len: %d\n", | 436 | "REGISTER WRITE FAILED, multi len: %d\n", |
439 | priv->wmi->multi_write_idx); | 437 | priv->wmi->multi_write_idx); |
440 | } | 438 | } |
@@ -512,8 +510,7 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv, | |||
512 | tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2); | 510 | tx_streams = ath9k_cmn_count_streams(priv->ah->txchainmask, 2); |
513 | rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2); | 511 | rx_streams = ath9k_cmn_count_streams(priv->ah->rxchainmask, 2); |
514 | 512 | ||
515 | ath_dbg(common, ATH_DBG_CONFIG, | 513 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
516 | "TX streams %d, RX streams: %d\n", | ||
517 | tx_streams, rx_streams); | 514 | tx_streams, rx_streams); |
518 | 515 | ||
519 | if (tx_streams != rx_streams) { | 516 | if (tx_streams != rx_streams) { |
@@ -876,9 +873,8 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv, | |||
876 | goto err_world; | 873 | goto err_world; |
877 | } | 874 | } |
878 | 875 | ||
879 | ath_dbg(common, ATH_DBG_CONFIG, | 876 | ath_dbg(common, CONFIG, |
880 | "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, " | 877 | "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n", |
881 | "BE:%d, BK:%d, VI:%d, VO:%d\n", | ||
882 | priv->wmi_cmd_ep, | 878 | priv->wmi_cmd_ep, |
883 | priv->beacon_ep, | 879 | priv->beacon_ep, |
884 | priv->cab_ep, | 880 | priv->cab_ep, |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c index f8ce4ea6f65c..539f4455076e 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c | |||
@@ -266,7 +266,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv, | |||
266 | 266 | ||
267 | ath9k_wmi_event_drain(priv); | 267 | ath9k_wmi_event_drain(priv); |
268 | 268 | ||
269 | ath_dbg(common, ATH_DBG_CONFIG, | 269 | ath_dbg(common, CONFIG, |
270 | "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n", | 270 | "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n", |
271 | priv->ah->curchan->channel, | 271 | priv->ah->curchan->channel, |
272 | channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf), | 272 | channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf), |
@@ -415,7 +415,7 @@ static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv) | |||
415 | priv->vif_sta_pos[priv->mon_vif_idx] = sta_idx; | 415 | priv->vif_sta_pos[priv->mon_vif_idx] = sta_idx; |
416 | priv->ah->is_monitoring = true; | 416 | priv->ah->is_monitoring = true; |
417 | 417 | ||
418 | ath_dbg(common, ATH_DBG_CONFIG, | 418 | ath_dbg(common, CONFIG, |
419 | "Attached a monitor interface at idx: %d, sta idx: %d\n", | 419 | "Attached a monitor interface at idx: %d, sta idx: %d\n", |
420 | priv->mon_vif_idx, sta_idx); | 420 | priv->mon_vif_idx, sta_idx); |
421 | 421 | ||
@@ -427,7 +427,7 @@ err_sta: | |||
427 | */ | 427 | */ |
428 | __ath9k_htc_remove_monitor_interface(priv); | 428 | __ath9k_htc_remove_monitor_interface(priv); |
429 | err_vif: | 429 | err_vif: |
430 | ath_dbg(common, ATH_DBG_FATAL, "Unable to attach a monitor interface\n"); | 430 | ath_dbg(common, FATAL, "Unable to attach a monitor interface\n"); |
431 | 431 | ||
432 | return ret; | 432 | return ret; |
433 | } | 433 | } |
@@ -452,7 +452,7 @@ static int ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv) | |||
452 | priv->nstations--; | 452 | priv->nstations--; |
453 | priv->ah->is_monitoring = false; | 453 | priv->ah->is_monitoring = false; |
454 | 454 | ||
455 | ath_dbg(common, ATH_DBG_CONFIG, | 455 | ath_dbg(common, CONFIG, |
456 | "Removed a monitor interface at idx: %d, sta idx: %d\n", | 456 | "Removed a monitor interface at idx: %d, sta idx: %d\n", |
457 | priv->mon_vif_idx, sta_idx); | 457 | priv->mon_vif_idx, sta_idx); |
458 | 458 | ||
@@ -512,11 +512,11 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv, | |||
512 | } | 512 | } |
513 | 513 | ||
514 | if (sta) { | 514 | if (sta) { |
515 | ath_dbg(common, ATH_DBG_CONFIG, | 515 | ath_dbg(common, CONFIG, |
516 | "Added a station entry for: %pM (idx: %d)\n", | 516 | "Added a station entry for: %pM (idx: %d)\n", |
517 | sta->addr, tsta.sta_index); | 517 | sta->addr, tsta.sta_index); |
518 | } else { | 518 | } else { |
519 | ath_dbg(common, ATH_DBG_CONFIG, | 519 | ath_dbg(common, CONFIG, |
520 | "Added a station entry for VIF %d (idx: %d)\n", | 520 | "Added a station entry for VIF %d (idx: %d)\n", |
521 | avp->index, tsta.sta_index); | 521 | avp->index, tsta.sta_index); |
522 | } | 522 | } |
@@ -556,11 +556,11 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv, | |||
556 | } | 556 | } |
557 | 557 | ||
558 | if (sta) { | 558 | if (sta) { |
559 | ath_dbg(common, ATH_DBG_CONFIG, | 559 | ath_dbg(common, CONFIG, |
560 | "Removed a station entry for: %pM (idx: %d)\n", | 560 | "Removed a station entry for: %pM (idx: %d)\n", |
561 | sta->addr, sta_idx); | 561 | sta->addr, sta_idx); |
562 | } else { | 562 | } else { |
563 | ath_dbg(common, ATH_DBG_CONFIG, | 563 | ath_dbg(common, CONFIG, |
564 | "Removed a station entry for VIF %d (idx: %d)\n", | 564 | "Removed a station entry for VIF %d (idx: %d)\n", |
565 | avp->index, sta_idx); | 565 | avp->index, sta_idx); |
566 | } | 566 | } |
@@ -665,7 +665,7 @@ static void ath9k_htc_init_rate(struct ath9k_htc_priv *priv, | |||
665 | ath9k_htc_setup_rate(priv, sta, &trate); | 665 | ath9k_htc_setup_rate(priv, sta, &trate); |
666 | ret = ath9k_htc_send_rate_cmd(priv, &trate); | 666 | ret = ath9k_htc_send_rate_cmd(priv, &trate); |
667 | if (!ret) | 667 | if (!ret) |
668 | ath_dbg(common, ATH_DBG_CONFIG, | 668 | ath_dbg(common, CONFIG, |
669 | "Updated target sta: %pM, rate caps: 0x%X\n", | 669 | "Updated target sta: %pM, rate caps: 0x%X\n", |
670 | sta->addr, be32_to_cpu(trate.capflags)); | 670 | sta->addr, be32_to_cpu(trate.capflags)); |
671 | } | 671 | } |
@@ -692,7 +692,7 @@ static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv, | |||
692 | 692 | ||
693 | ret = ath9k_htc_send_rate_cmd(priv, &trate); | 693 | ret = ath9k_htc_send_rate_cmd(priv, &trate); |
694 | if (!ret) | 694 | if (!ret) |
695 | ath_dbg(common, ATH_DBG_CONFIG, | 695 | ath_dbg(common, CONFIG, |
696 | "Updated target sta: %pM, rate caps: 0x%X\n", | 696 | "Updated target sta: %pM, rate caps: 0x%X\n", |
697 | bss_conf->bssid, be32_to_cpu(trate.capflags)); | 697 | bss_conf->bssid, be32_to_cpu(trate.capflags)); |
698 | } | 698 | } |
@@ -721,11 +721,11 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv, | |||
721 | 721 | ||
722 | WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr); | 722 | WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr); |
723 | if (ret) | 723 | if (ret) |
724 | ath_dbg(common, ATH_DBG_CONFIG, | 724 | ath_dbg(common, CONFIG, |
725 | "Unable to %s TX aggregation for (%pM, %d)\n", | 725 | "Unable to %s TX aggregation for (%pM, %d)\n", |
726 | (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid); | 726 | (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid); |
727 | else | 727 | else |
728 | ath_dbg(common, ATH_DBG_CONFIG, | 728 | ath_dbg(common, CONFIG, |
729 | "%s TX aggregation for (%pM, %d)\n", | 729 | "%s TX aggregation for (%pM, %d)\n", |
730 | (aggr.aggr_enable) ? "Starting" : "Stopping", | 730 | (aggr.aggr_enable) ? "Starting" : "Stopping", |
731 | sta->addr, tid); | 731 | sta->addr, tid); |
@@ -784,7 +784,7 @@ void ath9k_htc_ani_work(struct work_struct *work) | |||
784 | /* Long calibration runs independently of short calibration. */ | 784 | /* Long calibration runs independently of short calibration. */ |
785 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { | 785 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
786 | longcal = true; | 786 | longcal = true; |
787 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); | 787 | ath_dbg(common, ANI, "longcal @%lu\n", jiffies); |
788 | common->ani.longcal_timer = timestamp; | 788 | common->ani.longcal_timer = timestamp; |
789 | } | 789 | } |
790 | 790 | ||
@@ -793,8 +793,7 @@ void ath9k_htc_ani_work(struct work_struct *work) | |||
793 | if ((timestamp - common->ani.shortcal_timer) >= | 793 | if ((timestamp - common->ani.shortcal_timer) >= |
794 | short_cal_interval) { | 794 | short_cal_interval) { |
795 | shortcal = true; | 795 | shortcal = true; |
796 | ath_dbg(common, ATH_DBG_ANI, | 796 | ath_dbg(common, ANI, "shortcal @%lu\n", jiffies); |
797 | "shortcal @%lu\n", jiffies); | ||
798 | common->ani.shortcal_timer = timestamp; | 797 | common->ani.shortcal_timer = timestamp; |
799 | common->ani.resetcal_timer = timestamp; | 798 | common->ani.resetcal_timer = timestamp; |
800 | } | 799 | } |
@@ -866,7 +865,7 @@ static void ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
866 | padsize = padpos & 3; | 865 | padsize = padpos & 3; |
867 | if (padsize && skb->len > padpos) { | 866 | if (padsize && skb->len > padpos) { |
868 | if (skb_headroom(skb) < padsize) { | 867 | if (skb_headroom(skb) < padsize) { |
869 | ath_dbg(common, ATH_DBG_XMIT, "No room for padding\n"); | 868 | ath_dbg(common, XMIT, "No room for padding\n"); |
870 | goto fail_tx; | 869 | goto fail_tx; |
871 | } | 870 | } |
872 | skb_push(skb, padsize); | 871 | skb_push(skb, padsize); |
@@ -875,13 +874,13 @@ static void ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
875 | 874 | ||
876 | slot = ath9k_htc_tx_get_slot(priv); | 875 | slot = ath9k_htc_tx_get_slot(priv); |
877 | if (slot < 0) { | 876 | if (slot < 0) { |
878 | ath_dbg(common, ATH_DBG_XMIT, "No free TX slot\n"); | 877 | ath_dbg(common, XMIT, "No free TX slot\n"); |
879 | goto fail_tx; | 878 | goto fail_tx; |
880 | } | 879 | } |
881 | 880 | ||
882 | ret = ath9k_htc_tx_start(priv, skb, slot, false); | 881 | ret = ath9k_htc_tx_start(priv, skb, slot, false); |
883 | if (ret != 0) { | 882 | if (ret != 0) { |
884 | ath_dbg(common, ATH_DBG_XMIT, "Tx failed\n"); | 883 | ath_dbg(common, XMIT, "Tx failed\n"); |
885 | goto clear_slot; | 884 | goto clear_slot; |
886 | } | 885 | } |
887 | 886 | ||
@@ -909,7 +908,7 @@ static int ath9k_htc_start(struct ieee80211_hw *hw) | |||
909 | 908 | ||
910 | mutex_lock(&priv->mutex); | 909 | mutex_lock(&priv->mutex); |
911 | 910 | ||
912 | ath_dbg(common, ATH_DBG_CONFIG, | 911 | ath_dbg(common, CONFIG, |
913 | "Starting driver with initial channel: %d MHz\n", | 912 | "Starting driver with initial channel: %d MHz\n", |
914 | curchan->center_freq); | 913 | curchan->center_freq); |
915 | 914 | ||
@@ -943,7 +942,7 @@ static int ath9k_htc_start(struct ieee80211_hw *hw) | |||
943 | 942 | ||
944 | ret = ath9k_htc_update_cap_target(priv, 0); | 943 | ret = ath9k_htc_update_cap_target(priv, 0); |
945 | if (ret) | 944 | if (ret) |
946 | ath_dbg(common, ATH_DBG_CONFIG, | 945 | ath_dbg(common, CONFIG, |
947 | "Failed to update capability in target\n"); | 946 | "Failed to update capability in target\n"); |
948 | 947 | ||
949 | priv->op_flags &= ~OP_INVALID; | 948 | priv->op_flags &= ~OP_INVALID; |
@@ -980,7 +979,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw) | |||
980 | mutex_lock(&priv->mutex); | 979 | mutex_lock(&priv->mutex); |
981 | 980 | ||
982 | if (priv->op_flags & OP_INVALID) { | 981 | if (priv->op_flags & OP_INVALID) { |
983 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | 982 | ath_dbg(common, ANY, "Device not present\n"); |
984 | mutex_unlock(&priv->mutex); | 983 | mutex_unlock(&priv->mutex); |
985 | return; | 984 | return; |
986 | } | 985 | } |
@@ -1027,7 +1026,7 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw) | |||
1027 | 1026 | ||
1028 | priv->op_flags |= OP_INVALID; | 1027 | priv->op_flags |= OP_INVALID; |
1029 | 1028 | ||
1030 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); | 1029 | ath_dbg(common, CONFIG, "Driver halt\n"); |
1031 | mutex_unlock(&priv->mutex); | 1030 | mutex_unlock(&priv->mutex); |
1032 | } | 1031 | } |
1033 | 1032 | ||
@@ -1120,8 +1119,8 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw, | |||
1120 | ath9k_htc_start_ani(priv); | 1119 | ath9k_htc_start_ani(priv); |
1121 | } | 1120 | } |
1122 | 1121 | ||
1123 | ath_dbg(common, ATH_DBG_CONFIG, | 1122 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d at idx: %d\n", |
1124 | "Attach a VIF of type: %d at idx: %d\n", vif->type, avp->index); | 1123 | vif->type, avp->index); |
1125 | 1124 | ||
1126 | out: | 1125 | out: |
1127 | ath9k_htc_ps_restore(priv); | 1126 | ath9k_htc_ps_restore(priv); |
@@ -1177,7 +1176,7 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw, | |||
1177 | ath9k_htc_stop_ani(priv); | 1176 | ath9k_htc_stop_ani(priv); |
1178 | } | 1177 | } |
1179 | 1178 | ||
1180 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface at idx: %d\n", avp->index); | 1179 | ath_dbg(common, CONFIG, "Detach Interface at idx: %d\n", avp->index); |
1181 | 1180 | ||
1182 | ath9k_htc_ps_restore(priv); | 1181 | ath9k_htc_ps_restore(priv); |
1183 | mutex_unlock(&priv->mutex); | 1182 | mutex_unlock(&priv->mutex); |
@@ -1202,8 +1201,7 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1202 | mutex_unlock(&priv->htc_pm_lock); | 1201 | mutex_unlock(&priv->htc_pm_lock); |
1203 | 1202 | ||
1204 | if (enable_radio) { | 1203 | if (enable_radio) { |
1205 | ath_dbg(common, ATH_DBG_CONFIG, | 1204 | ath_dbg(common, CONFIG, "not-idle: enabling radio\n"); |
1206 | "not-idle: enabling radio\n"); | ||
1207 | ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); | 1205 | ath9k_htc_setpower(priv, ATH9K_PM_AWAKE); |
1208 | ath9k_htc_radio_enable(hw); | 1206 | ath9k_htc_radio_enable(hw); |
1209 | } | 1207 | } |
@@ -1225,7 +1223,7 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1225 | struct ieee80211_channel *curchan = hw->conf.channel; | 1223 | struct ieee80211_channel *curchan = hw->conf.channel; |
1226 | int pos = curchan->hw_value; | 1224 | int pos = curchan->hw_value; |
1227 | 1225 | ||
1228 | ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", | 1226 | ath_dbg(common, CONFIG, "Set channel: %d MHz\n", |
1229 | curchan->center_freq); | 1227 | curchan->center_freq); |
1230 | 1228 | ||
1231 | ath9k_cmn_update_ichannel(&priv->ah->channels[pos], | 1229 | ath9k_cmn_update_ichannel(&priv->ah->channels[pos], |
@@ -1265,8 +1263,7 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed) | |||
1265 | } | 1263 | } |
1266 | mutex_unlock(&priv->htc_pm_lock); | 1264 | mutex_unlock(&priv->htc_pm_lock); |
1267 | 1265 | ||
1268 | ath_dbg(common, ATH_DBG_CONFIG, | 1266 | ath_dbg(common, CONFIG, "idle: disabling radio\n"); |
1269 | "idle: disabling radio\n"); | ||
1270 | ath9k_htc_radio_disable(hw); | 1267 | ath9k_htc_radio_disable(hw); |
1271 | } | 1268 | } |
1272 | 1269 | ||
@@ -1298,7 +1295,7 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw, | |||
1298 | *total_flags &= SUPPORTED_FILTERS; | 1295 | *total_flags &= SUPPORTED_FILTERS; |
1299 | 1296 | ||
1300 | if (priv->op_flags & OP_INVALID) { | 1297 | if (priv->op_flags & OP_INVALID) { |
1301 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_ANY, | 1298 | ath_dbg(ath9k_hw_common(priv->ah), ANY, |
1302 | "Unable to configure filter on invalid state\n"); | 1299 | "Unable to configure filter on invalid state\n"); |
1303 | mutex_unlock(&priv->mutex); | 1300 | mutex_unlock(&priv->mutex); |
1304 | return; | 1301 | return; |
@@ -1309,8 +1306,8 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw, | |||
1309 | rfilt = ath9k_htc_calcrxfilter(priv); | 1306 | rfilt = ath9k_htc_calcrxfilter(priv); |
1310 | ath9k_hw_setrxfilter(priv->ah, rfilt); | 1307 | ath9k_hw_setrxfilter(priv->ah, rfilt); |
1311 | 1308 | ||
1312 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG, | 1309 | ath_dbg(ath9k_hw_common(priv->ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1313 | "Set HW RX filter: 0x%x\n", rfilt); | 1310 | rfilt); |
1314 | 1311 | ||
1315 | ath9k_htc_ps_restore(priv); | 1312 | ath9k_htc_ps_restore(priv); |
1316 | mutex_unlock(&priv->mutex); | 1313 | mutex_unlock(&priv->mutex); |
@@ -1377,7 +1374,7 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, | |||
1377 | 1374 | ||
1378 | qnum = get_hw_qnum(queue, priv->hwq_map); | 1375 | qnum = get_hw_qnum(queue, priv->hwq_map); |
1379 | 1376 | ||
1380 | ath_dbg(common, ATH_DBG_CONFIG, | 1377 | ath_dbg(common, CONFIG, |
1381 | "Configure tx [queue/hwq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | 1378 | "Configure tx [queue/hwq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1382 | queue, qnum, params->aifs, params->cw_min, | 1379 | queue, qnum, params->aifs, params->cw_min, |
1383 | params->cw_max, params->txop); | 1380 | params->cw_max, params->txop); |
@@ -1412,7 +1409,7 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw, | |||
1412 | return -ENOSPC; | 1409 | return -ENOSPC; |
1413 | 1410 | ||
1414 | mutex_lock(&priv->mutex); | 1411 | mutex_lock(&priv->mutex); |
1415 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); | 1412 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
1416 | ath9k_htc_ps_wakeup(priv); | 1413 | ath9k_htc_ps_wakeup(priv); |
1417 | 1414 | ||
1418 | switch (cmd) { | 1415 | switch (cmd) { |
@@ -1448,8 +1445,7 @@ static void ath9k_htc_set_bssid(struct ath9k_htc_priv *priv) | |||
1448 | struct ath_common *common = ath9k_hw_common(priv->ah); | 1445 | struct ath_common *common = ath9k_hw_common(priv->ah); |
1449 | 1446 | ||
1450 | ath9k_hw_write_associd(priv->ah); | 1447 | ath9k_hw_write_associd(priv->ah); |
1451 | ath_dbg(common, ATH_DBG_CONFIG, | 1448 | ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n", |
1452 | "BSSID: %pM aid: 0x%x\n", | ||
1453 | common->curbssid, common->curaid); | 1449 | common->curbssid, common->curaid); |
1454 | } | 1450 | } |
1455 | 1451 | ||
@@ -1487,7 +1483,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1487 | ath9k_htc_ps_wakeup(priv); | 1483 | ath9k_htc_ps_wakeup(priv); |
1488 | 1484 | ||
1489 | if (changed & BSS_CHANGED_ASSOC) { | 1485 | if (changed & BSS_CHANGED_ASSOC) { |
1490 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", | 1486 | ath_dbg(common, CONFIG, "BSS Changed ASSOC %d\n", |
1491 | bss_conf->assoc); | 1487 | bss_conf->assoc); |
1492 | 1488 | ||
1493 | bss_conf->assoc ? | 1489 | bss_conf->assoc ? |
@@ -1512,8 +1508,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1512 | } | 1508 | } |
1513 | 1509 | ||
1514 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon) { | 1510 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon) { |
1515 | ath_dbg(common, ATH_DBG_CONFIG, | 1511 | ath_dbg(common, CONFIG, "Beacon enabled for BSS: %pM\n", |
1516 | "Beacon enabled for BSS: %pM\n", bss_conf->bssid); | 1512 | bss_conf->bssid); |
1517 | ath9k_htc_set_tsfadjust(priv, vif); | 1513 | ath9k_htc_set_tsfadjust(priv, vif); |
1518 | priv->op_flags |= OP_ENABLE_BEACON; | 1514 | priv->op_flags |= OP_ENABLE_BEACON; |
1519 | ath9k_htc_beacon_config(priv, vif); | 1515 | ath9k_htc_beacon_config(priv, vif); |
@@ -1525,7 +1521,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1525 | * AP/IBSS interfaces. | 1521 | * AP/IBSS interfaces. |
1526 | */ | 1522 | */ |
1527 | if ((priv->num_ap_vif <= 1) || priv->num_ibss_vif) { | 1523 | if ((priv->num_ap_vif <= 1) || priv->num_ibss_vif) { |
1528 | ath_dbg(common, ATH_DBG_CONFIG, | 1524 | ath_dbg(common, CONFIG, |
1529 | "Beacon disabled for BSS: %pM\n", | 1525 | "Beacon disabled for BSS: %pM\n", |
1530 | bss_conf->bssid); | 1526 | bss_conf->bssid); |
1531 | priv->op_flags &= ~OP_ENABLE_BEACON; | 1527 | priv->op_flags &= ~OP_ENABLE_BEACON; |
@@ -1543,7 +1539,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw, | |||
1543 | (vif->type == NL80211_IFTYPE_AP)) { | 1539 | (vif->type == NL80211_IFTYPE_AP)) { |
1544 | priv->op_flags |= OP_TSF_RESET; | 1540 | priv->op_flags |= OP_TSF_RESET; |
1545 | } | 1541 | } |
1546 | ath_dbg(common, ATH_DBG_CONFIG, | 1542 | ath_dbg(common, CONFIG, |
1547 | "Beacon interval changed for BSS: %pM\n", | 1543 | "Beacon interval changed for BSS: %pM\n", |
1548 | bss_conf->bssid); | 1544 | bss_conf->bssid); |
1549 | ath9k_htc_beacon_config(priv, vif); | 1545 | ath9k_htc_beacon_config(priv, vif); |
@@ -1733,8 +1729,7 @@ static int ath9k_htc_set_bitrate_mask(struct ieee80211_hw *hw, | |||
1733 | goto out; | 1729 | goto out; |
1734 | } | 1730 | } |
1735 | 1731 | ||
1736 | ath_dbg(common, ATH_DBG_CONFIG, | 1732 | ath_dbg(common, CONFIG, "Set bitrate masks: 0x%x, 0x%x\n", |
1737 | "Set bitrate masks: 0x%x, 0x%x\n", | ||
1738 | mask->control[IEEE80211_BAND_2GHZ].legacy, | 1733 | mask->control[IEEE80211_BAND_2GHZ].legacy, |
1739 | mask->control[IEEE80211_BAND_5GHZ].legacy); | 1734 | mask->control[IEEE80211_BAND_5GHZ].legacy); |
1740 | out: | 1735 | out: |
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c index 2d81c700e201..3e40a6461512 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | |||
@@ -355,7 +355,7 @@ int ath9k_htc_tx_start(struct ath9k_htc_priv *priv, | |||
355 | vif_idx = avp->index; | 355 | vif_idx = avp->index; |
356 | } else { | 356 | } else { |
357 | if (!priv->ah->is_monitoring) { | 357 | if (!priv->ah->is_monitoring) { |
358 | ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT, | 358 | ath_dbg(ath9k_hw_common(priv->ah), XMIT, |
359 | "VIF is null, but no monitor interface !\n"); | 359 | "VIF is null, but no monitor interface !\n"); |
360 | return -EINVAL; | 360 | return -EINVAL; |
361 | } | 361 | } |
@@ -620,8 +620,7 @@ static struct sk_buff* ath9k_htc_tx_get_packet(struct ath9k_htc_priv *priv, | |||
620 | } | 620 | } |
621 | spin_unlock_irqrestore(&epid_queue->lock, flags); | 621 | spin_unlock_irqrestore(&epid_queue->lock, flags); |
622 | 622 | ||
623 | ath_dbg(common, ATH_DBG_XMIT, | 623 | ath_dbg(common, XMIT, "No matching packet for cookie: %d, epid: %d\n", |
624 | "No matching packet for cookie: %d, epid: %d\n", | ||
625 | txs->cookie, epid); | 624 | txs->cookie, epid); |
626 | 625 | ||
627 | return NULL; | 626 | return NULL; |
@@ -705,8 +704,7 @@ static inline bool check_packet(struct ath9k_htc_priv *priv, struct sk_buff *skb | |||
705 | if (time_after(jiffies, | 704 | if (time_after(jiffies, |
706 | tx_ctl->timestamp + | 705 | tx_ctl->timestamp + |
707 | msecs_to_jiffies(ATH9K_HTC_TX_TIMEOUT_INTERVAL))) { | 706 | msecs_to_jiffies(ATH9K_HTC_TX_TIMEOUT_INTERVAL))) { |
708 | ath_dbg(common, ATH_DBG_XMIT, | 707 | ath_dbg(common, XMIT, "Dropping a packet due to TX timeout\n"); |
709 | "Dropping a packet due to TX timeout\n"); | ||
710 | return true; | 708 | return true; |
711 | } | 709 | } |
712 | 710 | ||
@@ -753,7 +751,7 @@ void ath9k_htc_tx_cleanup_timer(unsigned long data) | |||
753 | 751 | ||
754 | skb = ath9k_htc_tx_get_packet(priv, &event->txs); | 752 | skb = ath9k_htc_tx_get_packet(priv, &event->txs); |
755 | if (skb) { | 753 | if (skb) { |
756 | ath_dbg(common, ATH_DBG_XMIT, | 754 | ath_dbg(common, XMIT, |
757 | "Found packet for cookie: %d, epid: %d\n", | 755 | "Found packet for cookie: %d, epid: %d\n", |
758 | event->txs.cookie, | 756 | event->txs.cookie, |
759 | MS(event->txs.ts_rate, ATH9K_HTC_TXSTAT_EPID)); | 757 | MS(event->txs.ts_rate, ATH9K_HTC_TXSTAT_EPID)); |
@@ -1167,8 +1165,7 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb, | |||
1167 | spin_unlock(&priv->rx.rxbuflock); | 1165 | spin_unlock(&priv->rx.rxbuflock); |
1168 | 1166 | ||
1169 | if (rxbuf == NULL) { | 1167 | if (rxbuf == NULL) { |
1170 | ath_dbg(common, ATH_DBG_ANY, | 1168 | ath_dbg(common, ANY, "No free RX buffer\n"); |
1171 | "No free RX buffer\n"); | ||
1172 | goto err; | 1169 | goto err; |
1173 | } | 1170 | } |
1174 | 1171 | ||
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 8cda9a1513a7..0fde03104ef0 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -133,7 +133,7 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) | |||
133 | udelay(AH_TIME_QUANTUM); | 133 | udelay(AH_TIME_QUANTUM); |
134 | } | 134 | } |
135 | 135 | ||
136 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, | 136 | ath_dbg(ath9k_hw_common(ah), ANY, |
137 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | 137 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
138 | timeout, reg, REG_READ(ah, reg), mask, val); | 138 | timeout, reg, REG_READ(ah, reg), mask, val); |
139 | 139 | ||
@@ -491,8 +491,7 @@ static int ath9k_hw_post_init(struct ath_hw *ah) | |||
491 | if (ecode != 0) | 491 | if (ecode != 0) |
492 | return ecode; | 492 | return ecode; |
493 | 493 | ||
494 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, | 494 | ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", |
495 | "Eeprom VER: %d, REV: %d\n", | ||
496 | ah->eep_ops->get_eeprom_ver(ah), | 495 | ah->eep_ops->get_eeprom_ver(ah), |
497 | ah->eep_ops->get_eeprom_rev(ah)); | 496 | ah->eep_ops->get_eeprom_rev(ah)); |
498 | 497 | ||
@@ -567,7 +566,7 @@ static int __ath9k_hw_init(struct ath_hw *ah) | |||
567 | } | 566 | } |
568 | } | 567 | } |
569 | 568 | ||
570 | ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", | 569 | ath_dbg(common, RESET, "serialize_regmode is %d\n", |
571 | ah->config.serialize_regmode); | 570 | ah->config.serialize_regmode); |
572 | 571 | ||
573 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | 572 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
@@ -958,8 +957,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |||
958 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) | 957 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
959 | { | 958 | { |
960 | if (tu > 0xFFFF) { | 959 | if (tu > 0xFFFF) { |
961 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, | 960 | ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", |
962 | "bad global tx timeout %u\n", tu); | 961 | tu); |
963 | ah->globaltxtimeout = (u32) -1; | 962 | ah->globaltxtimeout = (u32) -1; |
964 | return false; | 963 | return false; |
965 | } else { | 964 | } else { |
@@ -980,7 +979,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah) | |||
980 | int rx_lat = 0, tx_lat = 0, eifs = 0; | 979 | int rx_lat = 0, tx_lat = 0, eifs = 0; |
981 | u32 reg; | 980 | u32 reg; |
982 | 981 | ||
983 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", | 982 | ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", |
984 | ah->misc_mode); | 983 | ah->misc_mode); |
985 | 984 | ||
986 | if (!chan) | 985 | if (!chan) |
@@ -1275,7 +1274,7 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) | |||
1275 | (npend || type == ATH9K_RESET_COLD)) { | 1274 | (npend || type == ATH9K_RESET_COLD)) { |
1276 | int reset_err = 0; | 1275 | int reset_err = 0; |
1277 | 1276 | ||
1278 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, | 1277 | ath_dbg(ath9k_hw_common(ah), RESET, |
1279 | "reset MAC via external reset\n"); | 1278 | "reset MAC via external reset\n"); |
1280 | 1279 | ||
1281 | reset_err = ah->external_reset(); | 1280 | reset_err = ah->external_reset(); |
@@ -1298,8 +1297,7 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) | |||
1298 | 1297 | ||
1299 | REG_WRITE(ah, AR_RTC_RC, 0); | 1298 | REG_WRITE(ah, AR_RTC_RC, 0); |
1300 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { | 1299 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
1301 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, | 1300 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); |
1302 | "RTC stuck in MAC reset\n"); | ||
1303 | return false; | 1301 | return false; |
1304 | } | 1302 | } |
1305 | 1303 | ||
@@ -1344,8 +1342,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) | |||
1344 | AR_RTC_STATUS_M, | 1342 | AR_RTC_STATUS_M, |
1345 | AR_RTC_STATUS_ON, | 1343 | AR_RTC_STATUS_ON, |
1346 | AH_WAIT_TIMEOUT)) { | 1344 | AH_WAIT_TIMEOUT)) { |
1347 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, | 1345 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); |
1348 | "RTC not waking up\n"); | ||
1349 | return false; | 1346 | return false; |
1350 | } | 1347 | } |
1351 | 1348 | ||
@@ -1418,7 +1415,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, | |||
1418 | 1415 | ||
1419 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | 1416 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
1420 | if (ath9k_hw_numtxpending(ah, qnum)) { | 1417 | if (ath9k_hw_numtxpending(ah, qnum)) { |
1421 | ath_dbg(common, ATH_DBG_QUEUE, | 1418 | ath_dbg(common, QUEUE, |
1422 | "Transmit frames pending on queue %d\n", qnum); | 1419 | "Transmit frames pending on queue %d\n", qnum); |
1423 | return false; | 1420 | return false; |
1424 | } | 1421 | } |
@@ -1536,7 +1533,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1536 | if (mci_hw->bt_state == MCI_BT_CAL_START) { | 1533 | if (mci_hw->bt_state == MCI_BT_CAL_START) { |
1537 | u32 payload[4] = {0, 0, 0, 0}; | 1534 | u32 payload[4] = {0, 0, 0, 0}; |
1538 | 1535 | ||
1539 | ath_dbg(common, ATH_DBG_MCI, "MCI stop rx for BT CAL"); | 1536 | ath_dbg(common, MCI, "MCI stop rx for BT CAL\n"); |
1540 | 1537 | ||
1541 | mci_hw->bt_state = MCI_BT_CAL; | 1538 | mci_hw->bt_state = MCI_BT_CAL; |
1542 | 1539 | ||
@@ -1548,23 +1545,22 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1548 | 1545 | ||
1549 | ar9003_mci_disable_interrupt(ah); | 1546 | ar9003_mci_disable_interrupt(ah); |
1550 | 1547 | ||
1551 | ath_dbg(common, ATH_DBG_MCI, "send WLAN_CAL_GRANT"); | 1548 | ath_dbg(common, MCI, "send WLAN_CAL_GRANT\n"); |
1552 | MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); | 1549 | MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_GRANT); |
1553 | ar9003_mci_send_message(ah, MCI_GPM, 0, payload, | 1550 | ar9003_mci_send_message(ah, MCI_GPM, 0, payload, |
1554 | 16, true, false); | 1551 | 16, true, false); |
1555 | 1552 | ||
1556 | ath_dbg(common, ATH_DBG_MCI, "\nMCI BT is calibrating"); | 1553 | ath_dbg(common, MCI, "\nMCI BT is calibrating\n"); |
1557 | 1554 | ||
1558 | /* Wait BT calibration to be completed for 25ms */ | 1555 | /* Wait BT calibration to be completed for 25ms */ |
1559 | 1556 | ||
1560 | if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, | 1557 | if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, |
1561 | 0, 25000)) | 1558 | 0, 25000)) |
1562 | ath_dbg(common, ATH_DBG_MCI, | 1559 | ath_dbg(common, MCI, |
1563 | "MCI got BT_CAL_DONE\n"); | 1560 | "MCI got BT_CAL_DONE\n"); |
1564 | else | 1561 | else |
1565 | ath_dbg(common, ATH_DBG_MCI, | 1562 | ath_dbg(common, MCI, |
1566 | "MCI ### BT cal takes to long, force" | 1563 | "MCI ### BT cal takes to long, force bt_state to be bt_awake\n"); |
1567 | "bt_state to be bt_awake\n"); | ||
1568 | mci_hw->bt_state = MCI_BT_AWAKE; | 1564 | mci_hw->bt_state = MCI_BT_AWAKE; |
1569 | /* MCI FIX: enable mci interrupt here */ | 1565 | /* MCI FIX: enable mci interrupt here */ |
1570 | ar9003_mci_enable_interrupt(ah); | 1566 | ar9003_mci_enable_interrupt(ah); |
@@ -1825,14 +1821,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1825 | * message exchanges again and recal. | 1821 | * message exchanges again and recal. |
1826 | */ | 1822 | */ |
1827 | 1823 | ||
1828 | ath_dbg(common, ATH_DBG_MCI, "MCI BT wakes up" | 1824 | ath_dbg(common, MCI, |
1829 | "during WLAN calibration\n"); | 1825 | "MCI BT wakes up during WLAN calibration\n"); |
1830 | 1826 | ||
1831 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, | 1827 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, |
1832 | AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | | 1828 | AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET | |
1833 | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); | 1829 | AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE); |
1834 | ath_dbg(common, ATH_DBG_MCI, "MCI send" | 1830 | ath_dbg(common, MCI, "MCI send REMOTE_RESET\n"); |
1835 | "REMOTE_RESET\n"); | ||
1836 | ar9003_mci_remote_reset(ah, true); | 1831 | ar9003_mci_remote_reset(ah, true); |
1837 | ar9003_mci_send_sys_waking(ah, true); | 1832 | ar9003_mci_send_sys_waking(ah, true); |
1838 | udelay(1); | 1833 | udelay(1); |
@@ -1841,7 +1836,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1841 | 1836 | ||
1842 | mci_hw->bt_state = MCI_BT_AWAKE; | 1837 | mci_hw->bt_state = MCI_BT_AWAKE; |
1843 | 1838 | ||
1844 | ath_dbg(common, ATH_DBG_MCI, "MCI re-cal\n"); | 1839 | ath_dbg(common, MCI, "MCI re-cal\n"); |
1845 | 1840 | ||
1846 | if (caldata) { | 1841 | if (caldata) { |
1847 | caldata->done_txiqcal_once = false; | 1842 | caldata->done_txiqcal_once = false; |
@@ -1871,14 +1866,14 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, | |||
1871 | u32 mask; | 1866 | u32 mask; |
1872 | mask = REG_READ(ah, AR_CFG); | 1867 | mask = REG_READ(ah, AR_CFG); |
1873 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | 1868 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
1874 | ath_dbg(common, ATH_DBG_RESET, | 1869 | ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", |
1875 | "CFG Byte Swap Set 0x%x\n", mask); | 1870 | mask); |
1876 | } else { | 1871 | } else { |
1877 | mask = | 1872 | mask = |
1878 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | 1873 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
1879 | REG_WRITE(ah, AR_CFG, mask); | 1874 | REG_WRITE(ah, AR_CFG, mask); |
1880 | ath_dbg(common, ATH_DBG_RESET, | 1875 | ath_dbg(common, RESET, "Setting CFG 0x%x\n", |
1881 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); | 1876 | REG_READ(ah, AR_CFG)); |
1882 | } | 1877 | } |
1883 | } else { | 1878 | } else { |
1884 | if (common->bus_ops->ath_bus_type == ATH_USB) { | 1879 | if (common->bus_ops->ath_bus_type == ATH_USB) { |
@@ -2090,7 +2085,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) | |||
2090 | if (ah->power_mode == mode) | 2085 | if (ah->power_mode == mode) |
2091 | return status; | 2086 | return status; |
2092 | 2087 | ||
2093 | ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", | 2088 | ath_dbg(common, RESET, "%s -> %s\n", |
2094 | modes[ah->power_mode], modes[mode]); | 2089 | modes[ah->power_mode], modes[mode]); |
2095 | 2090 | ||
2096 | switch (mode) { | 2091 | switch (mode) { |
@@ -2107,8 +2102,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) | |||
2107 | if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) && | 2102 | if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) && |
2108 | (mci->bt_state != MCI_BT_SLEEP) && | 2103 | (mci->bt_state != MCI_BT_SLEEP) && |
2109 | !mci->halted_bt_gpm) { | 2104 | !mci->halted_bt_gpm) { |
2110 | ath_dbg(common, ATH_DBG_MCI, "MCI halt BT GPM" | 2105 | ath_dbg(common, MCI, |
2111 | "(full_sleep)"); | 2106 | "MCI halt BT GPM (full_sleep)\n"); |
2112 | ar9003_mci_send_coex_halt_bt_gpm(ah, | 2107 | ar9003_mci_send_coex_halt_bt_gpm(ah, |
2113 | true, true); | 2108 | true, true); |
2114 | } | 2109 | } |
@@ -2174,9 +2169,8 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) | |||
2174 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | 2169 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; |
2175 | break; | 2170 | break; |
2176 | default: | 2171 | default: |
2177 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, | 2172 | ath_dbg(ath9k_hw_common(ah), BEACON, |
2178 | "%s: unsupported opmode: %d\n", | 2173 | "%s: unsupported opmode: %d\n", __func__, ah->opmode); |
2179 | __func__, ah->opmode); | ||
2180 | return; | 2174 | return; |
2181 | break; | 2175 | break; |
2182 | } | 2176 | } |
@@ -2227,10 +2221,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |||
2227 | else | 2221 | else |
2228 | nextTbtt = bs->bs_nexttbtt; | 2222 | nextTbtt = bs->bs_nexttbtt; |
2229 | 2223 | ||
2230 | ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); | 2224 | ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
2231 | ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | 2225 | ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); |
2232 | ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | 2226 | ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); |
2233 | ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | 2227 | ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); |
2234 | 2228 | ||
2235 | ENABLE_REGWRITE_BUFFER(ah); | 2229 | ENABLE_REGWRITE_BUFFER(ah); |
2236 | 2230 | ||
@@ -2322,8 +2316,8 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
2322 | regulatory->current_rd += 5; | 2316 | regulatory->current_rd += 5; |
2323 | else if (regulatory->current_rd == 0x41) | 2317 | else if (regulatory->current_rd == 0x41) |
2324 | regulatory->current_rd = 0x43; | 2318 | regulatory->current_rd = 0x43; |
2325 | ath_dbg(common, ATH_DBG_REGULATORY, | 2319 | ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", |
2326 | "regdomain mapped to 0x%x\n", regulatory->current_rd); | 2320 | regulatory->current_rd); |
2327 | } | 2321 | } |
2328 | 2322 | ||
2329 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); | 2323 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
@@ -2848,7 +2842,7 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah) | |||
2848 | { | 2842 | { |
2849 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, | 2843 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
2850 | AH_TSF_WRITE_TIMEOUT)) | 2844 | AH_TSF_WRITE_TIMEOUT)) |
2851 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, | 2845 | ath_dbg(ath9k_hw_common(ah), RESET, |
2852 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); | 2846 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
2853 | 2847 | ||
2854 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); | 2848 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
@@ -2973,7 +2967,7 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah, | |||
2973 | 2967 | ||
2974 | timer_next = tsf + trig_timeout; | 2968 | timer_next = tsf + trig_timeout; |
2975 | 2969 | ||
2976 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, | 2970 | ath_dbg(ath9k_hw_common(ah), HWTIMER, |
2977 | "current tsf %x period %x timer_next %x\n", | 2971 | "current tsf %x period %x timer_next %x\n", |
2978 | tsf, timer_period, timer_next); | 2972 | tsf, timer_period, timer_next); |
2979 | 2973 | ||
@@ -3062,8 +3056,8 @@ void ath_gen_timer_isr(struct ath_hw *ah) | |||
3062 | index = rightmost_index(timer_table, &thresh_mask); | 3056 | index = rightmost_index(timer_table, &thresh_mask); |
3063 | timer = timer_table->timers[index]; | 3057 | timer = timer_table->timers[index]; |
3064 | BUG_ON(!timer); | 3058 | BUG_ON(!timer); |
3065 | ath_dbg(common, ATH_DBG_HWTIMER, | 3059 | ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", |
3066 | "TSF overflow for Gen timer %d\n", index); | 3060 | index); |
3067 | timer->overflow(timer->arg); | 3061 | timer->overflow(timer->arg); |
3068 | } | 3062 | } |
3069 | 3063 | ||
@@ -3071,7 +3065,7 @@ void ath_gen_timer_isr(struct ath_hw *ah) | |||
3071 | index = rightmost_index(timer_table, &trigger_mask); | 3065 | index = rightmost_index(timer_table, &trigger_mask); |
3072 | timer = timer_table->timers[index]; | 3066 | timer = timer_table->timers[index]; |
3073 | BUG_ON(!timer); | 3067 | BUG_ON(!timer); |
3074 | ath_dbg(common, ATH_DBG_HWTIMER, | 3068 | ath_dbg(common, HWTIMER, |
3075 | "Gen timer[%d] trigger\n", index); | 3069 | "Gen timer[%d] trigger\n", index); |
3076 | timer->trigger(timer->arg); | 3070 | timer->trigger(timer->arg); |
3077 | } | 3071 | } |
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index c5df98139c4d..58ce67f976f9 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c | |||
@@ -276,8 +276,7 @@ static void setup_ht_cap(struct ath_softc *sc, | |||
276 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); | 276 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
277 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | 277 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); |
278 | 278 | ||
279 | ath_dbg(common, ATH_DBG_CONFIG, | 279 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
280 | "TX streams %d, RX streams: %d\n", | ||
281 | tx_streams, rx_streams); | 280 | tx_streams, rx_streams); |
282 | 281 | ||
283 | if (tx_streams != rx_streams) { | 282 | if (tx_streams != rx_streams) { |
@@ -329,7 +328,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |||
329 | struct ath_buf *bf; | 328 | struct ath_buf *bf; |
330 | int i, bsize, error, desc_len; | 329 | int i, bsize, error, desc_len; |
331 | 330 | ||
332 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", | 331 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
333 | name, nbuf, ndesc); | 332 | name, nbuf, ndesc); |
334 | 333 | ||
335 | INIT_LIST_HEAD(head); | 334 | INIT_LIST_HEAD(head); |
@@ -375,7 +374,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |||
375 | goto fail; | 374 | goto fail; |
376 | } | 375 | } |
377 | ds = (u8 *) dd->dd_desc; | 376 | ds = (u8 *) dd->dd_desc; |
378 | ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", | 377 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
379 | name, ds, (u32) dd->dd_desc_len, | 378 | name, ds, (u32) dd->dd_desc_len, |
380 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | 379 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); |
381 | 380 | ||
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c index 0e4fbb3bea33..fd3f19c2e550 100644 --- a/drivers/net/wireless/ath/ath9k/mac.c +++ b/drivers/net/wireless/ath/ath9k/mac.c | |||
@@ -21,7 +21,7 @@ | |||
21 | static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, | 21 | static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, |
22 | struct ath9k_tx_queue_info *qi) | 22 | struct ath9k_tx_queue_info *qi) |
23 | { | 23 | { |
24 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT, | 24 | ath_dbg(ath9k_hw_common(ah), INTERRUPT, |
25 | "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", | 25 | "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", |
26 | ah->txok_interrupt_mask, ah->txerr_interrupt_mask, | 26 | ah->txok_interrupt_mask, ah->txerr_interrupt_mask, |
27 | ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, | 27 | ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, |
@@ -57,8 +57,7 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf); | |||
57 | 57 | ||
58 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q) | 58 | void ath9k_hw_txstart(struct ath_hw *ah, u32 q) |
59 | { | 59 | { |
60 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE, | 60 | ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); |
61 | "Enable TXE on queue: %u\n", q); | ||
62 | REG_WRITE(ah, AR_Q_TXE, 1 << q); | 61 | REG_WRITE(ah, AR_Q_TXE, 1 << q); |
63 | } | 62 | } |
64 | EXPORT_SYMBOL(ath9k_hw_txstart); | 63 | EXPORT_SYMBOL(ath9k_hw_txstart); |
@@ -202,12 +201,12 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, | |||
202 | 201 | ||
203 | qi = &ah->txq[q]; | 202 | qi = &ah->txq[q]; |
204 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 203 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
205 | ath_dbg(common, ATH_DBG_QUEUE, | 204 | ath_dbg(common, QUEUE, |
206 | "Set TXQ properties, inactive queue: %u\n", q); | 205 | "Set TXQ properties, inactive queue: %u\n", q); |
207 | return false; | 206 | return false; |
208 | } | 207 | } |
209 | 208 | ||
210 | ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); | 209 | ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q); |
211 | 210 | ||
212 | qi->tqi_ver = qinfo->tqi_ver; | 211 | qi->tqi_ver = qinfo->tqi_ver; |
213 | qi->tqi_subtype = qinfo->tqi_subtype; | 212 | qi->tqi_subtype = qinfo->tqi_subtype; |
@@ -266,7 +265,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, | |||
266 | 265 | ||
267 | qi = &ah->txq[q]; | 266 | qi = &ah->txq[q]; |
268 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 267 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
269 | ath_dbg(common, ATH_DBG_QUEUE, | 268 | ath_dbg(common, QUEUE, |
270 | "Get TXQ properties, inactive queue: %u\n", q); | 269 | "Get TXQ properties, inactive queue: %u\n", q); |
271 | return false; | 270 | return false; |
272 | } | 271 | } |
@@ -325,7 +324,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, | |||
325 | return -1; | 324 | return -1; |
326 | } | 325 | } |
327 | 326 | ||
328 | ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); | 327 | ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q); |
329 | 328 | ||
330 | qi = &ah->txq[q]; | 329 | qi = &ah->txq[q]; |
331 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { | 330 | if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { |
@@ -348,12 +347,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) | |||
348 | 347 | ||
349 | qi = &ah->txq[q]; | 348 | qi = &ah->txq[q]; |
350 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 349 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
351 | ath_dbg(common, ATH_DBG_QUEUE, | 350 | ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); |
352 | "Release TXQ, inactive queue: %u\n", q); | ||
353 | return false; | 351 | return false; |
354 | } | 352 | } |
355 | 353 | ||
356 | ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); | 354 | ath_dbg(common, QUEUE, "Release TX queue: %u\n", q); |
357 | 355 | ||
358 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; | 356 | qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; |
359 | ah->txok_interrupt_mask &= ~(1 << q); | 357 | ah->txok_interrupt_mask &= ~(1 << q); |
@@ -376,12 +374,11 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) | |||
376 | 374 | ||
377 | qi = &ah->txq[q]; | 375 | qi = &ah->txq[q]; |
378 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { | 376 | if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
379 | ath_dbg(common, ATH_DBG_QUEUE, | 377 | ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); |
380 | "Reset TXQ, inactive queue: %u\n", q); | ||
381 | return true; | 378 | return true; |
382 | } | 379 | } |
383 | 380 | ||
384 | ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); | 381 | ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q); |
385 | 382 | ||
386 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { | 383 | if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { |
387 | if (chan && IS_CHAN_B(chan)) | 384 | if (chan && IS_CHAN_B(chan)) |
@@ -784,7 +781,7 @@ void ath9k_hw_disable_interrupts(struct ath_hw *ah) | |||
784 | else | 781 | else |
785 | atomic_dec(&ah->intr_ref_cnt); | 782 | atomic_dec(&ah->intr_ref_cnt); |
786 | 783 | ||
787 | ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n"); | 784 | ath_dbg(common, INTERRUPT, "disable IER\n"); |
788 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); | 785 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
789 | (void) REG_READ(ah, AR_IER); | 786 | (void) REG_READ(ah, AR_IER); |
790 | if (!AR_SREV_9100(ah)) { | 787 | if (!AR_SREV_9100(ah)) { |
@@ -807,8 +804,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah) | |||
807 | return; | 804 | return; |
808 | 805 | ||
809 | if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { | 806 | if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { |
810 | ath_dbg(common, ATH_DBG_INTERRUPT, | 807 | ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n", |
811 | "Do not enable IER ref count %d\n", | ||
812 | atomic_read(&ah->intr_ref_cnt)); | 808 | atomic_read(&ah->intr_ref_cnt)); |
813 | return; | 809 | return; |
814 | } | 810 | } |
@@ -821,7 +817,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah) | |||
821 | if (ah->imask & ATH9K_INT_MCI) | 817 | if (ah->imask & ATH9K_INT_MCI) |
822 | async_mask |= AR_INTR_ASYNC_MASK_MCI; | 818 | async_mask |= AR_INTR_ASYNC_MASK_MCI; |
823 | 819 | ||
824 | ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n"); | 820 | ath_dbg(common, INTERRUPT, "enable IER\n"); |
825 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); | 821 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
826 | if (!AR_SREV_9100(ah)) { | 822 | if (!AR_SREV_9100(ah)) { |
827 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); | 823 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); |
@@ -830,7 +826,7 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah) | |||
830 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); | 826 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
831 | REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); | 827 | REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); |
832 | } | 828 | } |
833 | ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", | 829 | ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
834 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | 830 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |
835 | } | 831 | } |
836 | EXPORT_SYMBOL(ath9k_hw_enable_interrupts); | 832 | EXPORT_SYMBOL(ath9k_hw_enable_interrupts); |
@@ -845,7 +841,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah) | |||
845 | if (!(ints & ATH9K_INT_GLOBAL)) | 841 | if (!(ints & ATH9K_INT_GLOBAL)) |
846 | ath9k_hw_disable_interrupts(ah); | 842 | ath9k_hw_disable_interrupts(ah); |
847 | 843 | ||
848 | ath_dbg(common, ATH_DBG_INTERRUPT, "New interrupt mask 0x%x\n", ints); | 844 | ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints); |
849 | 845 | ||
850 | mask = ints & ATH9K_INT_COMMON; | 846 | mask = ints & ATH9K_INT_COMMON; |
851 | mask2 = 0; | 847 | mask2 = 0; |
@@ -908,7 +904,7 @@ void ath9k_hw_set_interrupts(struct ath_hw *ah) | |||
908 | mask2 |= AR_IMR_S2_CST; | 904 | mask2 |= AR_IMR_S2_CST; |
909 | } | 905 | } |
910 | 906 | ||
911 | ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); | 907 | ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask); |
912 | REG_WRITE(ah, AR_IMR, mask); | 908 | REG_WRITE(ah, AR_IMR, mask); |
913 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | | 909 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
914 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | | 910 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | |
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index 7fbc4bdd4efe..eb06e4fdf5b2 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c | |||
@@ -339,8 +339,7 @@ static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |||
339 | if (!ath_prepare_reset(sc, retry_tx, flush)) | 339 | if (!ath_prepare_reset(sc, retry_tx, flush)) |
340 | fastcc = false; | 340 | fastcc = false; |
341 | 341 | ||
342 | ath_dbg(common, ATH_DBG_CONFIG, | 342 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
343 | "Reset to %u MHz, HT40: %d fastcc: %d\n", | ||
344 | hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS | | 343 | hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS | |
345 | CHANNEL_HT40PLUS)), | 344 | CHANNEL_HT40PLUS)), |
346 | fastcc); | 345 | fastcc); |
@@ -429,7 +428,7 @@ static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int | |||
429 | txctl.paprd = BIT(chain); | 428 | txctl.paprd = BIT(chain); |
430 | 429 | ||
431 | if (ath_tx_start(hw, skb, &txctl) != 0) { | 430 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
432 | ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n"); | 431 | ath_dbg(common, CALIBRATE, "PAPRD TX failed\n"); |
433 | dev_kfree_skb_any(skb); | 432 | dev_kfree_skb_any(skb); |
434 | return false; | 433 | return false; |
435 | } | 434 | } |
@@ -438,7 +437,7 @@ static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int | |||
438 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | 437 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
439 | 438 | ||
440 | if (!time_left) | 439 | if (!time_left) |
441 | ath_dbg(common, ATH_DBG_CALIBRATE, | 440 | ath_dbg(common, CALIBRATE, |
442 | "Timeout waiting for paprd training on TX chain %d\n", | 441 | "Timeout waiting for paprd training on TX chain %d\n", |
443 | chain); | 442 | chain); |
444 | 443 | ||
@@ -487,27 +486,27 @@ void ath_paprd_calibrate(struct work_struct *work) | |||
487 | 486 | ||
488 | chain_ok = 0; | 487 | chain_ok = 0; |
489 | 488 | ||
490 | ath_dbg(common, ATH_DBG_CALIBRATE, | 489 | ath_dbg(common, CALIBRATE, |
491 | "Sending PAPRD frame for thermal measurement " | 490 | "Sending PAPRD frame for thermal measurement on chain %d\n", |
492 | "on chain %d\n", chain); | 491 | chain); |
493 | if (!ath_paprd_send_frame(sc, skb, chain)) | 492 | if (!ath_paprd_send_frame(sc, skb, chain)) |
494 | goto fail_paprd; | 493 | goto fail_paprd; |
495 | 494 | ||
496 | ar9003_paprd_setup_gain_table(ah, chain); | 495 | ar9003_paprd_setup_gain_table(ah, chain); |
497 | 496 | ||
498 | ath_dbg(common, ATH_DBG_CALIBRATE, | 497 | ath_dbg(common, CALIBRATE, |
499 | "Sending PAPRD training frame on chain %d\n", chain); | 498 | "Sending PAPRD training frame on chain %d\n", chain); |
500 | if (!ath_paprd_send_frame(sc, skb, chain)) | 499 | if (!ath_paprd_send_frame(sc, skb, chain)) |
501 | goto fail_paprd; | 500 | goto fail_paprd; |
502 | 501 | ||
503 | if (!ar9003_paprd_is_done(ah)) { | 502 | if (!ar9003_paprd_is_done(ah)) { |
504 | ath_dbg(common, ATH_DBG_CALIBRATE, | 503 | ath_dbg(common, CALIBRATE, |
505 | "PAPRD not yet done on chain %d\n", chain); | 504 | "PAPRD not yet done on chain %d\n", chain); |
506 | break; | 505 | break; |
507 | } | 506 | } |
508 | 507 | ||
509 | if (ar9003_paprd_create_curve(ah, caldata, chain)) { | 508 | if (ar9003_paprd_create_curve(ah, caldata, chain)) { |
510 | ath_dbg(common, ATH_DBG_CALIBRATE, | 509 | ath_dbg(common, CALIBRATE, |
511 | "PAPRD create curve failed on chain %d\n", | 510 | "PAPRD create curve failed on chain %d\n", |
512 | chain); | 511 | chain); |
513 | break; | 512 | break; |
@@ -604,8 +603,9 @@ void ath_ani_calibrate(unsigned long data) | |||
604 | ah->rxchainmask, longcal); | 603 | ah->rxchainmask, longcal); |
605 | } | 604 | } |
606 | 605 | ||
607 | ath_dbg(common, ATH_DBG_ANI, | 606 | ath_dbg(common, ANI, |
608 | "Calibration @%lu finished: %s %s %s, caldone: %s\n", jiffies, | 607 | "Calibration @%lu finished: %s %s %s, caldone: %s\n", |
608 | jiffies, | ||
609 | longcal ? "long" : "", shortcal ? "short" : "", | 609 | longcal ? "long" : "", shortcal ? "short" : "", |
610 | aniflag ? "ani" : "", common->ani.caldone ? "true" : "false"); | 610 | aniflag ? "ani" : "", common->ani.caldone ? "true" : "false"); |
611 | 611 | ||
@@ -715,8 +715,7 @@ void ath9k_tasklet(unsigned long data) | |||
715 | * TSF sync does not look correct; remain awake to sync with | 715 | * TSF sync does not look correct; remain awake to sync with |
716 | * the next Beacon. | 716 | * the next Beacon. |
717 | */ | 717 | */ |
718 | ath_dbg(common, ATH_DBG_PS, | 718 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
719 | "TSFOOR - Sync with next Beacon\n"); | ||
720 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; | 719 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
721 | } | 720 | } |
722 | 721 | ||
@@ -936,8 +935,8 @@ void ath_hw_check(struct work_struct *work) | |||
936 | busy = ath_update_survey_stats(sc); | 935 | busy = ath_update_survey_stats(sc); |
937 | spin_unlock_irqrestore(&common->cc_lock, flags); | 936 | spin_unlock_irqrestore(&common->cc_lock, flags); |
938 | 937 | ||
939 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " | 938 | ath_dbg(common, RESET, "Possible baseband hang, busy=%d (try %d)\n", |
940 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | 939 | busy, sc->hw_busy_count + 1); |
941 | if (busy >= 99) { | 940 | if (busy >= 99) { |
942 | if (++sc->hw_busy_count >= 3) { | 941 | if (++sc->hw_busy_count >= 3) { |
943 | RESET_STAT_INC(sc, RESET_TYPE_BB_HANG); | 942 | RESET_STAT_INC(sc, RESET_TYPE_BB_HANG); |
@@ -960,8 +959,7 @@ static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) | |||
960 | count++; | 959 | count++; |
961 | if (count == 3) { | 960 | if (count == 3) { |
962 | /* Rx is hung for more than 500ms. Reset it */ | 961 | /* Rx is hung for more than 500ms. Reset it */ |
963 | ath_dbg(common, ATH_DBG_RESET, | 962 | ath_dbg(common, RESET, "Possible RX hang, resetting\n"); |
964 | "Possible RX hang, resetting"); | ||
965 | RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG); | 963 | RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG); |
966 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | 964 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
967 | count = 0; | 965 | count = 0; |
@@ -1001,7 +999,7 @@ static int ath9k_start(struct ieee80211_hw *hw) | |||
1001 | struct ath9k_channel *init_channel; | 999 | struct ath9k_channel *init_channel; |
1002 | int r; | 1000 | int r; |
1003 | 1001 | ||
1004 | ath_dbg(common, ATH_DBG_CONFIG, | 1002 | ath_dbg(common, CONFIG, |
1005 | "Starting driver with initial channel: %d MHz\n", | 1003 | "Starting driver with initial channel: %d MHz\n", |
1006 | curchan->center_freq); | 1004 | curchan->center_freq); |
1007 | 1005 | ||
@@ -1120,7 +1118,7 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
1120 | if (ieee80211_is_data(hdr->frame_control) && | 1118 | if (ieee80211_is_data(hdr->frame_control) && |
1121 | !ieee80211_is_nullfunc(hdr->frame_control) && | 1119 | !ieee80211_is_nullfunc(hdr->frame_control) && |
1122 | !ieee80211_has_pm(hdr->frame_control)) { | 1120 | !ieee80211_has_pm(hdr->frame_control)) { |
1123 | ath_dbg(common, ATH_DBG_PS, | 1121 | ath_dbg(common, PS, |
1124 | "Add PM=1 for a TX frame while in PS mode\n"); | 1122 | "Add PM=1 for a TX frame while in PS mode\n"); |
1125 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | 1123 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1126 | } | 1124 | } |
@@ -1143,12 +1141,11 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
1143 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) | 1141 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1144 | ath9k_hw_setrxabort(sc->sc_ah, 0); | 1142 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1145 | if (ieee80211_is_pspoll(hdr->frame_control)) { | 1143 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
1146 | ath_dbg(common, ATH_DBG_PS, | 1144 | ath_dbg(common, PS, |
1147 | "Sending PS-Poll to pick a buffered frame\n"); | 1145 | "Sending PS-Poll to pick a buffered frame\n"); |
1148 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; | 1146 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
1149 | } else { | 1147 | } else { |
1150 | ath_dbg(common, ATH_DBG_PS, | 1148 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1151 | "Wake up to complete TX\n"); | ||
1152 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; | 1149 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
1153 | } | 1150 | } |
1154 | /* | 1151 | /* |
@@ -1162,10 +1159,10 @@ static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
1162 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | 1159 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
1163 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; | 1160 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
1164 | 1161 | ||
1165 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); | 1162 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
1166 | 1163 | ||
1167 | if (ath_tx_start(hw, skb, &txctl) != 0) { | 1164 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
1168 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); | 1165 | ath_dbg(common, XMIT, "TX failed\n"); |
1169 | goto exit; | 1166 | goto exit; |
1170 | } | 1167 | } |
1171 | 1168 | ||
@@ -1186,7 +1183,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) | |||
1186 | ath_cancel_work(sc); | 1183 | ath_cancel_work(sc); |
1187 | 1184 | ||
1188 | if (sc->sc_flags & SC_OP_INVALID) { | 1185 | if (sc->sc_flags & SC_OP_INVALID) { |
1189 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | 1186 | ath_dbg(common, ANY, "Device not present\n"); |
1190 | mutex_unlock(&sc->mutex); | 1187 | mutex_unlock(&sc->mutex); |
1191 | return; | 1188 | return; |
1192 | } | 1189 | } |
@@ -1252,7 +1249,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) | |||
1252 | 1249 | ||
1253 | mutex_unlock(&sc->mutex); | 1250 | mutex_unlock(&sc->mutex); |
1254 | 1251 | ||
1255 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); | 1252 | ath_dbg(common, CONFIG, "Driver halt\n"); |
1256 | } | 1253 | } |
1257 | 1254 | ||
1258 | bool ath9k_uses_beacons(int type) | 1255 | bool ath9k_uses_beacons(int type) |
@@ -1467,8 +1464,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, | |||
1467 | goto out; | 1464 | goto out; |
1468 | } | 1465 | } |
1469 | 1466 | ||
1470 | ath_dbg(common, ATH_DBG_CONFIG, | 1467 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
1471 | "Attach a VIF of type: %d\n", vif->type); | ||
1472 | 1468 | ||
1473 | sc->nvifs++; | 1469 | sc->nvifs++; |
1474 | 1470 | ||
@@ -1488,7 +1484,7 @@ static int ath9k_change_interface(struct ieee80211_hw *hw, | |||
1488 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 1484 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1489 | int ret = 0; | 1485 | int ret = 0; |
1490 | 1486 | ||
1491 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | 1487 | ath_dbg(common, CONFIG, "Change Interface\n"); |
1492 | mutex_lock(&sc->mutex); | 1488 | mutex_lock(&sc->mutex); |
1493 | ath9k_ps_wakeup(sc); | 1489 | ath9k_ps_wakeup(sc); |
1494 | 1490 | ||
@@ -1531,7 +1527,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, | |||
1531 | struct ath_softc *sc = hw->priv; | 1527 | struct ath_softc *sc = hw->priv; |
1532 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | 1528 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1533 | 1529 | ||
1534 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); | 1530 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
1535 | 1531 | ||
1536 | ath9k_ps_wakeup(sc); | 1532 | ath9k_ps_wakeup(sc); |
1537 | mutex_lock(&sc->mutex); | 1533 | mutex_lock(&sc->mutex); |
@@ -1622,12 +1618,10 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) | |||
1622 | 1618 | ||
1623 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { | 1619 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1624 | if (conf->flags & IEEE80211_CONF_MONITOR) { | 1620 | if (conf->flags & IEEE80211_CONF_MONITOR) { |
1625 | ath_dbg(common, ATH_DBG_CONFIG, | 1621 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
1626 | "Monitor mode is enabled\n"); | ||
1627 | sc->sc_ah->is_monitoring = true; | 1622 | sc->sc_ah->is_monitoring = true; |
1628 | } else { | 1623 | } else { |
1629 | ath_dbg(common, ATH_DBG_CONFIG, | 1624 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
1630 | "Monitor mode is disabled\n"); | ||
1631 | sc->sc_ah->is_monitoring = false; | 1625 | sc->sc_ah->is_monitoring = false; |
1632 | } | 1626 | } |
1633 | } | 1627 | } |
@@ -1647,8 +1641,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) | |||
1647 | else | 1641 | else |
1648 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | 1642 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; |
1649 | 1643 | ||
1650 | ath_dbg(common, ATH_DBG_CONFIG, | 1644 | ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", |
1651 | "Set channel: %d MHz type: %d\n", | ||
1652 | curchan->center_freq, conf->channel_type); | 1645 | curchan->center_freq, conf->channel_type); |
1653 | 1646 | ||
1654 | /* update survey stats for the old channel before switching */ | 1647 | /* update survey stats for the old channel before switching */ |
@@ -1705,8 +1698,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) | |||
1705 | } | 1698 | } |
1706 | 1699 | ||
1707 | if (changed & IEEE80211_CONF_CHANGE_POWER) { | 1700 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
1708 | ath_dbg(common, ATH_DBG_CONFIG, | 1701 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
1709 | "Set power: %d\n", conf->power_level); | ||
1710 | sc->config.txpowlimit = 2 * conf->power_level; | 1702 | sc->config.txpowlimit = 2 * conf->power_level; |
1711 | ath9k_cmn_update_txpow(ah, sc->curtxpow, | 1703 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1712 | sc->config.txpowlimit, &sc->curtxpow); | 1704 | sc->config.txpowlimit, &sc->curtxpow); |
@@ -1746,8 +1738,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw, | |||
1746 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | 1738 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); |
1747 | ath9k_ps_restore(sc); | 1739 | ath9k_ps_restore(sc); |
1748 | 1740 | ||
1749 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, | 1741 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1750 | "Set HW RX filter: 0x%x\n", rfilt); | 1742 | rfilt); |
1751 | } | 1743 | } |
1752 | 1744 | ||
1753 | static int ath9k_sta_add(struct ieee80211_hw *hw, | 1745 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
@@ -1841,7 +1833,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, | |||
1841 | qi.tqi_cwmax = params->cw_max; | 1833 | qi.tqi_cwmax = params->cw_max; |
1842 | qi.tqi_burstTime = params->txop; | 1834 | qi.tqi_burstTime = params->txop; |
1843 | 1835 | ||
1844 | ath_dbg(common, ATH_DBG_CONFIG, | 1836 | ath_dbg(common, CONFIG, |
1845 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | 1837 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1846 | queue, txq->axq_qnum, params->aifs, params->cw_min, | 1838 | queue, txq->axq_qnum, params->aifs, params->cw_min, |
1847 | params->cw_max, params->txop); | 1839 | params->cw_max, params->txop); |
@@ -1890,7 +1882,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw, | |||
1890 | 1882 | ||
1891 | mutex_lock(&sc->mutex); | 1883 | mutex_lock(&sc->mutex); |
1892 | ath9k_ps_wakeup(sc); | 1884 | ath9k_ps_wakeup(sc); |
1893 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); | 1885 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
1894 | 1886 | ||
1895 | switch (cmd) { | 1887 | switch (cmd) { |
1896 | case SET_KEY: | 1888 | case SET_KEY: |
@@ -1942,9 +1934,8 @@ static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |||
1942 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | 1934 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1943 | common->curaid = bss_conf->aid; | 1935 | common->curaid = bss_conf->aid; |
1944 | ath9k_hw_write_associd(sc->sc_ah); | 1936 | ath9k_hw_write_associd(sc->sc_ah); |
1945 | ath_dbg(common, ATH_DBG_CONFIG, | 1937 | ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", |
1946 | "Bss Info ASSOC %d, bssid: %pM\n", | 1938 | bss_conf->aid, common->curbssid); |
1947 | bss_conf->aid, common->curbssid); | ||
1948 | ath_beacon_config(sc, vif); | 1939 | ath_beacon_config(sc, vif); |
1949 | /* | 1940 | /* |
1950 | * Request a re-configuration of Beacon related timers | 1941 | * Request a re-configuration of Beacon related timers |
@@ -1975,8 +1966,7 @@ static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) | |||
1975 | 1966 | ||
1976 | /* Reconfigure bss info */ | 1967 | /* Reconfigure bss info */ |
1977 | if (avp->primary_sta_vif && !bss_conf->assoc) { | 1968 | if (avp->primary_sta_vif && !bss_conf->assoc) { |
1978 | ath_dbg(common, ATH_DBG_CONFIG, | 1969 | ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n", |
1979 | "Bss Info DISASSOC %d, bssid %pM\n", | ||
1980 | common->curaid, common->curbssid); | 1970 | common->curaid, common->curbssid); |
1981 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); | 1971 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); |
1982 | avp->primary_sta_vif = false; | 1972 | avp->primary_sta_vif = false; |
@@ -2018,7 +2008,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
2018 | if (changed & BSS_CHANGED_BSSID) { | 2008 | if (changed & BSS_CHANGED_BSSID) { |
2019 | ath9k_config_bss(sc, vif); | 2009 | ath9k_config_bss(sc, vif); |
2020 | 2010 | ||
2021 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", | 2011 | ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n", |
2022 | common->curbssid, common->curaid); | 2012 | common->curbssid, common->curaid); |
2023 | } | 2013 | } |
2024 | 2014 | ||
@@ -2096,7 +2086,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
2096 | } | 2086 | } |
2097 | 2087 | ||
2098 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { | 2088 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
2099 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", | 2089 | ath_dbg(common, CONFIG, "BSS Changed PREAMBLE %d\n", |
2100 | bss_conf->use_short_preamble); | 2090 | bss_conf->use_short_preamble); |
2101 | if (bss_conf->use_short_preamble) | 2091 | if (bss_conf->use_short_preamble) |
2102 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | 2092 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; |
@@ -2105,7 +2095,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw, | |||
2105 | } | 2095 | } |
2106 | 2096 | ||
2107 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { | 2097 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
2108 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", | 2098 | ath_dbg(common, CONFIG, "BSS Changed CTS PROT %d\n", |
2109 | bss_conf->use_cts_prot); | 2099 | bss_conf->use_cts_prot); |
2110 | if (bss_conf->use_cts_prot && | 2100 | if (bss_conf->use_cts_prot && |
2111 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | 2101 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) |
@@ -2271,13 +2261,13 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop) | |||
2271 | cancel_delayed_work_sync(&sc->tx_complete_work); | 2261 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2272 | 2262 | ||
2273 | if (ah->ah_flags & AH_UNPLUGGED) { | 2263 | if (ah->ah_flags & AH_UNPLUGGED) { |
2274 | ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n"); | 2264 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
2275 | mutex_unlock(&sc->mutex); | 2265 | mutex_unlock(&sc->mutex); |
2276 | return; | 2266 | return; |
2277 | } | 2267 | } |
2278 | 2268 | ||
2279 | if (sc->sc_flags & SC_OP_INVALID) { | 2269 | if (sc->sc_flags & SC_OP_INVALID) { |
2280 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | 2270 | ath_dbg(common, ANY, "Device not present\n"); |
2281 | mutex_unlock(&sc->mutex); | 2271 | mutex_unlock(&sc->mutex); |
2282 | return; | 2272 | return; |
2283 | } | 2273 | } |
diff --git a/drivers/net/wireless/ath/ath9k/mci.c b/drivers/net/wireless/ath/ath9k/mci.c index 691bf47906e2..ca9b53cc4001 100644 --- a/drivers/net/wireless/ath/ath9k/mci.c +++ b/drivers/net/wireless/ath/ath9k/mci.c | |||
@@ -43,14 +43,14 @@ static bool ath_mci_add_profile(struct ath_common *common, | |||
43 | 43 | ||
44 | if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) && | 44 | if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) && |
45 | (info->type == MCI_GPM_COEX_PROFILE_VOICE)) { | 45 | (info->type == MCI_GPM_COEX_PROFILE_VOICE)) { |
46 | ath_dbg(common, ATH_DBG_MCI, | 46 | ath_dbg(common, MCI, |
47 | "Too many SCO profile, failed to add new profile\n"); | 47 | "Too many SCO profile, failed to add new profile\n"); |
48 | return false; | 48 | return false; |
49 | } | 49 | } |
50 | 50 | ||
51 | if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) && | 51 | if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) && |
52 | (info->type != MCI_GPM_COEX_PROFILE_VOICE)) { | 52 | (info->type != MCI_GPM_COEX_PROFILE_VOICE)) { |
53 | ath_dbg(common, ATH_DBG_MCI, | 53 | ath_dbg(common, MCI, |
54 | "Too many ACL profile, failed to add new profile\n"); | 54 | "Too many ACL profile, failed to add new profile\n"); |
55 | return false; | 55 | return false; |
56 | } | 56 | } |
@@ -80,8 +80,7 @@ static void ath_mci_del_profile(struct ath_common *common, | |||
80 | entry = ath_mci_find_profile(mci, info); | 80 | entry = ath_mci_find_profile(mci, info); |
81 | 81 | ||
82 | if (!entry) { | 82 | if (!entry) { |
83 | ath_dbg(common, ATH_DBG_MCI, | 83 | ath_dbg(common, MCI, "Profile to be deleted not found\n"); |
84 | "Profile to be deleted not found\n"); | ||
85 | return; | 84 | return; |
86 | } | 85 | } |
87 | DEC_PROF(mci, entry); | 86 | DEC_PROF(mci, entry); |
@@ -132,30 +131,30 @@ static void ath_mci_update_scheme(struct ath_softc *sc) | |||
132 | list); | 131 | list); |
133 | if (mci->num_sco && info->T == 12) { | 132 | if (mci->num_sco && info->T == 12) { |
134 | mci->aggr_limit = 8; | 133 | mci->aggr_limit = 8; |
135 | ath_dbg(common, ATH_DBG_MCI, | 134 | ath_dbg(common, MCI, |
136 | "Single SCO, aggregation limit 2 ms\n"); | 135 | "Single SCO, aggregation limit 2 ms\n"); |
137 | } else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) && | 136 | } else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) && |
138 | !info->master) { | 137 | !info->master) { |
139 | btcoex->btcoex_period = 60; | 138 | btcoex->btcoex_period = 60; |
140 | ath_dbg(common, ATH_DBG_MCI, | 139 | ath_dbg(common, MCI, |
141 | "Single slave PAN/FTP, bt period 60 ms\n"); | 140 | "Single slave PAN/FTP, bt period 60 ms\n"); |
142 | } else if ((info->type == MCI_GPM_COEX_PROFILE_HID) && | 141 | } else if ((info->type == MCI_GPM_COEX_PROFILE_HID) && |
143 | (info->T > 0 && info->T < 50) && | 142 | (info->T > 0 && info->T < 50) && |
144 | (info->A > 1 || info->W > 1)) { | 143 | (info->A > 1 || info->W > 1)) { |
145 | btcoex->duty_cycle = 30; | 144 | btcoex->duty_cycle = 30; |
146 | mci->aggr_limit = 8; | 145 | mci->aggr_limit = 8; |
147 | ath_dbg(common, ATH_DBG_MCI, | 146 | ath_dbg(common, MCI, |
148 | "Multiple attempt/timeout single HID " | 147 | "Multiple attempt/timeout single HID " |
149 | "aggregation limit 2 ms dutycycle 30%%\n"); | 148 | "aggregation limit 2 ms dutycycle 30%%\n"); |
150 | } | 149 | } |
151 | } else if ((num_profile == 2) && (mci->num_hid == 2)) { | 150 | } else if ((num_profile == 2) && (mci->num_hid == 2)) { |
152 | btcoex->duty_cycle = 30; | 151 | btcoex->duty_cycle = 30; |
153 | mci->aggr_limit = 8; | 152 | mci->aggr_limit = 8; |
154 | ath_dbg(common, ATH_DBG_MCI, | 153 | ath_dbg(common, MCI, |
155 | "Two HIDs aggregation limit 2 ms dutycycle 30%%\n"); | 154 | "Two HIDs aggregation limit 2 ms dutycycle 30%%\n"); |
156 | } else if (num_profile > 3) { | 155 | } else if (num_profile > 3) { |
157 | mci->aggr_limit = 6; | 156 | mci->aggr_limit = 6; |
158 | ath_dbg(common, ATH_DBG_MCI, | 157 | ath_dbg(common, MCI, |
159 | "Three or more profiles aggregation limit 1.5 ms\n"); | 158 | "Three or more profiles aggregation limit 1.5 ms\n"); |
160 | } | 159 | } |
161 | 160 | ||
@@ -194,42 +193,41 @@ static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) | |||
194 | switch (opcode) { | 193 | switch (opcode) { |
195 | case MCI_GPM_BT_CAL_REQ: | 194 | case MCI_GPM_BT_CAL_REQ: |
196 | 195 | ||
197 | ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_REQ\n"); | 196 | ath_dbg(common, MCI, "MCI received BT_CAL_REQ\n"); |
198 | 197 | ||
199 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { | 198 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) { |
200 | ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL); | 199 | ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL); |
201 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | 200 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
202 | } else | 201 | } else |
203 | ath_dbg(common, ATH_DBG_MCI, | 202 | ath_dbg(common, MCI, "MCI State mismatches: %d\n", |
204 | "MCI State mismatches: %d\n", | ||
205 | ar9003_mci_state(ah, MCI_STATE_BT, NULL)); | 203 | ar9003_mci_state(ah, MCI_STATE_BT, NULL)); |
206 | 204 | ||
207 | break; | 205 | break; |
208 | 206 | ||
209 | case MCI_GPM_BT_CAL_DONE: | 207 | case MCI_GPM_BT_CAL_DONE: |
210 | 208 | ||
211 | ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_DONE\n"); | 209 | ath_dbg(common, MCI, "MCI received BT_CAL_DONE\n"); |
212 | 210 | ||
213 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_CAL) | 211 | if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_CAL) |
214 | ath_dbg(common, ATH_DBG_MCI, "MCI error illegal!\n"); | 212 | ath_dbg(common, MCI, "MCI error illegal!\n"); |
215 | else | 213 | else |
216 | ath_dbg(common, ATH_DBG_MCI, "MCI BT not in CAL state\n"); | 214 | ath_dbg(common, MCI, "MCI BT not in CAL state\n"); |
217 | 215 | ||
218 | break; | 216 | break; |
219 | 217 | ||
220 | case MCI_GPM_BT_CAL_GRANT: | 218 | case MCI_GPM_BT_CAL_GRANT: |
221 | 219 | ||
222 | ath_dbg(common, ATH_DBG_MCI, "MCI received BT_CAL_GRANT\n"); | 220 | ath_dbg(common, MCI, "MCI received BT_CAL_GRANT\n"); |
223 | 221 | ||
224 | /* Send WLAN_CAL_DONE for now */ | 222 | /* Send WLAN_CAL_DONE for now */ |
225 | ath_dbg(common, ATH_DBG_MCI, "MCI send WLAN_CAL_DONE\n"); | 223 | ath_dbg(common, MCI, "MCI send WLAN_CAL_DONE\n"); |
226 | MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); | 224 | MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE); |
227 | ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload, | 225 | ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload, |
228 | 16, false, true); | 226 | 16, false, true); |
229 | break; | 227 | break; |
230 | 228 | ||
231 | default: | 229 | default: |
232 | ath_dbg(common, ATH_DBG_MCI, "MCI Unknown GPM CAL message\n"); | 230 | ath_dbg(common, MCI, "MCI Unknown GPM CAL message\n"); |
233 | break; | 231 | break; |
234 | } | 232 | } |
235 | } | 233 | } |
@@ -272,8 +270,7 @@ static void ath_mci_process_status(struct ath_softc *sc, | |||
272 | 270 | ||
273 | /* Link status type are not handled */ | 271 | /* Link status type are not handled */ |
274 | if (status->is_link) { | 272 | if (status->is_link) { |
275 | ath_dbg(common, ATH_DBG_MCI, | 273 | ath_dbg(common, MCI, "Skip link type status update\n"); |
276 | "Skip link type status update\n"); | ||
277 | return; | 274 | return; |
278 | } | 275 | } |
279 | 276 | ||
@@ -281,14 +278,13 @@ static void ath_mci_process_status(struct ath_softc *sc, | |||
281 | 278 | ||
282 | info.conn_handle = status->conn_handle; | 279 | info.conn_handle = status->conn_handle; |
283 | if (ath_mci_find_profile(mci, &info)) { | 280 | if (ath_mci_find_profile(mci, &info)) { |
284 | ath_dbg(common, ATH_DBG_MCI, | 281 | ath_dbg(common, MCI, |
285 | "Skip non link state update for existing profile %d\n", | 282 | "Skip non link state update for existing profile %d\n", |
286 | status->conn_handle); | 283 | status->conn_handle); |
287 | return; | 284 | return; |
288 | } | 285 | } |
289 | if (status->conn_handle >= ATH_MCI_MAX_PROFILE) { | 286 | if (status->conn_handle >= ATH_MCI_MAX_PROFILE) { |
290 | ath_dbg(common, ATH_DBG_MCI, | 287 | ath_dbg(common, MCI, "Ignore too many non-link update\n"); |
291 | "Ignore too many non-link update\n"); | ||
292 | return; | 288 | return; |
293 | } | 289 | } |
294 | if (status->is_critical) | 290 | if (status->is_critical) |
@@ -320,35 +316,32 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) | |||
320 | switch (opcode) { | 316 | switch (opcode) { |
321 | 317 | ||
322 | case MCI_GPM_COEX_VERSION_QUERY: | 318 | case MCI_GPM_COEX_VERSION_QUERY: |
323 | ath_dbg(common, ATH_DBG_MCI, | 319 | ath_dbg(common, MCI, "MCI Recv GPM COEX Version Query\n"); |
324 | "MCI Recv GPM COEX Version Query.\n"); | ||
325 | version = ar9003_mci_state(ah, | 320 | version = ar9003_mci_state(ah, |
326 | MCI_STATE_SEND_WLAN_COEX_VERSION, NULL); | 321 | MCI_STATE_SEND_WLAN_COEX_VERSION, NULL); |
327 | break; | 322 | break; |
328 | 323 | ||
329 | case MCI_GPM_COEX_VERSION_RESPONSE: | 324 | case MCI_GPM_COEX_VERSION_RESPONSE: |
330 | ath_dbg(common, ATH_DBG_MCI, | 325 | ath_dbg(common, MCI, "MCI Recv GPM COEX Version Response\n"); |
331 | "MCI Recv GPM COEX Version Response.\n"); | ||
332 | major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION); | 326 | major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION); |
333 | minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION); | 327 | minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION); |
334 | ath_dbg(common, ATH_DBG_MCI, | 328 | ath_dbg(common, MCI, "MCI BT Coex version: %d.%d\n", |
335 | "MCI BT Coex version: %d.%d\n", major, minor); | 329 | major, minor); |
336 | version = (major << 8) + minor; | 330 | version = (major << 8) + minor; |
337 | version = ar9003_mci_state(ah, | 331 | version = ar9003_mci_state(ah, |
338 | MCI_STATE_SET_BT_COEX_VERSION, &version); | 332 | MCI_STATE_SET_BT_COEX_VERSION, &version); |
339 | break; | 333 | break; |
340 | 334 | ||
341 | case MCI_GPM_COEX_STATUS_QUERY: | 335 | case MCI_GPM_COEX_STATUS_QUERY: |
342 | ath_dbg(common, ATH_DBG_MCI, | 336 | ath_dbg(common, MCI, |
343 | "MCI Recv GPM COEX Status Query = 0x%02x.\n", | 337 | "MCI Recv GPM COEX Status Query = 0x%02x\n", |
344 | *(rx_payload + MCI_GPM_COEX_B_WLAN_BITMAP)); | 338 | *(rx_payload + MCI_GPM_COEX_B_WLAN_BITMAP)); |
345 | ar9003_mci_state(ah, | 339 | ar9003_mci_state(ah, |
346 | MCI_STATE_SEND_WLAN_CHANNELS, NULL); | 340 | MCI_STATE_SEND_WLAN_CHANNELS, NULL); |
347 | break; | 341 | break; |
348 | 342 | ||
349 | case MCI_GPM_COEX_BT_PROFILE_INFO: | 343 | case MCI_GPM_COEX_BT_PROFILE_INFO: |
350 | ath_dbg(common, ATH_DBG_MCI, | 344 | ath_dbg(common, MCI, "MCI Recv GPM Coex BT profile info\n"); |
351 | "MCI Recv GPM Coex BT profile info\n"); | ||
352 | memcpy(&profile_info, | 345 | memcpy(&profile_info, |
353 | (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10); | 346 | (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10); |
354 | 347 | ||
@@ -356,9 +349,9 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) | |||
356 | || (profile_info.type >= | 349 | || (profile_info.type >= |
357 | MCI_GPM_COEX_PROFILE_MAX)) { | 350 | MCI_GPM_COEX_PROFILE_MAX)) { |
358 | 351 | ||
359 | ath_dbg(common, ATH_DBG_MCI, | 352 | ath_dbg(common, MCI, |
360 | "illegal profile type = %d," | 353 | "illegal profile type = %d, state = %d\n", |
361 | "state = %d\n", profile_info.type, | 354 | profile_info.type, |
362 | profile_info.start); | 355 | profile_info.start); |
363 | break; | 356 | break; |
364 | } | 357 | } |
@@ -375,9 +368,8 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) | |||
375 | MCI_GPM_COEX_B_STATUS_STATE); | 368 | MCI_GPM_COEX_B_STATUS_STATE); |
376 | 369 | ||
377 | seq_num = *((u32 *)(rx_payload + 12)); | 370 | seq_num = *((u32 *)(rx_payload + 12)); |
378 | ath_dbg(common, ATH_DBG_MCI, | 371 | ath_dbg(common, MCI, |
379 | "MCI Recv GPM COEX BT_Status_Update: " | 372 | "MCI Recv GPM COEX BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n", |
380 | "is_link=%d, linkId=%d, state=%d, SEQ=%d\n", | ||
381 | profile_status.is_link, profile_status.conn_handle, | 373 | profile_status.is_link, profile_status.conn_handle, |
382 | profile_status.is_critical, seq_num); | 374 | profile_status.is_critical, seq_num); |
383 | 375 | ||
@@ -385,8 +377,8 @@ static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload) | |||
385 | break; | 377 | break; |
386 | 378 | ||
387 | default: | 379 | default: |
388 | ath_dbg(common, ATH_DBG_MCI, | 380 | ath_dbg(common, MCI, "MCI Unknown GPM COEX message = 0x%02x\n", |
389 | "MCI Unknown GPM COEX message = 0x%02x\n", opcode); | 381 | opcode); |
390 | break; | 382 | break; |
391 | } | 383 | } |
392 | } | 384 | } |
@@ -428,7 +420,7 @@ int ath_mci_setup(struct ath_softc *sc) | |||
428 | mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE; | 420 | mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE; |
429 | 421 | ||
430 | if (ath_mci_buf_alloc(sc, &mci->sched_buf)) { | 422 | if (ath_mci_buf_alloc(sc, &mci->sched_buf)) { |
431 | ath_dbg(common, ATH_DBG_FATAL, "MCI buffer alloc failed\n"); | 423 | ath_dbg(common, FATAL, "MCI buffer alloc failed\n"); |
432 | error = -ENOMEM; | 424 | error = -ENOMEM; |
433 | goto fail; | 425 | goto fail; |
434 | } | 426 | } |
@@ -481,10 +473,9 @@ void ath_mci_intr(struct ath_softc *sc) | |||
481 | if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) { | 473 | if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) { |
482 | 474 | ||
483 | ar9003_mci_state(sc->sc_ah, MCI_STATE_INIT_GPM_OFFSET, NULL); | 475 | ar9003_mci_state(sc->sc_ah, MCI_STATE_INIT_GPM_OFFSET, NULL); |
484 | ath_dbg(common, ATH_DBG_MCI, | 476 | ath_dbg(common, MCI, "MCI interrupt but MCI disabled\n"); |
485 | "MCI interrupt but MCI disabled\n"); | ||
486 | 477 | ||
487 | ath_dbg(common, ATH_DBG_MCI, | 478 | ath_dbg(common, MCI, |
488 | "MCI interrupt: intr = 0x%x, intr_rxmsg = 0x%x\n", | 479 | "MCI interrupt: intr = 0x%x, intr_rxmsg = 0x%x\n", |
489 | mci_int, mci_int_rxmsg); | 480 | mci_int, mci_int_rxmsg); |
490 | return; | 481 | return; |
@@ -499,11 +490,11 @@ void ath_mci_intr(struct ath_softc *sc) | |||
499 | * only when BT wake up. Now they are always sent, as a | 490 | * only when BT wake up. Now they are always sent, as a |
500 | * recovery method to reset BT MCI's RX alignment. | 491 | * recovery method to reset BT MCI's RX alignment. |
501 | */ | 492 | */ |
502 | ath_dbg(common, ATH_DBG_MCI, "MCI interrupt send REMOTE_RESET\n"); | 493 | ath_dbg(common, MCI, "MCI interrupt send REMOTE_RESET\n"); |
503 | 494 | ||
504 | ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, | 495 | ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0, |
505 | payload, 16, true, false); | 496 | payload, 16, true, false); |
506 | ath_dbg(common, ATH_DBG_MCI, "MCI interrupt send SYS_WAKING\n"); | 497 | ath_dbg(common, MCI, "MCI interrupt send SYS_WAKING\n"); |
507 | ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0, | 498 | ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0, |
508 | NULL, 0, true, false); | 499 | NULL, 0, true, false); |
509 | 500 | ||
@@ -513,7 +504,7 @@ void ath_mci_intr(struct ath_softc *sc) | |||
513 | /* | 504 | /* |
514 | * always do this for recovery and 2G/5G toggling and LNA_TRANS | 505 | * always do this for recovery and 2G/5G toggling and LNA_TRANS |
515 | */ | 506 | */ |
516 | ath_dbg(common, ATH_DBG_MCI, "MCI Set BT state to AWAKE.\n"); | 507 | ath_dbg(common, MCI, "MCI Set BT state to AWAKE\n"); |
517 | ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL); | 508 | ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL); |
518 | } | 509 | } |
519 | 510 | ||
@@ -525,17 +516,16 @@ void ath_mci_intr(struct ath_softc *sc) | |||
525 | 516 | ||
526 | if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) | 517 | if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) |
527 | == MCI_BT_SLEEP) | 518 | == MCI_BT_SLEEP) |
528 | ath_dbg(common, ATH_DBG_MCI, | 519 | ath_dbg(common, MCI, |
529 | "MCI BT stays in sleep mode\n"); | 520 | "MCI BT stays in sleep mode\n"); |
530 | else { | 521 | else { |
531 | ath_dbg(common, ATH_DBG_MCI, | 522 | ath_dbg(common, MCI, |
532 | "MCI Set BT state to AWAKE.\n"); | 523 | "MCI Set BT state to AWAKE\n"); |
533 | ar9003_mci_state(ah, | 524 | ar9003_mci_state(ah, |
534 | MCI_STATE_SET_BT_AWAKE, NULL); | 525 | MCI_STATE_SET_BT_AWAKE, NULL); |
535 | } | 526 | } |
536 | } else | 527 | } else |
537 | ath_dbg(common, ATH_DBG_MCI, | 528 | ath_dbg(common, MCI, "MCI BT stays in AWAKE mode\n"); |
538 | "MCI BT stays in AWAKE mode.\n"); | ||
539 | } | 529 | } |
540 | 530 | ||
541 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) { | 531 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) { |
@@ -546,23 +536,22 @@ void ath_mci_intr(struct ath_softc *sc) | |||
546 | 536 | ||
547 | if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) | 537 | if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) |
548 | == MCI_BT_AWAKE) | 538 | == MCI_BT_AWAKE) |
549 | ath_dbg(common, ATH_DBG_MCI, | 539 | ath_dbg(common, MCI, |
550 | "MCI BT stays in AWAKE mode.\n"); | 540 | "MCI BT stays in AWAKE mode\n"); |
551 | else { | 541 | else { |
552 | ath_dbg(common, ATH_DBG_MCI, | 542 | ath_dbg(common, MCI, |
553 | "MCI SetBT state to SLEEP\n"); | 543 | "MCI SetBT state to SLEEP\n"); |
554 | ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP, | 544 | ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP, |
555 | NULL); | 545 | NULL); |
556 | } | 546 | } |
557 | } else | 547 | } else |
558 | ath_dbg(common, ATH_DBG_MCI, | 548 | ath_dbg(common, MCI, "MCI BT stays in SLEEP mode\n"); |
559 | "MCI BT stays in SLEEP mode\n"); | ||
560 | } | 549 | } |
561 | 550 | ||
562 | if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || | 551 | if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) || |
563 | (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) { | 552 | (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) { |
564 | 553 | ||
565 | ath_dbg(common, ATH_DBG_MCI, "MCI RX broken, skip GPM msgs\n"); | 554 | ath_dbg(common, MCI, "MCI RX broken, skip GPM msgs\n"); |
566 | ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL); | 555 | ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL); |
567 | skip_gpm = true; | 556 | skip_gpm = true; |
568 | } | 557 | } |
@@ -624,7 +613,7 @@ void ath_mci_intr(struct ath_softc *sc) | |||
624 | 613 | ||
625 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) { | 614 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO) { |
626 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO; | 615 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO; |
627 | ath_dbg(common, ATH_DBG_MCI, "MCI LNA_INFO\n"); | 616 | ath_dbg(common, MCI, "MCI LNA_INFO\n"); |
628 | } | 617 | } |
629 | 618 | ||
630 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { | 619 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) { |
@@ -635,16 +624,14 @@ void ath_mci_intr(struct ath_softc *sc) | |||
635 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO; | 624 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO; |
636 | 625 | ||
637 | if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL)) | 626 | if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL)) |
638 | ath_dbg(common, ATH_DBG_MCI, | 627 | ath_dbg(common, MCI, |
639 | "MCI CONT_INFO: " | 628 | "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n", |
640 | "(tx) pri = %d, pwr = %d dBm\n", | ||
641 | ar9003_mci_state(ah, | 629 | ar9003_mci_state(ah, |
642 | MCI_STATE_CONT_PRIORITY, NULL), | 630 | MCI_STATE_CONT_PRIORITY, NULL), |
643 | value_dbm); | 631 | value_dbm); |
644 | else | 632 | else |
645 | ath_dbg(common, ATH_DBG_MCI, | 633 | ath_dbg(common, MCI, |
646 | "MCI CONT_INFO:" | 634 | "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n", |
647 | "(rx) pri = %d,pwr = %d dBm\n", | ||
648 | ar9003_mci_state(ah, | 635 | ar9003_mci_state(ah, |
649 | MCI_STATE_CONT_PRIORITY, NULL), | 636 | MCI_STATE_CONT_PRIORITY, NULL), |
650 | value_dbm); | 637 | value_dbm); |
@@ -652,12 +639,12 @@ void ath_mci_intr(struct ath_softc *sc) | |||
652 | 639 | ||
653 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) { | 640 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK) { |
654 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK; | 641 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK; |
655 | ath_dbg(common, ATH_DBG_MCI, "MCI CONT_NACK\n"); | 642 | ath_dbg(common, MCI, "MCI CONT_NACK\n"); |
656 | } | 643 | } |
657 | 644 | ||
658 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) { | 645 | if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST) { |
659 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST; | 646 | mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST; |
660 | ath_dbg(common, ATH_DBG_MCI, "MCI CONT_RST\n"); | 647 | ath_dbg(common, MCI, "MCI CONT_RST\n"); |
661 | } | 648 | } |
662 | } | 649 | } |
663 | 650 | ||
@@ -667,7 +654,6 @@ void ath_mci_intr(struct ath_softc *sc) | |||
667 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); | 654 | AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT); |
668 | 655 | ||
669 | if (mci_int_rxmsg & 0xfffffffe) | 656 | if (mci_int_rxmsg & 0xfffffffe) |
670 | ath_dbg(common, ATH_DBG_MCI, | 657 | ath_dbg(common, MCI, "MCI not processed mci_int_rxmsg = 0x%x\n", |
671 | "MCI not processed mci_int_rxmsg = 0x%x\n", | ||
672 | mci_int_rxmsg); | 658 | mci_int_rxmsg); |
673 | } | 659 | } |
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c index 528d5f3e868c..b3c3798fe513 100644 --- a/drivers/net/wireless/ath/ath9k/rc.c +++ b/drivers/net/wireless/ath/ath9k/rc.c | |||
@@ -1199,7 +1199,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc, | |||
1199 | return &ar5416_11na_ratetable; | 1199 | return &ar5416_11na_ratetable; |
1200 | return &ar5416_11a_ratetable; | 1200 | return &ar5416_11a_ratetable; |
1201 | default: | 1201 | default: |
1202 | ath_dbg(common, ATH_DBG_CONFIG, "Invalid band\n"); | 1202 | ath_dbg(common, CONFIG, "Invalid band\n"); |
1203 | return NULL; | 1203 | return NULL; |
1204 | } | 1204 | } |
1205 | } | 1205 | } |
@@ -1276,8 +1276,7 @@ static void ath_rc_init(struct ath_softc *sc, | |||
1276 | ath_rc_priv->valid_rate_index[k-1]; | 1276 | ath_rc_priv->valid_rate_index[k-1]; |
1277 | ath_rc_priv->rate_table = rate_table; | 1277 | ath_rc_priv->rate_table = rate_table; |
1278 | 1278 | ||
1279 | ath_dbg(common, ATH_DBG_CONFIG, | 1279 | ath_dbg(common, CONFIG, "RC Initialized with capabilities: 0x%x\n", |
1280 | "RC Initialized with capabilities: 0x%x\n", | ||
1281 | ath_rc_priv->ht_cap); | 1280 | ath_rc_priv->ht_cap); |
1282 | } | 1281 | } |
1283 | 1282 | ||
@@ -1474,7 +1473,7 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband, | |||
1474 | oper_cw40, oper_sgi); | 1473 | oper_cw40, oper_sgi); |
1475 | ath_rc_init(sc, priv_sta, sband, sta, rate_table); | 1474 | ath_rc_init(sc, priv_sta, sband, sta, rate_table); |
1476 | 1475 | ||
1477 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, | 1476 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, |
1478 | "Operating HT Bandwidth changed to: %d\n", | 1477 | "Operating HT Bandwidth changed to: %d\n", |
1479 | sc->hw->conf.channel_type); | 1478 | sc->hw->conf.channel_type); |
1480 | } | 1479 | } |
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c index ad5176de07dc..0e666fbe0842 100644 --- a/drivers/net/wireless/ath/ath9k/recv.c +++ b/drivers/net/wireless/ath/ath9k/recv.c | |||
@@ -172,7 +172,7 @@ static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |||
172 | u32 nbuf = 0; | 172 | u32 nbuf = 0; |
173 | 173 | ||
174 | if (list_empty(&sc->rx.rxbuf)) { | 174 | if (list_empty(&sc->rx.rxbuf)) { |
175 | ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n"); | 175 | ath_dbg(common, QUEUE, "No free rx buf available\n"); |
176 | return; | 176 | return; |
177 | } | 177 | } |
178 | 178 | ||
@@ -337,7 +337,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs) | |||
337 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { | 337 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
338 | return ath_rx_edma_init(sc, nbufs); | 338 | return ath_rx_edma_init(sc, nbufs); |
339 | } else { | 339 | } else { |
340 | ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", | 340 | ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n", |
341 | common->cachelsz, common->rx_bufsize); | 341 | common->cachelsz, common->rx_bufsize); |
342 | 342 | ||
343 | /* Initialize rx descriptors */ | 343 | /* Initialize rx descriptors */ |
@@ -591,7 +591,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) | |||
591 | 591 | ||
592 | if (sc->ps_flags & PS_BEACON_SYNC) { | 592 | if (sc->ps_flags & PS_BEACON_SYNC) { |
593 | sc->ps_flags &= ~PS_BEACON_SYNC; | 593 | sc->ps_flags &= ~PS_BEACON_SYNC; |
594 | ath_dbg(common, ATH_DBG_PS, | 594 | ath_dbg(common, PS, |
595 | "Reconfigure Beacon timers based on timestamp from the AP\n"); | 595 | "Reconfigure Beacon timers based on timestamp from the AP\n"); |
596 | ath_set_beacon(sc); | 596 | ath_set_beacon(sc); |
597 | } | 597 | } |
@@ -604,7 +604,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) | |||
604 | * a backup trigger for returning into NETWORK SLEEP state, | 604 | * a backup trigger for returning into NETWORK SLEEP state, |
605 | * so we are waiting for it as well. | 605 | * so we are waiting for it as well. |
606 | */ | 606 | */ |
607 | ath_dbg(common, ATH_DBG_PS, | 607 | ath_dbg(common, PS, |
608 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); | 608 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); |
609 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; | 609 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
610 | return; | 610 | return; |
@@ -617,8 +617,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) | |||
617 | * been delivered. | 617 | * been delivered. |
618 | */ | 618 | */ |
619 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; | 619 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
620 | ath_dbg(common, ATH_DBG_PS, | 620 | ath_dbg(common, PS, "PS wait for CAB frames timed out\n"); |
621 | "PS wait for CAB frames timed out\n"); | ||
622 | } | 621 | } |
623 | } | 622 | } |
624 | 623 | ||
@@ -643,13 +642,13 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon) | |||
643 | * point. | 642 | * point. |
644 | */ | 643 | */ |
645 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); | 644 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
646 | ath_dbg(common, ATH_DBG_PS, | 645 | ath_dbg(common, PS, |
647 | "All PS CAB frames received, back to sleep\n"); | 646 | "All PS CAB frames received, back to sleep\n"); |
648 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && | 647 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
649 | !is_multicast_ether_addr(hdr->addr1) && | 648 | !is_multicast_ether_addr(hdr->addr1) && |
650 | !ieee80211_has_morefrags(hdr->frame_control)) { | 649 | !ieee80211_has_morefrags(hdr->frame_control)) { |
651 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; | 650 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
652 | ath_dbg(common, ATH_DBG_PS, | 651 | ath_dbg(common, PS, |
653 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", | 652 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", |
654 | sc->ps_flags & (PS_WAIT_FOR_BEACON | | 653 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
655 | PS_WAIT_FOR_CAB | | 654 | PS_WAIT_FOR_CAB | |
@@ -932,7 +931,7 @@ static int ath9k_process_rate(struct ath_common *common, | |||
932 | * No valid hardware bitrate found -- we should not get here | 931 | * No valid hardware bitrate found -- we should not get here |
933 | * because hardware has already validated this frame as OK. | 932 | * because hardware has already validated this frame as OK. |
934 | */ | 933 | */ |
935 | ath_dbg(common, ATH_DBG_ANY, | 934 | ath_dbg(common, ANY, |
936 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", | 935 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", |
937 | rx_stats->rs_rate); | 936 | rx_stats->rs_rate); |
938 | 937 | ||
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index 35422fc1f2ce..65c8894c5f81 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c | |||
@@ -187,7 +187,7 @@ void ath9k_fatal_work(struct work_struct *work) | |||
187 | fatal_work); | 187 | fatal_work); |
188 | struct ath_common *common = ath9k_hw_common(priv->ah); | 188 | struct ath_common *common = ath9k_hw_common(priv->ah); |
189 | 189 | ||
190 | ath_dbg(common, ATH_DBG_FATAL, "FATAL Event received, resetting device\n"); | 190 | ath_dbg(common, FATAL, "FATAL Event received, resetting device\n"); |
191 | ath9k_htc_reset(priv); | 191 | ath9k_htc_reset(priv); |
192 | } | 192 | } |
193 | 193 | ||
@@ -330,8 +330,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, | |||
330 | 330 | ||
331 | time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout); | 331 | time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout); |
332 | if (!time_left) { | 332 | if (!time_left) { |
333 | ath_dbg(common, ATH_DBG_WMI, | 333 | ath_dbg(common, WMI, "Timeout waiting for WMI command: %s\n", |
334 | "Timeout waiting for WMI command: %s\n", | ||
335 | wmi_cmd_to_name(cmd_id)); | 334 | wmi_cmd_to_name(cmd_id)); |
336 | mutex_unlock(&wmi->op_mutex); | 335 | mutex_unlock(&wmi->op_mutex); |
337 | return -ETIMEDOUT; | 336 | return -ETIMEDOUT; |
@@ -342,8 +341,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, | |||
342 | return 0; | 341 | return 0; |
343 | 342 | ||
344 | out: | 343 | out: |
345 | ath_dbg(common, ATH_DBG_WMI, | 344 | ath_dbg(common, WMI, "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id)); |
346 | "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id)); | ||
347 | mutex_unlock(&wmi->op_mutex); | 345 | mutex_unlock(&wmi->op_mutex); |
348 | kfree_skb(skb); | 346 | kfree_skb(skb); |
349 | 347 | ||
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c index 23e80e63bca9..7c80ec791a53 100644 --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c | |||
@@ -1626,8 +1626,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, | |||
1626 | bf = list_first_entry(head, struct ath_buf, list); | 1626 | bf = list_first_entry(head, struct ath_buf, list); |
1627 | bf_last = list_entry(head->prev, struct ath_buf, list); | 1627 | bf_last = list_entry(head->prev, struct ath_buf, list); |
1628 | 1628 | ||
1629 | ath_dbg(common, ATH_DBG_QUEUE, | 1629 | ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", |
1630 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | 1630 | txq->axq_qnum, txq->axq_depth); |
1631 | 1631 | ||
1632 | if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { | 1632 | if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { |
1633 | list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); | 1633 | list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); |
@@ -1638,8 +1638,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, | |||
1638 | 1638 | ||
1639 | if (txq->axq_link) { | 1639 | if (txq->axq_link) { |
1640 | ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); | 1640 | ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); |
1641 | ath_dbg(common, ATH_DBG_XMIT, | 1641 | ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", |
1642 | "link[%u] (%p)=%llx (%p)\n", | ||
1643 | txq->axq_qnum, txq->axq_link, | 1642 | txq->axq_qnum, txq->axq_link, |
1644 | ito64(bf->bf_daddr), bf->bf_desc); | 1643 | ito64(bf->bf_daddr), bf->bf_desc); |
1645 | } else if (!edma) | 1644 | } else if (!edma) |
@@ -1651,7 +1650,7 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, | |||
1651 | if (puttxbuf) { | 1650 | if (puttxbuf) { |
1652 | TX_STAT_INC(txq->axq_qnum, puttxbuf); | 1651 | TX_STAT_INC(txq->axq_qnum, puttxbuf); |
1653 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | 1652 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); |
1654 | ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n", | 1653 | ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", |
1655 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | 1654 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); |
1656 | } | 1655 | } |
1657 | 1656 | ||
@@ -1793,7 +1792,7 @@ static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, | |||
1793 | 1792 | ||
1794 | bf = ath_tx_get_buffer(sc); | 1793 | bf = ath_tx_get_buffer(sc); |
1795 | if (!bf) { | 1794 | if (!bf) { |
1796 | ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n"); | 1795 | ath_dbg(common, XMIT, "TX buffers are full\n"); |
1797 | goto error; | 1796 | goto error; |
1798 | } | 1797 | } |
1799 | 1798 | ||
@@ -1952,7 +1951,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |||
1952 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; | 1951 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1953 | int q, padpos, padsize; | 1952 | int q, padpos, padsize; |
1954 | 1953 | ||
1955 | ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); | 1954 | ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); |
1956 | 1955 | ||
1957 | if (!(tx_flags & ATH_TX_ERROR)) | 1956 | if (!(tx_flags & ATH_TX_ERROR)) |
1958 | /* Frame was ACKed */ | 1957 | /* Frame was ACKed */ |
@@ -1971,7 +1970,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, | |||
1971 | 1970 | ||
1972 | if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { | 1971 | if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { |
1973 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; | 1972 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; |
1974 | ath_dbg(common, ATH_DBG_PS, | 1973 | ath_dbg(common, PS, |
1975 | "Going back to sleep after having received TX status (0x%lx)\n", | 1974 | "Going back to sleep after having received TX status (0x%lx)\n", |
1976 | sc->ps_flags & (PS_WAIT_FOR_BEACON | | 1975 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
1977 | PS_WAIT_FOR_CAB | | 1976 | PS_WAIT_FOR_CAB | |
@@ -2122,7 +2121,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) | |||
2122 | struct ath_tx_status ts; | 2121 | struct ath_tx_status ts; |
2123 | int status; | 2122 | int status; |
2124 | 2123 | ||
2125 | ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", | 2124 | ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", |
2126 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | 2125 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), |
2127 | txq->axq_link); | 2126 | txq->axq_link); |
2128 | 2127 | ||
@@ -2216,7 +2215,7 @@ static void ath_tx_complete_poll_work(struct work_struct *work) | |||
2216 | } | 2215 | } |
2217 | 2216 | ||
2218 | if (needreset) { | 2217 | if (needreset) { |
2219 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, | 2218 | ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, |
2220 | "tx hung, resetting the chip\n"); | 2219 | "tx hung, resetting the chip\n"); |
2221 | RESET_STAT_INC(sc, RESET_TYPE_TX_HANG); | 2220 | RESET_STAT_INC(sc, RESET_TYPE_TX_HANG); |
2222 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | 2221 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
@@ -2259,8 +2258,7 @@ void ath_tx_edma_tasklet(struct ath_softc *sc) | |||
2259 | if (status == -EINPROGRESS) | 2258 | if (status == -EINPROGRESS) |
2260 | break; | 2259 | break; |
2261 | if (status == -EIO) { | 2260 | if (status == -EIO) { |
2262 | ath_dbg(common, ATH_DBG_XMIT, | 2261 | ath_dbg(common, XMIT, "Error processing tx status\n"); |
2263 | "Error processing tx status\n"); | ||
2264 | break; | 2262 | break; |
2265 | } | 2263 | } |
2266 | 2264 | ||
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c index 4cf7c5eb4813..0e81904956cf 100644 --- a/drivers/net/wireless/ath/key.c +++ b/drivers/net/wireless/ath/key.c | |||
@@ -143,7 +143,7 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry, | |||
143 | break; | 143 | break; |
144 | case ATH_CIPHER_AES_CCM: | 144 | case ATH_CIPHER_AES_CCM: |
145 | if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) { | 145 | if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) { |
146 | ath_dbg(common, ATH_DBG_ANY, | 146 | ath_dbg(common, ANY, |
147 | "AES-CCM not supported by this mac rev\n"); | 147 | "AES-CCM not supported by this mac rev\n"); |
148 | return false; | 148 | return false; |
149 | } | 149 | } |
@@ -152,15 +152,15 @@ static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry, | |||
152 | case ATH_CIPHER_TKIP: | 152 | case ATH_CIPHER_TKIP: |
153 | keyType = AR_KEYTABLE_TYPE_TKIP; | 153 | keyType = AR_KEYTABLE_TYPE_TKIP; |
154 | if (entry + 64 >= common->keymax) { | 154 | if (entry + 64 >= common->keymax) { |
155 | ath_dbg(common, ATH_DBG_ANY, | 155 | ath_dbg(common, ANY, |
156 | "entry %u inappropriate for TKIP\n", entry); | 156 | "entry %u inappropriate for TKIP\n", entry); |
157 | return false; | 157 | return false; |
158 | } | 158 | } |
159 | break; | 159 | break; |
160 | case ATH_CIPHER_WEP: | 160 | case ATH_CIPHER_WEP: |
161 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { | 161 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
162 | ath_dbg(common, ATH_DBG_ANY, | 162 | ath_dbg(common, ANY, "WEP key length %u too small\n", |
163 | "WEP key length %u too small\n", k->kv_len); | 163 | k->kv_len); |
164 | return false; | 164 | return false; |
165 | } | 165 | } |
166 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) | 166 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |