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authorSujith <Sujith.Manoharan@atheros.com>2009-08-07 00:15:13 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-14 09:13:15 -0400
commit6780ccf5652a04493f72fafd9af0d9964ee977ad (patch)
tree52da2e34c44a17b9461d0c347dd3540adf0f861a /drivers/net/wireless/ath
parentc16c9d0657268daaf8a03e7895fb5c5f005285db (diff)
ath9k: Remove a few DEBUG mesages
We have never used these at all. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath')
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c126
1 files changed, 23 insertions, 103 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 4303a4d88288..79310225d3ab 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -236,9 +236,6 @@ static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
236 pPDADCValues[i] = 0xFF; 236 pPDADCValues[i] = 0xFF;
237} 237}
238 238
239
240
241
242static void ath9k_hw_get_target_powers(struct ath_hw *ah, 239static void ath9k_hw_get_target_powers(struct ath_hw *ah,
243 struct ath9k_channel *chan, 240 struct ath9k_channel *chan,
244 struct cal_target_power_ht *powInfo, 241 struct cal_target_power_ht *powInfo,
@@ -905,20 +902,8 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
905 ah->eep_ops->get_eeprom_rev(ah) <= 2) 902 ah->eep_ops->get_eeprom_rev(ah) <= 2)
906 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 903 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
907 904
908 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
909 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
910 "EXT_ADDITIVE %d\n",
911 ctlMode, numCtlModes, isHt40CtlMode,
912 (pCtlMode[ctlMode] & EXT_ADDITIVE));
913
914 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && 905 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
915 pEepData->ctlIndex[i]; i++) { 906 pEepData->ctlIndex[i]; i++) {
916 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
917 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
918 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
919 "chan %d\n",
920 i, cfgCtl, pCtlMode[ctlMode],
921 pEepData->ctlIndex[i], chan->channel);
922 907
923 if ((((cfgCtl & ~CTL_MODE_M) | 908 if ((((cfgCtl & ~CTL_MODE_M) |
924 (pCtlMode[ctlMode] & CTL_MODE_M)) == 909 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
@@ -936,13 +921,6 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
936 IS_CHAN_2GHZ(chan), 921 IS_CHAN_2GHZ(chan),
937 AR5416_EEP4K_NUM_BAND_EDGES); 922 AR5416_EEP4K_NUM_BAND_EDGES);
938 923
939 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
940 " MATCH-EE_IDX %d: ch %d is2 %d "
941 "2xMinEdge %d chainmask %d chains %d\n",
942 i, freq, IS_CHAN_2GHZ(chan),
943 twiceMinEdgePower, tx_chainmask,
944 ar5416_get_ntxchains
945 (tx_chainmask));
946 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 924 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
947 twiceMaxEdgePower = 925 twiceMaxEdgePower =
948 min(twiceMaxEdgePower, 926 min(twiceMaxEdgePower,
@@ -956,12 +934,6 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
956 934
957 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 935 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
958 936
959 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
960 " SEL-Min ctlMode %d pCtlMode %d "
961 "2xMaxEdge %d sP %d minCtlPwr %d\n",
962 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
963 scaledPower, minCtlPower);
964
965 switch (pCtlMode[ctlMode]) { 937 switch (pCtlMode[ctlMode]) {
966 case CTL_11B: 938 case CTL_11B:
967 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); 939 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
@@ -2491,20 +2463,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2491 ah->eep_ops->get_eeprom_rev(ah) <= 2) 2463 ah->eep_ops->get_eeprom_rev(ah) <= 2)
2492 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 2464 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2493 2465
2494 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2495 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2496 "EXT_ADDITIVE %d\n",
2497 ctlMode, numCtlModes, isHt40CtlMode,
2498 (pCtlMode[ctlMode] & EXT_ADDITIVE));
2499
2500 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 2466 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2501 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2502 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2503 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2504 "chan %d\n",
2505 i, cfgCtl, pCtlMode[ctlMode],
2506 pEepData->ctlIndex[i], chan->channel);
2507
2508 if ((((cfgCtl & ~CTL_MODE_M) | 2467 if ((((cfgCtl & ~CTL_MODE_M) |
2509 (pCtlMode[ctlMode] & CTL_MODE_M)) == 2468 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2510 pEepData->ctlIndex[i]) || 2469 pEepData->ctlIndex[i]) ||
@@ -2517,13 +2476,6 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2517 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], 2476 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2518 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); 2477 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2519 2478
2520 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2521 " MATCH-EE_IDX %d: ch %d is2 %d "
2522 "2xMinEdge %d chainmask %d chains %d\n",
2523 i, freq, IS_CHAN_2GHZ(chan),
2524 twiceMinEdgePower, tx_chainmask,
2525 ar5416_get_ntxchains
2526 (tx_chainmask));
2527 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 2479 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2528 twiceMaxEdgePower = min(twiceMaxEdgePower, 2480 twiceMaxEdgePower = min(twiceMaxEdgePower,
2529 twiceMinEdgePower); 2481 twiceMinEdgePower);
@@ -2536,12 +2488,6 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2536 2488
2537 minCtlPower = min(twiceMaxEdgePower, scaledPower); 2489 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2538 2490
2539 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2540 " SEL-Min ctlMode %d pCtlMode %d "
2541 "2xMaxEdge %d sP %d minCtlPwr %d\n",
2542 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
2543 scaledPower, minCtlPower);
2544
2545 switch (pCtlMode[ctlMode]) { 2491 switch (pCtlMode[ctlMode]) {
2546 case CTL_11B: 2492 case CTL_11B:
2547 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { 2493 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
@@ -2898,17 +2844,15 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
2898 2844
2899 if (!ath9k_hw_use_flash(ah)) { 2845 if (!ath9k_hw_use_flash(ah)) {
2900 if (!ath9k_hw_nvram_read 2846 if (!ath9k_hw_nvram_read
2901 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 2847 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
2902 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2848 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2903 "Reading Magic # failed\n"); 2849 "Reading Magic # failed\n");
2904 return false; 2850 return false;
2905 } 2851 }
2906 2852
2907 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2853 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2908 "Read Magic = 0x%04X\n", magic); 2854 "Read Magic = 0x%04X\n", magic);
2909 if (magic != AR5416_EEPROM_MAGIC) { 2855 if (magic != AR5416_EEPROM_MAGIC) {
2910
2911
2912 magic2 = swab16(magic); 2856 magic2 = swab16(magic);
2913 2857
2914 if (magic2 == AR5416_EEPROM_MAGIC) { 2858 if (magic2 == AR5416_EEPROM_MAGIC) {
@@ -2924,13 +2868,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
2924 } 2868 }
2925 } else { 2869 } else {
2926 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2870 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2927 "Invalid EEPROM Magic. " 2871 "Invalid EEPROM Magic. "
2928 "endianness mismatch.\n"); 2872 "endianness mismatch.\n");
2929 return -EINVAL; } 2873 return -EINVAL;
2874 }
2930 } 2875 }
2931 } 2876 }
2932 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? 2877 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
2933 "True" : "False"); 2878 "True" : "False");
2934 2879
2935 if (need_swap) 2880 if (need_swap)
2936 el = swab16(ah->eeprom.map9287.baseEepHeader.length); 2881 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -3360,19 +3305,19 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
3360 3305
3361 if (i == 0) { 3306 if (i == 0) {
3362 if (!ath9k_hw_AR9287_get_eeprom( 3307 if (!ath9k_hw_AR9287_get_eeprom(
3363 ah, EEP_OL_PWRCTRL)) { 3308 ah, EEP_OL_PWRCTRL)) {
3364 REG_WRITE(ah, AR_PHY_TPCRG5 + 3309 REG_WRITE(ah, AR_PHY_TPCRG5 +
3365 regChainOffset, 3310 regChainOffset,
3366 SM(pdGainOverlap_t2, 3311 SM(pdGainOverlap_t2,
3367 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 3312 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
3368 SM(gainBoundaries[0], 3313 SM(gainBoundaries[0],
3369 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) 3314 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3370 | SM(gainBoundaries[1], 3315 | SM(gainBoundaries[1],
3371 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) 3316 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3372 | SM(gainBoundaries[2], 3317 | SM(gainBoundaries[2],
3373 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) 3318 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3374 | SM(gainBoundaries[3], 3319 | SM(gainBoundaries[3],
3375 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 3320 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3376 } 3321 }
3377 } 3322 }
3378 3323
@@ -3394,6 +3339,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
3394 pdadcValues[ 3339 pdadcValues[
3395 AR9287_NUM_PDADC_VALUES-diff]; 3340 AR9287_NUM_PDADC_VALUES-diff];
3396 } 3341 }
3342
3397 if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { 3343 if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
3398 regOffset = AR_PHY_BASE + (672 << 2) + 3344 regOffset = AR_PHY_BASE + (672 << 2) +
3399 regChainOffset; 3345 regChainOffset;
@@ -3412,6 +3358,7 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
3412 "PDADC (%d,%4x): %4.4x %8.8x\n", 3358 "PDADC (%d,%4x): %4.4x %8.8x\n",
3413 i, regChainOffset, regOffset, 3359 i, regChainOffset, regOffset,
3414 reg32); 3360 reg32);
3361
3415 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 3362 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3416 "PDADC: Chain %d | " 3363 "PDADC: Chain %d | "
3417 "PDADC %3d Value %3d | " 3364 "PDADC %3d Value %3d | "
@@ -3542,20 +3489,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3542 ah->eep_ops->get_eeprom_rev(ah) <= 2) 3489 ah->eep_ops->get_eeprom_rev(ah) <= 2)
3543 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 3490 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
3544 3491
3545 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 3492 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
3546 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d,"
3547 "EXT_ADDITIVE %d\n", ctlMode, numCtlModes,
3548 isHt40CtlMode, (pCtlMode[ctlMode] & EXT_ADDITIVE));
3549
3550 for (i = 0; (i < AR9287_NUM_CTLS)
3551 && pEepData->ctlIndex[i]; i++) {
3552 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3553 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x"
3554 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x"
3555 "chan %d chanctl=xxxx\n",
3556 i, cfgCtl, pCtlMode[ctlMode],
3557 pEepData->ctlIndex[i], chan->channel);
3558
3559 if ((((cfgCtl & ~CTL_MODE_M) | 3493 if ((((cfgCtl & ~CTL_MODE_M) |
3560 (pCtlMode[ctlMode] & CTL_MODE_M)) == 3494 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
3561 pEepData->ctlIndex[i]) || 3495 pEepData->ctlIndex[i]) ||
@@ -3571,13 +3505,6 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3571 tx_chainmask) - 1], 3505 tx_chainmask) - 1],
3572 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); 3506 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
3573 3507
3574 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3575 "MATCH-EE_IDX %d: ch %d is2 %d"
3576 "2xMinEdge %d chainmask %d chains %d\n",
3577 i, freq, IS_CHAN_2GHZ(chan),
3578 twiceMinEdgePower, tx_chainmask,
3579 ar5416_get_ntxchains(tx_chainmask));
3580
3581 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) 3508 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
3582 twiceMaxEdgePower = min( 3509 twiceMaxEdgePower = min(
3583 twiceMaxEdgePower, 3510 twiceMaxEdgePower,
@@ -3591,14 +3518,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3591 3518
3592 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); 3519 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
3593 3520
3594 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3595 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d"
3596 "sP %d minCtlPwr %d\n",
3597 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
3598 scaledPower, minCtlPower);
3599
3600 switch (pCtlMode[ctlMode]) { 3521 switch (pCtlMode[ctlMode]) {
3601
3602 case CTL_11B: 3522 case CTL_11B:
3603 for (i = 0; 3523 for (i = 0;
3604 i < ARRAY_SIZE(targetPowerCck.tPow2x); 3524 i < ARRAY_SIZE(targetPowerCck.tPow2x);
@@ -3670,7 +3590,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3670 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 3590 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
3671 3591
3672 if (IS_CHAN_2GHZ(chan)) { 3592 if (IS_CHAN_2GHZ(chan)) {
3673 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 3593 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
3674 ratesArray[rate2s] = ratesArray[rate2l] = 3594 ratesArray[rate2s] = ratesArray[rate2l] =
3675 targetPowerCck.tPow2x[1]; 3595 targetPowerCck.tPow2x[1];
3676 ratesArray[rate5_5s] = ratesArray[rate5_5l] = 3596 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
@@ -3686,7 +3606,7 @@ static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3686 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 3606 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
3687 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 3607 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
3688 if (IS_CHAN_2GHZ(chan)) 3608 if (IS_CHAN_2GHZ(chan))
3689 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 3609 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
3690 } 3610 }
3691 3611
3692#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN 3612#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 01:52:04 -0500