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authorSujith <Sujith.Manoharan@atheros.com>2008-08-11 04:34:32 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-08-29 16:23:56 -0400
commit6a2b9e8c8f4be9954933051719b312adcfb7263d (patch)
tree71c869c2694117ba0c591df6f0c49a20eb07eb09 /drivers/net/wireless/ath9k
parentd2d80ee9c6ae3d60bcbffb200959db645f5a558f (diff)
ath9k: Unused macros, variables
Signed-off-by: Sujith Manoharan <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k')
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h18
-rw-r--r--drivers/net/wireless/ath9k/hw.h116
2 files changed, 50 insertions, 84 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index d1b0fbae5a32..3e7072dcb439 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -790,19 +790,20 @@ struct ath_hal {
790 u32 ah_magic; 790 u32 ah_magic;
791 u16 ah_devid; 791 u16 ah_devid;
792 u16 ah_subvendorid; 792 u16 ah_subvendorid;
793 struct ath_softc *ah_sc;
794 void __iomem *ah_sh;
795 u16 ah_countryCode;
796 u32 ah_macVersion; 793 u32 ah_macVersion;
797 u16 ah_macRev; 794 u16 ah_macRev;
798 u16 ah_phyRev; 795 u16 ah_phyRev;
799 u16 ah_analog5GhzRev; 796 u16 ah_analog5GhzRev;
800 u16 ah_analog2GhzRev; 797 u16 ah_analog2GhzRev;
801 u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE]; 798
802 u32 ah_flags; 799 void __iomem *ah_sh;
800 struct ath_softc *ah_sc;
803 enum ath9k_opmode ah_opmode; 801 enum ath9k_opmode ah_opmode;
804 struct ath9k_ops_config ah_config; 802 struct ath9k_ops_config ah_config;
805 struct ath9k_hw_capabilities ah_caps; 803 struct ath9k_hw_capabilities ah_caps;
804
805 u16 ah_countryCode;
806 u32 ah_flags;
806 int16_t ah_powerLimit; 807 int16_t ah_powerLimit;
807 u16 ah_maxPowerLevel; 808 u16 ah_maxPowerLevel;
808 u32 ah_tpScale; 809 u32 ah_tpScale;
@@ -812,15 +813,16 @@ struct ath_hal {
812 u16 ah_currentRD5G; 813 u16 ah_currentRD5G;
813 u16 ah_currentRD2G; 814 u16 ah_currentRD2G;
814 char ah_iso[4]; 815 char ah_iso[4];
815 enum start_adhoc_option ah_adHocMode; 816
816 bool ah_commonMode;
817 struct ath9k_channel ah_channels[150]; 817 struct ath9k_channel ah_channels[150];
818 u32 ah_nchan;
819 struct ath9k_channel *ah_curchan; 818 struct ath9k_channel *ah_curchan;
819 u32 ah_nchan;
820
820 u16 ah_rfsilent; 821 u16 ah_rfsilent;
821 bool ah_rfkillEnabled; 822 bool ah_rfkillEnabled;
822 bool ah_isPciExpress; 823 bool ah_isPciExpress;
823 u16 ah_txTrigLevel; 824 u16 ah_txTrigLevel;
825
824#ifndef ATH_NF_PER_CHAN 826#ifndef ATH_NF_PER_CHAN
825 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; 827 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
826#endif 828#endif
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index ae680f21ba7e..5cb3912ad392 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -314,14 +314,11 @@ struct ar5416_desc {
314#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ 314#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
315 MS(ads->ds_rxstatus0, AR_RxRate) : \ 315 MS(ads->ds_rxstatus0, AR_RxRate) : \
316 (ads->ds_rxstatus3 >> 2) & 0xFF) 316 (ads->ds_rxstatus3 >> 2) & 0xFF)
317#define RXSTATUS_DUPLICATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
318 MS(ads->ds_rxstatus3, AR_Parallel40) : \
319 (ads->ds_rxstatus3 >> 10) & 0x1)
320 317
321#define set11nTries(_series, _index) \ 318#define set11nTries(_series, _index) \
322 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 319 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
323 320
324#define set11nRate(_series, _index) \ 321#define set11nRate(_series, _index) \
325 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 322 (SM((_series)[_index].Rate, AR_XmitRate##_index))
326 323
327#define set11nPktDurRTSCTS(_series, _index) \ 324#define set11nPktDurRTSCTS(_series, _index) \
@@ -330,11 +327,11 @@ struct ar5416_desc {
330 AR_RTSCTSQual##_index : 0)) 327 AR_RTSCTSQual##_index : 0))
331 328
332#define set11nRateFlags(_series, _index) \ 329#define set11nRateFlags(_series, _index) \
333 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 330 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
334 AR_2040_##_index : 0) \ 331 AR_2040_##_index : 0) \
335 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 332 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
336 AR_GI##_index : 0) \ 333 AR_GI##_index : 0) \
337 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 334 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
338 335
339#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) 336#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100)
340 337
@@ -346,9 +343,6 @@ struct ar5416_desc {
346#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 343#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
347#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 344#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
348 345
349#define NUM_CORNER_FIX_BITS_2133 7
350#define CCK_OFDM_GAIN_DELTA 15
351
352struct ar5416AniState { 346struct ar5416AniState {
353 struct ath9k_channel c; 347 struct ath9k_channel c;
354 u8 noiseImmunityLevel; 348 u8 noiseImmunityLevel;
@@ -377,11 +371,8 @@ struct ar5416AniState {
377}; 371};
378 372
379#define HAL_PROCESS_ANI 0x00000001 373#define HAL_PROCESS_ANI 0x00000001
380#define HAL_RADAR_EN 0x80000000
381#define HAL_AR_EN 0x40000000
382
383#define DO_ANI(ah) \ 374#define DO_ANI(ah) \
384 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) 375 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
385 376
386struct ar5416Stats { 377struct ar5416Stats {
387 u32 ast_ani_niup; 378 u32 ast_ani_niup;
@@ -425,7 +416,6 @@ struct ar5416Stats {
425#define AR5416_EEP_MINOR_VER_7 0x7 416#define AR5416_EEP_MINOR_VER_7 0x7
426#define AR5416_EEP_MINOR_VER_9 0x9 417#define AR5416_EEP_MINOR_VER_9 0x9
427 418
428#define AR5416_EEP_START_LOC 256
429#define AR5416_NUM_5G_CAL_PIERS 8 419#define AR5416_NUM_5G_CAL_PIERS 8
430#define AR5416_NUM_2G_CAL_PIERS 4 420#define AR5416_NUM_2G_CAL_PIERS 4
431#define AR5416_NUM_5G_20_TARGET_POWERS 8 421#define AR5416_NUM_5G_20_TARGET_POWERS 8
@@ -441,25 +431,10 @@ struct ar5416Stats {
441#define AR5416_EEPROM_MODAL_SPURS 5 431#define AR5416_EEPROM_MODAL_SPURS 5
442#define AR5416_MAX_RATE_POWER 63 432#define AR5416_MAX_RATE_POWER 63
443#define AR5416_NUM_PDADC_VALUES 128 433#define AR5416_NUM_PDADC_VALUES 128
444#define AR5416_NUM_RATES 16
445#define AR5416_BCHAN_UNUSED 0xFF 434#define AR5416_BCHAN_UNUSED 0xFF
446#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 435#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
447#define AR5416_EEPMISC_BIG_ENDIAN 0x01
448#define AR5416_MAX_CHAINS 3 436#define AR5416_MAX_CHAINS 3
449#define AR5416_ANT_16S 25
450
451#define AR5416_NUM_ANT_CHAIN_FIELDS 7
452#define AR5416_NUM_ANT_COMMON_FIELDS 4
453#define AR5416_SIZE_ANT_CHAIN_FIELD 3
454#define AR5416_SIZE_ANT_COMMON_FIELD 4
455#define AR5416_ANT_CHAIN_MASK 0x7
456#define AR5416_ANT_COMMON_MASK 0xf
457#define AR5416_CHAIN_0_IDX 0
458#define AR5416_CHAIN_1_IDX 1
459#define AR5416_CHAIN_2_IDX 2
460
461#define AR5416_PWR_TABLE_OFFSET -5 437#define AR5416_PWR_TABLE_OFFSET -5
462#define AR5416_LEGACY_CHAINMASK 1
463 438
464enum eeprom_param { 439enum eeprom_param {
465 EEP_NFTHRESH_5, 440 EEP_NFTHRESH_5,
@@ -633,7 +608,7 @@ struct ar5416IniArray {
633}; 608};
634 609
635#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 610#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
636 (iniarray)->ia_array = (u32 *)(array); \ 611 (iniarray)->ia_array = (u32 *)(array); \
637 (iniarray)->ia_rows = (rows); \ 612 (iniarray)->ia_rows = (rows); \
638 (iniarray)->ia_columns = (columns); \ 613 (iniarray)->ia_columns = (columns); \
639 } while (0) 614 } while (0)
@@ -641,16 +616,16 @@ struct ar5416IniArray {
641#define INI_RA(iniarray, row, column) \ 616#define INI_RA(iniarray, row, column) \
642 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 617 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
643 618
644#define INIT_CAL(_perCal) do { \ 619#define INIT_CAL(_perCal) do { \
645 (_perCal)->calState = CAL_WAITING; \ 620 (_perCal)->calState = CAL_WAITING; \
646 (_perCal)->calNext = NULL; \ 621 (_perCal)->calNext = NULL; \
647 } while (0) 622 } while (0)
648 623
649#define INSERT_CAL(_ahp, _perCal) \ 624#define INSERT_CAL(_ahp, _perCal) \
650 do { \ 625 do { \
651 if ((_ahp)->ah_cal_list_last == NULL) { \ 626 if ((_ahp)->ah_cal_list_last == NULL) { \
652 (_ahp)->ah_cal_list = \ 627 (_ahp)->ah_cal_list = \
653 (_ahp)->ah_cal_list_last = (_perCal); \ 628 (_ahp)->ah_cal_list_last = (_perCal); \
654 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ 629 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
655 } else { \ 630 } else { \
656 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ 631 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
@@ -696,25 +671,29 @@ struct hal_cal_list {
696struct ath_hal_5416 { 671struct ath_hal_5416 {
697 struct ath_hal ah; 672 struct ath_hal ah;
698 struct ar5416_eeprom ah_eeprom; 673 struct ar5416_eeprom ah_eeprom;
674 struct ar5416Stats ah_stats;
675 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
676 void __iomem *ah_cal_mem;
677
699 u8 ah_macaddr[ETH_ALEN]; 678 u8 ah_macaddr[ETH_ALEN];
700 u8 ah_bssid[ETH_ALEN]; 679 u8 ah_bssid[ETH_ALEN];
701 u8 ah_bssidmask[ETH_ALEN]; 680 u8 ah_bssidmask[ETH_ALEN];
702 u16 ah_assocId; 681 u16 ah_assocId;
682
703 int16_t ah_curchanRadIndex; 683 int16_t ah_curchanRadIndex;
704 u32 ah_maskReg; 684 u32 ah_maskReg;
705 struct ar5416Stats ah_stats;
706 u32 ah_txDescMask;
707 u32 ah_txOkInterruptMask; 685 u32 ah_txOkInterruptMask;
708 u32 ah_txErrInterruptMask; 686 u32 ah_txErrInterruptMask;
709 u32 ah_txDescInterruptMask; 687 u32 ah_txDescInterruptMask;
710 u32 ah_txEolInterruptMask; 688 u32 ah_txEolInterruptMask;
711 u32 ah_txUrnInterruptMask; 689 u32 ah_txUrnInterruptMask;
712 struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];
713 enum ath9k_power_mode ah_powerMode;
714 bool ah_chipFullSleep; 690 bool ah_chipFullSleep;
715 u32 ah_atimWindow; 691 u32 ah_atimWindow;
716 enum ath9k_ant_setting ah_diversityControl;
717 u16 ah_antennaSwitchSwap; 692 u16 ah_antennaSwitchSwap;
693 enum ath9k_power_mode ah_powerMode;
694 enum ath9k_ant_setting ah_diversityControl;
695
696 /* Calibration */
718 enum hal_cal_types ah_suppCals; 697 enum hal_cal_types ah_suppCals;
719 struct hal_cal_list ah_iqCalData; 698 struct hal_cal_list ah_iqCalData;
720 struct hal_cal_list ah_adcGainCalData; 699 struct hal_cal_list ah_adcGainCalData;
@@ -751,16 +730,16 @@ struct ath_hal_5416 {
751 int32_t sign[AR5416_MAX_CHAINS]; 730 int32_t sign[AR5416_MAX_CHAINS];
752 } ah_Meas3; 731 } ah_Meas3;
753 u16 ah_CalSamples; 732 u16 ah_CalSamples;
754 u32 ah_tx6PowerInHalfDbm; 733
755 u32 ah_staId1Defaults; 734 u32 ah_staId1Defaults;
756 u32 ah_miscMode; 735 u32 ah_miscMode;
757 bool ah_tpcEnabled;
758 u32 ah_beaconInterval;
759 enum { 736 enum {
760 AUTO_32KHZ, 737 AUTO_32KHZ,
761 USE_32KHZ, 738 USE_32KHZ,
762 DONT_USE_32KHZ, 739 DONT_USE_32KHZ,
763 } ah_enable32kHzClock; 740 } ah_enable32kHzClock;
741
742 /* RF */
764 u32 *ah_analogBank0Data; 743 u32 *ah_analogBank0Data;
765 u32 *ah_analogBank1Data; 744 u32 *ah_analogBank1Data;
766 u32 *ah_analogBank2Data; 745 u32 *ah_analogBank2Data;
@@ -770,8 +749,9 @@ struct ath_hal_5416 {
770 u32 *ah_analogBank7Data; 749 u32 *ah_analogBank7Data;
771 u32 *ah_addac5416_21; 750 u32 *ah_addac5416_21;
772 u32 *ah_bank6Temp; 751 u32 *ah_bank6Temp;
773 u32 ah_ofdmTxPower; 752
774 int16_t ah_txPowerIndexOffset; 753 int16_t ah_txPowerIndexOffset;
754 u32 ah_beaconInterval;
775 u32 ah_slottime; 755 u32 ah_slottime;
776 u32 ah_acktimeout; 756 u32 ah_acktimeout;
777 u32 ah_ctstimeout; 757 u32 ah_ctstimeout;
@@ -780,7 +760,8 @@ struct ath_hal_5416 {
780 u32 ah_gpioSelect; 760 u32 ah_gpioSelect;
781 u32 ah_polarity; 761 u32 ah_polarity;
782 u32 ah_gpioBit; 762 u32 ah_gpioBit;
783 bool ah_eepEnabled; 763
764 /* ANI */
784 u32 ah_procPhyErr; 765 u32 ah_procPhyErr;
785 bool ah_hasHwPhyCounters; 766 bool ah_hasHwPhyCounters;
786 u32 ah_aniPeriod; 767 u32 ah_aniPeriod;
@@ -790,18 +771,14 @@ struct ath_hal_5416 {
790 int ah_coarseHigh[5]; 771 int ah_coarseHigh[5];
791 int ah_coarseLow[5]; 772 int ah_coarseLow[5];
792 int ah_firpwr[5]; 773 int ah_firpwr[5];
793 u16 ah_ratesArray[16]; 774 enum ath9k_ani_cmd ah_ani_function;
775
794 u32 ah_intrTxqs; 776 u32 ah_intrTxqs;
795 bool ah_intrMitigation; 777 bool ah_intrMitigation;
796 u32 ah_cycleCount;
797 u32 ah_ctlBusy;
798 u32 ah_extBusy;
799 enum ath9k_ht_extprotspacing ah_extprotspacing; 778 enum ath9k_ht_extprotspacing ah_extprotspacing;
800 u8 ah_txchainmask; 779 u8 ah_txchainmask;
801 u8 ah_rxchainmask; 780 u8 ah_rxchainmask;
802 int ah_hwp; 781
803 void __iomem *ah_cal_mem;
804 enum ath9k_ani_cmd ah_ani_function;
805 struct ar5416IniArray ah_iniModes; 782 struct ar5416IniArray ah_iniModes;
806 struct ar5416IniArray ah_iniCommon; 783 struct ar5416IniArray ah_iniCommon;
807 struct ar5416IniArray ah_iniBank0; 784 struct ar5416IniArray ah_iniBank0;
@@ -820,10 +797,6 @@ struct ath_hal_5416 {
820 797
821#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 798#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
822 799
823#define IS_5416_EMU(ah) \
824 ((ah->ah_devid == AR5416_DEVID_EMU) || \
825 (ah->ah_devid == AR5416_DEVID_EMU_PCIE))
826
827#define ar5416RfDetach(ah) do { \ 800#define ar5416RfDetach(ah) do { \
828 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \ 801 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \
829 AH5416(ah)->ah_rfHal.rfDetach(ah); \ 802 AH5416(ah)->ah_rfHal.rfDetach(ah); \
@@ -841,8 +814,8 @@ struct ath_hal_5416 {
841#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 814#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
842 int r; \ 815 int r; \
843 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 816 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
844 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ 817 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
845 INI_RA((iniarray), r, (column))); \ 818 INI_RA((iniarray), r, (column))); \
846 DO_DELAY(regWr); \ 819 DO_DELAY(regWr); \
847 } \ 820 } \
848 } while (0) 821 } while (0)
@@ -860,22 +833,17 @@ struct ath_hal_5416 {
860 833
861#define AR5416_EEPROM_S 2 834#define AR5416_EEPROM_S 2
862#define AR5416_EEPROM_OFFSET 0x2000 835#define AR5416_EEPROM_OFFSET 0x2000
863#define AR5416_EEPROM_START_ADDR \ 836#define AR5416_EEPROM_START_ADDR \
864 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 837 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
865#define AR5416_EEPROM_MAX 0xae0 838#define AR5416_EEPROM_MAX 0xae0
866#define ar5416_get_eep_ver(_ahp) \ 839#define ar5416_get_eep_ver(_ahp) \
867 (((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF) 840 (((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF)
868#define ar5416_get_eep_rev(_ahp) \ 841#define ar5416_get_eep_rev(_ahp) \
869 (((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF) 842 (((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF)
870#define ar5416_get_ntxchains(_txchainmask) \ 843#define ar5416_get_ntxchains(_txchainmask) \
871 (((_txchainmask >> 2) & 1) + \ 844 (((_txchainmask >> 2) & 1) + \
872 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 845 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
873 846
874#define IS_EEP_MINOR_V3(_ahp) \
875 (ath9k_hw_get_eeprom((_ahp), EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_3)
876
877#define FIXED_CCA_THRESHOLD 15
878
879#ifdef __BIG_ENDIAN 847#ifdef __BIG_ENDIAN
880#define AR5416_EEPROM_MAGIC 0x5aa5 848#define AR5416_EEPROM_MAGIC 0x5aa5
881#else 849#else
@@ -910,8 +878,6 @@ struct ath_hal_5416 {
910#define AR_GPIOD_MASK 0x00001FFF 878#define AR_GPIOD_MASK 0x00001FFF
911#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 879#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
912 880
913#define MAX_ANALOG_START 319
914
915#define HAL_EP_RND(x, mul) \ 881#define HAL_EP_RND(x, mul) \
916 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 882 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
917#define BEACON_RSSI(ahp) \ 883#define BEACON_RSSI(ahp) \
@@ -923,8 +889,6 @@ struct ath_hal_5416 {
923#define AH_TIMEOUT 100000 889#define AH_TIMEOUT 100000
924#define AH_TIME_QUANTUM 10 890#define AH_TIME_QUANTUM 10
925 891
926#define IS(_c, _f) (((_c)->channelFlags & _f) || 0)
927
928#define AR_KEYTABLE_SIZE 128 892#define AR_KEYTABLE_SIZE 128
929#define POWER_UP_TIME 200000 893#define POWER_UP_TIME 200000
930 894
@@ -964,6 +928,6 @@ struct ath_hal_5416 {
964#define OFDM_SYMBOL_TIME_QUARTER 16 928#define OFDM_SYMBOL_TIME_QUARTER 16
965 929
966u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp, 930u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
967 enum eeprom_param param); 931 enum eeprom_param param);
968 932
969#endif 933#endif