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authorSujith <Sujith.Manoharan@atheros.com>2009-02-09 02:57:12 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-13 13:45:05 -0500
commitcbe61d8a41210600bc76b212edcd4dc0f55c014f (patch)
treed8bd8e43d3556c58d410f1bef0d2ca3bf7d75c92 /drivers/net/wireless/ath9k/phy.c
parentba52da58be0acf3b7775972b2b5234ce64388c79 (diff)
ath9k: Merge ath_hal and ath_hal_5416 structures
Finally, merge these structures and have a single HW specific data structure. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/phy.c')
-rw-r--r--drivers/net/wireless/ath9k/phy.c194
1 files changed, 91 insertions, 103 deletions
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index ea29941412d4..da4165b8d6be 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -17,16 +17,14 @@
17#include "ath9k.h" 17#include "ath9k.h"
18 18
19void 19void
20ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, 20ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex,
21 int regWrites) 21 int regWrites)
22{ 22{
23 struct ath_hal_5416 *ahp = AH5416(ah); 23 REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites);
24
25 REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites);
26} 24}
27 25
28bool 26bool
29ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) 27ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
30{ 28{
31 u32 channelSel = 0; 29 u32 channelSel = 0;
32 u32 bModeSynth = 0; 30 u32 bModeSynth = 0;
@@ -93,14 +91,13 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
93 REG_WRITE(ah, AR_PHY(0x37), reg32); 91 REG_WRITE(ah, AR_PHY(0x37), reg32);
94 92
95 ah->ah_curchan = chan; 93 ah->ah_curchan = chan;
96 94 ah->ah_curchanRadIndex = -1;
97 AH5416(ah)->ah_curchanRadIndex = -1;
98 95
99 return true; 96 return true;
100} 97}
101 98
102bool 99bool
103ath9k_hw_ar9280_set_channel(struct ath_hal *ah, 100ath9k_hw_ar9280_set_channel(struct ath_hw *ah,
104 struct ath9k_channel *chan) 101 struct ath9k_channel *chan)
105{ 102{
106 u16 bMode, fracMode, aModeRefSel = 0; 103 u16 bMode, fracMode, aModeRefSel = 0;
@@ -164,8 +161,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah,
164 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 161 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
165 162
166 ah->ah_curchan = chan; 163 ah->ah_curchan = chan;
167 164 ah->ah_curchanRadIndex = -1;
168 AH5416(ah)->ah_curchanRadIndex = -1;
169 165
170 return true; 166 return true;
171} 167}
@@ -198,11 +194,9 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
198} 194}
199 195
200bool 196bool
201ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, 197ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
202 u16 modesIndex) 198 u16 modesIndex)
203{ 199{
204 struct ath_hal_5416 *ahp = AH5416(ah);
205
206 u32 eepMinorRev; 200 u32 eepMinorRev;
207 u32 ob5GHz = 0, db5GHz = 0; 201 u32 ob5GHz = 0, db5GHz = 0;
208 u32 ob2GHz = 0, db2GHz = 0; 202 u32 ob2GHz = 0, db2GHz = 0;
@@ -213,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
213 207
214 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); 208 eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV);
215 209
216 RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1); 210 RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1);
217 211
218 RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1); 212 RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1);
219 213
220 RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1); 214 RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1);
221 215
222 RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3, 216 RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3,
223 modesIndex); 217 modesIndex);
224 { 218 {
225 int i; 219 int i;
226 for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) { 220 for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) {
227 ahp->ah_analogBank6Data[i] = 221 ah->ah_analogBank6Data[i] =
228 INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex); 222 INI_RA(&ah->ah_iniBank6TPC, i, modesIndex);
229 } 223 }
230 } 224 }
231 225
@@ -233,137 +227,132 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan,
233 if (IS_CHAN_2GHZ(chan)) { 227 if (IS_CHAN_2GHZ(chan)) {
234 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); 228 ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2);
235 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); 229 db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2);
236 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 230 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
237 ob2GHz, 3, 197, 0); 231 ob2GHz, 3, 197, 0);
238 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 232 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
239 db2GHz, 3, 194, 0); 233 db2GHz, 3, 194, 0);
240 } else { 234 } else {
241 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); 235 ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5);
242 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); 236 db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5);
243 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 237 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
244 ob5GHz, 3, 203, 0); 238 ob5GHz, 3, 203, 0);
245 ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, 239 ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data,
246 db5GHz, 3, 200, 0); 240 db5GHz, 3, 200, 0);
247 } 241 }
248 } 242 }
249 243
250 RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1); 244 RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1);
251 245
252 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data, 246 REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data,
253 regWrites); 247 regWrites);
254 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data, 248 REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data,
255 regWrites); 249 regWrites);
256 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data, 250 REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data,
257 regWrites); 251 regWrites);
258 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data, 252 REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data,
259 regWrites); 253 regWrites);
260 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data, 254 REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data,
261 regWrites); 255 regWrites);
262 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data, 256 REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data,
263 regWrites); 257 regWrites);
264 258
265 return true; 259 return true;
266} 260}
267 261
268void 262void
269ath9k_hw_rfdetach(struct ath_hal *ah) 263ath9k_hw_rfdetach(struct ath_hw *ah)
270{ 264{
271 struct ath_hal_5416 *ahp = AH5416(ah); 265 if (ah->ah_analogBank0Data != NULL) {
272 266 kfree(ah->ah_analogBank0Data);
273 if (ahp->ah_analogBank0Data != NULL) { 267 ah->ah_analogBank0Data = NULL;
274 kfree(ahp->ah_analogBank0Data);
275 ahp->ah_analogBank0Data = NULL;
276 } 268 }
277 if (ahp->ah_analogBank1Data != NULL) { 269 if (ah->ah_analogBank1Data != NULL) {
278 kfree(ahp->ah_analogBank1Data); 270 kfree(ah->ah_analogBank1Data);
279 ahp->ah_analogBank1Data = NULL; 271 ah->ah_analogBank1Data = NULL;
280 } 272 }
281 if (ahp->ah_analogBank2Data != NULL) { 273 if (ah->ah_analogBank2Data != NULL) {
282 kfree(ahp->ah_analogBank2Data); 274 kfree(ah->ah_analogBank2Data);
283 ahp->ah_analogBank2Data = NULL; 275 ah->ah_analogBank2Data = NULL;
284 } 276 }
285 if (ahp->ah_analogBank3Data != NULL) { 277 if (ah->ah_analogBank3Data != NULL) {
286 kfree(ahp->ah_analogBank3Data); 278 kfree(ah->ah_analogBank3Data);
287 ahp->ah_analogBank3Data = NULL; 279 ah->ah_analogBank3Data = NULL;
288 } 280 }
289 if (ahp->ah_analogBank6Data != NULL) { 281 if (ah->ah_analogBank6Data != NULL) {
290 kfree(ahp->ah_analogBank6Data); 282 kfree(ah->ah_analogBank6Data);
291 ahp->ah_analogBank6Data = NULL; 283 ah->ah_analogBank6Data = NULL;
292 } 284 }
293 if (ahp->ah_analogBank6TPCData != NULL) { 285 if (ah->ah_analogBank6TPCData != NULL) {
294 kfree(ahp->ah_analogBank6TPCData); 286 kfree(ah->ah_analogBank6TPCData);
295 ahp->ah_analogBank6TPCData = NULL; 287 ah->ah_analogBank6TPCData = NULL;
296 } 288 }
297 if (ahp->ah_analogBank7Data != NULL) { 289 if (ah->ah_analogBank7Data != NULL) {
298 kfree(ahp->ah_analogBank7Data); 290 kfree(ah->ah_analogBank7Data);
299 ahp->ah_analogBank7Data = NULL; 291 ah->ah_analogBank7Data = NULL;
300 } 292 }
301 if (ahp->ah_addac5416_21 != NULL) { 293 if (ah->ah_addac5416_21 != NULL) {
302 kfree(ahp->ah_addac5416_21); 294 kfree(ah->ah_addac5416_21);
303 ahp->ah_addac5416_21 = NULL; 295 ah->ah_addac5416_21 = NULL;
304 } 296 }
305 if (ahp->ah_bank6Temp != NULL) { 297 if (ah->ah_bank6Temp != NULL) {
306 kfree(ahp->ah_bank6Temp); 298 kfree(ah->ah_bank6Temp);
307 ahp->ah_bank6Temp = NULL; 299 ah->ah_bank6Temp = NULL;
308 } 300 }
309} 301}
310 302
311bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) 303bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
312{ 304{
313 struct ath_hal_5416 *ahp = AH5416(ah);
314
315 if (!AR_SREV_9280_10_OR_LATER(ah)) { 305 if (!AR_SREV_9280_10_OR_LATER(ah)) {
316 306 ah->ah_analogBank0Data =
317 ahp->ah_analogBank0Data =
318 kzalloc((sizeof(u32) * 307 kzalloc((sizeof(u32) *
319 ahp->ah_iniBank0.ia_rows), GFP_KERNEL); 308 ah->ah_iniBank0.ia_rows), GFP_KERNEL);
320 ahp->ah_analogBank1Data = 309 ah->ah_analogBank1Data =
321 kzalloc((sizeof(u32) * 310 kzalloc((sizeof(u32) *
322 ahp->ah_iniBank1.ia_rows), GFP_KERNEL); 311 ah->ah_iniBank1.ia_rows), GFP_KERNEL);
323 ahp->ah_analogBank2Data = 312 ah->ah_analogBank2Data =
324 kzalloc((sizeof(u32) * 313 kzalloc((sizeof(u32) *
325 ahp->ah_iniBank2.ia_rows), GFP_KERNEL); 314 ah->ah_iniBank2.ia_rows), GFP_KERNEL);
326 ahp->ah_analogBank3Data = 315 ah->ah_analogBank3Data =
327 kzalloc((sizeof(u32) * 316 kzalloc((sizeof(u32) *
328 ahp->ah_iniBank3.ia_rows), GFP_KERNEL); 317 ah->ah_iniBank3.ia_rows), GFP_KERNEL);
329 ahp->ah_analogBank6Data = 318 ah->ah_analogBank6Data =
330 kzalloc((sizeof(u32) * 319 kzalloc((sizeof(u32) *
331 ahp->ah_iniBank6.ia_rows), GFP_KERNEL); 320 ah->ah_iniBank6.ia_rows), GFP_KERNEL);
332 ahp->ah_analogBank6TPCData = 321 ah->ah_analogBank6TPCData =
333 kzalloc((sizeof(u32) * 322 kzalloc((sizeof(u32) *
334 ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL); 323 ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL);
335 ahp->ah_analogBank7Data = 324 ah->ah_analogBank7Data =
336 kzalloc((sizeof(u32) * 325 kzalloc((sizeof(u32) *
337 ahp->ah_iniBank7.ia_rows), GFP_KERNEL); 326 ah->ah_iniBank7.ia_rows), GFP_KERNEL);
338 327
339 if (ahp->ah_analogBank0Data == NULL 328 if (ah->ah_analogBank0Data == NULL
340 || ahp->ah_analogBank1Data == NULL 329 || ah->ah_analogBank1Data == NULL
341 || ahp->ah_analogBank2Data == NULL 330 || ah->ah_analogBank2Data == NULL
342 || ahp->ah_analogBank3Data == NULL 331 || ah->ah_analogBank3Data == NULL
343 || ahp->ah_analogBank6Data == NULL 332 || ah->ah_analogBank6Data == NULL
344 || ahp->ah_analogBank6TPCData == NULL 333 || ah->ah_analogBank6TPCData == NULL
345 || ahp->ah_analogBank7Data == NULL) { 334 || ah->ah_analogBank7Data == NULL) {
346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 335 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
347 "Cannot allocate RF banks\n"); 336 "Cannot allocate RF banks\n");
348 *status = -ENOMEM; 337 *status = -ENOMEM;
349 return false; 338 return false;
350 } 339 }
351 340
352 ahp->ah_addac5416_21 = 341 ah->ah_addac5416_21 =
353 kzalloc((sizeof(u32) * 342 kzalloc((sizeof(u32) *
354 ahp->ah_iniAddac.ia_rows * 343 ah->ah_iniAddac.ia_rows *
355 ahp->ah_iniAddac.ia_columns), GFP_KERNEL); 344 ah->ah_iniAddac.ia_columns), GFP_KERNEL);
356 if (ahp->ah_addac5416_21 == NULL) { 345 if (ah->ah_addac5416_21 == NULL) {
357 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 346 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
358 "Cannot allocate ah_addac5416_21\n"); 347 "Cannot allocate ah_addac5416_21\n");
359 *status = -ENOMEM; 348 *status = -ENOMEM;
360 return false; 349 return false;
361 } 350 }
362 351
363 ahp->ah_bank6Temp = 352 ah->ah_bank6Temp =
364 kzalloc((sizeof(u32) * 353 kzalloc((sizeof(u32) *
365 ahp->ah_iniBank6.ia_rows), GFP_KERNEL); 354 ah->ah_iniBank6.ia_rows), GFP_KERNEL);
366 if (ahp->ah_bank6Temp == NULL) { 355 if (ah->ah_bank6Temp == NULL) {
367 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 356 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
368 "Cannot allocate ah_bank6Temp\n"); 357 "Cannot allocate ah_bank6Temp\n");
369 *status = -ENOMEM; 358 *status = -ENOMEM;
@@ -375,23 +364,22 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
375} 364}
376 365
377void 366void
378ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) 367ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan)
379{ 368{
380 int i, regWrites = 0; 369 int i, regWrites = 0;
381 struct ath_hal_5416 *ahp = AH5416(ah);
382 u32 bank6SelMask; 370 u32 bank6SelMask;
383 u32 *bank6Temp = ahp->ah_bank6Temp; 371 u32 *bank6Temp = ah->ah_bank6Temp;
384 372
385 switch (ahp->ah_diversityControl) { 373 switch (ah->ah_diversityControl) {
386 case ATH9K_ANT_FIXED_A: 374 case ATH9K_ANT_FIXED_A:
387 bank6SelMask = 375 bank6SelMask =
388 (ahp-> 376 (ah->
389 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : 377 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 :
390 REDUCE_CHAIN_1; 378 REDUCE_CHAIN_1;
391 break; 379 break;
392 case ATH9K_ANT_FIXED_B: 380 case ATH9K_ANT_FIXED_B:
393 bank6SelMask = 381 bank6SelMask =
394 (ahp-> 382 (ah->
395 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : 383 ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 :
396 REDUCE_CHAIN_0; 384 REDUCE_CHAIN_0;
397 break; 385 break;
@@ -403,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
403 break; 391 break;
404 } 392 }
405 393
406 for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++) 394 for (i = 0; i < ah->ah_iniBank6.ia_rows; i++)
407 bank6Temp[i] = ahp->ah_analogBank6Data[i]; 395 bank6Temp[i] = ah->ah_analogBank6Data[i];
408 396
409 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); 397 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask);
410 398
@@ -418,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan)
418 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); 406 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0);
419 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); 407 ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0);
420 408
421 REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites); 409 REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites);
422 410
423 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); 411 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053);
424#ifdef ALTER_SWITCH 412#ifdef ALTER_SWITCH