diff options
author | Sujith <Sujith.Manoharan@atheros.com> | 2009-02-09 02:57:26 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-02-13 13:45:10 -0500 |
commit | 2660b81a378ab227b78c4cc618453fa7e19a7c7b (patch) | |
tree | ea305af43f0e27c86538fecce6c9a4e0151dbc78 /drivers/net/wireless/ath9k/phy.c | |
parent | f74df6fbe31561091bf42be0ed30232be2b9d3ac (diff) |
ath9k: Remove all the useless ah_ variable prefixes
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/phy.c')
-rw-r--r-- | drivers/net/wireless/ath9k/phy.c | 176 |
1 files changed, 88 insertions, 88 deletions
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index 5a42969b35a6..52aa2a7abe7a 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c | |||
@@ -20,7 +20,7 @@ void | |||
20 | ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, | 20 | ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, |
21 | int regWrites) | 21 | int regWrites) |
22 | { | 22 | { |
23 | REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); | 23 | REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); |
24 | } | 24 | } |
25 | 25 | ||
26 | bool | 26 | bool |
@@ -90,8 +90,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |||
90 | 90 | ||
91 | REG_WRITE(ah, AR_PHY(0x37), reg32); | 91 | REG_WRITE(ah, AR_PHY(0x37), reg32); |
92 | 92 | ||
93 | ah->ah_curchan = chan; | 93 | ah->curchan = chan; |
94 | ah->ah_curchanRadIndex = -1; | 94 | ah->curchan_rad_index = -1; |
95 | 95 | ||
96 | return true; | 96 | return true; |
97 | } | 97 | } |
@@ -160,8 +160,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah, | |||
160 | 160 | ||
161 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | 161 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); |
162 | 162 | ||
163 | ah->ah_curchan = chan; | 163 | ah->curchan = chan; |
164 | ah->ah_curchanRadIndex = -1; | 164 | ah->curchan_rad_index = -1; |
165 | 165 | ||
166 | return true; | 166 | return true; |
167 | } | 167 | } |
@@ -207,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, | |||
207 | 207 | ||
208 | eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); | 208 | eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); |
209 | 209 | ||
210 | RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); | 210 | RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); |
211 | 211 | ||
212 | RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); | 212 | RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); |
213 | 213 | ||
214 | RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); | 214 | RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); |
215 | 215 | ||
216 | RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, | 216 | RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, |
217 | modesIndex); | 217 | modesIndex); |
218 | { | 218 | { |
219 | int i; | 219 | int i; |
220 | for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { | 220 | for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { |
221 | ah->ah_analogBank6Data[i] = | 221 | ah->analogBank6Data[i] = |
222 | INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); | 222 | INI_RA(&ah->iniBank6TPC, i, modesIndex); |
223 | } | 223 | } |
224 | } | 224 | } |
225 | 225 | ||
@@ -227,33 +227,33 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, | |||
227 | if (IS_CHAN_2GHZ(chan)) { | 227 | if (IS_CHAN_2GHZ(chan)) { |
228 | ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); | 228 | ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); |
229 | db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); | 229 | db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); |
230 | ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, | 230 | ath9k_phy_modify_rx_buffer(ah->analogBank6Data, |
231 | ob2GHz, 3, 197, 0); | 231 | ob2GHz, 3, 197, 0); |
232 | ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, | 232 | ath9k_phy_modify_rx_buffer(ah->analogBank6Data, |
233 | db2GHz, 3, 194, 0); | 233 | db2GHz, 3, 194, 0); |
234 | } else { | 234 | } else { |
235 | ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); | 235 | ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); |
236 | db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); | 236 | db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); |
237 | ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, | 237 | ath9k_phy_modify_rx_buffer(ah->analogBank6Data, |
238 | ob5GHz, 3, 203, 0); | 238 | ob5GHz, 3, 203, 0); |
239 | ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, | 239 | ath9k_phy_modify_rx_buffer(ah->analogBank6Data, |
240 | db5GHz, 3, 200, 0); | 240 | db5GHz, 3, 200, 0); |
241 | } | 241 | } |
242 | } | 242 | } |
243 | 243 | ||
244 | RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); | 244 | RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); |
245 | 245 | ||
246 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, | 246 | REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, |
247 | regWrites); | 247 | regWrites); |
248 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, | 248 | REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, |
249 | regWrites); | 249 | regWrites); |
250 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, | 250 | REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, |
251 | regWrites); | 251 | regWrites); |
252 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, | 252 | REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, |
253 | regWrites); | 253 | regWrites); |
254 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, | 254 | REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, |
255 | regWrites); | 255 | regWrites); |
256 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, | 256 | REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, |
257 | regWrites); | 257 | regWrites); |
258 | 258 | ||
259 | return true; | 259 | return true; |
@@ -262,99 +262,99 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, | |||
262 | void | 262 | void |
263 | ath9k_hw_rfdetach(struct ath_hw *ah) | 263 | ath9k_hw_rfdetach(struct ath_hw *ah) |
264 | { | 264 | { |
265 | if (ah->ah_analogBank0Data != NULL) { | 265 | if (ah->analogBank0Data != NULL) { |
266 | kfree(ah->ah_analogBank0Data); | 266 | kfree(ah->analogBank0Data); |
267 | ah->ah_analogBank0Data = NULL; | 267 | ah->analogBank0Data = NULL; |
268 | } | 268 | } |
269 | if (ah->ah_analogBank1Data != NULL) { | 269 | if (ah->analogBank1Data != NULL) { |
270 | kfree(ah->ah_analogBank1Data); | 270 | kfree(ah->analogBank1Data); |
271 | ah->ah_analogBank1Data = NULL; | 271 | ah->analogBank1Data = NULL; |
272 | } | 272 | } |
273 | if (ah->ah_analogBank2Data != NULL) { | 273 | if (ah->analogBank2Data != NULL) { |
274 | kfree(ah->ah_analogBank2Data); | 274 | kfree(ah->analogBank2Data); |
275 | ah->ah_analogBank2Data = NULL; | 275 | ah->analogBank2Data = NULL; |
276 | } | 276 | } |
277 | if (ah->ah_analogBank3Data != NULL) { | 277 | if (ah->analogBank3Data != NULL) { |
278 | kfree(ah->ah_analogBank3Data); | 278 | kfree(ah->analogBank3Data); |
279 | ah->ah_analogBank3Data = NULL; | 279 | ah->analogBank3Data = NULL; |
280 | } | 280 | } |
281 | if (ah->ah_analogBank6Data != NULL) { | 281 | if (ah->analogBank6Data != NULL) { |
282 | kfree(ah->ah_analogBank6Data); | 282 | kfree(ah->analogBank6Data); |
283 | ah->ah_analogBank6Data = NULL; | 283 | ah->analogBank6Data = NULL; |
284 | } | 284 | } |
285 | if (ah->ah_analogBank6TPCData != NULL) { | 285 | if (ah->analogBank6TPCData != NULL) { |
286 | kfree(ah->ah_analogBank6TPCData); | 286 | kfree(ah->analogBank6TPCData); |
287 | ah->ah_analogBank6TPCData = NULL; | 287 | ah->analogBank6TPCData = NULL; |
288 | } | 288 | } |
289 | if (ah->ah_analogBank7Data != NULL) { | 289 | if (ah->analogBank7Data != NULL) { |
290 | kfree(ah->ah_analogBank7Data); | 290 | kfree(ah->analogBank7Data); |
291 | ah->ah_analogBank7Data = NULL; | 291 | ah->analogBank7Data = NULL; |
292 | } | 292 | } |
293 | if (ah->ah_addac5416_21 != NULL) { | 293 | if (ah->addac5416_21 != NULL) { |
294 | kfree(ah->ah_addac5416_21); | 294 | kfree(ah->addac5416_21); |
295 | ah->ah_addac5416_21 = NULL; | 295 | ah->addac5416_21 = NULL; |
296 | } | 296 | } |
297 | if (ah->ah_bank6Temp != NULL) { | 297 | if (ah->bank6Temp != NULL) { |
298 | kfree(ah->ah_bank6Temp); | 298 | kfree(ah->bank6Temp); |
299 | ah->ah_bank6Temp = NULL; | 299 | ah->bank6Temp = NULL; |
300 | } | 300 | } |
301 | } | 301 | } |
302 | 302 | ||
303 | bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) | 303 | bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) |
304 | { | 304 | { |
305 | if (!AR_SREV_9280_10_OR_LATER(ah)) { | 305 | if (!AR_SREV_9280_10_OR_LATER(ah)) { |
306 | ah->ah_analogBank0Data = | 306 | ah->analogBank0Data = |
307 | kzalloc((sizeof(u32) * | 307 | kzalloc((sizeof(u32) * |
308 | ah->ah_iniBank0.ia_rows), GFP_KERNEL); | 308 | ah->iniBank0.ia_rows), GFP_KERNEL); |
309 | ah->ah_analogBank1Data = | 309 | ah->analogBank1Data = |
310 | kzalloc((sizeof(u32) * | 310 | kzalloc((sizeof(u32) * |
311 | ah->ah_iniBank1.ia_rows), GFP_KERNEL); | 311 | ah->iniBank1.ia_rows), GFP_KERNEL); |
312 | ah->ah_analogBank2Data = | 312 | ah->analogBank2Data = |
313 | kzalloc((sizeof(u32) * | 313 | kzalloc((sizeof(u32) * |
314 | ah->ah_iniBank2.ia_rows), GFP_KERNEL); | 314 | ah->iniBank2.ia_rows), GFP_KERNEL); |
315 | ah->ah_analogBank3Data = | 315 | ah->analogBank3Data = |
316 | kzalloc((sizeof(u32) * | 316 | kzalloc((sizeof(u32) * |
317 | ah->ah_iniBank3.ia_rows), GFP_KERNEL); | 317 | ah->iniBank3.ia_rows), GFP_KERNEL); |
318 | ah->ah_analogBank6Data = | 318 | ah->analogBank6Data = |
319 | kzalloc((sizeof(u32) * | 319 | kzalloc((sizeof(u32) * |
320 | ah->ah_iniBank6.ia_rows), GFP_KERNEL); | 320 | ah->iniBank6.ia_rows), GFP_KERNEL); |
321 | ah->ah_analogBank6TPCData = | 321 | ah->analogBank6TPCData = |
322 | kzalloc((sizeof(u32) * | 322 | kzalloc((sizeof(u32) * |
323 | ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); | 323 | ah->iniBank6TPC.ia_rows), GFP_KERNEL); |
324 | ah->ah_analogBank7Data = | 324 | ah->analogBank7Data = |
325 | kzalloc((sizeof(u32) * | 325 | kzalloc((sizeof(u32) * |
326 | ah->ah_iniBank7.ia_rows), GFP_KERNEL); | 326 | ah->iniBank7.ia_rows), GFP_KERNEL); |
327 | 327 | ||
328 | if (ah->ah_analogBank0Data == NULL | 328 | if (ah->analogBank0Data == NULL |
329 | || ah->ah_analogBank1Data == NULL | 329 | || ah->analogBank1Data == NULL |
330 | || ah->ah_analogBank2Data == NULL | 330 | || ah->analogBank2Data == NULL |
331 | || ah->ah_analogBank3Data == NULL | 331 | || ah->analogBank3Data == NULL |
332 | || ah->ah_analogBank6Data == NULL | 332 | || ah->analogBank6Data == NULL |
333 | || ah->ah_analogBank6TPCData == NULL | 333 | || ah->analogBank6TPCData == NULL |
334 | || ah->ah_analogBank7Data == NULL) { | 334 | || ah->analogBank7Data == NULL) { |
335 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | 335 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
336 | "Cannot allocate RF banks\n"); | 336 | "Cannot allocate RF banks\n"); |
337 | *status = -ENOMEM; | 337 | *status = -ENOMEM; |
338 | return false; | 338 | return false; |
339 | } | 339 | } |
340 | 340 | ||
341 | ah->ah_addac5416_21 = | 341 | ah->addac5416_21 = |
342 | kzalloc((sizeof(u32) * | 342 | kzalloc((sizeof(u32) * |
343 | ah->ah_iniAddac.ia_rows * | 343 | ah->iniAddac.ia_rows * |
344 | ah->ah_iniAddac.ia_columns), GFP_KERNEL); | 344 | ah->iniAddac.ia_columns), GFP_KERNEL); |
345 | if (ah->ah_addac5416_21 == NULL) { | 345 | if (ah->addac5416_21 == NULL) { |
346 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | 346 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
347 | "Cannot allocate ah_addac5416_21\n"); | 347 | "Cannot allocate addac5416_21\n"); |
348 | *status = -ENOMEM; | 348 | *status = -ENOMEM; |
349 | return false; | 349 | return false; |
350 | } | 350 | } |
351 | 351 | ||
352 | ah->ah_bank6Temp = | 352 | ah->bank6Temp = |
353 | kzalloc((sizeof(u32) * | 353 | kzalloc((sizeof(u32) * |
354 | ah->ah_iniBank6.ia_rows), GFP_KERNEL); | 354 | ah->iniBank6.ia_rows), GFP_KERNEL); |
355 | if (ah->ah_bank6Temp == NULL) { | 355 | if (ah->bank6Temp == NULL) { |
356 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, | 356 | DPRINTF(ah->ah_sc, ATH_DBG_FATAL, |
357 | "Cannot allocate ah_bank6Temp\n"); | 357 | "Cannot allocate bank6Temp\n"); |
358 | *status = -ENOMEM; | 358 | *status = -ENOMEM; |
359 | return false; | 359 | return false; |
360 | } | 360 | } |
@@ -368,19 +368,19 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) | |||
368 | { | 368 | { |
369 | int i, regWrites = 0; | 369 | int i, regWrites = 0; |
370 | u32 bank6SelMask; | 370 | u32 bank6SelMask; |
371 | u32 *bank6Temp = ah->ah_bank6Temp; | 371 | u32 *bank6Temp = ah->bank6Temp; |
372 | 372 | ||
373 | switch (ah->ah_diversityControl) { | 373 | switch (ah->diversity_control) { |
374 | case ATH9K_ANT_FIXED_A: | 374 | case ATH9K_ANT_FIXED_A: |
375 | bank6SelMask = | 375 | bank6SelMask = |
376 | (ah-> | 376 | (ah-> |
377 | ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : | 377 | antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : |
378 | REDUCE_CHAIN_1; | 378 | REDUCE_CHAIN_1; |
379 | break; | 379 | break; |
380 | case ATH9K_ANT_FIXED_B: | 380 | case ATH9K_ANT_FIXED_B: |
381 | bank6SelMask = | 381 | bank6SelMask = |
382 | (ah-> | 382 | (ah-> |
383 | ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : | 383 | antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : |
384 | REDUCE_CHAIN_0; | 384 | REDUCE_CHAIN_0; |
385 | break; | 385 | break; |
386 | case ATH9K_ANT_VARIABLE: | 386 | case ATH9K_ANT_VARIABLE: |
@@ -391,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) | |||
391 | break; | 391 | break; |
392 | } | 392 | } |
393 | 393 | ||
394 | for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) | 394 | for (i = 0; i < ah->iniBank6.ia_rows; i++) |
395 | bank6Temp[i] = ah->ah_analogBank6Data[i]; | 395 | bank6Temp[i] = ah->analogBank6Data[i]; |
396 | 396 | ||
397 | REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); | 397 | REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); |
398 | 398 | ||
@@ -406,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) | |||
406 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); | 406 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); |
407 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); | 407 | ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); |
408 | 408 | ||
409 | REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); | 409 | REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites); |
410 | 410 | ||
411 | REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); | 411 | REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); |
412 | #ifdef ALTER_SWITCH | 412 | #ifdef ALTER_SWITCH |