ath9k: introduce bus specific cache size routine

The PCI specific bus_read_cachesize routine won't work on the AHB bus,
we have to replace it with a suitable one later.

Changes-licensed-under: ISC

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Tested-by: Pavel Roskin <proski@gnu.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 7 insertions, 2 deletions

diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index ebf0467674cf..884469a30235 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -42,7 +42,7 @@ static void ath_detach(struct ath_softc *sc);
 
 /* return bus cachesize in 4B word units */
 
-static void bus_read_cachesize(struct ath_softc *sc, int *csz)
+static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
 {
         u8 u8tmp;
 
@@ -1338,7 +1338,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
          * Cache line size is used to size and align various
          * structures used to communicate with the hardware.
          */
-        bus_read_cachesize(sc, &csz);
+        ath_read_cachesize(sc, &csz);
         /* XXX assert csz is non-zero */
         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
 
@@ -2534,6 +2534,10 @@ ath_rf_name(u16 rf_version)
         return "????";
 }
 
+static struct ath_bus_ops ath_pci_bus_ops = {
+        .read_cachesize = ath_pci_read_cachesize,
+};
+
 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
         void __iomem *mem;
@@ -2622,6 +2626,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         sc->hw = hw;
         sc->dev = &pdev->dev;
         sc->mem = mem;
+        sc->bus_ops = &ath_pci_bus_ops;
 
         if (ath_attach(id->device, sc) != 0) {
                 ret = -ENODEV;