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authorSujith <Sujith.Manoharan@atheros.com>2008-12-07 11:14:03 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-12-12 14:02:17 -0500
commitb77f483fcf0579de28873828897f53371a33a0ea (patch)
treea08d0f942d4b5d0cd8a7893753f9b7554ebc89e4 /drivers/net/wireless/ath9k/main.c
parent59651e89187293e88863891b821c7379391ef75c (diff)
ath9k: Refactor struct ath_softc
Split ath_softc into smaller structures for rx, tx and beacon handling. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/main.c')
-rw-r--r--drivers/net/wireless/ath9k/main.c60
1 files changed, 30 insertions, 30 deletions
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index 9455a6939876..02e1771bb274 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -348,7 +348,7 @@ static void ath_ani_calibrate(unsigned long data)
348 * don't calibrate when we're scanning. 348 * don't calibrate when we're scanning.
349 * we are most likely not on our home channel. 349 * we are most likely not on our home channel.
350 */ 350 */
351 if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC) 351 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
352 return; 352 return;
353 353
354 /* Long calibration runs independently of short calibration. */ 354 /* Long calibration runs independently of short calibration. */
@@ -487,9 +487,9 @@ static void ath9k_tasklet(unsigned long data)
487 487
488 if (status & 488 if (status &
489 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { 489 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
490 spin_lock_bh(&sc->sc_rxflushlock); 490 spin_lock_bh(&sc->rx.rxflushlock);
491 ath_rx_tasklet(sc, 0); 491 ath_rx_tasklet(sc, 0);
492 spin_unlock_bh(&sc->sc_rxflushlock); 492 spin_unlock_bh(&sc->rx.rxflushlock);
493 } 493 }
494 /* XXX: optimize this */ 494 /* XXX: optimize this */
495 if (status & ATH9K_INT_TX) 495 if (status & ATH9K_INT_TX)
@@ -1306,7 +1306,7 @@ static void ath_detach(struct ath_softc *sc)
1306 /* cleanup tx queues */ 1306 /* cleanup tx queues */
1307 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1307 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1308 if (ATH_TXQ_SETUP(sc, i)) 1308 if (ATH_TXQ_SETUP(sc, i))
1309 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 1309 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1310 1310
1311 ath9k_hw_detach(sc->sc_ah); 1311 ath9k_hw_detach(sc->sc_ah);
1312 ath9k_exit_debug(sc); 1312 ath9k_exit_debug(sc);
@@ -1397,15 +1397,15 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1397 * priority. Note that the hal handles reseting 1397 * priority. Note that the hal handles reseting
1398 * these queues at the needed time. 1398 * these queues at the needed time.
1399 */ 1399 */
1400 sc->sc_bhalq = ath_beaconq_setup(ah); 1400 sc->beacon.beaconq = ath_beaconq_setup(ah);
1401 if (sc->sc_bhalq == -1) { 1401 if (sc->beacon.beaconq == -1) {
1402 DPRINTF(sc, ATH_DBG_FATAL, 1402 DPRINTF(sc, ATH_DBG_FATAL,
1403 "Unable to setup a beacon xmit queue\n"); 1403 "Unable to setup a beacon xmit queue\n");
1404 error = -EIO; 1404 error = -EIO;
1405 goto bad2; 1405 goto bad2;
1406 } 1406 }
1407 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 1407 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1408 if (sc->sc_cabq == NULL) { 1408 if (sc->beacon.cabq == NULL) {
1409 DPRINTF(sc, ATH_DBG_FATAL, 1409 DPRINTF(sc, ATH_DBG_FATAL,
1410 "Unable to setup CAB xmit queue\n"); 1410 "Unable to setup CAB xmit queue\n");
1411 error = -EIO; 1411 error = -EIO;
@@ -1415,8 +1415,8 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1415 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME; 1415 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1416 ath_cabq_update(sc); 1416 ath_cabq_update(sc);
1417 1417
1418 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++) 1418 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1419 sc->sc_haltype2q[i] = -1; 1419 sc->tx.hwq_map[i] = -1;
1420 1420
1421 /* Setup data queues */ 1421 /* Setup data queues */
1422 /* NB: ensure BK queue is the lowest priority h/w queue */ 1422 /* NB: ensure BK queue is the lowest priority h/w queue */
@@ -1496,7 +1496,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1496 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; 1496 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1497 1497
1498 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 1498 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1499 sc->sc_defant = ath9k_hw_getdefantenna(ah); 1499 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1500 1500
1501 ath9k_hw_getmac(ah, sc->sc_myaddr); 1501 ath9k_hw_getmac(ah, sc->sc_myaddr);
1502 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { 1502 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
@@ -1505,11 +1505,11 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1505 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); 1505 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1506 } 1506 }
1507 1507
1508 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ 1508 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1509 1509
1510 /* initialize beacon slots */ 1510 /* initialize beacon slots */
1511 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++) 1511 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1512 sc->sc_bslot[i] = ATH_IF_ID_ANY; 1512 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1513 1513
1514 /* save MISC configurations */ 1514 /* save MISC configurations */
1515 sc->sc_config.swBeaconProcess = 1; 1515 sc->sc_config.swBeaconProcess = 1;
@@ -1535,7 +1535,7 @@ bad2:
1535 /* cleanup tx queues */ 1535 /* cleanup tx queues */
1536 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1536 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1537 if (ATH_TXQ_SETUP(sc, i)) 1537 if (ATH_TXQ_SETUP(sc, i))
1538 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 1538 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1539bad: 1539bad:
1540 if (ah) 1540 if (ah)
1541 ath9k_hw_detach(ah); 1541 ath9k_hw_detach(ah);
@@ -1673,9 +1673,9 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1673 int i; 1673 int i;
1674 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1674 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1675 if (ATH_TXQ_SETUP(sc, i)) { 1675 if (ATH_TXQ_SETUP(sc, i)) {
1676 spin_lock_bh(&sc->sc_txq[i].axq_lock); 1676 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1677 ath_txq_schedule(sc, &sc->sc_txq[i]); 1677 ath_txq_schedule(sc, &sc->tx.txq[i]);
1678 spin_unlock_bh(&sc->sc_txq[i].axq_lock); 1678 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1679 } 1679 }
1680 } 1680 }
1681 } 1681 }
@@ -1810,19 +1810,19 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1810 1810
1811 switch (queue) { 1811 switch (queue) {
1812 case 0: 1812 case 0:
1813 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO]; 1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1814 break; 1814 break;
1815 case 1: 1815 case 1:
1816 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI]; 1816 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1817 break; 1817 break;
1818 case 2: 1818 case 2:
1819 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; 1819 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1820 break; 1820 break;
1821 case 3: 1821 case 3:
1822 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK]; 1822 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1823 break; 1823 break;
1824 default: 1824 default:
1825 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; 1825 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1826 break; 1826 break;
1827 } 1827 }
1828 1828
@@ -1993,9 +1993,9 @@ static int ath9k_tx(struct ieee80211_hw *hw,
1993 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1993 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1994 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1994 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1995 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1995 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1996 sc->seq_no += 0x10; 1996 sc->tx.seq_no += 0x10;
1997 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1997 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1998 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); 1998 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1999 } 1999 }
2000 2000
2001 /* Add the padding after the header if this is not already done */ 2001 /* Add the padding after the header if this is not already done */
@@ -2049,7 +2049,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2049 ath_stoprecv(sc); 2049 ath_stoprecv(sc);
2050 ath9k_hw_phy_disable(sc->sc_ah); 2050 ath9k_hw_phy_disable(sc->sc_ah);
2051 } else 2051 } else
2052 sc->sc_rxlink = NULL; 2052 sc->rx.rxlink = NULL;
2053 2053
2054#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2054#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2055 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 2055 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
@@ -2131,7 +2131,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2131 /* Reclaim beacon resources */ 2131 /* Reclaim beacon resources */
2132 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || 2132 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2133 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { 2133 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2134 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); 2134 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2135 ath_beacon_return(sc, avp); 2135 ath_beacon_return(sc, avp);
2136 } 2136 }
2137 2137
@@ -2250,7 +2250,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
2250 * causes reconfiguration; we may be called 2250 * causes reconfiguration; we may be called
2251 * with beacon transmission active. 2251 * with beacon transmission active.
2252 */ 2252 */
2253 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); 2253 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2254 2254
2255 error = ath_beacon_alloc(sc, 0); 2255 error = ath_beacon_alloc(sc, 0);
2256 if (error != 0) 2256 if (error != 0)
@@ -2296,7 +2296,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2296 changed_flags &= SUPPORTED_FILTERS; 2296 changed_flags &= SUPPORTED_FILTERS;
2297 *total_flags &= SUPPORTED_FILTERS; 2297 *total_flags &= SUPPORTED_FILTERS;
2298 2298
2299 sc->rx_filter = *total_flags; 2299 sc->rx.rxfilter = *total_flags;
2300 rfilt = ath_calcrxfilter(sc); 2300 rfilt = ath_calcrxfilter(sc);
2301 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 2301 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2302 2302
@@ -2305,7 +2305,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2305 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0); 2305 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2306 } 2306 }
2307 2307
2308 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter); 2308 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2309} 2309}
2310 2310
2311static void ath9k_sta_notify(struct ieee80211_hw *hw, 2311static void ath9k_sta_notify(struct ieee80211_hw *hw,