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authorSujith <Sujith.Manoharan@atheros.com>2009-02-16 02:53:20 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-02-27 14:52:37 -0500
commit0caa7b14f36e8c3c43dd9294a960ae55cafe07fb (patch)
tree13a878857346d4bb67e57b31f6ab25a03ed4c6d7 /drivers/net/wireless/ath9k/mac.c
parent70768496db9ee27d53d3d03d50c93fbf4c0198a0 (diff)
ath9k: Fix HW wait timeout
RX and calibration have different timeout requirements. This patch fixes it by changing the HW wait routine to accept a timeout value. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/mac.c')
-rw-r--r--drivers/net/wireless/ath9k/mac.c28
1 files changed, 23 insertions, 5 deletions
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index f32c622db6e7..a6c204283ad5 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -886,7 +886,8 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
886 REG_SET_BIT(ah, AR_DIAG_SW, 886 REG_SET_BIT(ah, AR_DIAG_SW,
887 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); 887 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
888 888
889 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) { 889 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
890 0, AH_WAIT_TIMEOUT)) {
890 REG_CLR_BIT(ah, AR_DIAG_SW, 891 REG_CLR_BIT(ah, AR_DIAG_SW,
891 (AR_DIAG_RX_DIS | 892 (AR_DIAG_RX_DIS |
892 AR_DIAG_RX_ABORT)); 893 AR_DIAG_RX_ABORT));
@@ -933,15 +934,32 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah)
933 934
934bool ath9k_hw_stopdmarecv(struct ath_hw *ah) 935bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
935{ 936{
937#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
938#define AH_RX_TIME_QUANTUM 100 /* usec */
939
940 int i;
941
936 REG_WRITE(ah, AR_CR, AR_CR_RXD); 942 REG_WRITE(ah, AR_CR, AR_CR_RXD);
937 943
938 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { 944 /* Wait for rx enable bit to go low */
945 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
946 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
947 break;
948 udelay(AH_TIME_QUANTUM);
949 }
950
951 if (i == 0) {
939 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 952 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
940 "dma failed to stop in 10ms\n" 953 "dma failed to stop in %d ms "
941 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 954 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
942 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); 955 AH_RX_STOP_DMA_TIMEOUT / 1000,
956 REG_READ(ah, AR_CR),
957 REG_READ(ah, AR_DIAG_SW));
943 return false; 958 return false;
944 } else { 959 } else {
945 return true; 960 return true;
946 } 961 }
962
963#undef AH_RX_TIME_QUANTUM
964#undef AH_RX_STOP_DMA_TIMEOUT
947} 965}