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authorSujith <Sujith.Manoharan@atheros.com>2009-03-30 05:58:22 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-04-22 16:54:29 -0400
commitbdbdf46daa6dccb472f56559854477faddc44de9 (patch)
tree24e6968f86689aab0e4db417e4d4f7205ad2911e /drivers/net/wireless/ath9k/hw.h
parent8782b41d13c8e5f9a201477d3c15edf9fe7c372c (diff)
ath9k: Remove a few unused flags
This patch removes unused HW capability flags and HW operation variables, and a chainmask flag that we don't use anywhere. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath9k/hw.h')
-rw-r--r--drivers/net/wireless/ath9k/hw.h52
1 files changed, 18 insertions, 34 deletions
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index 0b594e0ee260..5ba6a4b60356 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -124,29 +124,24 @@ enum wireless_mode {
124}; 124};
125 125
126enum ath9k_hw_caps { 126enum ath9k_hw_caps {
127 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), 127 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
128 ATH9K_HW_CAP_MIC_AESCCM = BIT(1), 128 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
129 ATH9K_HW_CAP_MIC_CKIP = BIT(2), 129 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
130 ATH9K_HW_CAP_MIC_TKIP = BIT(3), 130 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
131 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), 131 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
132 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), 132 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
133 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), 133 ATH9K_HW_CAP_VEOL = BIT(6),
134 ATH9K_HW_CAP_VEOL = BIT(7), 134 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
135 ATH9K_HW_CAP_BSSIDMASK = BIT(8), 135 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
136 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), 136 ATH9K_HW_CAP_HT = BIT(9),
137 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), 137 ATH9K_HW_CAP_GTT = BIT(10),
138 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), 138 ATH9K_HW_CAP_FASTCC = BIT(11),
139 ATH9K_HW_CAP_HT = BIT(12), 139 ATH9K_HW_CAP_RFSILENT = BIT(12),
140 ATH9K_HW_CAP_GTT = BIT(13), 140 ATH9K_HW_CAP_CST = BIT(13),
141 ATH9K_HW_CAP_FASTCC = BIT(14), 141 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
142 ATH9K_HW_CAP_RFSILENT = BIT(15), 142 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
143 ATH9K_HW_CAP_WOW = BIT(16), 143 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
144 ATH9K_HW_CAP_CST = BIT(17), 144 ATH9K_HW_CAP_BT_COEX = BIT(17)
145 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
146 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
147 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
148 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
149 ATH9K_HW_CAP_BT_COEX = BIT(22)
150}; 145};
151 146
152enum ath9k_capability_type { 147enum ath9k_capability_type {
@@ -166,7 +161,6 @@ struct ath9k_hw_capabilities {
166 u16 keycache_size; 161 u16 keycache_size;
167 u16 low_5ghz_chan, high_5ghz_chan; 162 u16 low_5ghz_chan, high_5ghz_chan;
168 u16 low_2ghz_chan, high_2ghz_chan; 163 u16 low_2ghz_chan, high_2ghz_chan;
169 u16 num_mr_retries;
170 u16 rts_aggr_limit; 164 u16 rts_aggr_limit;
171 u8 tx_chainmask; 165 u8 tx_chainmask;
172 u8 rx_chainmask; 166 u8 rx_chainmask;
@@ -184,11 +178,8 @@ struct ath9k_ops_config {
184 int ack_6mb; 178 int ack_6mb;
185 int cwm_ignore_extcca; 179 int cwm_ignore_extcca;
186 u8 pcie_powersave_enable; 180 u8 pcie_powersave_enable;
187 u8 pcie_l1skp_enable;
188 u8 pcie_clock_req; 181 u8 pcie_clock_req;
189 u32 pcie_waen; 182 u32 pcie_waen;
190 int pcie_power_reset;
191 u8 pcie_restore;
192 u8 analog_shiftreg; 183 u8 analog_shiftreg;
193 u8 ht_enable; 184 u8 ht_enable;
194 u32 ofdm_trig_low; 185 u32 ofdm_trig_low;
@@ -196,13 +187,6 @@ struct ath9k_ops_config {
196 u32 cck_trig_high; 187 u32 cck_trig_high;
197 u32 cck_trig_low; 188 u32 cck_trig_low;
198 u32 enable_ani; 189 u32 enable_ani;
199 u8 noise_immunity_level;
200 u32 ofdm_weaksignal_det;
201 u32 cck_weaksignal_thr;
202 u8 spur_immunity_level;
203 u8 firstep_level;
204 int8_t rssi_thr_high;
205 int8_t rssi_thr_low;
206 u16 diversity_control; 190 u16 diversity_control;
207 u16 antenna_switch_swap; 191 u16 antenna_switch_swap;
208 int serialize_regmode; 192 int serialize_regmode;